Data storage system and method using FLASH to simulate EEPROM

Abstract

The invention relates to a data storage system and method for simulating an EEPROM (Electrically Erasable Programmable Read-Only Memory) by using FLASH, which are characterized in that deep improvement is carried out based on an existing similar FLASH simulation EEPROM hardware implementation method, a digital circuit controller for simulating an EEPROM function is designed by using FLASH, an SRAM (Static Random Access Memory) and other memory devices, the EEPROM function is simulated by using a hardware method, an improved data storage structure and a finer digital circuit control method are adopted, for example, state information is introduced, 'ping-pong operation 'management is adopted to alternately execute internal backup transfer operation and write operation corresponding to an external host, and a'background recovery' management mechanism is designed to perform background recovery on analog EEPROM data blocks; and meanwhile, an exception management mechanism is introduced for diagnosis and exception management, so that the hardware implementation performance loss of simulating the EEPROM by using the FLASH is greatly reduced, and the utilization rate of storage resources is effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of data storage, and relates to a data storage system and method using FLASH to simulate EEPROM. Background Art

[0002] The non-volatile memory commonly used in current integrated circuit design includes EEPROM (Electrically Erasable Programmable Read-Only Memory) and FLASH (Flash Memory). EEPROM has the advantages of high erase and write times and flexible read and write by byte, but it has the disadvantages of low resource utilization and large read and write access delay, so it is suitable for storage scenarios with frequent and flexible updates of small data volumes. FLASH has the advantages of high resource utilization and small read and write access delay, but it has the disadvantages of low erase and write times and does not support erase and write by byte. FLASH can generally only erase large amounts of data by data block (sector) and can only perform the next write operation after the erase operation is completed, so it is suitable for storage scenarios with large amounts of data and fast read and write.

[0003] In actual integrated circuit design, due to process reasons (for example, the process of the semiconductor manufacturing plant (foundry) does not support EEPROM), or for design cost and performance considerations (for example, wanting to combine the advantages of EEPROM and FLASH), the implementation technology of FLASH emulation EEPROM is often used. There are usually two methods of using FLASH to emulate EEPROM: software implementation and hardware implementation, and the overall design ideas are similar. The existing hardware implementation method of the same type of FLASH emulation EEPROM generally uses FLASH storage space that is several times the capacity of the target emulation EEPROM and SRAM (static random access memory) that is equal to the capacity of the target emulation EEPROM, combined with an emulation EEPROM controller circuit to implement the FLASH emulation EEPROM function. Its design architecture divides the FLASH storage space into several emulation EEPROM data blocks (i.e., FLASH BANKs), and the capacity of each FLASH BANK is the capacity of the target emulation EEPROM. However, the traditional hardware implementation method of using FLASH to simulate EEPROM still has technical problems such as large performance loss and low storage resource utilization when the FLASH BANK "page turning" phenomenon occurs and the amount of effective data in the simulated EEPROM is large. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a data storage system using FLASH to simulate EEPROM and a data storage management method using FLASH to simulate EEPROM, which can greatly reduce the performance loss of hardware implementation using FLASH to simulate EEPROM and effectively improve the storage resource utilization of FLASH storage body.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a data storage system using FLASH to simulate EEPROM is provided, including a simulated EEPROM controller, SRAM and FLASH storage body; The capacity of each simulated EEPROM data block in the FLASH storage body is greater than the target simulated EEPROM capacity, and the data structure of each simulated EEPROM data block includes a first type of address bit and a second type of address bit, the first type of address bit is used to store the status information of the simulated EEPROM data block, including an erase status flag bit, a backup status flag bit, a write status flag bit and a transfer status flag bit, and the second type of address bit is used to store the simulated EEPROM data, the simulated EEPROM data address and the data validity status; When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, the simulated EEPROM controller performs the backup transfer operation of continuously reading the simulated EEPROM data from the SRAM one by one and writing them into the storage space of the empty simulated EEPROM data block in the FLASH storage body when there is no simulated EEPROM write operation request initiated by the external host, and when there is a simulated EEPROM write operation request initiated by the external host, the write operation corresponding to the simulated EEPROM write operation request initiated by the external host and the backup transfer operation are performed alternately; The simulated EEPROM controller is also used to perform background recovery of simulated EEPROM data blocks that have been fully written in the FLASH storage body and have not participated in the simulated EEPROM data writing or backup transfer operation. The simulated EEPROM controller performs diagnosis and exception management based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data during the system power-on initialization phase when restoring the simulated EEPROM data from the simulated EEPROM data blocks to SRAM.

[0006] On the other hand, a data storage management method using FLASH to simulate EEPROM is also provided, which is applied to the above-mentioned data storage system using FLASH to simulate EEPROM. The data storage management method using FLASH to simulate EEPROM comprises the steps of: When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, when there is no simulated EEPROM write operation request initiated by the external host, the simulated EEPROM controller executes the backup transfer operation of continuously reading the simulated EEPROM data from the SRAM one by one and writing them into the storage space of the empty simulated EEPROM data block in the FLASH storage body; When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, when there is a simulated EEPROM write operation request initiated by the external host, the simulated EEPROM controller alternately executes the write operation and the backup transfer operation corresponding to the simulated EEPROM write operation request initiated by the external host; The simulated EEPROM controller is used to perform background recycling of simulated EEPROM data blocks that are fully written in the FLASH storage body and do not participate in the simulated EEPROM data writing or backup transfer operation; In the process of restoring the simulated EEPROM data from the simulated EEPROM data block to the SRAM during the system power-on initialization phase, diagnosis and abnormality management are performed based on the status information of the simulated EEPROM data block and the backed-up simulated EEPROM data.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The data storage system and method using FLASH to simulate EEPROM are deeply improved based on the existing hardware implementation method of similar FLASH to simulate EEPROM, and a digital circuit controller is designed to realize the function of simulating EEPROM by using storage devices such as FLASH and SRAM, and the function of simulating EEPROM is realized by hardware method. Moreover, through the improved data storage structure and more sophisticated digital circuit control method, such as introducing status information such as erase status flag bit, backup status flag bit, write status flag bit and transfer status flag bit, "ping-pong operation" management is adopted to alternately execute internal backup transfer operation and write operation corresponding to external host, and a "background recycling" management mechanism is designed to perform background recycling on the simulated EEPROM data blocks that are already full in the FLASH storage body and have not participated in the simulated EEPROM data writing or backup transfer operation, and at the same time, an exception management mechanism is introduced to perform diagnosis and exception management according to the status information of the simulated EEPROM data block and the backup simulated EEPROM data in the process of restoring the simulated EEPROM data from the simulated EEPROM data block to SRAM in the system power-on initialization stage, which greatly reduces the performance loss of the hardware implementation of FLASH to simulate EEPROM and effectively improves the utilization rate of storage resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 This is a schematic diagram of the existing hardware implementation of using FLASH to simulate EEPROM; Figure 2 A schematic diagram of hardware implementation of a data storage system using FLASH to simulate EEPROM in one embodiment; Figure 3 A schematic diagram of a "ping-pong operation" for simulating EEPROM data backup transfer in one embodiment; Figure 4 A schematic diagram of a data structure of a simulated EEPROM data block in one embodiment; Figure 5 A schematic diagram of the working process of a data storage system using FLASH to simulate EEPROM in one embodiment; Figure 6 The figure is a flow chart of a data storage management method using FLASH to simulate EEPROM in one embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] like Figure 1 The figure shows a schematic diagram of the existing FLASH emulation EEPROM hardware implementation method, and the overall process of emulation EEPROM data access is as follows: when the device is powered off, the emulation EEPROM data and its corresponding emulation EEPROM address are stored in the FLASH storage space. When the device is powered on, the emulation EEPROM controller first reads out the emulation EEPROM data stored in the FLASH storage body one by one and restores and writes them to the corresponding emulation EEPROM address space in the SRAM according to its emulation EEPROM address. When the external host reads the emulation EEPROM, the corresponding emulation EEPROM data is directly read from the corresponding emulation EEPROM read access address in the SRAM. When the external host writes to the emulation EEPROM, the write data is first updated to the emulation EEPROM write operation address space in the SRAM, and then the emulation EEPROM controller writes the updated emulation EEPROM data and its corresponding emulation EEPROM address to the corresponding FLASH BANK storage space according to whether the current write operation changes the emulation EEPROM data of the current write operation address, so that the emulation EEPROM data can be restored after the device is powered off / on.

[0014] Since FLASH has the characteristic that after a write operation, the next write operation can only be performed after the erase operation is completed, the simulated EEPROM controller needs to divide the simulated EEPROM data blocks (such as Figure 1The emulated EEPROM controller performs erase and write management for FLASH BANK0 to FLASH BANK7 in the SRAM. After the storage space of the current FLASHBANK is full, if a new emulated EEPROM write operation by the external host is detected, the next FLASHBANK needs to be erased first, and then the emulated EEPROM data in the SRAM is traversed, and the valid data (non-binary all-1 data, binary all-1 data is the default data after the memory is initialized, and no need to be saved) and its corresponding emulated EEPROM address are backed up and transferred to the storage space of the next FLASH BANK, so that the emulated EEPROM data can be restored after the device is powered off and then powered on. Then, it can respond to the new emulated EEPROM write operation of the external host, update the new emulated EEPROM write data to the emulated EEPROM write operation address space in the SRAM, and write the updated emulated EEPROM data and its corresponding emulated EEPROM address together into the corresponding FLASH BANK storage space, so that the emulated EEPROM data can be restored after the device is powered off and then powered on.

[0015] In the current design of the same type of hardware method to realize the FLASH emulation EEPROM function, due to the widespread "page turning" phenomenon, that is, after the FLASH sector is fully programmed, it is necessary to first perform time-consuming operations such as erasing the sector and transferring the backup data before the new emulation EEPROM write operation data can be written into the FLASH for backup and preservation. The existence of this phenomenon makes the emulation EEPROM write operation time-consuming and unstable, and the larger the amount of effective data in the emulation EEPROM, the more frequent the "page turning" phenomenon will be, and the more obvious the time-consuming and unstable impact of the emulation EEPROM write operation. At the same time, most of the FLASH storage space resources are used to save the data of the emulation EEPROM backup transfer, resulting in low resource utilization.

[0016] Specifically, under the specific working clock frequency used in the example, the FLASH BANK erase operation generally takes milliseconds, and the FLASH BANK data write operation generally takes microseconds, and the time consumption of a large amount of data write operation will increase exponentially, and eventually reach tens of milliseconds. Therefore, when the "page flip" phenomenon occurs, the external host's write operation needs to wait for the erase operation of all data blocks (sectors) of the FLASH BANK and the FLASH write operation of all valid simulated EEPROM data to be completed, and the access delay is huge, which is dozens or even hundreds of times that of the simulated EEPROM write operation during normal operation. As the target simulated EEPROM data capacity increases, more simulated EEPROM data needs to be backed up and transferred each time the "page turning" phenomenon occurs, and the access delay will be greater. As the amount of valid data in the simulated EEPROM increases, the remaining available data space in the new FLASH BANK after the "page turning" backup and transfer operation will decrease, and the "page turning" phenomenon will become more frequent. It may even happen that the storage space resource utilization of the FLASH BANK is extremely low when the simulated EEPROM is full of valid data, resulting in an extreme scenario where each simulated EEPROM write data operation will trigger the "page turning" phenomenon.

[0017] In one embodiment, Figure 2 As shown, a data storage system using FLASH to simulate EEPROM is provided, including a simulated EEPROM controller, SRAM and FLASH storage body. The capacity of each simulated EEPROM data block in the FLASH storage body is greater than the target simulated EEPROM capacity, and the data structure of each simulated EEPROM data block includes a first type of address bit and a second type of address bit. The first type of address bit is used to store the status information of the simulated EEPROM data block, including an erase status flag bit, a backup status flag bit, a write status flag bit and a transfer status flag bit. The second type of address bit is used to store simulated EEPROM data, simulated EEPROM data address and data validity status. When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, the simulated EEPROM controller, when there is no simulated EEPROM write operation request initiated by an external host, executes a backup transfer operation of continuously reading the simulated EEPROM data from the SRAM one by one and writing them into the storage space of the empty simulated EEPROM data block in the FLASH storage body; when there is a simulated EEPROM write operation request initiated by an external host, the write operation corresponding to the simulated EEPROM write operation request initiated by the external host and the backup transfer operation are executed alternately.

[0018] The simulated EEPROM controller is also used to perform background recovery of simulated EEPROM data blocks that have been fully written in the FLASH storage body and have not participated in the simulated EEPROM data writing or backup transfer operation. The simulated EEPROM controller performs diagnosis and exception management based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data during the system power-on initialization phase when restoring the simulated EEPROM data from the simulated EEPROM data blocks to SRAM.

[0019] Understandably, Figure 2 A0 represents the sequential erasure of all FLASH BANKs in the current FLASH bank when the data backup and transfer operation of the first FLASH BANK of the next FLASH bank is completed. A2 represents the FLASH BANK status management, and A3 represents the FLASH BANK number rotation in response to the external host emulating the EEPROM write operation.

[0020] In the present embodiment, a new relationship between the simulated EEPROM and FLASH BANK storage space structure division, as well as a new management and control method for FLASH BANK erasing and simulated EEPROM data backup transfer are designed, thereby eliminating the loss of simulated EEPROM access performance caused by the "page turning" phenomenon in the existing FLASH simulated EEPROM hardware implementation method as much as possible, reducing the low storage space resource utilization caused by the increase in the amount of effective data in the simulated EEPROM, and significantly improving the disadvantage of frequent "page turning" phenomenon.

[0021] This embodiment is based on the existing FLASH emulation EEPROM hardware implementation method, and improves the FLASH storage space emulation EEPROM data block (FLASH BANK) division structure. Specifically, the capacity of the FLASH storage space emulation EEPROM data block (FLASH BANK) is changed from being equal to the target emulation EEPROM capacity to being larger than the target emulation EEPROM capacity. For example, Figure 2 The capacity of each FLASH BANK is twice the capacity of the target simulated EEPROM. This improved design allows for a proper amount of storage space to be left for new simulated EEPROM write operations to save new data after the storage space of the FLASH BANK is occupied by the simulated EEPROM data backup transfer during "page turning" when the simulated EEPROM is full of valid data, thus avoiding frequent "page turning" and effectively avoiding wasting the main storage space resources of the FLASH BANK on the backup transfer of simulated EEPROM data during frequent "page turning", thus improving resource utilization.

[0022] Next, based on the existing FLASH emulated EEPROM hardware implementation method, the scheme of emulated EEPROM data backup transfer during "page turning" is improved. Specifically, in this embodiment, when the data space of the emulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next emulated EEPROM data block is not completed, when there is no emulated EEPROM write operation request initiated by the external host, the emulated EEPROM data is continuously read out from the SRAM one by one, and then written into the storage space of the new (empty) FLASH BANK to complete the emulated EEPROM data backup transfer operation; when there is a emulated EEPROM write operation request initiated by the external host, the write operation request initiated by the external host needs to write to the FLASH BANK, which will conflict with the requirement of the emulated EEPROM data backup operation to write to the FLASH BANK, so the emulated EEPROM data backup transfer operation is no longer continuously performed, and the write operation requests for these two types of FLASH BANK are instead performed as follows. Figure 3 The "ping-pong operation" management shown, that is, the simulated EEPROM write operation initiated by the external host and the simulated EEPROM data backup transfer operation are performed alternately, and according to the proportional relationship between the FLASH BANK capacity and the target simulated EEPROM capacity, each specific simulated EEPROM data backup transfer operation is controlled to be executed 2 times or more, so that the simulated EEPROM data backup transfer operation can be completed as soon as possible, and it is avoided that the FLASH BANK storage space has been filled with the simulated EEPROM write operation initiated by the external host, and the simulated EEPROM data backup transfer operation has not been completed.

[0023] For example, when the FLASH BANK capacity is twice greater than the target emulated EEPROM capacity, the ratio of the emulated EEPROM write operation and the emulated EEPROM data backup transfer operation initiated by the external host can be set to 1:1 and executed alternately; when the FLASH BANK capacity is less than twice the target emulated EEPROM capacity, the aforementioned operation ratio needs to be set to 1:2; when the FLASH BANK capacity is less than 1.5 times the target emulated EEPROM capacity, the aforementioned operation ratio needs to be set to 1:3. The purpose is to successfully complete the backup transfer of all emulated EEPROM data under the maximum valid data volume in a FLASH BANK, which can be understood as allocating the FLASH BANK capacity to the emulated EEPROM write operation data and the emulated EEPROM data backup transfer operation data initiated by the external host according to the aforementioned operation ratio, wherein the data space allocated to the emulated EEPROM data backup transfer operation data must be greater than the capacity of the target emulated EEPROM, otherwise it will not be possible to complete the backup transfer of all emulated EEPROM data under the maximum valid data volume in the FLASH BANK.

[0024] By improving the scheme of simulating EEPROM data backup transfer when "turning pages", the huge delay in the existing method of waiting for the completion of all simulated EEPROM data backup transfer before responding to new external host simulated EEPROM write operations is distributed to multiple external host simulated EEPROM write operations, and the delay of external host simulated EEPROM write operations in the worst scenario is controlled within the total time of several FLASH BANK write operations according to the size of the actual write operation data.

[0025] The data storage system using FLASH to simulate EEPROM is deeply improved based on the existing hardware implementation method of similar FLASH to simulate EEPROM, and a digital circuit controller that realizes the function of simulating EEPROM is designed by using storage devices such as FLASH and SRAM, and the function of simulating EEPROM is realized by hardware method. In addition, through the improved data storage structure and more sophisticated digital circuit control method, such as introducing status information such as erase status flag bit, backup status flag bit, write status flag bit and transfer status flag bit, a "ping-pong operation" management is adopted to alternately execute the internal backup transfer operation and the write operation corresponding to the external host, and a "background recycling" management mechanism is designed to perform background recycling on the simulated EEPROM data blocks that are already full in the FLASH storage body and have not participated in the simulated EEPROM data writing or backup transfer operation. At the same time, an exception management mechanism is introduced to perform diagnosis and exception management according to the status information of the simulated EEPROM data block and the backup simulated EEPROM data in the process of restoring the simulated EEPROM data from the simulated EEPROM data block to SRAM in the system power-on initialization phase, which greatly reduces the performance loss of the hardware implementation of FLASH to simulate EEPROM and effectively improves the utilization rate of storage resources.

[0026] In one embodiment, the values ​​of the erase status flag and the backup status flag both include specific valid values, and a count value that is initially all 1 and decreases with each update, and the values ​​of the write status flag and the transfer status flag are both specific valid values. The erase status flag is used to detect whether the erase status of the simulated EEPROM data block to which it belongs is legal, and the value of the erase status flag is updated and written by the simulated EEPROM controller immediately after each background recovery and erasure of the simulated EEPROM data block to which it belongs is completed. The backup status flag is used to find and determine the simulated EEPROM data block to which the current backup is valid, and the value of the backup status flag is updated and written by the simulated EEPROM controller when the backup transfer operation of the valid simulated EEPROM data is completed on the simulated EEPROM data block to which it belongs. The write status flag is used to determine whether the simulated EEPROM data block to which it currently belongs has been subjected to a simulated EEPROM data write operation after the last background recovery and erasure, and the value of the write status flag is written by the simulated EEPROM controller before enabling a new simulated EEPROM data block to perform a simulated EEPROM data write operation of an external host after the previous simulated EEPROM data block is full. The transfer status flag is used to determine whether the current simulated EEPROM data block has performed a backup transfer operation of the simulated EEPROM data after the last background recovery and erasure. The value of the transfer status flag is written by the simulated EEPROM controller after the previous simulated EEPROM data block is full and before the new simulated EEPROM data block is enabled and the backup transfer operation of the simulated EEPROM data is performed.

[0027] It can be understood that based on the existing FLASH emulation EEPROM hardware implementation method, the FLASH BANK erasure management method is improved. This embodiment provides a "background recycling" management mechanism for FLASH BANK, which can use two or more independent FLASH storage bodies (it should be noted that: the design scheme of the present invention can also be applied when only one FLASH storage body is used, but the functional characteristics of "background recycling" cannot be realized, so when the "page turning" phenomenon occurs, the delay performance loss of the emulation EEPROM data block erasure operation waiting for the FLASH storage body will be inevitable), when the FLASHBANK in the corresponding FLASH storage body has been filled and does not participate in the emulation EEPROM data writing or emulation EEPROM data backup management, the emulation EEPROM controller performs a parallel erasure operation, and after the erasure is completed, the "recycling" is realized, and it can be delivered for use again for FLASH write operations. Since the currently "recycled" FLASH BANK does not participate in the emulation EEPROM function implementation, this background "recycling" operation is carried out in parallel with the normal emulation EEPROM function, which can effectively eliminate the huge performance loss caused by waiting for the FLASH BANK erase operation in the existing method.

[0028] It can be understood that the present embodiment also provides a new data structure, state management mechanism and exception management mechanism of the FLASH simulated EEPROM data block (FLASH BANK) storage space, so that the system can cope with the influence of abnormal power failure on the simulated EEPROM function when the external host performs simulated EEPROM write operation or simulated EEPROM data backup transfer.

[0029] Among them, data structure: optional, the data bit width of the simulated EEPROM data block in each FLASH storage body is at least greater than the sum of the simulated EEPROM address bit width, data bit width and data valid status information bit width, and is used to store simulated EEPROM data and its corresponding address information, as well as data valid status (a specific valid value, which can be set according to usage needs). Figure 4 As shown, at the same time, the storage space of 4 addresses (called first-class address bits, and correspondingly, the remaining address bits are called second-class address bits (in some embodiments, the first-class address bits are, for example but not limited to, the first 4 address bits of the simulated EEPROM data block)) in each FLASH BANK is used to save the status information of the FLASH BANK, and the status information includes an erase status flag bit, a backup status flag bit, a write status flag bit and a transfer status flag bit.

[0030] State management mechanism: According to the control requirements of the simulated EEPROM, four state flags are defined for each FLASH BANK, namely, the erase state flag, backup state flag, write state flag, and transfer state flag. Among them, the erase state flag and the backup state flag are a combination of a specific valid value and a count value that is initially all 1 and decreases with each update. The write state flag and the transfer state flag are a specific valid value.

[0031] The erase status flag is used to detect whether the erase status is legal: the control logic ensures that the count value of the erase status flag of each FLASH BANK should be continuous and the difference should not be too large. The erase status flag is updated and written immediately after each FLASH BANK "background recycling" erase is completed.

[0032] The backup status flag is used to find and determine the valid FLASH BANK for the current backup: the data in the FLASH BANK with the smallest count value of the backup status flag is the valid simulated EEPROM data. Combined with the write status flag of the next FLASH BANK, it is determined whether the next FLASH BANK also contains valid simulated EEPROM data. During the system power-on initialization phase, the simulated EEPROM data can be restored from the currently used FLASH BANK. The backup status flag is updated and written when all valid data in the simulated EEPROM have completed the backup transfer operation.

[0033] The write status flag is used to determine whether the current FLASH BANK has been written to the simulated EEPROM data after the last "background recycling" erase. Combined with the backup status flag of the previous FLASH BANK, it can be determined whether the current FLASH BANK contains valid simulated EEPROM data. After the previous FLASH BANK is full, the write status flag is written with a valid value before enabling the new FLASH BANK to write simulated EEPROM data from the external host.

[0034] The transfer status flag is used to determine whether the current FLASH BANK has been subjected to the simulated EEPROM data backup transfer operation after the last "background recycling" erase, which can assist in determining the simulated EEPROM data backup status. After the previous FLASH BANK is full, the transfer status flag is written with a valid value before enabling the new FLASH BANK and performing the simulated EEPROM data backup transfer operation.

[0035] Exception management mechanism: During the system power-on initialization phase, when restoring the simulated EEPROM data from the FLASH BANK to the SRAM, the status flags of all FLASH BANKs and the backed-up simulated EEPROM data are first diagnosed, and if an abnormality is detected, it will be reported.

[0036] Since power failure during the writing process of FLASH may cause errors in the written data, the abnormalities can be divided into two categories: The first category is a minor abnormality (power failure abnormality): the status flag of FLASH BANK is detected during the power-on process or the simulated EEPROM data is detected. Power failure occurs during the writing process, resulting in abnormal status flags or simulated EEPROM data. This abnormality only loses the data of the last simulated EEPROM write operation, and the remaining data can still be recovered. The second category is a serious abnormality: the status flag of FLASH BANK or the simulated EEPROM data is detected during the power-on process. There is a situation that does not comply with the system's established standard process control logic. This type of abnormality indicates that the simulated EEPROM data is no longer trustworthy or the simulated EEPROM function is abnormal and unavailable.

[0037] In one embodiment, when the simulated EEPROM controller performs diagnosis and abnormality management, if a minor abnormality is detected, the simulated EEPROM controller performs an emergency recovery operation or an emergency backup operation based on the abnormality diagnosis based on the status flag. The minor abnormality is the situation that the status flag of the simulated EEPROM data block is detected during the system power-on process or the power is lost during the writing process of the simulated EEPROM data, resulting in the abnormality of the status flag or the simulated EEPROM data.

[0038] Specifically, if a minor abnormality is detected, the analog EEPROM controller will perform the following operations based on the specific diagnosis: (1) "Emergency recovery" operation: Perform an "emergency recovery" erase operation on the FLASH BANK whose erase status flag is diagnosed as abnormal. (2) "Emergency backup" operation: Restore the analog EEPROM data from the FLASH BANK to the SRAM, erase all other FLASH BANKs that do not store valid analog EEPROM data, and urgently backup the analog EEPROM data from the SRAM to the new FLASH BANK. After the emergency backup transfer of all analog EEPROM data is completed, it can be put back into use.

[0039] In one embodiment, when the simulated EEPROM controller performs diagnosis and abnormality management, if a serious abnormality is detected, the simulated EEPROM controller reports the diagnostic information corresponding to the serious abnormality. The serious abnormality is the detection of the status flag of the simulated EEPROM data block during the system power-on process or the presence of simulated EEPROM data that does not conform to the standard process control logic of the system.

[0040] It can be understood that if a serious abnormality is detected, the simulated EEPROM controller reports diagnostic information corresponding to the serious abnormality.

[0041] In one embodiment, when the simulated EEPROM controller performs diagnosis and exception management, if there are two or more simulated EEPROM data blocks with abnormal erase status, a serious exception is reported. If there is only one simulated EEPROM data block with abnormal erase status and the count value of the erase status flag of the adjacent previous simulated EEPROM data block is not the minimum value, a serious exception is reported. If there is only one simulated EEPROM data block with abnormal erase status and the count value of the erase status flag of the adjacent previous simulated EEPROM data block is the minimum value, a power-off exception is reported and an emergency recovery operation is performed on the simulated EEPROM data block with abnormal erase status. If there is no simulated EEPROM data block with abnormal erase status or there is only one simulated EEPROM data block with abnormal erase status, and the difference between the maximum and minimum count values ​​of the erase status flag of all valid simulated EEPROM data blocks is greater than or equal to the set value, a serious exception is reported. Among them, for example Figure 2 In the example shown, when four FLASH BANKs are used, the set value may be 4, that is, the set value may be selected as the number of FLASH BANKs used.

[0042] Understandably, Figure 2 Taking the system structure of the four FLASH BANKs shown in the figure as an example, the specific diagnostic content of the exception management mechanism is introduced: The abnormal diagnosis process of the erase status flag includes: (1) If there are two or more FLASH BANKs with abnormal erase status, a serious abnormality is reported. (2) If there is only one FLASH BANK with abnormal erase status and the count value of the erase status flag of the previous FLASH BANK is not the minimum value, a serious abnormality is reported. (3) If there is only one FLASH BANK with abnormal erase status and the count value of the erase status flag of the previous FLASH BANK is the minimum value, a power-off abnormality is reported and an "emergency recovery" operation is performed. (4) If there is no FLASH BANK with abnormal erase status or only one FLASH BANK with abnormal erase status, and the difference between the maximum and minimum count values ​​of the erase status flag of all valid FLASH BANKs (i.e., FLASH BANKs with no abnormal erase status) is greater than or equal to 4, a serious abnormality is reported. (5) If there is no abnormality as mentioned above, it is normal.

[0043] In one embodiment, when the simulated EEPROM controller performs diagnosis and abnormal management, if it is detected that the backup status of no simulated EEPROM data block is valid among all simulated EEPROM data blocks, a serious abnormality is reported. If the backup status of 3 or more simulated EEPROM data blocks is abnormal, a serious abnormality is reported. If the backup status of 2 simulated EEPROM data blocks is abnormal, and the backup status of the previous simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag is abnormal, a serious abnormality is reported. If the backup status of 2 simulated EEPROM data blocks is abnormal, and the backup status of the previous simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag is valid, a power-off abnormality is reported and an emergency backup operation is performed. If the backup status of only 1 simulated EEPROM data block is abnormal, and the simulated EEPROM data block with the abnormal backup status is not the previous simulated EEPROM data block or the next simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag, a serious abnormality is reported. If there is only one simulated EEPROM data block with abnormal backup status, and the simulated EEPROM data block with abnormal backup status is the previous simulated EEPROM data block or the next simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag, a power failure exception is reported and an "emergency backup" operation is performed. If the write status flag or transfer status flag of the simulated EEPROM data block with the minimum count value of the current backup status flag is invalid, a serious exception is reported.

[0044] Specifically, the abnormal diagnosis process of the backup status flag includes: (1) If the backup status of no FLASH BANK is valid, a serious abnormality is reported. (2) If the backup status of three or more FLASH BANKs is abnormal, a serious abnormality is reported. (3) If the backup status of two FLASH BANKs is abnormal and the backup status of the previous FLASH BANK of the FLASH BANK with the minimum count value of the current backup status flag is abnormal, a serious abnormality is reported. (4) If the backup status of two FLASH BANKs is abnormal and the backup status of the previous FLASH BANK of the FLASH BANK with the minimum count value of the current backup status flag is valid, a power failure abnormality is reported and an "emergency backup" operation is performed. (5) If the backup status of only one FLASH BANK is abnormal, and the FLASH BANK is not the previous FLASH BANK or the next FLASH BANK of the FLASH BANK with the minimum count value of the current backup status flag, a serious abnormality is reported. (6) If there is only one FLASH BANK with abnormal backup status, and the FLASH BANK is the previous FLASH BANK or the next FLASH BANK of the FLASH BANK with the minimum count value of the current backup status flag, a power failure abnormality is reported and an "emergency backup" operation is performed. (7) If the write status flag or transfer status flag of the FLASH BANK with the minimum count value of the current backup status flag is invalid, a serious abnormality is reported. (8) If there is no abnormality as mentioned above, it is normal.

[0045] In one embodiment, when determining that the simulated EEPROM data block whose count value of the current backup status flag is the minimum value is a valid backup simulated EEPROM data block, if the current valid backup simulated EEPROM data block is not full, the simulated EEPROM controller performs data recovery and inspection from the current valid backup simulated EEPROM data block. If the current valid backup simulated EEPROM data block is full, and the write status flag or transfer status flag of the next simulated EEPROM data block is not the default value after the erase operation, the simulated EEPROM controller reports a power failure exception and performs an emergency backup operation. If the current valid backup simulated EEPROM data block is full, and the write status flag of the next simulated EEPROM data block is the default value after the erase operation, the simulated EEPROM controller performs data recovery and inspection from the current valid backup simulated EEPROM data block. During the simulated EEPROM data recovery process, the simulated EEPROM controller traverses all data spaces of the valid backup simulated EEPROM data block and checks the data validity status. If there is an abnormality in the data of only the last valid address, the simulated EEPROM controller reports a power-off abnormality and performs an emergency backup operation. If there is an abnormality in the data of a non-last valid address, the simulated EEPROM controller reports a serious abnormality.

[0046] Specifically, when it is determined that the FLASH BANK whose count value of the current backup status flag is the minimum value is the valid backup FLASH BANK, the process of diagnosing the simulated EEPROM data backed up and saved by it includes: (1) If the current valid backup FLASH BANK is not full, it is only necessary to recover and check the data from the current valid backup FLASH BANK. (2) If the current valid backup FLASH BANK is full, and the write status flag or transfer status flag of the next FLASH BANK is the default value after the non-erase operation (binary all 1), it indicates that the next FLASH BANK may have an abnormal power failure during the simulated EEPROM data backup and transfer process. At this time, the valid backup FLASH BANK includes the next FLASH BANK, and the simulated EEPROM controller needs to report the power failure abnormality and perform an "emergency backup" operation. (3) If the current valid backup FLASH BANK is full, and the write status flag of the next FLASH BANK is the default value after the erase operation (binary all 1), it is only necessary to recover and check the data from the current valid backup FLASH BANK. (4) During the simulated EEPROM data recovery process, all data spaces of the valid backup FLASH BANK are traversed and the data validity status is checked. If there is a data abnormality only in the last valid address (the data of subsequent addresses are all default values ​​after the erase operation (binary all 1)), the simulated EEPROM controller reports a power-off abnormality and performs an "emergency backup" operation; if there is a data abnormality in a non-last valid address, the simulated EEPROM controller reports a serious abnormality.

[0047] like Figure 5 The figure shows the workflow of the data storage system using FLASH to simulate EEPROM. The improved design has passed a large number of EDA (Electronic Design Automation) tool simulation verifications and FPGA prototype verifications. The simulation verification results are consistent with the design expectations. Compared with the traditional hardware implementation method, it has greatly amortized the performance loss caused by the "page turning" phenomenon, and is almost imperceptible to the "page turning" phenomenon. It has greatly reduced the low resource utilization caused by the frequent "page turning" phenomenon when the effective data volume of the simulated EEPROM increases.

[0048] In one embodiment, a data storage management method using FLASH to simulate EEPROM is provided, which is applied to the above-mentioned data storage system using FLASH to simulate EEPROM, such as Figure 6 As shown, the data storage management method using FLASH to simulate EEPROM may include the following steps S10 to S16: S10, when the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, and when there is no simulated EEPROM write operation request initiated by the external host, the simulated EEPROM controller executes the backup transfer operation of continuously reading the simulated EEPROM data from the SRAM one by one and writing them into the storage space of the empty simulated EEPROM data block in the FLASH storage body; S12, when the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, when there is a simulated EEPROM write operation request initiated by the external host, the simulated EEPROM controller alternately executes the write operation and the backup transfer operation corresponding to the simulated EEPROM write operation request initiated by the external host; S14, performing background recycling of simulated EEPROM data blocks that are fully written in the FLASH storage body and do not participate in the simulated EEPROM data writing or backup transfer operation through the simulated EEPROM controller; S16, performing diagnosis and abnormality management according to the status information of the simulated EEPROM data block and the backed-up simulated EEPROM data in the process of restoring the simulated EEPROM data from the simulated EEPROM data block to the SRAM during the system power-on initialization phase.

[0049] The data storage management method using FLASH to simulate EEPROM is deeply improved based on the existing hardware implementation method of similar FLASH to simulate EEPROM, and a digital circuit controller that realizes the function of simulating EEPROM is designed by using storage devices such as FLASH and SRAM, and the function of simulating EEPROM is realized by hardware method, and through improved data storage structure and more sophisticated digital circuit control method, such as introducing status information such as erase status flag bit, backup status flag bit, write status flag bit and transfer status flag bit, adopting "ping-pong operation" management to alternately execute internal backup transfer operation and write operation corresponding to external host, and designing "background recycling" management mechanism to perform background recycling on the simulated EEPROM data blocks that are already full in the FLASH storage body and have not participated in the simulated EEPROM data writing or backup transfer operation, and at the same time introducing an exception management mechanism to perform diagnosis and exception management according to the status information of the simulated EEPROM data block and the backup simulated EEPROM data in the process of restoring the simulated EEPROM data from the simulated EEPROM data block to SRAM in the system power-on initialization phase, thereby greatly reducing the performance loss of the hardware implementation of FLASH to simulate EEPROM and effectively improving the utilization rate of storage resources.

[0050] For specific limitations on the data storage management method using FLASH to simulate EEPROM, please refer to the corresponding limitations on the data storage system using FLASH to simulate EEPROM mentioned above, which will not be repeated here.

[0051] It should be understood that although Figure 6 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 6 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0052] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by hardware implementation methods such as digital integrated circuit design or FPGA digital circuit design. When the digital integrated circuit is working, the processes including the embodiments of the above-mentioned methods can be implemented. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0053] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A data storage system using FLASH to simulate EEPROM, characterized in that: Includes emulated EEPROM controller, SRAM and FLASH memory; The capacity of each simulated EEPROM data block in the FLASH storage body is greater than the target simulated EEPROM capacity, and the data structure of each simulated EEPROM data block includes a first type of address bit and a second type of address bit, wherein the first type of address bit is used to store the status information of the simulated EEPROM data block, including an erase status flag bit, a backup status flag bit, a write status flag bit and a transfer status flag bit, and the second type of address bit is used to store simulated EEPROM data, simulated EEPROM data address and data validity status; When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, the simulated EEPROM controller performs a backup transfer operation of continuously reading the simulated EEPROM data from the SRAM one by one and writing the simulated EEPROM data into the storage space of the empty simulated EEPROM data block in the FLASH storage body when there is no simulated EEPROM write operation request initiated by the external host, and when there is a simulated EEPROM write operation request initiated by the external host, the write operation corresponding to the simulated EEPROM write operation request initiated by the external host and the backup transfer operation are performed alternately; The simulated EEPROM controller is also used to perform background recovery of simulated EEPROM data blocks that have been fully written in the FLASH storage body and have not participated in the simulated EEPROM data writing or backup transfer operation. The simulated EEPROM controller performs diagnosis and abnormality management based on the status information of the simulated EEPROM data blocks and the backed-up simulated EEPROM data during the system power-on initialization phase when restoring the simulated EEPROM data from the simulated EEPROM data blocks to the SRAM.

2. The data storage system using FLASH to simulate EEPROM according to claim 1, characterized in that: The values ​​of the erase state flag and the backup state flag both include specific valid values, and a count value that is initially all 1 and decreases with each update, and the values ​​of the write state flag and the transfer state flag both include specific valid values; The erase status flag is used to detect whether the erase status of the simulated EEPROM data block is legal, and the value of the erase status flag is updated and written by the simulated EEPROM controller immediately after each background recovery and erasure of the simulated EEPROM data block; The backup status flag is used to find and determine the simulated EEPROM data block to which the current backup is valid, and the value of the backup status flag is updated and written by the simulated EEPROM controller when the backup transfer operation of the valid simulated EEPROM data is completed on the simulated EEPROM data block to which it belongs; The write status flag is used to determine whether the current simulated EEPROM data block has been subjected to a simulated EEPROM data write operation after the last background recovery and erasure. The value of the write status flag is written by the simulated EEPROM controller after the last simulated EEPROM data block is full and before a new simulated EEPROM data block is enabled to perform a simulated EEPROM data write operation of an external host. The transfer status flag is used to determine whether the current simulated EEPROM data block has performed a backup transfer operation of the simulated EEPROM data after the last background recovery and erasure. The value of the transfer status flag is written by the simulated EEPROM controller after the previous simulated EEPROM data block is full and before a new simulated EEPROM data block is enabled and a backup transfer operation of the simulated EEPROM data is performed.

3. The data storage system using FLASH to simulate EEPROM according to claim 1 or 2, characterized in that: When the simulated EEPROM controller performs diagnosis and abnormality management, if a slight abnormality is detected, the simulated EEPROM controller performs an emergency recovery operation or an emergency backup operation according to the abnormality diagnosis based on the status flag bit; The minor abnormality is a situation where a status flag of a simulated EEPROM data block is detected during system power-on or a power failure occurs during writing of simulated EEPROM data, resulting in abnormality of the status flag or simulated EEPROM data.

4. The data storage system using FLASH to simulate EEPROM according to claim 3, characterized in that: When the simulated EEPROM controller performs diagnosis and abnormality management, if a serious abnormality is detected, the simulated EEPROM controller reports diagnostic information corresponding to the serious abnormality; The serious anomaly is when the status flag of the simulated EEPROM data block is detected during the system power-on process or the simulated EEPROM data does not conform to the standard process control logic of the system.

5. The data storage system using FLASH to simulate EEPROM according to claim 4, characterized in that: When the simulated EEPROM controller performs diagnosis and abnormal management, if there are two or more simulated EEPROM data blocks with abnormal erase status, a serious abnormality is reported; If only one simulated EEPROM data block has an abnormal erase status and the count value of the erase status flag bit of the adjacent previous simulated EEPROM data block is not the minimum value, a serious abnormality is reported; If there is only one simulated EEPROM data block with an abnormal erase status and the count value of the erase status flag bit of the adjacent previous simulated EEPROM data block is the minimum value, then the power failure abnormality is reported and the simulated EEPROM data block with the abnormal erase status is urgently recovered; If there is no erase status abnormality in the simulated EEPROM data block or there is only one erase status abnormality in the simulated EEPROM data block, and the difference between the maximum and minimum count values ​​of the erase status flag bits of all valid simulated EEPROM data blocks is greater than or equal to the set value, a serious abnormality is reported.

6. The data storage system using FLASH to simulate EEPROM according to claim 4, characterized in that: When the simulated EEPROM controller performs diagnosis and abnormality management, if it is detected that the backup status of no simulated EEPROM data block in all simulated EEPROM data blocks is valid, a serious abnormality is reported; If the backup status of three or more simulated EEPROM data blocks is abnormal, a serious abnormality is reported; If the backup status of two simulated EEPROM data blocks is abnormal, and the backup status of the previous simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag is abnormal, a serious abnormality is reported; If the backup status of two simulated EEPROM data blocks is abnormal, and the backup status of the previous simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag is valid, then report the power failure abnormality and perform emergency backup operation; If there is only one simulated EEPROM data block with abnormal backup status, and the simulated EEPROM data block with abnormal backup status is not the previous simulated EEPROM data block or the next simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag bit, a serious exception is reported; If there is only one simulated EEPROM data block with abnormal backup status, and the simulated EEPROM data block with abnormal backup status is the previous simulated EEPROM data block or the next simulated EEPROM data block of the simulated EEPROM data block with the minimum count value of the current backup status flag, then report the power failure exception and perform the "emergency backup" operation; If the count value of the current backup status flag is the minimum value and the write status flag or transfer status flag of the simulated EEPROM data block is invalid, a serious exception is reported.

7. The data storage system using FLASH to emulate EEPROM according to claim 4, characterized in that: When determining that the simulated EEPROM data block whose count value of the current backup status flag is the minimum value is a valid backup simulated EEPROM data block, if the current valid backup simulated EEPROM data block is not full, the simulated EEPROM controller performs data recovery and inspection from the current valid backup simulated EEPROM data block; If the current valid backup simulated EEPROM data block is full, and the write status flag or transfer status flag of the next simulated EEPROM data block is not the default value after the erase operation, the simulated EEPROM controller reports a power failure exception and performs an emergency backup operation; If the current valid backup simulated EEPROM data block is full, and the write status flag of the next simulated EEPROM data block is the default value after the erase operation, the simulated EEPROM controller performs data recovery and inspection from the current valid backup simulated EEPROM data block; During the simulated EEPROM data recovery process, the simulated EEPROM controller traverses all data spaces of the valid backup simulated EEPROM data block and checks the data validity status. If there is a phenomenon that only the last valid address data is abnormal, the simulated EEPROM controller reports a power-off abnormality and performs an emergency backup operation. If there is a phenomenon that the data is not abnormal at the last valid address, the simulated EEPROM controller reports a serious abnormality.

8. The data storage system using FLASH to emulate EEPROM according to claim 3, characterized in that: The first type of address bits are the first 4 address bits of the simulated EEPROM data block.

9. The data storage system using FLASH to emulate EEPROM according to claim 3, characterized in that: The data bit width of the simulated EEPROM data block in each of the FLASH storage bodies is at least greater than the sum of the simulated EEPROM address bit width, data bit width and data valid status information bit width.

10. A data storage management method using FLASH to simulate EEPROM, characterized in that: Applicable to the data storage system using FLASH to simulate EEPROM as described in any one of claims 1 to 9, the data storage management method using FLASH to simulate EEPROM comprises the steps of: When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, when there is no simulated EEPROM write operation request initiated by the external host, the simulated EEPROM controller executes the backup transfer operation of continuously reading the simulated EEPROM data from the SRAM one by one and then writing it into the storage space of the empty simulated EEPROM data block in the FLASH storage body; When the data space of the simulated EEPROM data block in the current FLASH storage body is full and the backup transfer operation of the next simulated EEPROM data block is not completed, when there is a simulated EEPROM write operation request initiated by an external host, the simulated EEPROM controller alternately executes the write operation corresponding to the simulated EEPROM write operation request initiated by the external host and the backup transfer operation; The simulated EEPROM controller performs background recycling of simulated EEPROM data blocks that are fully written in the FLASH storage body and do not participate in the simulated EEPROM data writing or backup transfer operation; In the process of restoring the simulated EEPROM data from the simulated EEPROM data block to the SRAM during the system power-on initialization phase, diagnosis and abnormality management are performed based on the status information of the simulated EEPROM data block and the backed-up simulated EEPROM data.

Images