A multi-level task synchronization method based on processor three-level cache distribution and related device

Abstract

The application provides a multi-level task synchronization method based on a processor three-level cache distribution and related devices, including determining cores in each three-level cache of a processor which need to perform task synchronization and three-level caches which need to perform task synchronization; initializing a first-level synchronizer and a second-level synchronizer according to the number of cores which need to perform task synchronization and the number of three-level caches; performing task synchronization between cores and three-level caches by using the first-level synchronizer and the second-level synchronizer respectively, until all three-level caches which need to perform task synchronization are synchronized, and then the cores in each three-level cache are synchronized. The application significantly improves the synchronization efficiency between multiple cores and the system performance by optimizing the hierarchy of the three-level cache of the processor and task allocation. By using the multi-level synchronizer mechanism, the application effectively reduces the synchronization delay and resource consumption, and improves the stability and reliability of the system.

Description

Technical Field

[0001] This invention belongs to the field of inter-core synchronization technology for multi-core processors, specifically relating to a multi-level task synchronization method and related apparatus based on the distribution of the processor's three-level cache. Background Technology

[0002] Electromagnetic transient simulation is a complex computational process, especially when dealing with large-scale power grid models, requiring extremely high computing and data processing capabilities. To meet this demand, large power grid models are typically split into multiple sub-networks, with each sub-network handled by one or more processor cores for simulation calculations. However, this splitting approach also introduces challenges related to task synchronization and data consistency.

[0003] In multi-core simulation operations, each processor core is responsible for processing different subnets, but these subnets need to maintain data consistency and synchronization. Especially in electromagnetic transient simulations, the interaction and synchronization between subnets are crucial to ensuring the accuracy of simulation results. Therefore, how to efficiently achieve task synchronization between multiple cores has become an urgent problem to be solved.

[0004] In processor architectures with multiple L3 caches, task synchronization mechanisms face cache coherence operations triggered by cross-L3 cache data sharing reads and writes. This can indeed lead to significant performance degradation, especially for complex applications requiring high-efficiency electromagnetic transient simulations. To address this challenge, in addition to traditional synchronization primitives such as mutexes and reader-writer locks, a more efficient task synchronization mechanism is needed to meet the requirements of applications like electromagnetic transient simulations. Summary of the Invention

[0005] In view of this, the present invention provides a multi-level task synchronization method and related apparatus based on the distribution of the processor's three-level cache, aiming to achieve efficient synchronization between multiple cores by optimizing task allocation and cache management by utilizing the hierarchical structure and distribution characteristics of the processor's three-level cache.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0007] In a first aspect, the present invention provides a multi-level task synchronization method based on the distribution of a processor's three-level cache, comprising the following steps:

[0008] Identify the cores in each L3 cache of the processor that require task synchronization and the L3 caches that require task synchronization;

[0009] Initialize the first-level synchronizer and the second-level synchronizer according to the number of cores and the number of L3 caches required for task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the L3 cache, respectively.

[0010] The first-level synchronizer and the second-level synchronizer are used to synchronize tasks between cores and between L3 caches, respectively, until all L3 caches that need to be synchronized have been synchronized, and then the cores in each L3 cache are synchronized.

[0011] Furthermore, each core within the processor's L3 cache is a L1 communication domain, and all L3 caches are L2 communication domains;

[0012] After identifying the cores in each L3 cache of the processor that require task synchronization and the L3 caches that require task synchronization, the following steps are also included:

[0013] Each core in the primary communication domain that needs to synchronize tasks holds a primary synchronizer corresponding to its corresponding level 3 cache;

[0014] Each level 3 cache that needs to synchronize tasks in the level 2 communication domain holds a global level 2 synchronizer.

[0015] Furthermore, task synchronization is performed between cores and between the L3 cache using both Level 1 and Level 2 synchronizers, including:

[0016] The task synchronization between the three-level buffers is initiated in the second-level communication domain using a second-level synchronizer;

[0017] Synchronization between the three-level caches is repeated as needed based on the number of tasks to be synchronized in the two-level communication domain, until the synchronization task in the two-level communication domain is completed.

[0018] Inter-core task synchronization is performed in the primary communication domain using a primary synchronizer;

[0019] Inter-core task synchronization is repeated as needed based on the number of cores required for task synchronization and the number of synchronizations within the primary communication domain, until the synchronization task within the primary communication domain is completed.

[0020] Furthermore, both the primary synchronizer and the secondary synchronizer include: the expected number of synchronizations, a synchronization counter, and a higher-level synchronizer;

[0021] In the first-level synchronizer, the expected number of synchronizations is the number of cores in the corresponding third-level cache that need to be synchronized. The initial value of the synchronization counter is the expected number of synchronizations, and the value of the synchronization counter is decremented by 1 for each synchronization. The upper-level synchronizer is the second-level synchronizer.

[0022] In the secondary synchronizer, the expected number of synchronizations is the number of all the tertiary buffers that need to be synchronized for tasks. The initial count of the synchronization counter is the expected number of synchronizations, and the parent synchronizer is empty.

[0023] Furthermore, a secondary synchronizer is used to synchronize tasks across the tertiary caches until all tertiary caches requiring task synchronization have been synchronized, including:

[0024] Each secondary synchronizer performs a synchronization once and obtains the decremented synchronization counter value;

[0025] Determine whether the value of the synchronous counter after decrementing is equal to zero;

[0026] If the value is zero, then perform the following steps:

[0027] Set the synchronization counter value to the expected number of synchronizations;

[0028] If it is not equal to zero, then perform the following steps:

[0029] Busy waiting for the set time;

[0030] Determine if the synchronization counter value is equal to the expected number of synchronizations;

[0031] If not, then use the secondary synchronizer to continue synchronization until the synchronization counter value equals zero;

[0032] If so, then end synchronization and return to the first set synchronization status code.

[0033] Furthermore, a primary synchronizer is used to synchronize tasks between cores until all cores requiring task synchronization have completed synchronization, including:

[0034] Each primary synchronizer performs a synchronization once and obtains the decremented synchronization counter value;

[0035] Determine whether the value of the synchronous counter after decrementing is equal to zero;

[0036] If the value is zero, then perform the following steps:

[0037] Waiting for the secondary synchronizer to complete synchronization;

[0038] Set the synchronization counter value to the expected number of synchronizations, end synchronization and return to the second set synchronization status code;

[0039] If it is not equal to zero, then perform the following steps:

[0040] Busy waiting for the set time;

[0041] Determine if the synchronization counter value is equal to the expected number of synchronizations;

[0042] If not, then synchronization will continue using a secondary synchronizer;

[0043] If so, then end synchronization and return to the first set synchronization status code.

[0044] Furthermore, the synchronous counter uses an atomic decrement operation to reduce its value.

[0045] Secondly, the present invention provides a multi-level task synchronization device based on the distribution of a processor's three-level cache, comprising:

[0046] The synchronization acquisition module is used to determine the cores and L3 caches in each L3 cache of the processor that need to be synchronized.

[0047] The initialization module is used to initialize the first-level synchronizer and the second-level synchronizer according to the number of cores and the number of L3 caches required for task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the L3 cache, respectively.

[0048] The synchronization execution module is used to perform task synchronization between cores and between L3 caches using the first-level synchronizer and the second-level synchronizer respectively. After all L3 caches that need task synchronization have been synchronized, the cores in each L3 cache will then complete the synchronization.

[0049] Thirdly, the present invention provides a computer device, the device including a processor and a memory:

[0050] The memory is used to store computer programs and send the instructions of the computer programs to the processor;

[0051] The processor executes a multi-level task synchronization method based on the processor's three-level cache distribution, as described in the first aspect, according to the instructions of the computer program.

[0052] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements a multi-level task synchronization method based on the processor's three-level cache distribution as described in the first aspect.

[0053] In summary, this invention provides a multi-level task synchronization method and related apparatus based on the distribution of a processor's L3 cache. The method includes determining the cores requiring task synchronization and the L3 caches themselves in each L3 cache of the processor; initializing a Level 1 synchronizer and a Level 2 synchronizer according to the number of cores and L3 caches requiring task synchronization, respectively; using the Level 1 and Level 2 synchronizers to perform task synchronization between cores and L3 caches; and using the Level 1 and Level 2 synchronizers to perform task synchronization between cores and between L3 caches until all L3 caches requiring task synchronization have been synchronized, after which the cores in each L3 cache complete their synchronization. This invention significantly improves the synchronization efficiency and system performance between multiple cores by optimizing the hierarchical structure and task allocation of the processor's L3 cache. Utilizing the multi-level synchronizer mechanism, this invention effectively reduces synchronization latency and resource consumption, improving system stability and reliability. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 A flowchart of a multi-level task synchronization method based on processor three-level cache distribution provided in an embodiment of the present invention;

[0056] Figure 2 This is a schematic diagram illustrating the relationship between the synchronization core and the three-level synchronization cache provided in an embodiment of the present invention.

[0057] Figure 3 This is a schematic diagram of synchronizer initialization provided in an embodiment of the present invention;

[0058] Figure 4 A flowchart illustrating the synchronization process performed by the synchronizer, provided in an embodiment of the present invention;

[0059] Figure 5 A block diagram of a multi-level task synchronization device based on the distribution of a processor's three-level cache is provided in an embodiment of the present invention.

[0060] Figure 6 This is a block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0061] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0062] Please see Figure 1 This invention provides a multi-level task synchronization method based on the distribution of the processor's three-level cache, comprising the following steps:

[0063] S11: Determine the cores and L3 caches in each L3 cache of the processor that require task synchronization.

[0064] It should be noted that the Level 3 cache (L3 cache) is a type of processor cache located between the CPU and main memory. It is used to store frequently accessed data to reduce the number of times the processor accesses main memory and improve data processing speed.

[0065] A core is an independent processing unit in the L3 cache of a multi-core processor, capable of executing tasks independently.

[0066] This step aims to identify all cores and L3 caches in the processor that require task synchronization. For each set of cores corresponding to each L3 cache, the number of cores requiring task synchronization is analyzed and determined. Subsequently, based on these analysis results, the total number of L3 caches requiring task synchronization in the entire system is calculated. This reduces unnecessary synchronization operations and improves efficiency.

[0067] Please see Figure 2 , Figure 2 The relationship between the synchronous cores and the synchronous L3 cache is shown. The number of synchronous cores for the different L3 caches is 3, 4, and 0, indicating that the total number of synchronous L3 caches is 2.

[0068] S12: Initialize the first-level synchronizer and the second-level synchronizer according to the number of cores and the number of L3 caches required for task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and L3 caches, respectively.

[0069] It should be noted that the Level 1 synchronizer is used for inter-core synchronization, ensuring that multiple cores can coordinate and remain consistent when executing tasks. The Level 2 synchronizer is used for synchronization between Level 3 caches, ensuring data consistency across different cache regions.

[0070] This step configures the Level 1 and Level 2 synchronizers based on the number of cores and L3 caches required for synchronization. The Level 1 synchronizer handles synchronization between cores, while the Level 2 synchronizer handles synchronization between L3 caches. This design allows the system to be optimized at different levels to accommodate varying synchronization needs.

[0071] S13: Use the first-level synchronizer and the second-level synchronizer to perform task synchronization between cores and between the third-level caches respectively, until all the third-level caches that need to be synchronized have been synchronized, and then the cores in each third-level cache will be synchronized.

[0072] It's important to note that this step uses a Level 1 synchronizer to ensure synchronization between cores and a Level 2 synchronizer to ensure synchronization between Level 3 caches. This process continues until all Level 3 caches that need synchronization have been synchronized. Once the caches are synchronized, the cores within each Level 3 cache then complete their own synchronization.

[0073] This step implements a hierarchical synchronization strategy, which first performs synchronization at the cache level and then at the kernel level. This hierarchical synchronization strategy reduces direct communication between kernels, lowers synchronization latency, and ensures data consistency and system stability.

[0074] This embodiment provides a multi-level task synchronization method based on the processor's three-level cache distribution. This method proposes a multi-level synchronizer mechanism to reduce synchronization latency and resource consumption. The multi-level synchronizer includes a first-level synchronizer and a second-level synchronizer, which are responsible for synchronization between cores and between the three-level cache, respectively. The introduction of this mechanism allows synchronization operations to be performed at different levels, thereby improving synchronization efficiency.

[0075] The coordinated operation of the Level 1 and Level 2 synchronizers is key to achieving efficient synchronization. The Level 1 synchronizer ensures synchronization between cores, while the Level 2 synchronizer ensures synchronization between Level 3 caches. This hierarchical synchronization strategy allows the system to synchronize at the cache level first, reducing direct communication between cores and lowering synchronization latency. Once cache-level synchronization is complete, core-level synchronization follows, ensuring that every core in the Level 3 cache is synchronized.

[0076] Through the aforementioned optimizations and multi-level synchronizer mechanism, the method proposed in this embodiment significantly improves the synchronization efficiency between multiple cores. This improved synchronization efficiency directly leads to enhanced system performance, as synchronization operations are one of the key bottlenecks in multi-core processors. By reducing synchronization latency and resource consumption, the system can perform multitasking more efficiently, thereby improving overall system performance and reliability.

[0077] In one embodiment, the cores within each L3 cache of the processor constitute a L1 communication domain, and all L3 caches constitute a L2 communication domain; after determining the cores in each L3 cache of the processor that require task synchronization and the L3 caches that require task synchronization, the method further includes:

[0078] Each core in the primary communication domain that needs to synchronize tasks holds a primary synchronizer corresponding to its corresponding level 3 cache;

[0079] Each level 3 cache that needs to synchronize tasks in the level 2 communication domain holds a global level 2 synchronizer.

[0080] In this embodiment, each core within a L3 cache is defined as a Level 1 communication domain, and all cores within the same L3 cache need to communicate and synchronize with each other. All L3 caches are defined as Level 2 communication domains, and different L3 caches need to communicate and synchronize with each other.

[0081] Each core that needs to synchronize tasks will hold a Level 1 synchronizer corresponding to its Level 3 cache. That is, within a Level 3 cache, if two cores need to synchronize, then each of these two cores will hold a Level 1 synchronizer for synchronization between them.

[0082] Each L3 cache that needs to be synchronized will hold a global L2 synchronizer. That is, if there are three L3 caches that need to be synchronized, then each of these three L3 caches will hold a L2 synchronizer for synchronization between them.

[0083] Within the Level 1 communication domain, i.e., within each Level 3 cache, the cores holding the Level 1 synchronizer will use these synchronizers to coordinate task synchronization among them. This ensures that cores within the same Level 3 cache can execute tasks consistently. Within the Level 2 communication domain, i.e., among all Level 3 caches, the Level 3 caches holding the global Level 2 synchronizer will use these synchronizers to coordinate task synchronization among them. This ensures data consistency and task coordination between different Level 3 caches.

[0084] This embodiment defines communication domains at different levels. Cores within the same L3 cache are grouped into a L1 communication domain, improving synchronization efficiency within the L1 domain. L3 caches are grouped into L2 communication domains as objects, thereby reducing the number of synchronization operations across L3 caches. Furthermore, a dedicated synchronizer is allocated to each core and L3 cache requiring synchronization, achieving high efficiency and stability in task synchronization across multi-core processors.

[0085] Based on the communication domain settings in the above embodiments, in a further embodiment, task synchronization is performed between cores and between the L3 cache using a primary synchronizer and a secondary synchronizer, respectively, including:

[0086] S21: Use the secondary synchronizer to begin task synchronization between the three-level buffers in the secondary communication domain.

[0087] S22: Repeat the synchronization between the three-level caches as needed and the synchronization in the second-level communication domain until the synchronization task in the second-level communication domain is completed.

[0088] S23: Use a primary synchronizer to perform inter-core task synchronization in the primary communication domain;

[0089] S24: Repeat the inter-core task synchronization as needed based on the number of cores required for task synchronization and the number of synchronizations in the primary communication domain, until the synchronization task in the primary communication domain is completed.

[0090] This embodiment achieves synchronization operations at different levels by using a hierarchical first-level synchronizer and a second-level synchronizer. First, synchronization is performed between the three levels of cache to ensure data consistency across different cache regions. Then, synchronization is performed between cores to ensure data consistency across different cores within the same cache. This method not only improves synchronization efficiency but also ensures system stability and reliability, which has significant practical implications for parallel task processing in multi-core processors.

[0091] In one embodiment, both the primary synchronizer and the secondary synchronizer include: a desired number of synchronizations, a synchronization counter, and a parent synchronizer;

[0092] In the first-level synchronizer, the expected number of synchronizations is the number of cores in the corresponding third-level cache that need to be synchronized. The initial value of the synchronization counter is the expected number of synchronizations, and the value of the synchronization counter is decremented by 1 for each synchronization. The upper-level synchronizer is the second-level synchronizer.

[0093] In the secondary synchronizer, the expected number of synchronizations is the number of all the tertiary buffers that need to be synchronized for tasks. The initial count of the synchronization counter is the expected number of synchronizations, and the parent synchronizer is empty.

[0094] It should be noted that each synchronizer contains the expected number of synchronizations N, a synchronization counter C, and the previous synchronizer S.

[0095] like Figure 3 As shown, a global secondary synchronizer S2 is set up, and each tertiary cache holds the global secondary synchronizer S2. The expected synchronization quantity N of the secondary synchronizer S2 is the total number of tertiary caches that need to perform task synchronization in the entire system as determined in step S11. The synchronization counter C is equal to the expected synchronization quantity N, and the previous level synchronizer is set to empty.

[0096] Each L3 cache is equipped with a Level 1 synchronizer S1. Each core in the L3 cache holds its own Level 1 synchronizer S1. The number of synchronizations by Level 1 synchronizer S1 is the number of cores in the L3 cache that need to perform task synchronization as determined in step S11. The synchronization counter C is equal to the expected number of synchronizations N. The next level synchronizer is set as Level 2 synchronizer S2.

[0097] Based on the synchronizer design in the foregoing embodiments, a further embodiment proposes a synchronizer execution flow, which is as follows: Figure 4 As shown, it includes:

[0098] 1) When each synchronizer performs a synchronization, the synchronization counter C is decremented by 1 and the decremented counter value C' is obtained;

[0099] Whether it is a primary synchronizer or a secondary synchronizer, each synchronizer will perform a synchronization operation once, and atomically decrement the counter by 1 after the operation to obtain the updated synchronization counter value.

[0100] 2) Determine the value of C';

[0101] Check if the synchronization counter value is equal to zero to determine if all components that need to be synchronized (Level 3 cache or core) have been synchronized.

[0102] 3) If C' equals 0, it means that all synchronization cores have completed synchronization, and steps 5) and 6) are executed;

[0103] 4) If C' is not equal to 0, it means that some cores have not completed synchronization, and steps 7), 8), 9), and 10) are executed;

[0104] 5) If a parent synchronizer is set, then synchronization with the parent synchronizer needs to be performed until the parent synchronizer completes synchronization.

[0105] 6) Set counter C to the synchronization quantity N, end synchronization and return synchronization status code 1;

[0106] For a secondary synchronizer, the synchronization counter is reset to the expected synchronization count, synchronization ends, and a success status code is returned.

[0107] For a primary synchronizer, it is necessary to wait for its parent synchronizer (secondary synchronizer) to complete synchronization before resetting the synchronization counter to the expected synchronization count, ending the synchronization, and returning a success status code.

[0108] 7) Busy waiting for several microseconds;

[0109] 8) Determine the value of counter C;

[0110] 9) If the value of counter C is not equal to the number of synchronizations N, it means that a core has not completed synchronization. Repeat step 1).

[0111] 10) If the value of counter C is equal to the number of synchronizations N, it means that all cores have completed synchronization, the synchronization ends and the synchronization status code 0 is returned.

[0112] Both the primary synchronizer and the secondary synchronizer perform synchronization according to the above process.

[0113] This embodiment proposes a hierarchical synchronization mechanism, in which a first-level synchronizer is responsible for synchronization between cores, while a second-level synchronizer is responsible for synchronization between third-level caches. Each synchronizer performs a synchronization operation and determines whether synchronization is complete based on the value of a synchronization counter. If synchronization is not complete, busy waiting and repeated synchronization will be performed until all components are synchronized.

[0114] In one embodiment, the decrement operation of the synchronization counter is performed atomically by decrementing by 1, ensuring the security and consistency of synchronization operations in a multi-core environment.

[0115] Based on the same inventive concept, this application also provides a multi-level task synchronization device based on processor three-level cache distribution for implementing the multi-level task synchronization method based on processor three-level cache distribution described above. The solution provided by this device is similar to the implementation scheme described in the above method. Therefore, the specific limitations of the following embodiment of the multi-level task synchronization device based on processor three-level cache distribution can be found in the above-described limitations of the multi-level task synchronization method based on processor three-level cache distribution, and will not be repeated here.

[0116] Please see Figure 5 This invention also provides a multi-level task synchronization device based on the distribution of a processor's three-level cache, comprising:

[0117] The synchronization acquisition module is used to determine the cores and L3 caches in each L3 cache of the processor that need to be synchronized.

[0118] The initialization module is used to initialize the first-level synchronizer and the second-level synchronizer according to the number of cores and the number of L3 caches required for task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the L3 cache, respectively.

[0119] The synchronization execution module is used to perform task synchronization between cores and between L3 caches using the first-level synchronizer and the second-level synchronizer respectively. After all L3 caches that need task synchronization have been synchronized, the cores in each L3 cache will then complete the synchronization.

[0120] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0121] Reference Figure 6 The present invention also provides a computer device, including: a memory and a processor, and a computer program stored in the memory. When the computer program is executed on the processor, it implements a multi-level task synchronization method based on the processor's three-level cache distribution as described in any of the above methods.

[0122] The computer device may be a desktop computer, laptop, handheld computer, or cloud server, etc. This computer device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 6 The examples of computer devices are merely examples and do not constitute a limitation on computer devices. They may include more or fewer components than shown in the illustration, or combinations of certain components, or different components. For example, they may also include input / output devices, network access devices, etc.

[0123] The processor referred to can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0124] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard drive or RAM. In other embodiments, the memory may be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory may include both internal and external storage units of the computer device. The memory is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

[0125] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a multi-level task synchronization method based on the distribution of a processor's three-level cache as described in any of the above methods.

[0126] In this embodiment, if the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0127] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] In the embodiments disclosed in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0130] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-level task synchronization method based on processor three-level cache distribution, characterized in that, Includes the following steps: Identify the cores in each L3 cache of the processor that require task synchronization and the L3 caches that require task synchronization; The first-level synchronizer and the second-level synchronizer are initialized according to the number of cores and the number of L3 caches required for task synchronization. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization on the cores and the L3 cache, respectively. The first-level synchronizer and the second-level synchronizer are used to perform task synchronization between cores and between the third-level caches respectively. After all the third-level caches that need to be synchronized have been synchronized, the cores in each third-level cache are then synchronized. Each core within the processor's L3 cache is a L1 communication domain, and all L3 caches constitute a L2 communication domain. After identifying the cores in each L3 cache of the processor that require task synchronization and the L3 caches that require task synchronization, the following steps are also included: Each core in the primary communication domain that needs to perform task synchronization shall hold a primary synchronizer corresponding to its respective level 3 cache; Each of the three-level caches that needs to perform task synchronization in the two-level communication domain holds the global two-level synchronizer; Task synchronization is performed between cores and between the L3 cache using the primary synchronizer and the secondary synchronizer, respectively, including: The secondary synchronizer is used to initiate task synchronization between the three-level buffers in the secondary communication domain; The synchronization between the three-level caches is repeated as needed based on the number of tasks to be synchronized in the two-level communication domain, until the synchronization task in the two-level communication domain is completed. The primary synchronizer is used to perform inter-core task synchronization in the primary communication domain; Inter-core task synchronization is repeated as needed based on the number of cores required for task synchronization and the number of synchronizations in the primary communication domain, until the synchronization task in the primary communication domain is completed.

2. The multi-level task synchronization method based on processor three-level cache distribution according to claim 1, characterized in that, Both the primary synchronizer and the secondary synchronizer include: the expected number of synchronizations, a synchronization counter, and a parent synchronizer; In the first-level synchronizer, the expected synchronization quantity is the number of cores that need to be synchronized within the corresponding third-level cache. The initial value of the synchronization counter is the expected synchronization quantity, and the value of the synchronization counter is decremented by 1 for each synchronization. The upper-level synchronizer is the second-level synchronizer. In the secondary synchronizer, the expected synchronization quantity is the number of all tertiary caches that need to be synchronized for tasks, the initial count value of the synchronization counter is the expected synchronization quantity, and the parent synchronizer is empty.

3. The multi-level task synchronization method based on processor three-level cache distribution according to claim 2, characterized in that, The secondary synchronizer is used to synchronize tasks among the three-level caches until all the three-level caches that require task synchronization have been synchronized, including: Each of the secondary synchronizers performs a synchronization once and obtains the decremented synchronization counter value; Determine whether the value of the synchronous counter after the decrement is equal to zero; If the value is zero, then perform the following steps: Set the synchronization counter value to the expected number of synchronizations; If it is not equal to zero, then perform the following steps: Busy waiting for the set time; Determine whether the value of the synchronization counter is equal to the expected number of synchronizations; If not, then the synchronization will continue using the secondary synchronizer until the synchronization counter value equals zero; If so, then end synchronization and return to the first set synchronization status code.

4. The multi-level task synchronization method based on processor three-level cache distribution according to claim 3, characterized in that, The primary synchronizer is used to perform task synchronization between cores until all cores requiring task synchronization have completed synchronization, including: Each of the first-level synchronizers performs a synchronization once and obtains the decremented synchronization counter value; Determine whether the value of the synchronous counter after the decrement is equal to zero; If the value is zero, then perform the following steps: Wait for the secondary synchronizer to complete synchronization; Set the synchronization counter value to the expected synchronization quantity, end synchronization and return to the second set synchronization status code; If it is not equal to zero, then perform the following steps: Busy waiting for the set time; Determine whether the value of the synchronization counter is equal to the expected number of synchronizations; If not, then synchronization will continue using the secondary synchronizer; If so, then end synchronization and return to the first set synchronization status code.

5. The multi-level task synchronization method based on processor three-level cache distribution according to claim 2, characterized in that, The synchronous counter decrements its value using an atomic decrement operation.

6. A multi-level task synchronization device based on processor three-level cache distribution, characterized in that, include: The synchronization acquisition module is used to determine the cores and L3 caches in each L3 cache of the processor that need to be synchronized. An initialization module is used to initialize a first-level synchronizer and a second-level synchronizer respectively according to the number of cores and the number of L3 caches to be synchronized for tasks. The first-level synchronizer and the second-level synchronizer are used to synchronize tasks for the cores and the L3 cache respectively. The synchronization execution module is used to perform task synchronization between cores and between the level 3 cache using the first-level synchronizer and the second-level synchronizer respectively, until all the level 3 caches that need to be synchronized have been synchronized, and then the cores in each level 3 cache are synchronized. Each core within the processor's L3 cache is a L1 communication domain, and all L3 caches constitute a L2 communication domain. After identifying the cores in each L3 cache of the processor that require task synchronization and the L3 caches that require task synchronization, the following steps are also included: Each core in the primary communication domain that needs to perform task synchronization shall hold a primary synchronizer corresponding to its respective level 3 cache; Each of the three-level caches that needs to perform task synchronization in the two-level communication domain holds the global two-level synchronizer; Task synchronization is performed between cores and between the L3 cache using the primary synchronizer and the secondary synchronizer, respectively, including: The secondary synchronizer is used to initiate task synchronization between the three-level buffers in the secondary communication domain; The synchronization between the three-level caches is repeated as needed based on the number of tasks to be synchronized in the two-level communication domain, until the synchronization task in the two-level communication domain is completed. The primary synchronizer is used to perform inter-core task synchronization in the primary communication domain; Inter-core task synchronization is repeated as needed based on the number of cores required for task synchronization and the number of synchronizations in the primary communication domain, until the synchronization task in the primary communication domain is completed.

7. A computer device, characterized in that, The device includes a processor and a memory: The memory is used to store computer programs and send the instructions of the computer programs to the processor; The processor executes, according to the instructions of the computer program, a multi-level task synchronization method based on the processor's three-level cache distribution as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements a multi-level task synchronization method based on the distribution of a processor's three-level cache as described in any one of claims 1-5.

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