Data processing method, device, computer equipment and storage medium

Abstract

The present application relates to a data processing method, device, computer equipment, storage medium and computer program product. The method includes: obtaining the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determining the transmission strategy; obtaining the data of the source address, and according to the transmission strategy, transmitting the data of the source address to different target addresses of the memory in sequence; when the remaining data volume of the source address is less than the data volume of each transmission, transmitting the remaining data to the target address, obtaining the data of the next source address, transmitting the data of the next source address to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address meets the data volume of each transmission; and using the transmission strategy, transmitting the remaining data of the next source address in sequence. The use of this method can improve data processing and access efficiency.

Description

Technical Field

[0001] The present application relates to the field of neural network technology, and in particular to a data processing method, apparatus, computer equipment, storage medium and computer program product. Background Art

[0002] With the development of machine learning, the importance of neural networks in various fields continues to rise. However, although neural networks have shown great potential in computing power, their computing units themselves do not have data storage capabilities. This makes neural networks more dependent on data storage when performing tasks, especially when processing large amounts of data, where data access speed and efficiency become key factors.

[0003] Current technologies usually use multiple memories to disperse data storage to improve access efficiency. However, this method is prone to memory conflicts. In addition, when feature map data is stored in memory, it is often necessary to fill in zero values, which will cause discontinuity in address access and thus fail to meet the needs of actual applications. Summary of the invention

[0004] Based on this, it is necessary to provide a data processing method, apparatus, computer device, computer-readable storage medium and computer program product to address the above technical issues.

[0005] In a first aspect, the present application provides a data processing method. The method comprises:

[0006] Obtain the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determine the transmission strategy according to the maximum storage data volume and the number of input channels; wherein the transmission strategy includes the amount of data transmitted each time by the target address;

[0007] Acquire data of a source address, and transmit the data of the source address to different target addresses of the memory in sequence according to the transmission strategy; wherein each time the data of the transmission is stored in a different target address of the memory;

[0008] When the amount of remaining data at the source address is less than the amount of data transmitted each time, the remaining data is transmitted to the target address, and the data of the next source address is obtained, and the data of the next source address is transmitted to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address satisfies the amount of data transmitted each time; and the remaining data of the next source address is transmitted sequentially using the transmission strategy.

[0009] In one embodiment, determining the transmission strategy according to the maximum amount of stored data and the number of input channels includes:

[0010] In a case where the maximum amount of stored data is greater than or equal to the number of input channels, determining the amount of data transmitted each time to be the number of input channels;

[0011] In a case where the maximum amount of stored data is less than the number of input channels, determining the number of target addresses required to store data of the number of input channels according to the number of input channels and the maximum amount of stored data;

[0012] Determine a transmission period according to the number of target addresses, and determine within the transmission period that the data transmitted each time is the maximum storage data amount;

[0013] After each transmission cycle, the amount of data transmitted this time is determined as the difference between the data of the input channel and the amount of data transmitted in the previous cycle, and the next transmission cycle is continued.

[0014] In one embodiment, after the data of the source address is sequentially transmitted to different target addresses of the memory, the method further includes:

[0015] Determining whether the amount of data stored in the memory meets a preset threshold;

[0016] When the amount of data stored in the memory meets a preset threshold, convolution processing is performed on the amount of data in the memory.

[0017] In one embodiment, performing convolution processing on the amount of data in the memory includes:

[0018] Performing standardization processing on the data in the memory to obtain initial target data; wherein the standardization processing includes at least one of the following: data alignment and data zero padding;

[0019] The initial target data is subjected to convolution processing.

[0020] In one embodiment, transferring data to different addresses of the memory includes:

[0021] The data is transferred to different addresses of the memory, and a memory transfer data identifier is established; wherein the memory transfer data identifier is used to characterize the data transferred this time.

[0022] In one embodiment, the transmitting the data of the source address to different target addresses of the memory in sequence includes:

[0023] The data of the source address is sequentially transmitted to different target addresses of the memory; wherein the target addresses of two adjacent transmissions are continuous target addresses.

[0024] In a second aspect, the present application further provides a data processing device. The device comprises:

[0025] A strategy confirmation module is used to obtain the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determine the transmission strategy according to the maximum storage data volume and the number of input channels; wherein the transmission strategy includes the amount of data transmitted each time by the target address;

[0026] A data transmission module, used for acquiring data of a source address, and transmitting the data of the source address to different target addresses of the memory in sequence according to the transmission strategy; wherein each time the data of the transmission is stored in a different target address of the memory;

[0027] The data transmission module is also used to transmit the remaining data to the target address when the remaining data amount of the source address is less than the data amount transmitted each time, and obtain the data of the next source address, and transmit the data of the next source address to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address meets the data amount transmitted each time; and use the transmission strategy to transmit the remaining data of the next source address in sequence.

[0028] In one embodiment, the policy determination module is further used to:

[0029] In a case where the maximum amount of stored data is greater than or equal to the number of input channels, determining the amount of data transmitted each time to be the number of input channels;

[0030] In a case where the maximum amount of stored data is less than the number of input channels, determining the number of target addresses required to store data of the number of input channels according to the number of input channels and the maximum amount of stored data;

[0031] Determine a transmission period according to the number of target addresses, and determine within the transmission period that the data transmitted each time is the maximum storage data amount;

[0032] After each transmission cycle, the amount of data transmitted this time is determined as the difference between the data of the input channel and the amount of data transmitted in the previous cycle, and the next transmission cycle is continued.

[0033] In one embodiment, the device further comprises a convolution processing module, configured to:

[0034] Determining whether the amount of data stored in the memory meets a preset threshold;

[0035] When the amount of data stored in the memory meets a preset threshold, convolution processing is performed on the amount of data in the memory.

[0036] In one embodiment, the convolution processing module includes:

[0037] A data standardization submodule is used to perform standardization processing on the data in the memory to obtain initial target data; wherein the standardization processing includes at least one of the following: data alignment and data zero padding;

[0038] The convolution processing submodule is used to perform convolution processing on the initial target data.

[0039] In one embodiment, the device comprises:

[0040] The data identification establishment module is used to transfer data to different addresses of the memory and establish a memory transfer data identification; wherein the memory transfer data identification is used to characterize the data transmitted this time.

[0041] In one embodiment, the transmitting the data of the source address to different target addresses of the memory in sequence includes:

[0042] The data of the source address is sequentially transmitted to different target addresses of the memory; wherein the target addresses of two adjacent transmissions are continuous target addresses.

[0043] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the data processing method as described in any one of the embodiments of the present disclosure is implemented.

[0044] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the data processing method as described in any one of the embodiments of the present disclosure is implemented.

[0045] In a fifth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the data processing method as described in any one of the embodiments of the present disclosure is implemented.

[0046] The above-mentioned data processing method, device, computer equipment, storage medium and computer program product determine the transmission strategy by comparing the maximum storage data volume of the target address in the memory and the number of input channels, and transmit the data of the source address in sequence according to the transmission strategy and using the transmission strategy, and use the data of the next source address to supplement the data of the target address. In this way, it is possible to avoid padding the data with zeros during data transmission, and further avoid the low data reading efficiency caused by the discontinuity of the data. The sequential reading of data is guaranteed, the time delay of random access is reduced, and the data access efficiency is improved. At the same time, the utilization rate of the memory is improved, and the waste of memory caused by zero padding is avoided, thereby improving the overall performance and response speed of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a flow chart of a data processing method in one embodiment;

[0048] Figure 2 A schematic diagram of a flow chart of transmission strategy confirmation in one embodiment;

[0049] Figure 3 A schematic diagram of a flow chart of data convolution processing in one embodiment;

[0050] Figure 4 Schematic diagram of a process of data normalization and convolution in one embodiment;

[0051] Figure 5 A schematic diagram of a flow chart of a data processing method in one embodiment;

[0052] Figure 6 A schematic diagram of a data transmission strategy in one embodiment;

[0053] Figure 7 is a schematic diagram of data transmission in one embodiment;

[0054] Figure 8 A schematic diagram of data placement in one embodiment;

[0055] Fig. 9 is a schematic diagram of matrix multiplication in one embodiment;

[0056] Fig.10 is a structural block diagram of a data processing device in one embodiment;

[0057] Fig.11 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0059] In order to facilitate those skilled in the art to understand the technical solution provided by the embodiments of the present disclosure, the technical environment in which the technical solution is implemented is described below.

[0060] In the prior art, multiple banks (data banks) are usually used to store data evenly. This method not only makes the actual hardware area larger and increases power consumption, but also slows down the speed of hardware operations and increases the complexity of hardware logic when reading data from the data bank when the feature size is small. In addition, when the number of input channels of the feature map does not meet the integer multiples of the bank width, the feature map data needs to be padded with zeros when written from L1_buffer to the bank. This writing method causes additional discontinuity in the data access address or requires additional zero padding of the data in the channel number to an integer multiple of the bank width before fetching the feature data. The former will greatly slow down the speed of hardware communication data retrieval, and the latter will additionally increase the space for storing data, which places extremely high requirements on the hardware.

[0061] Based on the actual technical requirements similar to those described above, this solution proposes a data processing method, such as Figure 1 As shown, this embodiment uses the method applied to a terminal as an example for illustration. It is understandable that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0062] Step 100, obtain the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determine the transmission strategy based on the maximum storage data volume and the number of input channels; wherein the transmission strategy includes the amount of data transmitted each time by the target address.

[0063] In an exemplary embodiment, the memory may include a carrier of data information, such as SRAM, ROM, register, etc. The maximum storage data amount of each target address may include the maximum data amount that can be stored at each address in the memory, such as the amount of data that can be stored by a row width of SRAM, etc.

[0064] In an exemplary embodiment, the transmission strategy may include the amount of data transmitted each time, etc. Specifically, for example, the amount of data transported to the target address each time from the start of data transport to the end of data transport, etc. In another exemplary embodiment, the transmission strategy may also include the amount of data transmitted each time within a cycle, etc. For example, a cycle is three transmissions, the amount of data transmitted in the first two transmissions is the maximum storage amount of data at the target address, and the amount of data transmitted in the third transmission is the difference between the sum of the first two transmissions and the number of characteristic number input channels, etc.; three transmissions constitute a cycle, and the transmission is repeated in cycles, that is, after one cycle ends, the next cycle begins; it can be understood that, by adopting the method of the above embodiment, the amount of data transmitted in three cycles is equal to the number of input channels, and it can be realized that the data of one input channel can be stored once through multiple target addresses, etc.

[0065] Step S200, obtaining data of the source address, and transmitting the data of the source address to different target addresses of the memory in sequence according to the transmission strategy; wherein each time the transmitted data is stored in a different target address of the memory.

[0066] In an exemplary embodiment, the source address may include a source address of data storage, etc.; that is, the input needs to be transmitted from the source address to the target address, etc.

[0067] In an exemplary embodiment, the data of the source address is sequentially transmitted to different target addresses of the memory, which may include storing all the data of each transmission into one address, and storing the data of different transmissions into different addresses, etc. For example, there are three transmissions, namely data transmission A, data transmission B, and data transmission C; it can be understood that the data transmitted by data transmission A are all transmitted to the same address; and the target address of data transmission A and the target address of data transmission B are different. It is ensured that the data of a single transmission are all stored in the same target address, while the data of different transmissions are stored in different target addresses. It can be understood that this method can make the data of a single or multiple target addresses the data that needs to be input by all channels of the same point, etc. In actual use, the target addresses of continuous data transmissions can be set to adjacent addresses, so that the data from the target addresses are continuous, which is convenient for subsequent reading, etc.

[0068] Step S300, when the remaining data amount of the source address is less than the data amount transmitted each time, the remaining data is transmitted to the target address, and the data of the next source address is obtained, and the data of the next source address is transmitted to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address meets the data amount transmitted each time; and the remaining data of the next source address is transmitted in sequence using the transmission strategy.

[0069] In an exemplary embodiment, the remaining data amount of the source address may include the remaining data amount stored in the source address after transportation; for example, the amount of data stored in the source address is 20, and the transmission strategy is to transmit 8 at a time. After three transmissions, the amount of data stored in the source address is 2. At this time, the remaining data amount of the source address is less than the amount of data transmitted each time (8).

[0070] In an exemplary embodiment, the remaining data can be transmitted to a target address, and data can be obtained from the next source address and transmitted to the target address, so that the data volume of the target address meets the transmission strategy, etc.; for example, the remaining data volume is 2; 8 data need to be transmitted each time; then the remaining data volume is transmitted to the target address; at this time, there are two data at the target address; then data is obtained from the next source address, and 6 data are transmitted to the target address, so that the target address meets the data volume (8) transmitted each time, etc.

[0071] In an exemplary embodiment, when the data is transferred to the target address, the target address of the transfer can be continuous, etc., and each time, only the data of the source address needs to be stored in the target address, without the need to fill zeros, etc. In actual use, the mask of each write can be dynamically adjusted to determine the data of each transfer. For example, the mask of each data written to the target address is 16 1s; when three data are written to the target address, the mask is 13 0s and 3 1s, etc.

[0072] In the above data processing method, by comparing the maximum storage data volume of the target address in the memory and the number of input channels, a transmission strategy is determined, and according to and using the transmission strategy, the data of the source address is transmitted in sequence, and the data of the target address is supplemented with the data of the next source address. In this way, it is possible to avoid padding the data with zeros during data transmission, and further avoid the low data reading efficiency caused by the discontinuity of the data. The sequential reading of data is guaranteed, the time delay of random access is reduced, and the data access efficiency is improved. At the same time, the utilization rate of the memory is improved, and the waste of memory caused by zero padding is avoided, thereby improving the overall performance and response speed of the system.

[0073] In one embodiment, Figure 2 As shown, the transmission strategy is determined according to the maximum amount of stored data and the number of input channels, including:

[0074] Step S101, when the maximum storage data amount is greater than or equal to the number of input channels, determining the data amount of each transmission to be the number of input channels.

[0075] In an exemplary embodiment, when the maximum storage data is greater than or equal to the number of input channels, the amount of data transmitted each time is determined to be the number of input channels, which may include, when a single target address can store data of all channels of the same point, the amount of data transmitted to the target address each time is the data of all channels of one point, etc.

[0076] Step S102, when the maximum storage data amount is smaller than the number of input channels, determine the number of target addresses required to store data of the number of input channels according to the number of input channels and the maximum storage data amount.

[0077] In an exemplary embodiment, when the maximum amount of stored data is smaller than the data of the input channel, the storage memory of one target address may be insufficient to store the data of all channels of the same point; therefore, multiple target addresses are required to store the data of all channels of the same point, etc.; the number of target addresses here refers to how many target addresses are required to store the data of all channels of the same point, etc.

[0078] Step S103, determining a transmission period according to the number of target addresses, and determining within the transmission period that the data transmitted each time is the maximum storage data amount.

[0079] Step S104, after each transmission cycle, the amount of data transmitted this time is determined as the difference between the data of the input channel and the amount of data transmitted in the previous cycle, and the next transmission cycle is continued.

[0080] In an exemplary embodiment, the number of target addresses may include the number of target addresses required to store data of all channels of the same point, etc.; the transmission cycle may include how many transmissions are required to complete the data transmission of all channels of the same point, etc.; in actual use, the transmission cycle is the number of target addresses minus one; specifically, the input channels are 30; the maximum storage data volume of the target address is 8; at this time, the number of target addresses is 4; the transmission cycle is 3; that is, the first three cycles all require 8 transmissions; and the fourth transmission is 6 (the number of input channels-transmission cycle×the maximum storage data volume of the target address), ensuring that the data transmission of all channels of the same point is completed through four transmissions, etc. At the same time, four target addresses store the data of all channels of the same point, and in actual use, the data of all channels of the point can be directly obtained from the four target addresses.

[0081] In this embodiment, the amount of data transmitted each time is determined by the maximum amount of stored data and the number of input channels. This scheme optimizes the efficiency and flexibility of data transmission by dynamically adjusting the amount of data transmitted each time and the transmission cycle. When the maximum amount of stored data is greater than or equal to the number of input channels, the data stored at each target address is the data of all channels at the same point, and when the maximum amount of stored data is less than the number of input channels, the data stored at multiple target addresses is the data of all channels at the same point. By aggregating the data of all channels at the same point, the number of memory reads can be reduced, the access delay can be reduced, and the memory usage can be optimized. At the same time, in this way, parallel processing of data and fast calculation of the same position can be achieved, which is helpful for the overall performance of the deep learning model, thereby improving the responsiveness and computing efficiency of the system.

[0082] In one embodiment, Figure 3 As shown, after the data of the source address is transmitted to different target addresses of the memory in sequence, it also includes:

[0083] Step S201, determining whether the amount of data stored in the memory meets a preset threshold.

[0084] Step S202, when the amount of data stored in the memory meets a preset threshold, convolution processing is performed on the amount of data in the memory.

[0085] In an exemplary embodiment, the satisfying of the preset threshold may include whether the amount of data stored in the memory satisfies the convolution operation, and when the amount of stored data satisfies the amount of data for the convolution operation, the convolution operation is performed on the stored data, etc. Specifically, after each transmission is completed, it may be checked whether the amount of stored data satisfies the PE array operation, and if so, the PE array starts to calculate the convolution, etc.

[0086] In this embodiment, by judging whether the amount of data stored in the memory meets the preset threshold, and performing convolution processing when the threshold is reached, this strategy ensures that calculations are performed only when there is sufficient data, thereby optimizing resource utilization efficiency. When the amount of data is sufficient, batch processing can be performed to give full play to the computing power of the hardware and reduce the waste of calculations caused by insufficient data. At the same time, convolution processing is performed when the data meets the threshold, avoiding the need for multiple convolution processing after storing a large amount of data, which makes the system overloaded. The calculation frequency is reduced, the burden on the system is reduced, and frequent convolution calculations are avoided, thereby improving the overall processing performance and response speed.

[0087] In one embodiment, Figure 4 As shown, the convolution processing of the amount of data in the memory includes:

[0088] Step S211, performing standardization processing on the data in the memory to obtain initial target data; wherein the standardization processing includes at least one of the following: data alignment, data zero padding.

[0089] Step S212, performing convolution processing on the initial target data.

[0090] In an exemplary embodiment, the standardization process may include data alignment, data zero padding, averaging, variance normalization, scaling and offset, etc. Among them, the data queue may include data accuracy of convolution operation, etc.; data zero padding may include truncating a part of the data so that the form of the data can meet the format of the convolution operation, etc.; averaging may include subtracting their mean from the input data to eliminate the offset, etc.; the variance normalization may include dividing the mean-free data by the standard deviation to ensure that the data is at the same level, thereby reducing the variability of the activation value, etc.; the scaling and offset may include applying learnable scaling and offset parameters to maintain the learning ability of the model and adapt to different distributions, etc.

[0091] In this embodiment, standardization of the data in the memory (such as data alignment and data zero padding) can ensure that the input data has a consistent format and size before the convolution operation, which can effectively improve the efficiency and accuracy of the convolution calculation. Through data alignment, the data can be organized into a suitable structure to facilitate parallel computing; and through zero padding, information loss can be avoided and the integrity of the convolution operation can be maintained. The processed initial target data provides a good foundation for the convolution calculation, reduces the errors caused by data inconsistency, and thus improves the performance and stability of the model.

[0092] In one embodiment, transferring data to different addresses of the memory includes:

[0093] The data is transferred to different addresses of the memory, and a memory transfer data identifier is established; wherein the memory transfer data identifier is used to characterize the data transferred this time.

[0094] In an exemplary embodiment, the memory transmission data identifier may include a data mask, etc.; the memory data identifier can be used to obtain the data of each transmission; for example, the memory target address can store 16 addresses, then the mask can be 16 bits; wherein the mask is 1, which is the data transmitted this time; assuming that 3 data are transmitted this time, the memory data identifier is the first thirteen 0s and the last three 1s, which is used to represent that the first thirteen data are not the data transmitted this time, and the last three data are the data transmitted this time, etc.

[0095] In this embodiment, a memory transmission data identifier is established to achieve the determination of each transmission data, and each transmission data can be clearly distinguished, which is convenient for data tracking and management, and also convenient for subsequent data access and processing.

[0096] In one embodiment, the transmitting the data of the source address to different target addresses of the memory in sequence includes:

[0097] The data of the source address is sequentially transmitted to different target addresses of the memory; wherein the target addresses of two adjacent transmissions are continuous target addresses.

[0098] In an exemplary embodiment, the target addresses of two adjacent transmissions are continuous target addresses, which may include data of a single transmission being stored in the same target address, and data of different transmission times being stored in different target addresses, and the target addresses of two adjacent transmissions being continuous; for example, three consecutive transmissions are required, namely, data transmission A, data transmission B, and data transmission C; all data of data transmission A is stored in target address a, and all data of data transmission B will be stored in target address b continuous with target address a, and all data of data transmission C will be stored in target address c continuous with target address b, etc.

[0099] In this embodiment, the data of the source address is sequentially transmitted to different target addresses of the memory, and the target addresses of two adjacent transmissions are continuous addresses, which optimizes the storage efficiency and access speed of the memory. This continuous storage layout can reduce memory access latency, simplify data management and processing procedures, and significantly improve system performance, especially when a large amount of data processing is required.

[0100] In an exemplary embodiment, the data processing method may be implemented as follows: Figure 5 As shown, specifically including:

[0101] Step S401, the system is powered on and reset; this may include all circuit modules automatically returning to an initial state, etc.;

[0102] Step S402, loading feature map parameters; this may include the system loading and configuring the system's internal parameters according to the feature map size, convolution kernel size, step size, input and output channels, etc. that need to be calculated this time. These parameters also include the address location of the data required for the convolution operation, etc.

[0103] Step S403, calculating the amount of data required for this time; the system may calculate how many times data needs to be transmitted in total, how much data is required for convolution operation in each batch transmission according to the configured internal parameters, and the data transmitted once may include all the complete data required for a PE array to perform convolution operation, which may require multiple transmissions to complete, etc.;

[0104] Step S404, transmitting data; this may include transmitting each batch of data in batches to an actual storage controller, etc.;

[0105] Step S405, determining whether the batch data transmission is completed; if not, returning to step S404; if completed, proceeding to step S406;

[0106] Step S406, determine whether the data is fully prepared; if not, return to step S404, if yes, proceed to step S407;

[0107] Step S407, data processing, may include that the data in the storage space needs to be additionally processed before it can be handed over to the PE array for operation, and the data processing includes but is not limited to aligning data, padding data with zeros, etc.;

[0108] Step S408: The PE array starts calculating the convolution.

[0109] In an exemplary embodiment, the transmission strategy may be as follows: Figure 6 As shown, specifically including:

[0110] Step S501, the start of a data fetch; if the remaining data is sufficient for the amount of data to be transmitted, then proceed to S501; if the remaining data is insufficient for the amount of data to be transmitted, then proceed to S502;

[0111] Step S502: when the remaining data is not enough for the amount of data to be transmitted, if the remaining data of the data fetch has been written and the amount of data stored in the target address does not meet the amount of data to be transmitted, then proceed to S503; if the remaining data is not enough for the amount of data to be transmitted each time, then proceed to S502;

[0112] Step S503: If the fetched data is written and the amount of data stored in the target address does not meet the amount of data transmitted each time, enter S503; if the remaining data is sufficient for the amount of data transmitted each time, enter S501.

[0113] In an exemplary embodiment, the memory in the data processing method can use two SRAMs, so that one SRAM can be written while the other SRAM can be read, and the data can be read immediately. Since there are fewer read and write ports, compared with banks, the two SRAMs have a smaller area and power consumption for the same storage space. In an exemplary embodiment, the memory can also include a port masked ping-pong SRAM, which can write to the SRAM while accessing data such as features and weights, and can also read weights and feature data in another SRAM, while ensuring that the SRAM space is sufficient. It can increase the speed of convolution calculation, and can also perform continuous address writing of data.

[0114] In an exemplary embodiment, the width and depth of the two SRAM blocks included are not limited to the width of a row and the depth of a column of the PE array, and can be any width and depth that can complete the convolution calculation task issued at one time.

[0115] In an exemplary embodiment, the data processing method can be applied to convolution calculation of data, which can include convolution calculation that can divide the convolution calculation of an entire feature map into multiple convolution calculations. The task processor can be a CPU, or it can be a dedicated hardware or software that can be manually programmed to calculate the amount of each task.

[0116] In an exemplary embodiment, the data transmission may be as follows: Figure 7 As shown in the figure, the source address A includes the data "33222111", the number of input channels is 3, and the maximum storage data volume of the target address is greater than 3. Therefore, 3 data are transmitted each time, and the same address in the memory stores the data of all channels at the same point. When the data of source address A is not enough for the data of the target address, the remaining data is stored in the address 2 of the memory, and the data of source address B is used to supplement address 2.

[0117] In an exemplary embodiment, data is uniformly stored and read in the direction of channel number of data points 1-2-3... in an address incrementing method. Figure 8 As shown, the direction of address increment should be: 1-1-1-2-2-2-3-3-3-4-4-4...9-9-9. It can be understood that Figure 8 The example only takes the simple case of 3 channels. This solution is applicable to any number of channels if there is enough storage space.

[0118] In an exemplary embodiment, the feature data may be a sheet with a size of 4*4 and a number of input channels of 3. The matrix multiplication calculation of the feature data may be as follows: Fig. 9 As shown, the feature map data are numbered 0 to 15, including the entire input channels 1 to 3. For simplicity, this example uses the feature points of channel 1. Fig. 9In the first to fourth steps, the red box is the feature data point required for four convolution operations on the weighted data. In the first step, all the channel numbers represented by the feature expansion data 0-1-2-4-5-6--8-9-10 and the weight data 1~9 are sent to the PE array in turn, and the corresponding matrix multiplication calculation is performed. Similarly, the feature data represented by the second and fourth steps are also sent to the weight data 1~9 in turn for matrix multiplication calculation. In the memory, the feature data points 0~15 are all stored separately in a target address, and the weight data 1~9 are also stored separately in a target address. This ensures the correctness of the convolution result. The feature data can be expanded into a column of matrix multiplication using im2col, and other methods can also be used. There is no limitation here. The correctness of the convolution operation result can be guaranteed in the same channel number direction or the same data point direction.

[0119] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0120] Based on the same inventive concept, the embodiment of the present application also provides a data processing device for implementing the data processing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or more data processing device embodiments provided below can refer to the limitations on the data processing method above, and will not be repeated here.

[0121] In one embodiment, Fig.10 As shown, a data processing device 100 is provided, comprising: a policy confirmation module 101 and a data transmission module 102, wherein:

[0122] A strategy confirmation module is used to obtain the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determine the transmission strategy according to the maximum storage data volume and the number of input channels; wherein the transmission strategy includes the amount of data transmitted each time by the target address;

[0123] A data transmission module, used for acquiring data of a source address, and transmitting the data of the source address to different target addresses of the memory in sequence according to the transmission strategy; wherein each time the data of the transmission is stored in a different target address of the memory;

[0124] The data transmission module is also used to transmit the remaining data to the target address when the remaining data amount of the source address is less than the data amount transmitted each time, and obtain the data of the next source address, and transmit the data of the next source address to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address meets the data amount transmitted each time; and use the transmission strategy to transmit the remaining data of the next source address in sequence.

[0125] In one embodiment, the policy determination module is further used to:

[0126] In a case where the maximum amount of stored data is greater than or equal to the number of input channels, determining the amount of data transmitted each time to be the number of input channels;

[0127] In a case where the maximum amount of stored data is less than the number of input channels, determining the number of target addresses required to store data of the number of input channels according to the number of input channels and the maximum amount of stored data;

[0128] Determine a transmission period according to the number of target addresses, and determine within the transmission period that the data transmitted each time is the maximum storage data amount;

[0129] After each transmission cycle, the amount of data transmitted this time is determined as the difference between the data of the input channel and the amount of data transmitted in the previous cycle, and the next transmission cycle is continued.

[0130] In one embodiment, the device further comprises a convolution processing module, configured to:

[0131] Determining whether the amount of data stored in the memory meets a preset threshold;

[0132] When the amount of data stored in the memory meets a preset threshold, convolution processing is performed on the amount of data in the memory.

[0133] In one embodiment, the convolution processing module includes:

[0134] A data standardization submodule is used to perform standardization processing on the data in the memory to obtain initial target data; wherein the standardization processing includes at least one of the following: data alignment and data zero padding;

[0135] The convolution processing submodule is used to perform convolution processing on the initial target data.

[0136] In one embodiment, the device comprises:

[0137] The data identification establishment module is used to transfer data to different addresses of the memory and establish a memory transfer data identification; wherein the memory transfer data identification is used to characterize the data transmitted this time.

[0138] In one embodiment, the transmitting the data of the source address to different target addresses of the memory in sequence includes:

[0139] The data of the source address is sequentially transmitted to different target addresses of the memory; wherein the target addresses of two adjacent transmissions are continuous target addresses.

[0140] Each module in the above data processing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0141] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig.11 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store feature data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data processing method is implemented.

[0142] Those skilled in the art will understand that Fig.11 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0143] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0144] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0145] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A data processing method, characterized in that: A computing unit applied to a neural network; the method comprises: Obtain the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determine the transmission strategy according to the maximum storage data volume and the number of input channels; wherein the transmission strategy includes the amount of data transmitted each time by the target address; Acquire data of a source address, and transmit the data of the source address to different target addresses of the memory in sequence according to the transmission strategy; wherein each time the data of the transmission is stored in a different target address of the memory; When the amount of remaining data at the source address is less than the amount of data transmitted each time, the remaining data is transmitted to the target address, and the data of the next source address is obtained, and the data of the next source address is transmitted to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address satisfies the amount of data transmitted each time; and the remaining data of the next source address is transmitted sequentially using the transmission strategy.

2. The method according to claim 1, characterized in that The determining of the transmission strategy according to the maximum amount of stored data and the number of input channels includes: In a case where the maximum amount of stored data is greater than or equal to the number of input channels, determining the amount of data transmitted each time to be the number of input channels; In a case where the maximum amount of stored data is less than the number of input channels, determining the number of target addresses required to store data of the number of input channels according to the number of input channels and the maximum amount of stored data; Determine a transmission period according to the number of target addresses, and determine within the transmission period that the data transmitted each time is the maximum storage data amount; After each transmission cycle, the amount of data transmitted this time is determined as the difference between the data of the input channel and the amount of data transmitted in the previous cycle, and the next transmission cycle is continued.

3. The method according to claim 1, characterized in that: After the data of the source address is sequentially transmitted to different target addresses of the memory, the method further includes: Determining whether the amount of data stored in the memory meets a preset threshold; When the amount of data stored in the memory meets a preset threshold, convolution processing is performed on the amount of data in the memory.

4. The method according to claim 3, characterized in that: The performing convolution processing on the amount of data in the memory includes: Performing standardization processing on the data in the memory to obtain initial target data; wherein the standardization processing includes at least one of the following: data alignment and data zero padding; The initial target data is subjected to convolution processing.

5. The method according to any one of claims 1-2, characterized in that: Transfer data to different addresses of said memory, including: The data is transferred to different addresses of the memory, and a memory transfer data identifier is established; wherein the memory transfer data identifier is used to characterize the data transferred this time.

6. The method according to claim 1, characterized in that The transmitting the data of the source address to different target addresses of the memory in sequence includes: The data of the source address is sequentially transmitted to different target addresses of the memory; wherein the target addresses of two adjacent transmissions are continuous target addresses.

7. A data processing device, characterized in that: The device comprises: A strategy confirmation module is used to obtain the maximum storage data volume and the number of feature map input channels of each target address corresponding to the memory, and determine the transmission strategy according to the maximum storage data volume and the number of input channels; wherein the transmission strategy includes the amount of data transmitted each time by the target address; A data transmission module, used for acquiring data of a source address, and transmitting the data of the source address to different target addresses of the memory in sequence according to the transmission strategy; wherein each time the data of the transmission is stored in a different target address of the memory; The data transmission module is also used to transmit the remaining data to the target address when the remaining data amount of the source address is less than the data amount transmitted each time, and obtain the data of the next source address, and transmit the data of the next source address to the target address of the remaining data transmission of the previous source address, so that the data stored in the target address of the remaining data of the previous source address meets the data amount transmitted each time; and use the transmission strategy to transmit the remaining data of the next source address in sequence.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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