Flash memory data migration method

Abstract

The invention relates to the field of flash memory storage control, in particular to a flash memory data migration method. According to the method, the efficiency of data migration is improved by using a copyback command in garbage collection, meanwhile, the number of error bits is estimated according to priori data experience, and then a judgment on whether to use the copyback is made. The method comprises the following steps of: when garbage is recycled, comparing a page copyback frequency of a to-be-recycled block with a corresponding copyback threshold value THcb, if the copyback frequency CBs of the to-be-recycled block is less than the copyback threshold value THcb, carrying out copyback operation on the to-be-recycled block, and if the copyback frequency CBs of the to-be-recycled block is greater than the copyback threshold value THcb, not carrying out copyback operation on the to-be-recycled block. According to the method, high data reliability can be kept while high efficiency of the copyback is kept.

Description

Technical Field

[0001] The present invention relates to the field of flash memory storage control, and in particular to a flash memory data migration method for improving the efficiency of garbage collection of a flash memory storage device. Background Art

[0002] Flash memory (NAND FLASH) requires garbage collection due to its characteristics of erasing before writing and inconsistency between writing units and erasing units. First, valid data is read from the old block, then written to the new block, and then the old block is erased. At present, the reserved space of SSD is usually 7% to 28%, that is, the valid data of the block accounts for about 72% to 93%. During garbage collection, these data must be migrated. The efficiency of garbage collection affects the write speed of the host and the response time of IO commands. Therefore, improving the efficiency of garbage collection can improve the write performance of the storage device and shorten the response time of IO commands. Due to its physical characteristics and manufacturing process, the stored data of flash memory usually undergoes bit flipping. Therefore, SSD controllers are generally equipped with BCH or LDPC hardware encoding and decoding units to encode data when writing, and write user data and check data into the flash memory at the same time; decode data when reading data to detect and correct bit flip errors. The bit flip error of flash memory is affected by many factors, such as data retention time, number of reads, number of block erase cycles, etc. Especially with the increasing storage density (SLC->MLC->TLC->QLC) and the development of 3D NAND, the erase life and data retention ability of flash memory are getting worse and worse, and data reliability protection is becoming more and more important.

[0003] NAND manufacturers usually provide copyback flash operation commands to help improve the efficiency of data migration, but because the data is not transferred into NAND, LDPC encoding and decoding cannot be performed, which will lead to the accumulation of error bits. After a certain number of copyback operations, uncorrectable errors will occur during reading, and user data will be lost, which is unacceptable for solid-state storage devices. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a flash memory data migration method, which can maintain high data reliability while maintaining high copyback efficiency.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a flash memory data migration method, comprising the following steps: S01, obtaining a two-dimensional data table of erase and write cycle times and data retention time through experiments; S02, obtaining the maximum executable copyback times within each erase-write cycle number range through experiments; The data retention time and the maximum executable copyback times are fitted according to the erase and write cycles, and a copyback times threshold that varies with the erase and write cycles and data retention time is obtained. This three-dimensional data set is called CBth. S03, importing the three-dimensional data set CBth, and selecting the block S to be recycled; S04, read the erase / write cycle number PEs, the data retention time during writing, and the global data retention time of the block to be recovered S, and obtain the data retention time of the block by subtracting the data retention time during writing from the global data retention time; read the page copyback number CBs of the block to be recovered S; S05, selecting a free block D1 whose erase / write cycle number and PEs difference is less than a threshold value T, and selecting a free block D2 whose erase / write cycle number is the smallest according to the wear leveling requirement; S06, according to the erase and write cycle number and data retention time of the block to be recovered S, check the table to determine its corresponding copyback threshold THcb; S07, compare the page copyback times CBs of the block to be recovered S with the copyback threshold THcb. If the copyback times CBs of the block to be recovered are less than the copyback threshold THcb, perform a copyback operation from block S to D1, and increase the copyback count by one; if the copyback times CBs of the block to be recovered are greater than the copyback threshold THcb, perform a read / write command operation from block S to D2 through LDPC, and clear the copyback count; S08. Repeat step S07 until the recycling is completed.

[0006] Furthermore, the process of obtaining a two-dimensional data table of erase and write cycle times and data retention time through experiments is as follows: S11, select NAND particles, confirm their activation energy, and calculate the temperature acceleration coefficient according to the Arrhenius model; S12, placing the NAND in a temperature box, setting the number of erase and write cycles, adjusting the temperature of the temperature box to t degrees Celsius, keeping the NAND at t degrees Celsius for a period of time, reading the data in the NAND multiple times during the period, and checking the number of error bits through LDPC until the number of error bits exceeds the upper limit of the LDPC error correction capability, taking the time and temperature acceleration coefficient at this time to calculate the data retention time; S13, repeatedly perform step S12, traverse the number of erase and write cycles from 0 to the end of the life of the NAND according to the erase and write cycle interval T1, and traverse the temperature from 25 degrees Celsius to 85 degrees Celsius according to the temperature interval T2, and obtain a two-dimensional data table of the number of erase and write cycles and the data retention time; S14, fitting and reducing the data in step S13, and merging similar data.

[0007] Furthermore, the process of obtaining the maximum executable copyback times within each erase-write cycle range through experiments is as follows: S21, select a NAND block X with N erase cycles, encode the randomized data through LDPC, write it into a NAND WL, and repeat the writing until a NAND block is full; S22, selecting a NAND block Y with the same or similar erase cycle number as N, reading the data written in step S21, performing LDPC error detection and recording the number of error bits, and writing the data without LDPC error correction into NAND block Y through a copyback command; S23, repeat step S22 until the number of error bits exceeds the upper limit of LDPC error correction capability; S24, repeating steps S21 to S23, traversing the erase and write cycle times from 0 to the end of the NAND life according to the erase and write cycle times interval T1, and obtaining an error bit value table that changes with the erase and write cycle times; S25, combining and reducing the data obtained in step S24 to obtain the maximum number of copybacks that can be executed within the range of each erase-write cycle number, that is, if the copyback operation is performed again, the number of error bits will exceed the upper limit of LDPC error correction.

[0008] Furthermore, in step S07, user data written by the host in the flash storage system is placed separately in one block, and data written by garbage collection is placed separately in another block, that is, the data newly written by the host and the garbage collection do not use the same target block.

[0009] Furthermore, when each block is erased, the number of erase and write cycles is recorded in the system table, and when each block is written, the global data retention time of the current system is recorded. The global data retention time is obtained by periodically acquiring the NAND temperature and integrating it according to the Arrhenius model.

[0010] Furthermore, each time a copyback operation is performed, the number of copybacks is recorded.

[0011] Furthermore, the number of erase and write cycles, data retention time during block writing, and global data retention time are recorded in the memory table and written to the pSLC before the system is powered off. For the page copyback times, only the data of the current recycled block is saved in the memory table, and the non-current block data is stored in the pSLC.

[0012] Furthermore, the erase and write cycle interval T1 is 100 times, and the temperature interval T2 is 1 degree Celsius.

[0013] Furthermore, the erase-write cycle interval T1 is 100 times.

[0014] Furthermore, the difference between the erase and write cycles of NAND block Y and NAND block Y does not exceed 50 times.

[0015] Beneficial effects of the present invention: A flash memory data migration method of the present invention mainly improves data security by using copyback operation in the garbage collection process and based on prior experience, improves the garbage collection efficiency of solid-state storage devices and thus improves write performance, and shortens IO command response time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the existing garbage collection; Figure 2 The present invention is a flowchart of the method. DETAILED DESCRIPTION

[0017] The present invention will be further described below in conjunction with the accompanying drawings and specific implementations.

[0018] Example 1 Copyback is an important function in NAND Flash. It allows data to be moved inside NAND without going through an external controller, which is of great significance to improving operation efficiency. When the copyback operation is performed, the errors in the read data will be inherited to the newly written NAND area. After several copybacks, an LDPC error correction is performed, and the accumulated errors will be cleared.

[0019] Garbage collection without copyback first reads data from the NAND array to the page register and then to the buffer in the controller. After LDPC error correction, the corrected data is written to the buffer, then transferred to the page register and written to the NAND array. The process is as follows Figure 1 ->3->5->6->4->2.

[0020] There are two common usage methods: 1. Use copyback garbage collection to read from the NAND array to the page register, and then write directly from the page register to the array, as follows Figure 1->2; 2. Use the read command to read the data from the array to the page register, and then transfer it to the buffer in the controller. Use LDPC for error checking. If the number of error bits is within the acceptable range, directly write the data in the page register to the nand array. The process is as follows Figure 1 ->3->5->2. The data security of the first method cannot be guaranteed, and the efficiency of the second method is not as high as the first method.

[0021] However, due to the inherent characteristics of NAND, multiple copyback operations will lead to error accumulation and affect data security. Common factors that affect NAND data reliability are as follows: erase and write cycles, data retention, read interference, etc. This patent mainly relates to erase and write cycles and data retention. Each erase will generate a very large electric field in the tunneling oxide layer. Due to trap generation and interface damage, defects will be generated in the oxide layer, causing charge capture or release into the tunneling oxide layer, resulting in abnormal charge flowing into the storage layer. As the number of erase and write cycles increases, under the same voltage and time conditions, the charge injected into the storage layer will decrease as the number of erase and write cycles increases. Therefore, the more erase and write cycles there are, the greater the probability of errors. Data retention refers to the ability to store information without external power supply. The loss of charge in the storage layer causes the overall offset of the threshold voltage distribution. The longer the time, the greater the offset. Therefore, the longer the time, the more errors will be generated, and the temperature will accelerate this behavior. The temperature stress effect conforms to the Arrhenius model.

[0022] In view of this, the present embodiment discloses a data migration method applied to a flash memory storage system. The garbage collection of the method uses the copyback command to accelerate the efficiency of data migration, and at the same time makes an estimate of the number of error bits based on prior data experience, and then makes a decision on whether to use copyback. The method can maintain high efficiency of copyback while maintaining high data reliability.

[0023] The prior data collection process is as follows: S11, select NAND particles, confirm their activation energy, and calculate the temperature acceleration coefficient according to the Arrhenius model; S12, placing the NAND in a temperature box, setting the number of erase and write cycles, adjusting the temperature of the temperature box to t degrees Celsius, keeping the NAND at t degrees Celsius for a period of time, reading the data in the NAND multiple times during the period, and checking the number of error bits through LDPC until the number of error bits exceeds the upper limit of the LDPC error correction capability, taking the time and temperature acceleration coefficient at this time to calculate the data retention time; S13, repeatedly perform step S12, traverse the erase and write cycle number from 0 to the end of the NAND life according to the erase and write cycle number interval of 100, and traverse the temperature from 25 degrees Celsius to 85 degrees Celsius according to the temperature interval of 1 degree Celsius, and obtain a two-dimensional data table of the erase and write cycle number and the data retention time; The above erase and write cycle interval and temperature interval are set according to actual conditions and may be other values ​​in other embodiments.

[0024] (4) Fit and reduce the data in step (3) and merge similar data.

[0025] Copyback times and error bit count data collection: (1) Select a NAND block X with N erase cycles, encode the randomized data through LDPC, and write it into a NAND WL.

[0026] (2) Repeat step (1) until a NAND block is full; (3) Select a NAND block Y with a number of erase / write cycles of about N and a difference of no more than 50, read the data written in step (1), perform LDPC error detection and record the number of error bits, and write the data without LDPC error correction into block Y through the copyback command; (4) Repeat step (3) until the number of error bits exceeds the upper limit of LDPC error correction capability; (5) Repeat steps (1) to (4) to obtain, with an interval of 100 erase and write cycles, traversing the erase and write cycle number from 0 to the end of the declaration, to obtain a table of error bit values ​​that changes with the erase and write cycle number. The erase and write cycle number interval is set according to actual conditions and can also be other values ​​in other embodiments. (6) The data obtained in step (5) are combined and reduced to obtain the maximum number of copyback operations that can be performed within the range of each erase-write cycle number. That is, if the copyback operation is performed again, the number of error bits will exceed the upper limit of LDPC error correction.

[0027] The above two data are fitted according to the number of erase and write cycles to obtain a copyback threshold that varies with the number of erase and write cycles and the data retention time. This three-dimensional data set is called CBth.

[0028] The following are some additional data recording operations and rules that the system needs to perform: In step S07, in the flash memory storage system, user data written by the host is placed separately on a block, and data written by garbage collection is placed separately on a block, that is, the data newly written by the host and the garbage collection do not use the same target block.

[0029] When each block is erased, the number of erase and write cycles is recorded in the system table. When each block is written, the global data retention time of the current system is recorded. The global data retention time is obtained by regularly obtaining the NAND temperature and integrating it according to the Arrhenius model.

[0030] Each time a copyback operation is performed, the number of copybacks is recorded.

[0031] The above erase and write cycles, data retention time when writing blocks, and global data retention time are recorded in the memory table and written to the pSLC before the system is powered off. Page copyback times Only the data of the current recycled block is saved in the memory table, and the data of non-current blocks is stored in the pSLC.

[0032] During garbage collection, the three-dimensional data set CBth obtained from the prior experiment is imported and Figure 2 The process shown is for garbage collection: 1. Select the block S to be recycled; 2. Read the erase and write cycle count PEs of the block to be recycled S; 3. Read the data retention time when the block S to be recovered is written, read the global data retention time and make a difference to obtain the data retention time of the block.

[0033] 4. Read the page copyback count CBs of the block to be recycled S; 5. Select the free block D1 whose erase and write cycle times differ from PEs by less than 500 times; 6. Select the free block D2 with the minimum number of erase and write cycles according to the wear leveling requirement; 7. Determine the corresponding copyback threshold THcb according to the erase and write cycles and data retention time of the block to be recovered S; 8. If the copyback count CBs of the block to be recovered is less than the copyback threshold THcb in step (5), a copyback operation is performed from block S to D1, and the copyback count is increased by one; if it is greater than the threshold THcb in step (5), a read and write command operation through LDPC is performed from block S to D2, and the copyback count is cleared; 9. Repeat step (8) until the recycling is completed Example 2 The embodiment of the present disclosure provides a flash memory data migration device, including a processor and a memory. Optionally, the device may also include a communication interface and a bus. The processor, the communication interface, and the memory may communicate with each other through the bus. The communication interface may be used for information transmission. The processor may call the logic instructions in the memory to execute the flash memory data migration method of the above embodiment.

[0034] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0035] The memory, as a computer-readable storage medium, can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor executes the function application and data processing by running the program instructions / modules stored in the memory, that is, implementing the flash memory data migration method in the above embodiment.

[0036] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory may include a high-speed random access memory and may also include a non-volatile memory.

[0037] Example 3 An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the flash memory data migration method described in Embodiment 1.

[0038] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0039] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0040] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0041] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

Claims

1. A flash memory data migration method, characterized in that: The following steps are involved: S01, obtaining a two-dimensional data table of erase and write cycle times and data retention time through experiments; S02, obtaining the maximum executable copyback times within each erase-write cycle number range through experiments; The data retention time and the maximum executable copyback data erase and write cycles are fitted to obtain a copyback threshold that varies with the erase and write cycles and data retention time. This three-dimensional data set is called CBth. S03, importing the three-dimensional data set CBth, and selecting the block S to be recycled; S04, read the erase / write cycle number PEs, the data retention time during writing, and the global data retention time of the block to be recovered S, and obtain the data retention time of the block by subtracting the data retention time during writing from the global data retention time; read the page copyback number CBs of the block to be recovered S; S05, selecting a free block D1 whose erase / write cycle number and PEs difference is less than a threshold value T, and selecting a free block D2 whose erase / write cycle number is the smallest according to the wear leveling requirement; S06, according to the erase and write cycle number and data retention time of the block to be recovered S, check the table to determine its corresponding copyback threshold THcb; S07, compare the page copyback times CBs of the block to be recovered S with the copyback threshold THcb. If the copyback times CBs of the block to be recovered are less than the copyback threshold THcb, perform a copyback operation from block S to D1, and increase the copyback count by one; if the copyback times CBs of the block to be recovered are greater than the copyback threshold THcb, perform a read / write command operation from block S to D2 through LDPC, and clear the copyback count; S08. Repeat step S07 until the recycling is completed.

2. The flash memory data migration method according to claim 1, characterized in that: The process of obtaining a two-dimensional data table of erase and write cycle times and data retention time through experiments is as follows: S11, select NAND particles, confirm their activation energy, and calculate the temperature acceleration coefficient according to the Arrhenius model; S12, placing the NAND in a temperature box, setting the number of erase and write cycles, adjusting the temperature of the temperature box to t degrees Celsius, keeping the NAND at t degrees Celsius for a period of time, reading the data in the NAND multiple times during the period, and checking the number of error bits through LDPC until the number of error bits exceeds the upper limit of the LDPC error correction capability, taking the time and temperature acceleration coefficient at this time to calculate the data retention time; S13, repeatedly perform step S12, traverse the number of erase and write cycles from 0 to the end of the life of the NAND according to the erase and write cycle interval T1, and traverse the temperature from 25 degrees Celsius to 85 degrees Celsius according to the temperature interval T2, and obtain a two-dimensional data table of the number of erase and write cycles and the data retention time; S14, fitting and reducing the data in step S13, and merging similar data.

3. The flash memory data migration method according to claim 1, characterized in that: The process of obtaining the maximum number of executable copyback times within each erase-write cycle range through experiments is as follows: S21, select a NAND block X with N erase cycles, encode the randomized data through LDPC, write it into a NAND WL, and repeat the writing until a NAND block is full; S22, selecting a NAND block Y with the same or similar erase cycle number as N, reading the data written in step S21, performing LDPC error detection and recording the number of error bits, and writing the data without LDPC error correction into NAND block Y through a copyback command; S23, repeat step S22 until the number of error bits exceeds the upper limit of LDPC error correction capability; S24, repeating steps S21 to S23, traversing the erase and write cycle times from 0 to the end of the NAND life according to the erase and write cycle times interval T1, and obtaining an error bit value table that changes with the erase and write cycle times; S25, combining and reducing the data obtained in step S24 to obtain the maximum number of copybacks that can be executed within the range of each erase-write cycle number, that is, if the copyback operation is performed again, the number of error bits will exceed the upper limit of LDPC error correction.

4. The flash memory data migration method according to claim 1, characterized in that: In step S07, user data written by the host in the flash storage system is placed separately on one block, and data written by garbage collection is placed separately on another block, that is, the data newly written by the host and the garbage collection do not use the same target block.

5. The flash memory data migration method according to claim 2 or 3, characterized in that: When each block is erased, the number of erase and write cycles is recorded in the system table. When each block is written, the global data retention time of the current system is recorded. The global data retention time is obtained by periodically obtaining the NAND temperature and calculating and integrating it according to the Arrhenius model.

6. The flash memory data migration method according to claim 3, characterized in that: Each time a copyback operation is performed, the number of copybacks is recorded.

7. The flash memory data migration method according to claim 3, characterized in that: The number of erase and write cycles, data retention time when the block is written, and global data retention time are recorded in the memory table and written to the pSLC before the system is powered off. For the page copyback times, only the data of the current recycled block is saved in the memory table, and the non-current block data is stored in the pSLC.

8. The flash memory data migration method according to claim 2, characterized in that: The erase and write cycle interval T1 is 100 times, and the temperature interval T2 is 1 degree Celsius.

9. The flash memory data migration method according to claim 3, characterized in that: The erase and write cycle interval T1 is 100 times.

10. The flash memory data migration method according to claim 3, characterized in that: The difference in the number of erase and write cycles between NAND blocks Y and NAND blocks Y does not exceed 50 times.

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