An Inline ECC Implementation System

Abstract

The present invention relates to storage system optimization, and particularly to an Inline ECC implementation system. The AXI port arbitration unit completes arbitration for multiple AXI ports; the address mapping unit completes the mapping of the AXI system address to the DRAM address, as well as the generation and distribution of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; the task scheduling unit completes the caching and scheduling of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; the command decoding unit completes command decoding and converts the commands into standard DFI interface signals; the data verification unit completes read data verification and write data verification. The technical solution provided by the present invention can effectively overcome the defect of low read and write DRAM efficiency in Inline ECC existing in the prior art.

Description

Technical Field

[0001] The present invention relates to storage system optimization, and particularly to an Inline ECC implementation system. Background Art

[0002] Memory subsystems can experience errors due to design faults, defects, or electrical noise in any component. These errors are classified into hard errors (caused by design faults and defects) and soft errors (caused by system noise or bit flips in the memory array due to alpha rays, etc.). Most memory errors are caused by large memory arrays becoming increasingly dense to shrink the process node. Therefore, implementing end-to-end protection from the controller to DRAM is very necessary to improve the overall stability of the memory subsystem.

[0003] End-to-end protection allows the system to continue running when correctable errors occur, while recording detailed information about uncorrectable errors for future debugging. Inline ECC is a type of end-to-end protection. In Inline ECC, ECC data is stored on the same DRAM as the actual data. Due to this characteristic, the read DRAM commands sent by the controller need to be decomposed into read DRAM data commands and read DRAM ECC data commands, and the write DRAM commands need to be decomposed into write DRAM data commands and write DRAM ECC data commands, which results in a sharp decline in the read and write DRAM efficiency. Summary of the Invention

[0004] In view of the above-mentioned drawbacks of the prior art, the present invention provides an Inline ECC implementation system, which can effectively overcome the defect of low read and write DRAM efficiency in Inline ECC of the prior art.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0006] An Inline ECC implementation system includes the following units:

[0007] AXI port arbitration unit, which completes multi-AXI port arbitration;

[0008] Address mapping unit, which completes the mapping from AXI system address to DRAM address, as well as the generation and distribution of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands;

[0009] Task scheduling unit, which completes the caching and scheduling of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands;

[0010] The command decoding unit completes command decoding and converts the command into a standard DFI interface signal;

[0011] The data verification unit completes read data verification and write data verification.

[0012] Preferably, the address mapping unit includes the following modules:

[0013] The address mapping module ADDR MAP maps the addresses of the read command RD CMD and the write command WR CMD from the AXI system address to the DRAM address. At the same time, according to the address situation of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit, it generates the read-modify-write command RMW, generates the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD according to the read command RD CMD, and generates the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECCCMD according to the write command WR CMD, and allocates the generated commands to the task scheduling unit;

[0014] The DRAM data correction module CORRECTOR generates a read command RD CMD by the internal address generator and caches the read command RD CMD in the internal COR RD CMD FIFO. When the first command cache module RD Page FIFO, the second command cache module WR Page FIFO, and the third command cache module WR ECC CMD Reg are all empty, it sends the cached read command RD CMD to the address mapping module ADDRMAP.

[0015] Preferably, the address mapping module ADDR MAP includes the following modules:

[0016] The read-modify-write command generation module RMW GEN converts the read command RD CMD / write command WR CMD into a read-modify-write command RMW when the AXI system address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit is not aligned with the 64-bit data or the data bytes in the 64-bit data are masked. This command is decomposed by the address mapping module ADDR MAP into two read commands RD CMD and write commands WR CMD with the same and aligned addresses;

[0017] The command generation module ECC CMD GEN generates a read DRAM command RD DATA CMD and a read DRAM ECC command RD ECC CMD based on the read command RD CMD generated by the AXI port arbitration unit, the read command RD CMD generated by the DRAM data correction module CORRECTOR, or the read command RDCMD decomposed by the address mapping module ADDR MAP. It generates a write DRAM command WR DATA CMD and a write DRAM ECC command WR ECC CMD based on the write command WR CMD generated by the AXI port arbitration unit or the write command WR CMD decomposed by the address mapping module ADDR MAP;

[0018] The command distribution module BLOCK MAP distributes the commands generated by the command generation module ECC CMD GEN to the task scheduling unit.

[0019] Preferably, when the command distribution module BLOCK MAP receives a read command RD CMD with a block address of X, if there already exists a channel with a block address of X, and both the read command RD CMD indication flag Read and the channel valid flag valid are 1, then the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD generated according to the read command RD CMD, and the block label Btoken already allocated to this channel, to the first command cache module RD Page FIFO;

[0020] When the command distribution module BLOCK MAP receives a read command RD CMD with a block address of X, if there already exists a channel with a block address of X, and the read command RD CMD indication flag Read is 0 and the channel valid flag valid is 1, then set the read command RD CMD indication flag Read to 1. In the order of first sending the read DRAM ECC command RD ECC CMD and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, and the block label Btoken already allocated to this channel, to the first command cache module RD Page FIFO;

[0021] When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, but there is a channel with the channel valid flag valid being 0, use this channel, allocate a new block label Btoken, set both the read command RD CMD indication flag Read and the channel valid flag valid to 1, and in the order of first sending the read DRAM ECC command RD ECC CMD and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to this read command RD CMD, as well as the newly allocated block label Btoken to the first command cache module RD Page FIFO;

[0022] When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD and the channel valid flags valid of all channels are 1, then overwrite the channel pointed to by the write pointer wp, allocate a new block label Btoken, set both the read command RD CMD indication flag Read and the channel valid flag valid to 1, and in the order of first sending the read DRAM ECC command RD ECC CMD and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to this read command RD CMD, as well as the newly allocated block label Btoken to the first command cache module RDPage FIFO, and at the same time increment the write pointer wp by 1.

[0023] Preferably, when the command allocation module BLOCK MAP receives a write command WR CMD, and the block address of this command is X, if there already exists a channel with the block address X and both the write command WR CMD indication flag Write and the channel valid flag valid are 1, then the address mapping module ADDR MAP will send the write DRAM command WRDATA CMD generated according to this write command WR CMD, as well as the block label Btoken already allocated to this channel to the second command cache module WR PageFIFO;

[0024] When the command allocation module BLOCK MAP receives a write command WR CMD, and the block address of this command is X. If there already exists a channel with the block address X, and the write command WR CMD indicates that the Write flag is 0 and the channel valid flag valid is 1, then set the write command WR CMD's Write flag to 1. In the order of first sending the write DRAM command WR DATA CMD and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP will generate the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD according to this write command WR CMD, and send them together with the block label Btoken already allocated to this channel to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg;

[0025] When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, but there exists a channel with the channel valid flag valid being 0, use this channel, allocate a new block label Btoken, set both the write command WR CMD's Write flag and the channel valid flag valid to 1. In the order of first sending the write DRAM command WR DATA CMD and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP will generate the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD according to this write command WR CMD, and send them together with the newly allocated block label Btoken to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg;

[0026] When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD and the channel valid flags valid of all channels are 1, it will overwrite the channel pointed to by the write pointer wp, allocate a new block label Btoken, set both the write command WR CMD indication flag Write and the channel valid flag valid to 1. In the order of first sending the write DRAM command WR DATA CMD and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP will send the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg. At the same time, the write pointer wp is incremented by 1.

[0027] Preferably, the command allocation module BLOCK MAP includes 16 channels. The channel structure has a write pointer wp for indicating the channel to be overwritten. The structure of each channel is the same and specifically includes: block address, block label Btoken, read command RD CMD indication flag Read, write command WR CMD indication flag Write, channel valid flag valid.

[0028] After the command allocation module BLOCK MAP is reset, the channel valid flags valid of all channels are invalid, that is, valid = 0. At the same time, the write pointer wp points to the first channel Channel 0.

[0029] Preferably, the task scheduling unit includes the following modules:

[0030] The first command cache module RD Page FIFO caches the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD, and caches the commands in the corresponding FIFO according to the Page information of the commands.

[0031] The second command cache module WR Page FIFO caches the write DRAM command WR DATA CMD and caches the commands in the corresponding FIFO according to the Page information of the commands.

[0032] The third command cache module, WR ECC CMD Reg, caches the write DRAM ECC command, WR ECC CMD. The write DRAM ECC command, WR ECC CMD, can only be sent after the write DRAM command, WR DATA CMD, with the same block tag, Btoken, has been sent. The commands with the same block tag, Btoken, in the third command cache module, WR ECC CMD Reg, are merged in the order of the corresponding write DRAM commands, WR DATA CMD, that have been sent.

[0033] The task scheduling module, Task SCH, schedules the commands cached in the first command cache module, RD Page FIFO, the second command cache module, WR Page FIFO, and the third command cache module, WR ECC CMD Reg, according to their priorities. It first schedules all the commands corresponding to the block tag, Btoken, of the covered channels in the command allocation module, BLOCK MAP. Secondly, it schedules the read DRAM commands, RD DATA CMD, the read DRAM ECC commands, RD ECC CMD, and the write DRAM commands, WR DATA CMD, corresponding to the block tag, Btoken, of the uncovered channels in the command allocation module, BLOCK MAP. Finally, it schedules the write DRAM ECC commands, WR ECC CMD.

[0034] Preferably, 1 Page is a storage page of the DRAM. 1 Page is divided into 8 equal parts. The first 7 equal parts of 1 Page are used to store data, where each part is 1 block. 1 block is the data size of eight burst transmissions. 1 block is divided into 8 equal parts, and each equal part in 1 block is 1 access. 1 access is the data size of one burst transmission.

[0035] The last equal part of 1 Page is used to store the data check code, ECC. 1 block of data corresponds to 1 data check code, ECC.

[0036] Preferably, the command decoding unit includes the following modules:

[0037] The main state machine, Main FSM, controls the mode switching of the controller, caches the commands scheduled by the task scheduling module, Task SCH, and decodes the commands.

[0038] The command selection module, CMD MUX, switches between the commands decoded by the main state machine, Main FSM, the Active commands, and the Precharge commands.

[0039] The data cache module, i.e., WR Buffer, caches the write data of the write DRAM command, i.e., WR DATA CMD;

[0040] The fourth command cache module, i.e., CMD Buffer, caches the commands selected by the command selection module, i.e., CMD MUX;

[0041] The command decoding module, i.e., CMD decode, decodes the commands cached in the fourth command cache module, i.e., CMD Buffer, into standard DFI interface signals and sends them to the physical interface conversion module, i.e., PHY, to complete the conversion of digital interface signals to analog interface signals.

[0042] Preferably, the data verification unit includes the following modules:

[0043] The write data encoding module, i.e., ENCODER, calculates the corresponding data verification code, i.e., ECC, based on the write data of the write DRAM command, i.e., WR DATA CMD, to obtain the write data verification code, i.e., WR DATA ECC, corresponding to the write DRAM ECC command, i.e., WR ECC CMD;

[0044] The write data cache module, i.e., WECC REG, caches the write data verification code, i.e., WR DATA ECC, generated by the write data encoding module, i.e., ENCODER. When the write DRAM ECC command, i.e., WR ECC CMD, is to be sent, if the write data verification code, i.e., WR DATA ECC, with the same block label, i.e., Btoken, as this command is already ready at this time, and there is a read data verification code, i.e., RECC DATA, with the same block label, i.e., Btoken, in the read data cache module, i.e., RECC REG, then the write data corresponding to the write DRAM ECC command, i.e., WR ECC CMD, is the concatenated data of the write data verification code, i.e., WR DATA ECC, and the read data verification code, i.e., RECC DATA, with the same block label, i.e., Btoken. At the same time, the write DRAM ECC command, i.e., WR ECC CMD, is converted into a complete burst command;

[0045] The label cache module, i.e., RD token FIFO, caches the labels of the read DRAM command, i.e., RD DATA CMD. When the read data corresponding to the read DRAM command, i.e., RD DATA CMD, returns, the corresponding label is popped. This label includes the AXI token and the block label, i.e., Btoken;

[0046] The read data decoding module, i.e., DECODER, calculates the corresponding data verification code, i.e., ECC, based on the read data of the read DRAM command, i.e., RD DATA CMD, to obtain the read data verification code, i.e., RD DATA ECC, and sends it to the comparator, i.e., COMP;

[0047] In the read data cache module RECC REG, in the case of read-after-write with the same block label Btoken command, the internal data may have expired. The read data error correction code RECC DATA in the read data cache module RECC REG is concatenated with the write data error correction code WR DATA ECC in the write data cache module WECC REG and sent to the comparator COMP. At the same time, the write data error correction code WR DATA ECC in the write data cache module WECC REG is updated to the read data error correction code RECC DATA in the read data cache module RECC REG.

[0048] The comparator COMP compares the read data error correction code RD DATA ECC sent by the read data decoding module DECODER with the read data error correction code RECC DATA sent by the read data cache module RECC REG.

[0049] Compared with the prior art, an Inline ECC implementation system provided by the present invention can merge multiple read DRAM ECC data commands and write DRAM ECC data commands, send the write DRAM ECC data command in the idle state of the system, and at the same time solve the related problems existing in the read DRAM ECC data command and the write DRAM ECC data command. When the system is idle and there is no write DRAM ECC data command, it will also regularly send a read DRAM data command to verify the read-back DRAM data. If there are correctable errors in the read-back DRAM data, the corrected data will be written back to the DRAM. While greatly improving the read and write efficiency of the DRAM, the system effectively improves the overall stability of the memory subsystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0051] Figure 1 It is a schematic diagram of the system of the present invention;

[0052] Figure 2 It is a schematic diagram of the structure of the command allocation module BLOCK MAP in the present invention;

[0053] Figure 3 It is a schematic diagram of the address mapping of a Page in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0055] An Inline ECC implementation system, as Figure 1 shown, includes the following units:

[0056] AXI port arbitration unit, which completes multi-AXI port arbitration;

[0057] Address mapping unit, which completes the mapping of AXI system addresses to DRAM addresses, and the generation and distribution of read DRAM commands, read DRAM ECC commands, write DRAM commands and write DRAM ECC commands;

[0058] Task scheduling unit, which completes the caching and scheduling of read DRAM commands, read DRAM ECC commands, write DRAM commands and write DRAM ECC commands;

[0059] Command decoding unit, which completes command decoding and converts commands into standard DFI interface signals;

[0060] Data verification unit, which completes read data verification and write data verification.

[0061] ① As Figure 1 shown, the address mapping unit includes the following modules:

[0062] Address mapping module ADDR MAP, which maps the addresses of read commands RD CMD and write commands WR CMD from AXI system addresses to DRAM addresses, and generates read-modify-write commands RMW according to the address conditions of the read commands RD CMD / write commands WR CMD generated by the AXI port arbitration unit, generates read DRAM commands RD DATA CMD and read DRAM ECC commands RD ECC CMD according to the read commands RD CMD, generates write DRAM commands WR DATA CMD and write DRAM ECC commands WR ECCCMD according to the write commands WR CMD, and distributes the generated commands to the task scheduling unit;

[0063] The DRAM data correction module CORRECTOR, the internal address generator generates a read command RD CMD, and caches the read command RD CMD in the internal COR RD CMD FIFO. When the first command cache module RD Page FIFO, the second command cache module WR Page FIFO, and the third command cache module WR ECC CMD Reg are all empty, it sends the cached read command RD CMD to the address mapping module ADDRMAP.

[0064] Specifically, as Figure 1 shown, the address mapping module ADDR MAP includes the following modules:

[0065] The read-modify-write command generation module RMW GEN, when the AXI system address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit is not aligned with the 64-bit data or the data bytes in the 64-bit data are masked, converts the read command RD CMD / write command WR CMD into a read-modify-write command RMW, and this command is decomposed by the address mapping module ADDR MAP into two read commands RD CMD and write commands WR CMD with the same and aligned addresses;

[0066] The command generation module ECC CMD GEN generates a read DRAM command RD DATA CMD and a read DRAM ECC command RD ECC CMD according to the read command RD CMD generated by the AXI port arbitration unit or the read command RD CMD generated by the DRAM data correction module CORRECTOR or the read command RDCMD decomposed by the address mapping module ADDR MAP, and generates a write DRAM command WRDATA CMD and a write DRAM ECC command WR ECC CMD according to the write command WR CMD generated by the AXI port arbitration unit or the write command WR CMD decomposed by the address mapping module ADDR MAP;

[0067] The command distribution module BLOCK MAP distributes the commands generated by the command generation module ECC CMD GEN to the task scheduling unit.

[0068] Specifically, for the command distribution module BLOCK MAP:

[0069] When the command distribution module BLOCK MAP receives a read command RD CMD, the block address of this command is X. If there already exists a channel with the block address X, and both the read indication flag Read and the channel valid flag valid of the read command RD CMD are 1, then the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD generated according to this read command RD CMD, as well as the block label Btoken already allocated to this channel, to the first command buffer module RD Page FIFO;

[0070] When the command distribution module BLOCK MAP receives a read command RD CMD, the block address of this command is X. If there already exists a channel with the block address X, and the read indication flag Read of the read command RD CMD is 0 while the channel valid flag valid is 1, then set the read indication flag Read of the read command RD CMD to 1. In the order of first sending the read DRAM ECC command RD ECC CMD and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to this read command RD CMD, as well as the block label Btoken already allocated to this channel, to the first command buffer module RD Page FIFO;

[0071] When the command distribution module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, but there exists a channel with the channel valid flag valid being 0, use this channel, allocate a new block label Btoken, set both the read indication flag Read and the channel valid flag valid of the read command RD CMD to 1. In the order of first sending the read DRAM ECC command RD ECC CMD and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECCCMD generated according to this read command RD CMD, as well as the newly allocated block label Btoken, to the first command buffer module RD Page FIFO;

[0072] When the command distribution module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD and the channel valid flags valid of all channels are 1, it will overwrite the channel pointed to by the write pointer wp, allocate a new block label Btoken, set both the read command RD CMD indication flag Read and the channel valid flag valid to 1. In the order of first sending the read DRAM ECC command RD ECC CMD and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP will send the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to this read command RD CMD, as well as the newly allocated block label Btoken to the first command cache module RDPage FIFO, and at the same time increment the write pointer wp by 1;

[0073] When the command distribution module BLOCK MAP receives a write command WR CMD, and the block address of this command is X, if there already exists a channel with the block address X and both the write command WR CMD indication flag Write and the channel valid flag valid are 1, the address mapping module ADDR MAP will send the write DRAM command WR DATA CMD generated according to this write command WR CMD, as well as the block label Btoken already allocated to this channel to the second command cache module WR Page FIFO;

[0074] When the command distribution module BLOCK MAP receives a write command WR CMD, and the block address of this command is X, if there already exists a channel with the block address X and the write command WR CMD indication flag Write is 0 and the channel valid flag valid is 1, it will set the write command WR CMD indication flag Write to 1. In the order of first sending the write DRAM command WR DATA CMD and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP will send the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to this write command WR CMD, as well as the block label Btoken already allocated to this channel to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg;

[0075] When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, but there is a channel with the channel valid flag valid being 0, use this channel, and allocate a new block label Btoken. Set both the write command WR CMD indication flag Write and the channel valid flag valid to 1. In the order of first sending the write DRAM command WR DATA CMD and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP will send the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to this write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg;

[0076] When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD and the channel valid flags valid of all channels are 1, then overwrite the channel pointed to by the write pointer wp, and allocate a new block label Btoken. Set both the write command WR CMD indication flag Write and the channel valid flag valid to 1. In the order of first sending the write DRAM command WR DATA CMD and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP will send the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to this write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg, and at the same time increment the write pointer wp by 1.

[0077] As Figure 2 shown, the command allocation module BLOCK MAP includes 16 channels. The channel structure has a write pointer wp for indicating the channel to be overwritten. The structure of each channel is the same and specifically includes: block address, block label Btoken, read command RD CMD indication flag Read, write command WR CMD indication flag Write, channel valid flag valid;

[0078] After the command allocation module BLOCK MAP is reset, the channel valid flags valid of all channels are invalid, that is, valid = 0, and at the same time the write pointer wp points to the first channel Channel 0.

[0079] ②As shown Figure 1 in the figure, the task scheduling unit includes the following modules:

[0080] The first command cache module, RD Page FIFO, caches the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD, and caches the commands in the corresponding FIFO according to the Page information of the commands;

[0081] The second command cache module, WR Page FIFO, caches the write DRAM command WR DATA CMD, and caches the commands in the corresponding FIFO according to the Page information of the commands;

[0082] The third command cache module, WR ECC CMD Reg, caches the write DRAM ECC command WR ECC CMD. The write DRAM ECC command WR ECC CMD can be sent only after the write DRAM command WR DATA CMD with the same block tag Btoken has been sent. The commands with the same block tag Btoken in the third command cache module WR ECC CMD Reg are merged in the order of the corresponding write DRAM commands WR DATA CMD that have been sent;

[0083] The task scheduling module, Task SCH, schedules the commands cached in the first command cache module RD Page FIFO, the second command cache module WR Page FIFO, and the third command cache module WR ECC CMD Reg according to the priority. It preferentially schedules all the commands corresponding to the block tag Btoken of the covered channel in the command allocation module BLOCK MAP, then schedules the read DRAM command RD DATA CMD, the read DRAM ECC command RD ECC CMD, and the write DRAM command WR DATA CMD corresponding to the block tag Btoken of the uncovered channel in the command allocation module BLOCK MAP, and finally schedules the write DRAM ECC command WR ECC CMD.

[0084] As shown Figure 3 in the figure, 1 Page is a storage page of DRAM. 1 Page is divided into 8 equal parts. The first 7 equal parts of 1 Page are used to store data. Each part is 1 block. 1 block is the data size of eight burst transmissions. 1 block is divided into 8 equal parts. Each equal part in 1 block is 1 access. 1 access is the data size of one burst transmission;

[0085] The last equal part in one Page is used to store the data check code ECC, and one data check code ECC corresponds to the data of one block.

[0086] ③ As Figure 1 shown, the command decoding unit includes the following modules:

[0087] The main state machine Main FSM controls the mode switching of the controller, schedules the commands dispatched by the cache task scheduling module Task SCH, and decodes the commands.

[0088] The command selection module CMD MUX switches between the commands decoded by the main state machine Main FSM, the Active command, and the Precharge command.

[0089] The data cache module WR Buffer caches the write data of the write DRAM command WR DATA CMD.

[0090] The fourth command cache module CMD Buffer caches the commands selected by the command selection module CMD MUX.

[0091] The command decoding module CMD decode decodes the commands cached in the fourth command cache module CMD Buffer into standard DFI interface signals and sends them to the physical interface conversion module PHY to complete the conversion from digital interface signals to analog interface signals.

[0092] ④ As Figure 1 shown, the data check unit includes the following modules:

[0093] The write data encoding module ENCODER calculates the corresponding data check code ECC according to the write data of the write DRAM command WR DATA CMD to obtain the write data data check code WR DATA ECC corresponding to the write DRAM ECC command WR ECC CMD.

[0094] Write Data Cache Module WECC REG caches the write data data check code WR DATA ECC generated by the cache write data encoding module ENCODER. When sending a write DRAM ECC command WR ECC CMD, if the write data data check code WR DATA ECC with the same block label Btoken as this command is already ready at this time, and there is a read data data check code RECC DATA with the same block label Btoken in the read data cache module RECC REG, then the write data corresponding to the write DRAM ECC command WR ECC CMD is the concatenated data of the write data data check code WR DATA ECC and the read data data check code RECC DATA with the same block label Btoken. At the same time, the write DRAM ECC command WR ECC CMD is converted into a complete burst command;

[0095] Label Cache Module RD token FIFO caches the label of the read DRAM command RD DATA CMD. When the read data corresponding to the read DRAM command RD DATA CMD returns, the corresponding label is popped. This label includes the AXI token and the block label Btoken;

[0096] Read Data Decoding Module DECODER calculates the corresponding data check code ECC according to the read data of the read DRAM command RD DATA CMD, obtains the read data data check code RD DATA ECC, and sends it to the comparator COMP;

[0097] Read Data Cache Module RECC REG. In the case of read-after-write for commands with the same block label Btoken, the internal data may have expired. The read data data check code RECC DATA in the read data cache module RECC REG is concatenated with the write data data check code WR DATA ECC in the write data cache module WECC REG and sent to the comparator COMP. At the same time, the write data data check code WR DATA ECC in the write data cache module WECC REG is updated to the read data data check code RECC DATA in the read data cache module RECC REG;

[0098] Comparator COMP compares the read data data check code RD DATA ECC sent by the read data decoding module DECODER with the read data data check code RECC DATA sent by the read data cache module RECC REG.

[0099] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An Inline ECC implementation system, characterized by: The following units are included: AXI port arbitration unit, completes multi-AXI port arbitration; The address mapping unit completes the mapping of AXI system addresses to DRAM addresses, as well as the generation and allocation of read DRAM commands, read DRAM ECC commands, write DRAM commands, and write DRAM ECC commands; A task scheduling unit, which completes the caching and scheduling of a read DRAM command, a read DRAM ECC command, a write DRAM command, and a write DRAM ECC command. The task scheduling unit includes a task scheduling module Task SCH; The command decoding unit completes command decoding and converts the command into a standard DFI interface signal. The command decoding unit includes a main state machine Main FSM, which controls the controller mode switching, caches the commands scheduled by the task scheduling module Task SCH, and decodes the commands; The data verification unit calculates the corresponding data verification code ECC according to the write data of the write DRAM command WR DATA CMD, obtains the write data verification code WR DATA ECC corresponding to the write DRAM ECC command WR ECC CMD, calculates the corresponding data verification code ECC according to the read data of the read DRAM command RDDATA CMD, obtains the read data verification code RD DATA ECC, and completes the read data verification and the write data verification; The address mapping unit comprises: The address mapping module ADDR MAP maps the addresses of the read command RD CMD and the write command WR CMD from the AXI system address to the DRAM address, and generates a read-modify-write command RMW according to the address of the read command RD CMD / write command WR CMD generated by the AXI port arbitration unit, generates a read DRAM command RD DATA CMD and a read DRAM ECC command RDECC CMD according to the read command RD CMD, generates a write DRAM command WR DATA CMD and a write DRAM ECC command WR ECC CMD according to the write command WR CMD, and distributes the generated commands to the task scheduling unit; The address mapping module ADDR MAP includes the following modules: The read-modify-write command generating module RMW GEN converts the read command RDCMD / write command WR CMD into a read-modify-write command RMW when the AXI system address of the read command RD CMD / write command WRCMD generated by the AXI port arbitration unit is not aligned with the 64-bit data or the data bytes in the 64-bit data are masked. The read-modify-write command RMW is decomposed by the address mapping module ADDR MAP into two read commands RD CMD and write commands WR CMD with the same and aligned addresses; The command generation module ECC CMD GEN generates a DRAM read command RD DATA CMD and a DRAM ECC read command RD ECC CMD according to the read command RD CMD generated by the AXI port arbitration unit or the read command RD CMD generated by the DRAM data correction module CORRECTOR or the read command RD CMD decomposed by the address mapping module ADDR MAP, and generates a DRAM write command WR DATACMD and a DRAM ECC write command WR ECC CMD according to the write command WR CMD generated by the AXI port arbitration unit or the write command WR CMD decomposed by the address mapping module ADDR MAP; The command allocation module BLOCK MAP allocates the commands generated by the command generation module ECC CMD GEN to the task scheduling unit.

2. The Inline ECC implementation system according to claim 1, characterized in that: The address mapping unit also includes: DRAM data correction module CORRECTOR, the internal address generator generates a read command RD CMD, and caches the read command RDCMD in the internal COR RD CMD FIFO, when the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg are all empty, the cached read command RD CMD is sent to the address mapping module ADDR MAP.

3. The Inline ECC implementation system according to claim 1, characterized in that: When the command allocation module BLOCKMAP receives a read command RD CMD, the block address of the read command RD CMD is X. If there is already a channel with the block address X, and the read command RD CMD indication flag Read and the channel valid flag valid are both 1, the address mapping module ADDRMAP sends the read DRAM command RD DATA CMD generated according to the read command RD CMD and the block tag Btoken that has been allocated to the channel with the block address X to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, the block address of the read command RD CMD is X. If there is already a channel with the block address X, and the read command RD CMD indication flag Read is 0, and the channel valid flag valid is 1, the read command RD CMD indication flag Read is set to 1, and in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, and the block tag Btoken that has been allocated to the channel with the block address X to the first command cache module RD Page FIFO; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, but there is a channel with a channel valid flag valid being 0, the channel with a channel valid flag valid being 0 is used, and a new block tag Btoken is allocated, the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the newly allocated block tag Btoken to the first command cache module RDPage FIFO in the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD; When the command allocation module BLOCK MAP receives a read command RD CMD, if there is no channel with the same block address as the read command RD CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the read command RD CMD indication flag Read and the channel valid flag valid are both set to 1. In the order of sending the read DRAM ECC command RD ECC CMD first and then sending the read DRAM command RD DATA CMD, the address mapping module ADDR MAP sends the read DRAM command RD DATA CMD and the read DRAM ECC command RD ECC CMD generated according to the read command RD CMD, as well as the newly allocated block label Btoken to the first command cache module RDPage FIFO, and the write pointer wp is incremented by 1.

4. The Inline ECC implementation system according to claim 3, characterized in that: When the command allocation module BLOCKMAP receives a write command WR CMD, the block address of the write command WR CMD is X. If there is already a channel with the block address X, and the write command WR CMD indication flag Write and the channel valid flag valid are both 1, the address mapping module ADDRMAP sends the write DRAM command WR DATA CMD generated according to the write command WR CMD and the block tag Btoken that has been allocated to the channel with the block address X to the second command cache module WR Page FIFO; When the command allocation module BLOCK MAP receives a write command WR CMD, the block address of the write command WR CMD is X. If there is already a channel with the block address X, and the write command WR CMD indication flag Write is 0, and the channel valid flag valid is 1, the write command WR CMD indication flag Write is set to 1, and in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, and the block tag Btoken that has been allocated to the channel with the block address X to the second command cache module WR Page FIFO and the third command cache module WRECC CMD Reg; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, but there is a channel with a channel valid flag valid being 0, the channel with a channel valid flag valid being 0 is used, and a new block tag Btoken is allocated, the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1, and the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the newly allocated block tag Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg in the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD; When the command allocation module BLOCK MAP receives a write command WR CMD, if there is no channel with the same block address as the write command WR CMD, and the channel valid flags valid of all channels are 1, the channel pointed to by the write pointer wp is overwritten, and a new block label Btoken is allocated, and the write command WR CMD indication flag Write and the channel valid flag valid are both set to 1. In the order of sending the write DRAM command WR DATA CMD first and then sending the write DRAM ECC command WR ECC CMD, the address mapping module ADDR MAP sends the write DRAM command WR DATA CMD and the write DRAM ECC command WR ECC CMD generated according to the write command WR CMD, as well as the newly allocated block label Btoken to the second command cache module WRPage FIFO and the third command cache module WR ECC CMD Reg, and the write pointer wp is incremented by 1.

5. The Inline ECC implementation system according to claim 1, 3 or 4, characterized in that: The command allocation module BLOCK MAP includes 16 channels. The channel structure has a write pointer wp, which is used to indicate the channel to be covered. The structure of each channel is the same, specifically including: block address block address, block tag Btoken, read command RD CMD indication flag Read, write command WR CMD indication flag Write, channel valid flag valid; After the command allocation module BLOCK MAP is reset, the channel valid flags of all channels are invalid, that is, valid=0, and the write pointer wp points to the first channel Channel 0.

6. The Inline ECC implementation system according to claim 1, characterized in that: The task scheduling unit includes the following modules: The first command buffer module RD Page FIFO buffers the DRAM read command RD DATA CMD and the DRAM ECC read command RDECC CMD, and buffers the command in the corresponding FIFO according to the Page information of the command; The second command buffer module WR Page FIFO buffers the DRAM write command WR DATA CMD and buffers the command in the corresponding FIFO according to the Page information of the command; The third command cache module WR ECC CMD Reg caches the write DRAM ECC command WR ECC CMD. The write DRAM ECC command WR ECC CMD can be sent only after the write DRAM command WR DATA CMD with the same block tag Btoken is sent. The commands with the same block tag Btoken in the third command cache module WR ECC CMD Reg are write-merged in the order of the corresponding write DRAM command WR DATA CMD that has been sent. The task scheduling module Task SCH schedules the commands cached in the first command cache module RD Page FIFO, the second command cache module WR Page FIFO and the third command cache module WR ECC CMD Reg according to the priority, and prioritizes all commands corresponding to the block tag Btoken of the covered channels in the command allocation module BLOCK MAP, and then schedules the read DRAM command RD DATACMD, read DRAM ECC command RD ECC CMD and write DRAM command WR DATA CMD corresponding to the block tag Btoken of the uncovered channels in the command allocation module BLOCK MAP, and finally schedules the write DRAM ECC command WRECC CMD.

7. The Inline ECC implementation system according to claim 6, characterized in that: 1 Page is a storage page of DRAM. 1 Page is divided into 8 equal parts. The first 7 equal parts of 1 Page are used to store data, each of which is 1 block. 1 block is the data size of eight burst transmissions. 1 block is divided into 8 equal parts. Each equal part of 1 block is 1 access. 1 access is the data size of one burst transmission. The last part of a Page is used to store the data check code ECC. The data of one block corresponds to one data check code ECC.

8. The Inline ECC implementation system according to claim 6, characterized in that: The command decoding unit also includes the following modules: The command selection module CMD MUX switches between the commands decoded by the main state machine Main FSM, Active commands, and Precharge commands; A data buffer module WR Buffer, which buffers the write data of the write DRAM command WR DATA CMD; A fourth command buffer module CMD Buffer, which buffers the command selected by the command selection module CMD MUX; The command decoding module CMD decode decodes the command buffered in the fourth command buffer module CMD Buffer into a standard DFI interface signal, and sends the signal to the physical interface conversion module PHY to complete the conversion of the digital interface signal to the analog interface signal.

9. The Inline ECC implementation system according to claim 8, characterized in that: The data verification unit includes the following modules: The write data encoding module ENCODER calculates the corresponding data check code ECC according to the write data of the write DRAM command WR DATA CMD, and obtains the write data check code WR DATA ECC corresponding to the write DRAM ECC command WR ECC CMD; The write data cache module WECC REG caches the write data check code WRDATA ECC generated by the write data encoding module ENCODER. When sending the write DRAM ECC command WR ECC CMD, if the write data check code WR DATA ECC with the same block tag Btoken as the write DRAM ECC command WR ECC CMD is ready, and the read data check code RECC DATA with the same block tag Btoken exists in the read data cache module RECC REG, then the write data corresponding to the write DRAM ECC command WR ECC CMD is the concatenated data of the write data check code WR DATA ECC with the same block tag Btoken and the read data check code RECC DATA, and at the same time, the write DRAM ECC command WR ECC CMD is converted into a complete burst command; The tag cache module RD token FIFO caches the tag of the DRAM read command RD DATA CMD. When the read data corresponding to the DRAM read command RDDATA CMD is returned, the corresponding tag is popped out. The cache tag of the DRAM read command RDDATA CMD corresponding to the returned read data includes AXI token and block tag Btoken. The read data decoding module DECODER calculates the corresponding data check code ECC according to the read data of the read DRAM command RD DATA CMD, obtains the read data check code RD DATA ECC, and sends it to the comparator COMP; The read data cache module RECC REG, in the case of a write-after-read command with the same block tag Btoken, when the internal data expires, concatenates the read data data check code RECC DATA in the read data cache module RECC REG with the write data data check code WR DATA ECC in the write data cache module WECC REG, and sends them to the comparator COMP, and at the same time, the write data data check code WR DATA ECC in the write data cache module WECC REG is updated to the read data data check code RECC DATA in the read data cache module RECCREG; The comparator COMP compares the read data check code RD DATA ECC sent by the read data decoding module DECODER with the read data check code RECC DATA sent by the read data buffer module RECC REG.

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