Quantum state preparation method and related device

Abstract

The invention discloses a quantum state preparation method and a related device, and the method comprises the steps: determining each part of component of a to-be-prepared target quantum state, and each part of component comprises a ground state of the target quantum state and the amplitude of the ground state; a plurality of target matrixes are constructed based on the amplitudes of the partial components, SVD decomposition is performed on the target matrixes to obtain a unitary matrix, deentanglement quantum logic gates are determined based on the unitary matrix, and the plurality of deentanglement quantum logic gates act on quantum bits whose initial states are target quantum states to obtain a deentanglement quantum circuit; the deentanglement quantum circuit is subjected to inverse deduction to obtain a target quantum circuit, the target quantum circuit is provided with a target quantum logic gate, and the target quantum logic gate is determined based on a conjugate transpose matrix of the unitary matrix. According to the quantum state preparation method provided by the invention, the line depth only needs an O (logn) layer, the running time of a quantum computer is compressed in a super-exponential stage, and the amplitude preparation of the quantum state can be more efficiently carried out.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing, and in particular to a quantum state preparation method and related devices. Background Art

[0002] Quantum computing is a new computing model that follows the laws of quantum mechanics to control quantum information units for computing. Unlike classical computing, quantum computing follows the laws of quantum mechanics and is a new computing model that can break through the bottleneck of classical computing power. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because they have the ability to process mathematical problems more efficiently than ordinary computers. For example, they can speed up the time to crack RSA keys from hundreds of years to hours.

[0003] In quantum computing, quantum state encoding is crucial. It is a key step in converting classical information into quantum states, enabling quantum computers to process and manipulate this information, thereby exerting the performance advantages of quantum computing. Common quantum state encoding methods include ground state encoding, amplitude encoding, angle encoding, and MPS (Matrix Product State) encoding. Among them, MPS encoding is an effective method for representing quantum states. By decomposing quantum states in the form of known wave functions into a series of local tensor products, MPS encoding can effectively prepare and represent quantum states, especially those multi-body quantum states with local entanglement properties.

[0004] Therefore, if a more general amplitude preparation of quantum states can be achieved based on the encoding method of matrix product states, it will undoubtedly have great research prospects and practical value. Summary of the invention

[0005] The purpose of the present invention is to provide a quantum state preparation method and related devices to solve the technical problems in the prior art, which can more efficiently prepare the amplitude of the quantum state.

[0006] In a first aspect, the present invention provides a method for preparing a quantum state, the method comprising:

[0007] Determining each partial component of a target quantum state to be prepared, each of the partial components comprising a ground state of the target quantum state and an amplitude of the ground state;

[0008] Based on the amplitudes of the partial components, a plurality of target matrices are constructed, and the target matrices are decomposed by SVD to obtain a unitary matrix, and a disentanglement quantum logic gate is determined based on the unitary matrix, and the plurality of disentanglement quantum logic gates act on a quantum bit whose initial state is a target quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer of action sequence;

[0009] Determining the inverse circuit of the deentangled quantum circuit as the target quantum circuit;

[0010] The target quantum circuit is operated to prepare the target quantum state.

[0011] A method as described above, wherein preferably, the action relationship between the target quantum logic gate and the quantum bit in the previous action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next action sequence, including:

[0012] In each layer of action sequence, the qubits are regrouped to form a number of qubit pairs, each qubit pair includes a first qubit and a second qubit, the first qubit is at a lower level than the second qubit, and in each layer of action sequence, each qubit pair is acted upon by a target quantum logic gate;

[0013] In the last layer of action sequence, the qubits from the lowest bit to the highest bit are grouped in sequence, and every two adjacent qubits form a qubit pair;

[0014] In other layers of action sequences, a number of the quantum bits are regrouped according to the action relationship between the target quantum logic gate and the quantum bits in the latter layer of action sequence to form a quantum bit set, wherein the quantum bits in the quantum bit set come from the first quantum bit or the second quantum bit in each of the latter quantum bit pairs, and the quantum bits in the quantum bit set are grouped in sequence from low to high to form the quantum bit pair.

[0015] A method as described above, wherein preferably, a plurality of the qubits are regrouped according to the action relationship between the target quantum logic gate and the qubit in the next layer of action sequence to form a qubit set, comprising:

[0016] The quantum bit set includes a first quantum bit set and a second quantum bit set, the quantum bits in the first quantum bit set come from the first quantum bit in each subsequent quantum bit pair, and the quantum bits in the first quantum bit set are grouped in sequence from low to high to form the quantum bit pair; the quantum bits in the second quantum bit set come from the second quantum bit in each subsequent quantum bit pair, and the quantum bits in the second quantum bit set are grouped in sequence from low to high to form the quantum bit pair.

[0017] In the method as described above, preferably, the step of constructing a plurality of target matrices based on the amplitudes of the partial components comprises:

[0018] The number of quantum bits used to prepare the target quantum state is determined based on the number of ground states of the target quantum state, and the number of quantum bits n satisfies 2 n-1 <N≤2 n , N is the number of ground states of the target quantum state.

[0019] A method as described above, wherein preferably, the constructing of multiple target matrices based on the amplitudes of the partial components comprises: for each of the action timings, based on the number of the target quantum bits acted on by the target quantum logic gate, rearranging the amplitudes of the multiple partial components into 2 2 ×2 n-2 Scale the matrix to obtain a multiple of the target matrix.

[0020] A method as described above, wherein preferably, based on the number of target quantum bits acted by the target quantum logic gate, the amplitudes of the plurality of partial components are rearranged into 2 2 ×2 n-2 A matrix of scales, including:

[0021] The amplitudes of multiple ground states of the quantum bit pairs corresponding to the positions |00>, |01>, |10>, |11) are used as the 1st, 2nd, 3rd, and 4th rows of the matrix, and the 2 2 ×2 n-2 A matrix of size 2 n-2 The amplitudes are arranged in order based on the binary representation of the corresponding ground state.

[0022] In the method as described above, preferably, the step of performing SVD decomposition on the target matrix to obtain a unitary matrix includes:

[0023] For each of the target matrices, SVD decomposition is performed on the target matrix to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and the left singular vector matrix is ​​used as the unitary matrix.

[0024] In a second aspect, the present invention provides a quantum state preparation device, the device comprising:

[0025] An acquisition module, used to determine each partial component of the target quantum state to be prepared; wherein each of the partial components includes a ground state of the target quantum state and an amplitude of the ground state;

[0026] A de-entanglement quantum circuit construction module is used to construct a de-entanglement quantum circuit, obtain multiple target matrices based on the amplitude of the partial components, and perform SVD decomposition on the target matrix to obtain a unitary matrix, determine a de-entanglement quantum logic gate based on the unitary matrix, and multiple de-entanglement quantum logic gates act on a quantum bit whose initial state is a target quantum state to obtain a de-entanglement quantum circuit, wherein the action relationship between the de-entanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the de-entanglement quantum logic gate and the quantum bit in the previous layer of action sequence;

[0027] A target quantum circuit construction module, used to determine the inverse circuit of the deentangled quantum circuit as the target quantum circuit;

[0028] An operation module is used to operate the target quantum circuit to prepare the target quantum state.

[0029] In a third aspect, the present invention provides a storage medium storing a computer program, wherein the computer program is configured to implement the aforementioned method when run.

[0030] In a fourth aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the aforementioned method.

[0031] Compared with the prior art, the quantum state preparation method provided by the present invention only requires a circuit depth of O(10gn) layers, which super-exponentially compresses the running time of the quantum computer and can more efficiently prepare the amplitude of the quantum state. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a network block diagram of a quantum circuit construction system provided by an embodiment of the present invention;

[0033] Figure 2 is a flow chart of a quantum state preparation method provided by an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of the structure of a de-entangled quantum circuit provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the structure of a target quantum circuit provided by an embodiment of the present invention;

[0036] Figure 5 A flowchart of an SVD decomposition method provided by an embodiment of the present invention;

[0037] Figure 6 A schematic structural diagram of a quantum state preparation device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0039] [Structure of the quantum circuit construction system]

[0040] Figure 1 1 is a network block diagram of a quantum circuit construction system provided in an embodiment of the present application. The quantum circuit construction system may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0041] The network 110 is a medium for providing communication links between various devices and computers connected together in the quantum circuit construction system, including but not limited to the Internet, corporate intranet, local area network, mobile communication network and their combination. The connection method can be wired, wireless communication links or optical fiber cables.

[0042] The server 120 and the client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0043] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 162 (application 173). The application 162 (application 173) may be used to implement a quantum algorithm compiled according to the quantum circuit construction method provided in an embodiment of the present application.

[0044] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0045] It should be noted that a true quantum computer is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum calculations.

[0046] The classical processing system 160 and the quantum processing system 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum applications through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer measurement and control system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0047] In the classic processing system 160 based on silicon chips, the unit of the classic processor 161 is a CMOS tube. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and is available at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. At present, the number of computing units in a classic processor is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, for example: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0048] Unlike this logic unit in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. Making full use of the quantum bit within the available use time of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical functions to achieve the computing effect.

[0049] Based on these differences, the design of the logical function on the quantum bit (including the design of whether the quantum bit is used and the design of the efficiency of each quantum bit) is the key to improving the computing performance of quantum computers, and requires special design. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face.

[0050]

Quantum state preparation method

[0051] In the field of quantum computing, amplitude coding is a method of encoding classical data into quantum state amplitudes. In amplitude coding, the number of quantum states that can be represented by a given n qubits (i.e., the number of states that can be amplitude-encoded) is 2. n For n qubits, all possible quantum states they can represent are a 2 n dimensional complex vector space. Specifically, the number of all ground states that can be represented by n qubits is 2 n These ground states can be written as |0>, |1>, |2>, ..., |2 n -1> or in the form of binary numbers, such as the ground state of 6 quantum bits is represented by |000000>, |000001), ..., |111111>, etc., without specific limitation here.

[0052] First, define the quantum state amplitude on n quantum bits First, the amplitude is reorganized into four rows, which is to correspond to the fourth-order unitary matrix of the double quantum gate. The matrix composed of four rows is as follows:

[0053]

[0054] For this scale of 4×2 n-2 The matrix is ​​decomposed by SVD. SVD decomposition (Singular Value Decomposition, referred to as SVD) is a matrix decomposition technique widely used in numerical linear algebra. It reveals many important properties of the original matrix by decomposing a matrix into the product of three matrices.

[0055] After performing SVD decomposition on a target matrix A, we can obtain the multiplied left singular vector matrix U, singular value matrix S and right singular vector matrix The left singular vector matrix U is an orthogonal matrix, and its column vectors are the left singular vectors of the target matrix A, indicating the direction of the target matrix A after acting on the standard orthogonal vectors. In one embodiment, the left singular vector matrix U can be used as the unitary matrix, so that the de-entanglement quantum logic gates corresponding to the multiple unitary matrices work together to evolve the target quantum state |ψ> into |0> n state.

[0056] By performing SVD decomposition on the aforementioned fourth-order unitary matrix, we can obtain the unitary matrix U 12 And SV, through SVD decomposition, has low rank characteristics, that is, the last two diagonal elements of the diagonal matrix S can be ignored compared to the first two diagonal elements. At this time, the last two singular values ​​are truncated, and U1 is applied to the quantum circuit. The front of the remaining quantum state SV can be similar to 4×2 n-2 The matrix of S can be regarded as a rearrangement of quantum states, and due to the low-rank nature of S, the last two rows can be regarded as 0, and the information is only concentrated in the first two rows. The first two rows only have two cases, | 00> and | 01>, which means that the first quantum bit can be directly regarded as the | 0> state without consideration.

[0057] The above operation uses the first two quantum bits as indicators to rearrange the quantum state amplitude. For other quantum bits, the same method can be used to re-shoot the quantum state. For example, the 3rd and 4th bits are used as subscripts. The result of re-shooting the quantum state is to arrange the |··00…>, |··01…>, |··10…>, |··11…> quantum states in rows, and then perform SVD decomposition to obtain the unitary matrix U 34 , can act on the rearrangement amplitude, and the third quantum bit can be approximated to the |0> state.

[0058] The embodiment provided by the present invention assumes that the initial state of a certain de-entangled quantum circuit is the target quantum state to be prepared. Then, by de-entanglement and approximate truncation of the target quantum state |ψ>, a quantum circuit that evolves the target quantum state |ψ> to the |0> state can be obtained. The above steps are classical processing procedures and can be implemented using a quantum simulator.

[0059] Furthermore, the inverse circuit of the above-mentioned deentanglement quantum circuit can be constructed to obtain the target quantum circuit, run the target quantum circuit and act on the quantum bit with the initial state of |0>, so as to realize the approximate preparation of the target quantum state |ψ> on the real quantum chip.

[0060] In a feasible implementation mode, referring to Figure 2 As shown, the present invention provides a method for preparing a quantum state, comprising the following steps:

[0061] Step S101: determining each partial component of a target quantum state to be prepared, each partial component including a ground state of the target quantum state and an amplitude of the ground state.

[0062] The target quantum state to be prepared is For example, it includes 2 n partial components, each of which includes a ground state |x> of the target quantum state |ψ> and the amplitude α corresponding to the ground state x , that is, the number of ground states N of the target quantum state |ψ> satisfies N=2 n , where the sum of the squares of the amplitudes of each ground state is 1, that is,

[0063] Step S102: construct multiple target matrices based on the amplitudes of some components, and perform SVD decomposition on the target matrices to obtain unitary matrices, determine deentanglement quantum logic gates based on the unitary matrices, and act on quantum bits whose initial states are target quantum states to obtain deentanglement quantum circuits, wherein the action relationship between the deentanglement quantum logic gates and the quantum bits in the latter layer of action sequence is determined by the action relationship between the deentanglement quantum logic gates and the quantum bits in the previous layer of action sequence.

[0064] Among them, the de-entanglement quantum logic gate is determined based on the unitary matrix obtained by decomposition, and multiple de-entanglement quantum logic gates act on the quantum bits whose initial state is the target quantum state to obtain the de-entanglement quantum circuit, which is used to evolve the target quantum state into |0> n state.

[0065] Specifically, based on the idea of ​​disentanglement, the amplitudes of the various partial components determined in the above steps can be rearranged to construct multiple target matrices, which contain the amplitude information of the target quantum state to be prepared as |ψ>. Then, for each target matrix, SVD decomposition can be performed to obtain its corresponding unitary matrix.

[0066] Since the target matrix in this embodiment is obtained based on the amplitude rearrangement of the ground state of the target quantum state, each target matrix includes partial amplitude information of the target quantum state. Therefore, in the process of disentanglement and approximate truncation of the target quantum state, there is no need to strictly follow the order of quantum bits from high to low to achieve disentanglement between each other. Therefore, multiple quantum logic gates without shared quantum bits can run in parallel.

[0067] In the deentanglement quantum circuit, each deentanglement quantum logic gate acts on two preset quantum bits, which can be two adjacent quantum bits or two spaced quantum bits, depending on the setting of the circuit. It is not limited here. Along the action sequence, multiple deentanglement quantum logic gates are distributed in multiple layers, and each layer of deentanglement quantum logic gates includes at least one deentanglement quantum logic gate. The deentanglement quantum logic gates in the same layer of deentanglement quantum logic gates all act on the same action sequence.

[0068] In the disentanglement quantum circuit, the disentanglement quantum logic gate plays the role of disentangling two quantum bits. After the disentanglement quantum circuit is applied to the two quantum bits, the disentanglement of the two quantum bits is completed. After each layer of the action sequence of the disentanglement quantum logic gate, the quantum bits of the target quantum state are partially disentangled with each other, until after all the action sequences, an approximate |0> n state.

[0069] Furthermore, in the disentanglement quantum circuit, the action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer of action sequence. The parameters of the unitary matrix of the disentanglement quantum logic gate and the quantum bit acted on by the disentanglement quantum logic gate in the first layer of action sequence are obtained by referring to the amplitude of the target quantum state. After the first layer of action sequence, some quantum bits complete the disentanglement and change the target quantum state. The parameters of the unitary matrix of the disentanglement quantum logic gate and the quantum bit acted on by the disentanglement quantum logic gate in the second layer of action sequence are obtained by referring to the amplitude of the changed target quantum state. By analogy, the parameters of the unitary matrix of the disentanglement quantum logic gate and the quantum bit acted on by the disentanglement quantum logic gate of all layers of action sequence are obtained.

[0070] Step S103: The de-entangled quantum circuit is reversed to obtain a target quantum circuit, where the target quantum circuit has a target quantum logic gate, which is determined based on the conjugate transposed matrix of the unitary matrix, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence.

[0071] Among them, the inverse circuit of the disentanglement quantum circuit is the target quantum circuit, the number of target quantum logic gates of the target quantum circuit is the same as the number of disentanglement quantum logic gates of the disentanglement quantum circuit, and the execution timing of multiple target quantum logic gates is opposite to that of multiple disentanglement quantum logic gates. The disentanglement quantum logic gates of the disentanglement quantum circuit are determined based on the unitary matrix obtained by decomposition, and the target quantum logic gates of the target quantum circuit are determined based on the conjugate transposed matrix of the unitary matrix. Multiple target quantum logic gates act on quantum bits with an initial state of |0>n to evolve the target quantum state.

[0072] The target quantum circuit is obtained by inversely deducing the deentangled quantum circuit. In the target quantum circuit, each target quantum logic gate acts on two preset quantum bits. The two quantum bits can be two quantum bits at adjacent positions or two quantum bits at spaced positions. It can be determined according to the setting of the circuit and is not limited here. Along the action sequence, multiple target quantum logic gates are distributed in multiple layers. Each layer of target quantum logic gates includes at least one target quantum logic gate. The target quantum logic gates in the same layer of target quantum logic gates all act on the same action sequence.

[0073] In the target quantum circuit, the function of the target quantum logic gate is to generate a preset entangled state between two quantum bits, with the initial state being | 0> n Each time the quantum bits in the state pass through a layer of target quantum logic gates, some of the quantum bits will become entangled with each other until the target quantum state is obtained after all the action sequences have passed.

[0074] Furthermore, in the target quantum circuit, the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence. Referring to the construction of the aforementioned de-entanglement quantum circuit, the execution sequence of multiple target quantum logic gates is opposite to that of multiple de-entanglement quantum logic gates, and the target quantum logic gate is determined by the conjugate transposed matrix of the unitary matrix of the de-entanglement quantum logic at the corresponding position.

[0075] Step S104: Run the target quantum circuit to prepare the target quantum state. In the specific preparation, first obtain the target quantum circuit, and then run the quantum operation corresponding to the scalar quantum circuit on the quantum chip to prepare the target quantum state.

[0076] Based on the quantum state preparation method provided in the above embodiment, it is not necessary to predetermine the wave function of the target quantum state to be prepared, but to construct the target quantum circuit based on the idea of ​​disentanglement. First, the various partial components of the target quantum state to be prepared are determined, and each partial component includes a ground state of the target quantum state and the amplitude of the ground state. Then, multiple target matrices can be constructed based on the amplitudes of the partial components, and the target matrix can be decomposed by SVD to obtain a unitary matrix (that is, a disentangled quantum logic gate). The disentangled quantum logic gates corresponding to the multiple unitary matrices obtained by decomposition work together to evolve the target quantum state into | 0> n By constructing the conjugate transpose matrix (target quantum logic gate) of the multiple unitary matrices and acting on the quantum bits with the initial state of |0>n, the target quantum circuit can be obtained. The target quantum circuit is run to prepare the target quantum state. The depth of the target quantum circuit only requires O(log n) layers, which super-exponentially compresses the running time of the quantum computer and can more efficiently prepare the amplitude of the quantum state.

[0077] Furthermore, in each layer of the action sequence of the de-entanglement quantum circuit, the action relationship between the de-entanglement quantum logic gate and the quantum bit in the latter layer of the action sequence is determined by the action relationship between the de-entanglement quantum logic gate and the quantum bit in the previous layer of the action sequence. The specific method is:

[0078] Each quantum bit in the de-entangled quantum circuit needs to be uniquely identified, so each quantum bit will be assigned a unique number to distinguish different quantum bits. In the embodiment provided by the present invention, the quantum bits in the de-entangled quantum circuit are numbered from the lowest bit to the highest bit. For example, refer to Figure 3 As shown, the deentanglement quantum circuit has 8 quantum bits, and the 8 quantum bits are numbered from 1 to 8. Quantum bit 1 is located at the top of the diagram and is also the lowest-order quantum bit. Quantum bit 8 is located at the bottom of the diagram and is the highest-order quantum bit.

[0079] In each layer of action sequence, the quantum bits are reorganized to form several quantum bit pairs. Different quantum bit pairs include different quantum bits. Each quantum bit pair includes a first quantum bit and a second quantum bit. The first quantum bit is at a lower position than the second quantum bit. In each layer of action sequence, each quantum bit pair is acted upon by a deentanglement quantum logic gate.

[0080] In the first level of action sequence, the qubits from the lowest to the highest are grouped in sequence, and every two adjacent qubits form a qubit pair. From the lowest to the highest qubit, every two adjacent qubits are acted upon by a de-entanglement quantum logic gate, thereby de-entanglement of the two qubits. After the de-entanglement quantum logic gate acts on the two qubits, the de-entanglement of the two qubits is completed, and the first qubit or the second qubit is evolved into the |0> state.

[0081] In other layers of action sequences, several quantum bits are regrouped according to the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action sequence to form a quantum bit set. The quantum bits in the quantum bit set come from the first quantum bit or the second quantum bit in the quantum bit pair in each previous layer of action sequence that has not evolved to the |0> state. The quantum bits in the quantum bit set are grouped in sequence from low to high to form quantum bit pairs.

[0082] After each layer of disentanglement quantum logic gates, some of the quantum bits in the target quantum state are disentangled with each other until the initial approximate state is obtained after all the action sequences. n state.

[0083] In a feasible implementation mode, referring to Figure 3 As shown, a de-entangled quantum circuit with 8 qubits is used as an example:

[0084] In the first level of action sequence, every two adjacent quantum bits are grouped into four quantum bit pairs, namely [1, 2], [3, 4], [5, 6] and [7, 8]. Each quantum bit pair is acted upon by a unitary matrix (de-entanglement quantum logic gate), which limits the first quantum bit in the quantum bit pair to evolve into an approximate | 0> state, that is, quantum bits 1, 3, 5 and 7 are in an approximate | 0> state after being acted upon.

[0085] After the first layer of action sequence, the amplitude approximately exists on quantum bits No. 2, No. 4, No. 6 and No. 8. At this time, in the second layer of action sequence, the remaining quantum bits are regrouped. This time there are two quantum bit pairs, [2, 4] and [6, 8]. Each quantum bit pair is acted on by a unitary matrix (de-entangled quantum logic gate), which limits the first quantum bit in the quantum bit pair to evolve into an approximate | 0> state, that is, quantum bits No. 2 and No. 6 are in an approximate | 0> state after being acted on.

[0086] After the second level of action sequence, the amplitude only exists on quantum bits No. 4 and No. 8. At this time, in the third level of action sequence, it is only necessary to act on quantum bits No. 4 and No. 8 with the fourth-order unitary matrix to completely collapse the quantum states on quantum bits No. 4 and No. 8 to the | 0> state.

[0087] For n qubits, first assume that it is an exponential power of 2, that is, n = 2 m , where m is a positive integer. In the first-level action sequence, each quantum bit is grouped, and the quantum bit pairs are: [1, 2], [3, 4], [5, 6]…[2 m -1,2 m ].

[0088] The first qubit in the limited qubit pair is evolved into an approximate | 0> state. After the first layer of action sequence, the remaining qubits with amplitudes are 2, 4, and so on. m In the second-level action sequence, these remaining quantum bits are reorganized to obtain the following quantum bit pairs: [2,4], [6,8]…[2 m -2,2 m ].

[0089] This continues until the last layer, when only two quantum bits are left to be grouped, and a total of m=10gn layers of pairing are required.

[0090] When considering that n quantum bits are not an exponent of 2, the highest-order quantum bits are not grouped during the first-level action sequence, and are included in the grouping range only during the second-level action sequence.

[0091] Let's take 7 qubits as an example:

[0092] In the first-level action sequence, there are three quantum bit pairs: [1, 2], [3, 4], [5, 6], and the remaining quantum bit No. 7 is not grouped.

[0093] In the second-level action sequence, quantum bit No. 7 begins to be included in the grouping range, and there are two quantum bit pairs: [2, 4] and [6, 7].

[0094] In the third-level action sequence, the quantum bit pair is [4, 7].

[0095] In the embodiment provided by the present invention, the specific method for determining the action relationship between the target quantum logic gate and the quantum bit in the previous action sequence of the target quantum circuit by the action relationship between the target quantum logic gate and the quantum bit in the next action sequence is:

[0096] Each quantum bit in the target quantum circuit needs to be uniquely identified, so each quantum bit will be assigned a unique number to distinguish different quantum bits. In the embodiment provided by the present invention, the quantum bits in the target quantum circuit are numbered from the lowest bit to the highest bit. For example, refer to Figure 4 As shown, the target quantum circuit has 8 quantum bits, and the 8 quantum bits are numbered from 1 to 8. Quantum bit 1 is located at the top of the diagram and is also the lowest-order quantum bit. Quantum bit 8 is located at the bottom of the diagram, which is the highest-order quantum bit. The numbering here is the same as that of the deentanglement quantum circuit.

[0097] In each layer of action sequence, the quantum bits are reorganized to form several quantum bit pairs. Different quantum bit pairs include different quantum bits. Each quantum bit pair includes a first quantum bit and a second quantum bit. The first quantum bit is at a lower position than the second quantum bit. In each layer of action sequence, each quantum bit pair is acted upon by a target quantum logic gate.

[0098] In the last layer of action sequence, the quantum bits from the lowest to the highest are grouped in sequence, and every two adjacent quantum bits form a quantum bit pair. In the last layer of action sequence, every two adjacent quantum bits from the lowest to the highest quantum bits are acted upon by a target quantum logic gate. Since the target quantum circuit is obtained by reverse deduction based on the deentanglement quantum circuit, the quantum bit pair acted upon by the target quantum logic gate in the last layer of action sequence is the same as the quantum bit pair acted upon by the deentanglement quantum logic gate in the first layer of action sequence of the deentanglement quantum circuit.

[0099] In other layers of action sequences, several quantum bits are regrouped according to the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence to form a quantum bit set, and the quantum bits in the quantum bit set are grouped in sequence from low to high to form quantum bit pairs. This can be derived from the disentanglement quantum circuit. For example, in the penultimate layer of action sequence, the quantum bit pair acted on by the target quantum logic gate is the same as the quantum bit pair acted on by the disentanglement quantum logic gate in the second layer of action sequence of the disentanglement quantum circuit. By analogy, the quantum bit pairs of all action sequences of the target quantum circuit are obtained.

[0100] After each quantum bit in the initial state passes through a layer of target quantum logic gates, some of the quantum bits will become entangled with each other until the target quantum state is obtained after all the action sequences have passed.

[0101] In a feasible implementation mode, referring to Figure 4 As shown, a target quantum circuit with 8 qubits is used as an example:

[0102] In the last layer of action sequence, every two adjacent quantum bits are grouped into four quantum bit pairs, namely [1, 2], [3, 4], [5, 6] and [7, 8], and each quantum bit pair is acted upon by the conjugate transposed matrix of a unitary matrix (target quantum logic gate).

[0103] In the penultimate layer of action sequence, there are two quantum bit pairs, [2,4] and [6,8], and each quantum bit pair is acted upon by the conjugate transposed matrix of a unitary matrix (target quantum logic gate).

[0104] In the first level of action sequence, the target quantum logic gate is applied to quantum bits No. 4 and No. 8.

[0105] For n qubits, first assume that it is an exponential power of 2, that is, n = 2 m , where m is a positive integer. In the last layer of action sequence, each quantum bit is grouped, and the quantum bit pairs are: [1, 2], [3, 4], [5, 6]…[2 m -1, 2 m ].

[0106] In the penultimate layer of action sequence, the qubits are reorganized to obtain the following qubit pairs: [2, 4], [6, 8]…[2 m -2,2 m ].

[0107] By analogy to the first level of action sequence, only two quantum bits are left to be grouped, and a total of m=logn levels of pairing are required.

[0108] Through the quantum state preparation method provided in the above embodiment, the circuit depth only needs o(logn) layers, which can effectively compress the running time of the quantum computer and can more efficiently prepare the amplitude of the quantum state. This method can accurately prepare linear functions.

[0109] At the same time, the present invention also provides an improvement idea for the method. Under the logarithmic number of layers, the quantum state preparation method provided in the above embodiment does not fully utilize the parallel characteristics, that is, there are still remaining bits that have not been working. The present invention achieves more precise preparation by continuing to add quantum logic gates working in parallel.

[0110] Specifically, in the deentanglement quantum circuit, except for the first layer of action timing, in other layers of action timing, a number of quantum bits are regrouped according to the action relationship between the deentanglement quantum logic gate and the quantum bit in the previous layer of action timing to form a quantum bit set, and the quantum bit set includes a first quantum bit set and a second quantum bit set. The quantum bits in the first quantum bit set come from the first quantum bit in each previous quantum bit pair, and the quantum bits in the first quantum bit set are grouped in sequence from low to high to form a quantum bit pair; the quantum bits in the second quantum bit set come from the second quantum bit in each previous quantum bit pair, and the quantum bits in the second quantum bit set are grouped in sequence from low to high to form a quantum bit pair.

[0111] In a feasible implementation, a de-entangled quantum circuit with 8 qubits is used as an example for explanation:

[0112] In the first level of action sequence, every two adjacent quantum bits are grouped into four quantum bit pairs, namely [1, 2], [3, 4], [5, 6] and [7, 8], and each quantum bit pair is acted upon by a unitary matrix (de-entangled quantum logic gate).

[0113] After the first layer of action sequence, the quantum bits are reorganized in the second layer of action sequence. This time, there are also four quantum bit pairs, namely [2, 4], [6, 8], [1, 3] and [5, 7]. Each quantum bit pair is acted upon by a unitary matrix (de-entangled quantum logic gate).

[0114] After the second layer of action sequence, the quantum bits are reorganized in the third layer of action sequence. This time, there are also four quantum bit pairs, namely [4, 8], [1, 5], [2, 6] and [3, 7]. Each quantum bit pair is acted upon by a unitary matrix (de-entangled quantum logic gate).

[0115] For n qubits, first assume that it is an exponential power of 2, that is, n = 2 m , where m is a positive integer. In the first-level action sequence, each quantum bit is grouped, and the quantum bit pairs are: [1, 2], [3, 4], [5, 6]…[2 m -1, 2 m ].

[0116] After the first layer of action sequence, in the second layer of action sequence, several quantum bits are regrouped. The quantum bits in the first quantum bit set are No. 1, No. 3, No. 5...2 m -No. 3 and No. 2 m-1, the quantum bits in the first quantum bit set are grouped from low to high to form quantum bit pairs: [1,3], [5,6], [9,11]......[2 m -3,2 m -1], the quantum bits in the second quantum bit set are 2, 4, 5, .....2 m -No. 2 and 2 m The qubits in the second qubit set are grouped from low to high to form qubit pairs: [2,4], [6,8], [10,12]......[2 m -2,2 m ], the quantum bit pair of the first quantum bit set and the second quantum bit set of the second layer operation sequence is:

[0117] [1,3],[5,6],[9,11]......[2 m -3,2 m -1],[2,4],[6,8],[10,12]......[2 m -2,2 m ].

[0118] The quantum bit pairs of the third layer of action sequence are: [1,5], [3,7], [9,13]......[2 m -4,2 m ].

[0119] This continues until the last layer of action sequence, where the first quantum bit and the second quantum bit of the previous layer of action sequence are paired up in pairs. A total of m=logn layers of pairing are required.

[0120] When considering that n quantum bits are not an exponent of 2, they can be filled to 2. m The length of , that is, m = [logn], then arrange it according to the above method, and after arranging m layers, delete all the ones that are designed to exceed n. The following takes 7 quantum bits as an example.

[0121] Let's take 7 qubits as an example:

[0122] In the first layer of action sequence, the quantum bit pairs are: [1,2], [3,4], [5,6], [7,8].

[0123] In the second-level action sequence, the quantum bit pairs are: [1,3], [5,7], [2,4], [6,8].

[0124] In the third-level action sequence, the quantum bit pairs are: [1,5], [2,6], [3,7], [4,8].

[0125] Remove the qubit pair with qubit number 8, and we have:

[0126] In the first layer of action sequence, the quantum bit pairs are: [1,2], [3,4], [5,6].

[0127] In the second-level action sequence, the quantum bit pairs are: [1,3], [5,7], [2,4].

[0128] In the third-level action sequence, the quantum bit pairs are: [1,5], [2,6], [3,7].

[0129] In the embodiment provided by the present invention, in the target quantum circuit, except for the last layer of action timing, in other layers of action timing, a number of quantum bits are regrouped according to the action relationship between the target quantum logic gate and the quantum bit in the latter layer of action timing to form a quantum bit set, and the quantum bit set includes a first quantum bit set and a second quantum bit set. The quantum bits in the first quantum bit set come from the first quantum bit in each latter quantum bit pair, and the quantum bits in the first quantum bit set are grouped in sequence from low to high to form a quantum bit pair; the quantum bits in the second quantum bit set come from the second quantum bit in each latter quantum bit pair, and the quantum bits in the second quantum bit set are grouped in sequence from low to high to form a quantum bit pair.

[0130] In a feasible implementation, a target quantum circuit with 8 qubits is used as an example for explanation:

[0131] In the last layer of action sequence, every two adjacent quantum bits are grouped into four quantum bit pairs, namely [1, 2], [3, 4], [5, 6] and [7, 8], and each quantum bit pair is acted upon by the conjugate transposed matrix of a unitary matrix (target quantum logic gate).

[0132] In the penultimate layer of action sequence, the quantum bits are reorganized. This time, there are also four quantum bit pairs, namely [2, 4], [6, 8], [1, 3] and [5, 7]. Each quantum bit pair is acted upon by the conjugate transposed matrix of a unitary matrix (target quantum logic gate).

[0133] In the first layer of action sequence, the quantum bits are reorganized. This time, there are also four quantum bit pairs, namely [4, 8], [1, 5], [2, 6] and [3, 7]. Each quantum bit pair is acted upon by the conjugate transposed matrix of a unitary matrix (target quantum logic gate).

[0134] For n qubits, first assume that it is an exponential power of 2, that is, n = 2m , where m is a positive integer. In the last layer of action sequence, each quantum bit is grouped, and the quantum bit pairs are: [1, 2], [3, 4], [5, 6]…[2 m -1, 2 m ].

[0135] In the penultimate layer of the action sequence, several quantum bits are reorganized. The quantum bits in the first quantum bit set are 1, 3, 5, ... 2 m -No. 3 and No. 2 m -1, the qubits in the first qubit set are grouped from low to high to form qubit pairs:

[0136] [1,3],[5,6],[9,11]......[2 m -3,2 m -1], the quantum bits in the second quantum bit set are 2, 4, 5, .....2 m -No. 2 and 2 m The qubits in the second qubit set are grouped from low to high to form qubit pairs: [2,4], [6,8], [10,12]......[2 m -2,2 m ], the quantum bit pair of the first quantum bit set and the second quantum bit set of the penultimate layer operation sequence is:

[0137] [1,3],[5,6],[9,11]......[2 m -3,2 m -1],[2,4],[6,8],[10,12]......[2 m -2,2 m ].

[0138] The quantum bit pairs in the third-to-last layer are: [1,5], [3,7], [9,13]......[2 m -4,2 m ].

[0139] This continues until the first layer of action sequence is paired with the first quantum bit and the second quantum bit of the next layer of action sequence. A total of m=logn layers of pairing are required.

[0140] When considering that n quantum bits are not an exponent of 2, they can be filled to 2. m The length of , that is, m = [logn], then arrange it according to the above method, and after arranging m layers, delete all the ones that are designed to exceed n. The following takes 7 quantum bits as an example.

[0141] Let's take 7 qubits as an example:

[0142] In the last layer of action sequence, the quantum bit pairs are: [1,2], [3,4], [5,6], [7,8].

[0143] In the penultimate layer of action sequence, the quantum bit pairs are: [1,3], [5,7], [2,4], [6,8].

[0144] In the first layer of action sequence, the quantum bit pairs are: [1,5], [2,6], [3,7], [4,8].

[0145] Remove the qubit pair with qubit number 8, and we have:

[0146] In the last layer of action sequence, the quantum bit pairs are: [1,2], [3,4], [5,6].

[0147] In the penultimate layer of action sequence, the quantum bit pairs are: [1,3], [5,7], [2,4].

[0148] In the first layer of action sequence, the quantum bit pairs are: [1,5], [2,6], [3,7].

[0149] Reference Figure 5 As shown, as an implementation of an embodiment of the present invention, constructing multiple target matrices based on the amplitudes of some components may include the following steps:

[0150] Step 1021, determining the number n of quantum bits used to prepare the target quantum state based on the number N of ground states of the target quantum state;

[0151] Among them, the number of quantum bits n satisfies 2 n-1 <N≤2 n .

[0152] Specifically, for n quantum bits, all possible quantum states that they can represent are a 2 n dimensional complex vector space, that is, the number of all ground states that can be represented by n quantum bits is 2 n Then, based on the number N of ground states of the target quantum state determined in step 201, the number of quantum bits required for the amplitude preparation quantum circuit can be determined.

[0153] and Figure 3Corresponding to the de-entanglement quantum circuit shown in FIG. 1 , in the existing MPS coding quantum circuit, multiple coding modules for quantum state amplitude preparation are distributed in a step-like manner, acting on every two adjacent quantum bits in turn. Since some quantum bits in the quantum circuit have no quantum logic gates to act on for a long time, the circuit decorrelation phenomenon is prone to occur.

[0154] Therefore, in a specific implementation, the target quantum circuit includes multiple layers of target quantum logic gates connected in series; wherein each layer of target quantum logic gates is executed sequentially based on an action sequence, each layer of target quantum logic gates includes multiple target quantum logic gates executed in parallel, and each target quantum logic gate is determined based on a conjugate transposed matrix of a unitary matrix.

[0155] As the number of target quantum logic gates increases, the preparation accuracy of the target quantum circuit will also increase. Correspondingly, the classical complexity of the target quantum circuit will also increase, which is specifically reflected in the need for more target quantum logic gates. Therefore, in the specific encoding process, the number of target quantum logic gates can be selected based on the preparation accuracy requirements, and no specific restrictions are made here.

[0156] In this embodiment, compared with the existing matrix product state encoding circuit in which multiple target quantum logic gates are distributed in a step-like manner, this scheme does not need to predetermine the wave function of the target quantum state to be prepared, and the action timing of the quantum gate is more flexible, and multiple target quantum logic gates can be executed in parallel, thereby avoiding the situation where no quantum gates are in action for a long time, thereby reducing the decorrelation probability of the circuit and improving the fidelity.

[0157] Step 1022: For each action sequence, based on the quantum bit pair of the target quantum logic gate, the amplitudes of the multiple partial components are rearranged into 2 2 ×2 n-2 Scale the matrix to obtain multiple target matrices.

[0158] In a specific embodiment, the amplitudes of the multiple partial components are rearranged into 2 based on the number of the target quantum bits acted on by the target quantum logic gate. 2 ×2 n-2 The scale matrix can include:

[0159] The amplitudes of multiple ground states of the target quantum bits (|00>, |01>, |10>, |11) are taken as the 1st, 2nd, 3rd, and 4th rows of the matrix, and rearranged to obtain 2 2 ×2 n-2 A matrix of size 2 n-2 The amplitudes are arranged in order based on the binary representation of the corresponding ground state.

[0160] Specifically, in order to disentangle the first qubit from other qubits as much as possible, a unitary matrix U is applied to the first qubit and the second qubit. 12 , and the degree of entanglement between the first quantum bit and other quantum bits can be expressed by the entanglement entropy of the SVD diagonal element, that is, the goal of acting on the unitary matrix U1 is to make the maximum value of the diagonal element of the matrix between the first bit system and the remaining bit systems tend to 1.

[0161] Assuming that there are n quantum bits in the initial state of |ψ>, then act on this unitary matrix U 12 The quantum state then becomes Using the one-dimensional expansion formula The above evolution results can be written as a tensor:

[0162]

[0163] For the convenience of expression, the target quantum state |ψ> can be written into four parts, ω 00 , ψ 01 , ψ 10 , ψ 11 , where the subscript of each part represents the state of the first two qubits. This is divided into four parts of length 2 n-2 The vector is as follows:

[0164]

[0165] Perform SVD decomposition on it, and we have This time The SVD decomposition result can be written as:

[0166] |U 12 [ψ1,ψ2,ψ3,ψ4] T >>=[ψ′1,ψ′2,ψ′3,ψ′4] T

[0167] or,

[0168] |U′ 12 [s1v1, s2v2, s3v3, s4v4] T >>

[0169] Among them, s i are the singular values ​​arranged from largest to smallest.

[0170] The goal at this time is to hope that the diagonal The diagonal elements of the matrix make it more concentrated, thereby reducing the entanglement entropy. The two rows are orthogonal, so their singular values ​​are And choose any other non-identity matrix U 12 Neither can make the two eigenvalues ​​more concentrated, that is, the SVD entropy is smaller, which means that U 12 The fourth-order identity matrix is ​​the best choice.

[0171] Furthermore, still using the target quantum state to be prepared as above Taking the example of 1,2,3,4,5,6, and 2,3,4,5, as an example, in order to encode it into the amplitude of 6 quantum bits, we first need to perform de-entanglement operations on the quantum bit pairs numbered 1,2; 3,4;5,6 and the quantum bit pairs numbered 2,3;4,5. Taking the unitary matrix acting on the quantum bit pair numbered 1,2 as an example, we need to rearrange the amplitudes of multiple partial components to 2 2 ×2 6-2 The size is 4×16.

[0172] Among them, the first row of the target matrix is ​​the 16 amplitudes of the state of quantum bits 1 and 2 corresponding to the ground state|00), and the second, third, and fourth rows are the 16 amplitudes of the state of quantum bits 1 and 2 corresponding to the ground state|01>,|10>,|11) respectively. Among them, the 16 amplitudes in each row are arranged based on the binary representation order of the corresponding ground state, so that the following target matrix C1 can be obtained:

[0173] First line:

[0174] α 000000 , α 000100 , α 001000 , α 001100 , α 010000 , α 010100 , α 011000 , α 011100 ,

[0175] α 100000 , α 100100 , α 101000 , α 101100 , α 110000 , α 110100 , α 111000 , α 111100

[0176] Second behavior:

[0177] α 000001 , α 000101 , α 001001 , α 001101 , α 010001 , α 010101 , α 011001 , α 011101 ,

[0178] α100001 , α 100101 , α 101001 , α 101101 , α 110001 , α 110101 , α 111001 , α 111101

[0179] The third behavior:

[0180] α 000010 , α 000110 , α 001010 , α 001110 , α 010010 , α 010110 , α 011010 , α 011110 ,

[0181] α 100010 , α 100110 , α 101010 , α 101110 , α 110010 , α 110110 , α 111010 , α 111110

[0182] The fourth behavior is:

[0183] α 000011 , α 000111 , α 001011 , α 001111 , α 010011 , α 010111 , α 011011 , α 011111 ,

[0184] α 100011 , α 100111 , α 101011 , α 101111 , α 110011 , α 110111 , α 111011 , α 111111

[0185] As an implementation manner of an embodiment of the present invention, performing singular value decomposition on a target matrix to obtain a unitary matrix may include the following steps:

[0186] Step 1023: For each target matrix, perform SVD decomposition on the target matrix to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and use the left singular vector matrix as a unitary matrix.

[0187] Then, the SVD decomposition of the above 4×16-scale target matrix C1 is performed, and the left singular vector matrix obtained is a 4×4 unitary matrix U1, which is one of the multiple unitary matrices that evolve the target quantum state |ψ> to the |0> state; correspondingly, its conjugate transposed matrix (i.e., the inverse matrix ) is the unitary matrix mapped into the target quantum circuit.

[0188] Then, we can use the same method to rearrange qubits 3 and 4 as labels, that is, rearrange the 16 amplitudes of the corresponding ground state bits 3 and 4 to |00>, |01>, |10>, |11) into a 4×16 target matrix C2. Then perform SVD decomposition to obtain the unitary matrix U2, It is the second unitary matrix mapped to the amplitude-coded quantum circuit.

[0189] Similarly, we can determine the unitary matrix U3 acting on quantum bits 5 and 6 and the third unitary matrix in the amplitude-coded quantum circuit:

[0190] Furthermore, the above step 102 may also include the following steps:

[0191] Step 1024, using a quantum virtual machine to perform a simulated evolution of quantum logic gates corresponding to a plurality of unitary matrices on a target quantum state.

[0192] Step 1025, taking the final state obtained by the simulated evolution as the target quantum state to be prepared, and returning to step 101 to determine the various partial components of the target quantum state to be prepared, until the final state obtained by the simulated evolution is |0> n state, or, the iteration reaches a preset number of times.

[0193] Specifically, the quantum virtual machine can be used to perform a simulated evolution of the target quantum state |ω> based on the three quantum logic gates U1, U2, and U3 of the first layer, and the final state obtained by the evolution is used as the target quantum state to be prepared, and the steps of determining the various partial components of the target quantum state to be prepared are returned. Then, in the next iteration step, the goal becomes to disentangle the final state obtained by the above evolution to |0> n state, that is, unitary matrix encoding is performed again on the basis of the three quantum logic gates U1, U2, and U3 of the first layer, and the quantum logic gates of the first layer cannot act on the same quantum bit pair.

[0194] Based on the above scheme, we can calculate the two quantum logic gates of the second layer, which are U4 acting on bits 2 and 3 and U5 acting on quantum bits 4 and 5. Then, we repeat the above steps until the final state obtained by the simulated evolution is |0> nWhen the state is reached, it can be determined that the entanglement has been completely resolved; or when the number of iterations reaches a preset number, it can be considered that the deentanglement operation has reached a preset accuracy. The quantum circuit for deentanglement in this scheme can be obtained.

[0195] Then, the inverse mapping of the quantum logic gates corresponding to the multiple unitary matrices in the quantum circuit is applied to the six quantum bits whose initial state is | 0>n, and the obtained target quantum circuit can generate the target quantum state |ψ>.

[0196] [Structure of quantum state preparation device]

[0197] See also Figure 6 As shown, the quantum state preparation device includes:

[0198] The acquisition module is used to determine each partial component of the target quantum state to be prepared; wherein each partial component includes a ground state of the target quantum state and the amplitude of the ground state.

[0199] The de-entanglement quantum circuit construction module is used to construct a de-entanglement quantum circuit. Multiple target matrices are constructed based on the amplitudes of some components, and the target matrices are decomposed by SVD to obtain a unitary matrix. The de-entanglement quantum logic gates are determined based on the unitary matrix. Multiple de-entanglement quantum logic gates act on quantum bits whose initial states are the target quantum states to obtain a de-entanglement quantum circuit, wherein the action relationship between the de-entanglement quantum logic gates and the quantum bits in the latter layer of action sequence is determined by the action relationship between the de-entanglement quantum logic gates and the quantum bits in the previous layer of action sequence.

[0200] Among them, the de-entanglement quantum logic gate is determined based on the unitary matrix obtained by decomposition, and multiple de-entanglement quantum logic gates act on the quantum bits whose initial state is the target quantum state to obtain the de-entanglement quantum circuit, which is used to evolve the target quantum state into |0> n state.

[0201] The target quantum circuit construction module is used to determine that the inverse circuit of the deentangled quantum circuit is the target quantum circuit. The target quantum circuit has a target quantum logic gate. The target quantum logic gate is determined based on the conjugate transpose matrix of the unitary matrix. The action relationship between the target quantum logic gate and the quantum bit in the previous layer of action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence.

[0202] Among them, the inverse circuit of the disentanglement quantum circuit is the target quantum circuit, the number of target quantum logic gates of the target quantum circuit is the same as the number of disentanglement quantum logic gates of the disentanglement quantum circuit, and the execution timing of multiple target quantum logic gates is opposite to that of multiple disentanglement quantum logic gates. The disentanglement quantum logic gates of the disentanglement quantum circuit are determined based on the unitary matrix obtained by decomposition, and the target quantum logic gates of the target quantum circuit are determined based on the conjugate transposed matrix of the unitary matrix. Multiple target quantum logic gates act on quantum bits with an initial state of |0>n to evolve the target quantum state.

[0203] An operation module is used to operate the target quantum circuit to prepare the target quantum state.

[0204] Among them, the operation module is a quantum system that can run the quantum circuit. Exemplarily, the quantum hardware including a quantum processor and a quantum measurement and control system with communication connection is a system, wherein the quantum processor refers to a quantum chip, and the quantum measurement and control system is used to provide an analog signal for realizing the quantum logic gate in the quantum circuit. The analog signal acts on the quantum chip to realize the operation of the quantum circuit.

[0205]

Storage medium structure

[0206] An embodiment of the present invention further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to implement the steps of any of the above method embodiments when running.

[0207] Specifically, in this embodiment, the above storage medium may be configured to store a computer program for implementing the following steps:

[0208] Step S101: determining each partial component of a target quantum state to be prepared, each partial component including a ground state of the target quantum state and an amplitude of the ground state.

[0209] Step S102: construct multiple target matrices based on the amplitudes of some components, and perform SVD decomposition on the target matrices to obtain unitary matrices, determine deentanglement quantum logic gates based on the unitary matrices, and act on quantum bits whose initial states are target quantum states to obtain deentanglement quantum circuits, wherein the action relationship between the deentanglement quantum logic gates and the quantum bits in the latter layer of action sequence is determined by the action relationship between the deentanglement quantum logic gates and the quantum bits in the previous layer of action sequence.

[0210] Step S103: The de-entangled quantum circuit is reversed to obtain a target quantum circuit, where the target quantum circuit has a target quantum logic gate, which is determined based on the conjugate transposed matrix of the unitary matrix, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence.

[0211] Step S104: running the target quantum circuit to prepare the target quantum state.

[0212]

Structure of electronic devices

[0213] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to implement the steps in any one of the above method embodiments.

[0214] Specifically, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0215] Specifically, in this embodiment, the processor may be configured to implement the following steps through a computer program:

[0216] Step S101: determining each partial component of a target quantum state to be prepared, each partial component including a ground state of the target quantum state and an amplitude of the ground state.

[0217] Step S102: construct multiple target matrices based on the amplitudes of some components, and perform SVD decomposition on the target matrices to obtain unitary matrices, determine deentanglement quantum logic gates based on the unitary matrices, and act on quantum bits whose initial states are target quantum states to obtain deentanglement quantum circuits, wherein the action relationship between the deentanglement quantum logic gates and the quantum bits in the latter layer of action sequence is determined by the action relationship between the deentanglement quantum logic gates and the quantum bits in the previous layer of action sequence.

[0218] Step S103: The de-entangled quantum circuit is reversed to obtain a target quantum circuit, where the target quantum circuit has a target quantum logic gate, which is determined based on the conjugate transposed matrix of the unitary matrix, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous layer of action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence.

[0219] Step S104: running the target quantum circuit to prepare the target quantum state.

[0220] The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the drawings. Any changes made according to the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present invention.

Claims

1. A method for preparing a quantum state, characterized in that: The method comprises: Determining each partial component of a target quantum state to be prepared, each of the partial components comprising a ground state of the target quantum state and an amplitude of the ground state; Based on the amplitudes of the partial components, a plurality of target matrices are constructed, and the target matrices are decomposed by SVD to obtain a unitary matrix, and a disentanglement quantum logic gate is determined based on the unitary matrix, and the plurality of disentanglement quantum logic gates act on a quantum bit whose initial state is a target quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer of action sequence; Determining the inverse circuit of the deentangled quantum circuit as the target quantum circuit; The target quantum circuit is operated to prepare the target quantum state.

2. The method according to claim 1, characterized in that: The action relationship between the target quantum logic gate and the quantum bit in the previous action sequence is determined by the action relationship between the target quantum logic gate and the quantum bit in the next action sequence, including: In each layer of action sequence, the qubits are regrouped to form a number of qubit pairs, each qubit pair includes a first qubit and a second qubit, the first qubit is at a lower level than the second qubit, and in each layer of action sequence, each qubit pair is acted upon by a target quantum logic gate; In the last layer of action sequence, the qubits from the lowest bit to the highest bit are grouped in sequence, and every two adjacent qubits form a qubit pair; In other layers of action sequences, a number of the quantum bits are regrouped according to the action relationship between the target quantum logic gate and the quantum bits in the latter layer of action sequence to form a quantum bit set, wherein the quantum bits in the quantum bit set come from the first quantum bit or the second quantum bit in each of the latter quantum bit pairs, and the quantum bits in the quantum bit set are grouped in sequence from low to high to form the quantum bit pair.

3. The method according to claim 2, characterized in that: Regrouping the plurality of quantum bits according to the action relationship between the target quantum logic gate and the quantum bit in the next layer of action sequence to form a quantum bit set, including: The quantum bit set includes a first quantum bit set and a second quantum bit set, the quantum bits in the first quantum bit set come from the first quantum bit in each subsequent quantum bit pair, and the quantum bits in the first quantum bit set are grouped in sequence from low to high to form the quantum bit pair; the quantum bits in the second quantum bit set come from the second quantum bit in each subsequent quantum bit pair, and the quantum bits in the second quantum bit set are grouped in sequence from low to high to form the quantum bit pair.

4. The method according to claim 1, characterized in that: The multiple target matrices are constructed based on the amplitudes of the partial components, including: The number of quantum bits used to prepare the target quantum state is determined based on the number of ground states of the target quantum state, and the number of quantum bits n satisfies 2 n-1 <N≤2 n , N is the number of ground states of the target quantum state.

5. The method according to claim 4, characterized in that: The step of constructing a plurality of target matrices based on the amplitudes of the partial components comprises: for each of the action sequences, based on the number of the target quantum bits acted on by the target quantum logic gate, rearranging the amplitudes of the plurality of partial components into 2 2 ×2 n-2 Scale the matrix to obtain a multiple of the target matrix.

6. The method according to claim 5, characterized in that: Based on the number of the target quantum bits acted by the target quantum logic gate, the amplitudes of the multiple partial components are rearranged into 2 2 ×2 n-2 A matrix of scales, including: The amplitudes of the multiple ground states of the quantum bit pairs corresponding to the positions |00>, |01>, |10>, |11> are respectively used as the 1st, 2nd, 3rd, and 4th rows of the matrix, and the 2 2 ×2 n-2 A matrix of size 2 n-2 The amplitudes are arranged in order based on the binary representation of the corresponding ground state.

7. The method according to claim 6, characterized in that: The step of performing SVD decomposition on the target matrix to obtain a unitary matrix includes: For each of the target matrices, SVD decomposition is performed on the target matrix to obtain a multiplied left singular vector matrix, a singular value matrix and a right singular vector matrix, and the left singular vector matrix is ​​used as the unitary matrix.

8. A quantum state preparation device, characterized in that: The device comprises: An acquisition module, used to determine each partial component of the target quantum state to be prepared; wherein each of the partial components includes a ground state of the target quantum state and an amplitude of the ground state; A de-entanglement quantum circuit construction module is used to construct a de-entanglement quantum circuit, obtain multiple target matrices based on the amplitude of the partial components, and perform SVD decomposition on the target matrix to obtain a unitary matrix, determine a de-entanglement quantum logic gate based on the unitary matrix, and multiple de-entanglement quantum logic gates act on a quantum bit whose initial state is a target quantum state to obtain a de-entanglement quantum circuit, wherein the action relationship between the de-entanglement quantum logic gate and the quantum bit in the latter layer of action sequence is determined by the action relationship between the de-entanglement quantum logic gate and the quantum bit in the previous layer of action sequence; A target quantum circuit construction module, used to determine the inverse circuit of the deentangled quantum circuit as the target quantum circuit; An operation module is used to operate the target quantum circuit to prepare the target quantum state.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to implement the method according to any one of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to execute the computer program to implement the method according to any one of claims 1 to 7.

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