A wafer defect monitoring and classification method, system, computer and storage medium
By generating grain distribution maps and using deep learning models to learn defect feature, the problem of difficulty in time checking the causes of abnormalities in the existing technology is solved, efficient wafer defect monitoring and classification is achieved, and production efficiency is improved.
Patent Information
- Application Number
- CN202410679200.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-29
- Publication Date
- 2025-04-04
AI Technical Summary
In the prior art, it is difficult to promptly check the causes of abnormalities, resulting in low production efficiency.
By providing the classified sample set and setting card control indicators, a grain distribution map is generated, and using the convolutional network deep learning model to learn and train defect features, a defect classification detection model is obtained. Then, the test document is read through the MES system, a grain distribution map to be tested is generated, and the trained model is imported for analysis.
It has achieved rapid acquisition of defect classification parameters, improved classification efficiency, timely checked for abnormal causes, and improved production efficiency.
Smart Images
Figure CN119762830A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer defect monitoring and classification method, system, computer and storage medium. Background Art
[0002] In the LED semiconductor chip industry, after a 4-inch wafer (circle) is lit up by a testing machine, a test document including the optoelectronic data corresponding to each grain can be generated. Based on the number of grains with abnormal optoelectronic data, the yield of the corresponding wafer can be obtained, thereby screening out abnormal wafers that do not meet the preset yield.
[0003] In the prior art, based on the method of detecting anomalies based on photoelectric data, when wafer batch anomalies occur, the details of wafers with different defect types can only be collected and summarized manually, and the causes of the anomalies are investigated in combination with the physical appearance or FIB cutting results. This is inefficient and difficult to investigate the causes of the anomalies in a timely manner, affecting production efficiency. Summary of the invention
[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a wafer defect monitoring and classification method, aiming to solve the technical problems in the prior art that it is difficult to timely identify the causes of abnormalities and the production efficiency is low.
[0005] In order to achieve the above object, a first aspect of the present invention provides a wafer defect monitoring and classification method, comprising the following steps:
[0006] Providing a first classified sample set including a plurality of wafer samples, and setting a card control index, wherein the first classified sample set includes a defect classification parameter corresponding to each wafer, a grain coordinate parameter, and a yield parameter corresponding to each of the grain coordinate parameters;
[0007] Generate a corresponding grain distribution map based on the grain coordinate parameters, yield parameters and card control indicators corresponding to each wafer, wherein the grain distribution map includes a standard area where the yield parameters meet the card control indicators and a defective area where the yield parameters do not meet the card control indicators;
[0008] Select and locate the defective area in each of the grain distribution maps, and learn and train the defect features in the image through a convolutional network deep learning model based on the defect classification parameters to obtain a defect classification detection model related to the grain distribution map;
[0009] The unclassified test document uploaded from the test machine is read through the MES system, and a distribution map of the grains to be tested is generated based on the grain coordinate parameters and yield parameters in the unclassified test document. The distribution map of the grains to be tested is imported into the defect classification detection model for analysis to obtain defect classification parameters corresponding to the unclassified test document.
[0010] According to one aspect of the above technical solution, the step of obtaining a defect classification detection model related to the grain distribution map specifically includes:
[0011] Providing a second classified sample set, and importing each sample in the second classified sample set into a convolutional network deep learning model for testing, so as to obtain model accuracy by comparing the test results with the defect classification parameters in the classified sample set;
[0012] If the model accuracy is less than a preset value, multiple classified sample sets are provided in sequence to perform learning and training on the defect classification detection model until a defect classification detection model whose model accuracy meets the preset value is obtained.
[0013] According to one aspect of the above technical solution, before the step of framing and locating the defective regions in each of the grain distribution maps, the method further includes:
[0014] The size of the grain distribution map is processed, and the grain distribution map is smoothed and denoised.
[0015] According to one aspect of the above technical solution, the defect classification parameters include a plurality of defect classifications corresponding to the distribution area and distribution shape of the defect area;
[0016] If the model accuracy is less than a preset value, the steps of sequentially providing a plurality of classified sample sets to perform learning and training on the defect classification detection model specifically include:
[0017] If the model accuracy is less than a preset value, a high defect classification sample set corresponding to the defect classification less than the preset value is provided, so as to perform learning and training on the defect classification detection model based on the high defect classification sample set.
[0018] In a second aspect, the present invention provides a wafer defect monitoring and classification system, comprising:
[0019] A sample module, used to provide a first classified sample set including a plurality of wafer samples and set a card control index, wherein the first classified sample set includes a defect classification parameter corresponding to each wafer, a grain coordinate parameter and a yield parameter corresponding to each of the grain coordinate parameters;
[0020] An image module, for generating a corresponding grain distribution map based on the grain coordinate parameters, yield parameters and card control indicators corresponding to each wafer, wherein the grain distribution map includes a standard area where the yield parameters meet the card control indicators, and a defective area where the yield parameters do not meet the card control indicators;
[0021] A model module, used to select and locate the defect area in each of the grain distribution maps, and to learn and train the defect features in the image through a convolutional network deep learning model based on the defect classification parameters, so as to obtain a defect classification detection model related to the grain distribution map;
[0022] The classification module is used to read the unclassified test document uploaded from the test machine through the MES system, and generate a distribution map of the grains to be tested based on the grain coordinate parameters and yield parameters in the unclassified test document, and import the distribution map of the grains to be tested into the defect classification detection model for analysis to obtain the defect classification parameters corresponding to the unclassified test document.
[0023] According to one aspect of the above technical solution, the model module is specifically used for:
[0024] Providing a second classified sample set, and importing each sample in the second classified sample set into a convolutional network deep learning model for testing, so as to obtain model accuracy by comparing the test results with the defect classification parameters in the classified sample set;
[0025] If the model accuracy is less than a preset value, multiple classified sample sets are provided in sequence to perform learning and training on the defect classification detection model until a defect classification detection model whose model accuracy meets the preset value is obtained.
[0026] According to one aspect of the above technical solution, the wafer defect monitoring and classification system further includes:
[0027] The preprocessing module is used to process the size of the grain distribution map and perform smoothing and denoising on the grain distribution map.
[0028] According to one aspect of the above technical solution, the defect classification parameters include a plurality of defect classifications corresponding to the distribution area and distribution shape of the defect area;
[0029] The model module is also used to: if the model accuracy is less than a preset value, provide a high defect classification sample set corresponding to the defect classification less than the preset value, so as to learn and train the defect classification detection model based on the high defect classification sample set.
[0030] In a third aspect, an embodiment of the present application provides a computer, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, a wafer defect monitoring and classification method as described in the first aspect is implemented.
[0031] In a fourth aspect, an embodiment of the present application provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements a wafer defect monitoring and classification method as described in the first aspect.
[0032] Compared with the prior art, the beneficial effect of the present invention lies in: by drawing a grain distribution map corresponding to the wafer based on a historical classified sample set and setting a card control indicator, the sample set includes manually proofread defect classification parameters, and classifies each grain in the grain distribution map based on the card control indicator to generate a standard area that meets the card control indicator and a defect area whose yield parameters do not meet the card control indicator, and then trains the defect features in the image based on the convolutional network deep learning model to improve the defect classification detection model, and then reads the unclassified test document uploaded from the test machine in real time through the MES system, generates the corresponding grain distribution map to be tested through the document, and then imports it into the trained defect classification detection model to quickly obtain the defect classification parameters corresponding to the unclassified test document, thereby improving the classification efficiency, timely troubleshooting the cause of the abnormality, and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 Flow chart of the wafer defect monitoring and classification method in the first embodiment of the present invention;
[0034] Figure 2 A grain distribution diagram corresponding to the wafers in the first classified sample set in the first embodiment of the present invention;
[0035] Figure 3 It is a structural block diagram of a wafer defect monitoring and classification system in a second embodiment of the present invention;
[0036] Figure 4 is a schematic diagram of the hardware structure of a computer in a third embodiment of the present invention;
[0037] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0038] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.
[0039] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0041] See also Figure 1 , which is a flow chart of a wafer defect monitoring and classification method in a first embodiment of the present invention, as shown in the figure, the method includes the following steps:
[0042] Step S100, providing a first classified sample set including multiple wafer samples, and setting the card control index, wherein the first classified sample set includes defect classification parameters corresponding to each wafer, grain coordinate parameters and yield parameters corresponding to each of the grain coordinate parameters. Specifically, in the present embodiment, the above-mentioned first classified sample set includes corresponding photoelectric data obtained after the test machine is turned on, and defect classification parameters for classifying defects in the wafer based on manual detection. In some application scenarios of the present embodiment, the above-mentioned photoelectric data includes operating voltage VF data, current IR data and wavelength WLD data after the grain is turned on, as well as X, Y coordinate data of the grain corresponding to each data.
[0043] For ease of understanding, in this embodiment, the above defect classification parameters include multiple defect classifications corresponding to the distribution area and distribution shape of the defect area, such as outer circle or scattered point abnormality, which means that the defect distribution area is at the outer edge of the wafer or the defects are scattered; scratch or contamination abnormality, which means that the distribution shape of the defect is similar to scratch or contamination; and also includes the following regional abnormalities, which means that the defect distribution area is distributed in rows or columns, or concentrated in certain areas, etc. Through the classification of defects, the source of the abnormality can be accurately checked for easy maintenance.
[0044] Step S200, based on the grain coordinate parameters, yield parameters and card control indicators corresponding to each wafer, a corresponding grain distribution map is generated, wherein the grain distribution map includes a standard area where the yield parameters meet the card control indicators, and a defective area where the yield parameters do not meet the card control indicators. Specifically, by generating a grain distribution map of a size corresponding to a four-inch wafer, and coloring the defective area where the yield parameters do not meet the card control indicators, the distribution area and distribution shape of the defective area can be intuitively and accurately displayed.
[0045] Step S300, select and locate the defective area in each of the grain distribution maps, and learn and train the defect features in the image through the convolutional network deep learning model based on the defect classification parameters to obtain a defect classification detection model related to the grain distribution map. Specifically, in this embodiment, the convolutional neural network YOLO deep learning model is used to detect the location of the target defect in the image and frame its boundary box. Then, the AI deep learning model can repeatedly learn and identify defects for a large number of samples with different defects, thereby achieving the ability to effectively distinguish target defects of different categories. Figure 2 As shown, in this embodiment, a grain distribution diagram is drawn for current IR data. It can be seen from the figure that the defect of the wafer may be affected by contamination, that is, it meets the defect classification of "scratch or contamination abnormality".
[0046] Preferably, in this embodiment, the step of obtaining the defect classification detection model related to the grain distribution map specifically includes:
[0047] Step S310, providing a second classified sample set, and importing each sample in the second classified sample set into the convolutional network deep learning model for testing, so as to obtain the model accuracy by comparing the test results with the defect classification parameters in the classified sample set. The second classified sample set is the same as the first classified sample set, which is a sample set with defect classification parameters obtained after manual classification, so as to facilitate the guidance of model learning and training.
[0048] Step S320, if the model accuracy is less than the preset value, multiple classified sample sets are provided in sequence to train the defect classification detection model until a defect classification detection model with a model accuracy that meets the preset value is obtained. Preferably, in this embodiment, the preset value is preferably 98%, that is, the comparison conformity rate between the analysis result of the model and each defect classification in the pre-determined defect classification parameter needs to be greater than or equal to 98%.
[0049] Furthermore, in this embodiment, the above step S320 specifically includes:
[0050] Step S321, if the model accuracy is less than a preset value, provide a high defect classification sample set corresponding to the defect classification less than the preset value, so as to learn and train the defect classification detection model based on the high defect classification sample set. For ease of understanding, in some application scenarios of this implementation, when the relevant recognition accuracy of "scratch or contamination anomaly" is less than a preset value, a classified sample set that meets the "scratch or contamination anomaly" can be selected to conduct targeted training on the model, thereby improving the training effect.
[0051] In addition, in this embodiment, before the step of framing and locating the defective regions in each of the grain distribution maps, the method further includes:
[0052] Step S301, processing the size of the grain distribution map, and performing smoothing and denoising on the grain distribution map. In this embodiment, by unifying the size of the image, removing noise and standardizing the color, subsequent model analysis and identification can be facilitated.
[0053] Step S400, read the unclassified test document uploaded from the test machine through the MES system, and generate a distribution map of the grains to be tested based on the grain coordinate parameters and yield parameters in the unclassified test document, import the distribution map of the grains to be tested into the defect classification detection model for analysis, and obtain the defect classification parameters corresponding to the unclassified test document. In some application scenarios of this embodiment, the MES system reads the test document cast by the test machine through the network disk, and calculates various optical parameter and electrical data; the Mapping automatic classification monitoring system database obtains various information of the wafers to be monitored and classified by connecting to the MES system, obtains the corresponding card control indicators and settings from the network end, and then transmits the wafer information (including component coding, monitoring indicators and card control) to the underlying defect classification detection model, the model identifies and classifies the target defects of this wafer, and after the classification is completed, transmits the results to the system front end, and the system summarizes the results according to different classifications.
[0054] In summary, the wafer defect monitoring and classification method in the above-mentioned embodiment of the present invention draws a grain distribution map corresponding to the wafer based on a historical classified sample set and sets the card control index. The sample set includes manually proofread defect classification parameters, and classifies each grain in the grain distribution map based on the card control index to generate a standard area that meets the card control index and a defect area whose yield parameters do not meet the card control index. Then, the defect features in the image are learned and trained based on the convolutional network deep learning model to improve the defect classification detection model, and then the unclassified test document uploaded from the test machine is read in real time by the MES system, and the corresponding grain distribution map to be tested is generated through the document, and then it is imported into the trained defect classification detection model to quickly obtain the defect classification parameters corresponding to the unclassified test document, thereby improving the classification efficiency, timely troubleshooting the cause of the abnormality, and improving production efficiency.
[0055] A second embodiment of the present invention provides a wafer defect monitoring and classification system, such as Figure 3 FIG. 1 is a structural block diagram of a wafer defect monitoring and classification system in a second embodiment of the present invention. As shown in the figure, the system includes:
[0056] The sample module 100 is used to provide a first classified sample set including a plurality of wafer samples and set a card control index, wherein the first classified sample set includes a defect classification parameter corresponding to each wafer, a grain coordinate parameter and a yield parameter corresponding to each of the grain coordinate parameters;
[0057] An image module 200 is used to generate a corresponding grain distribution map based on the grain coordinate parameters, yield parameters and card control indicators corresponding to each wafer, wherein the grain distribution map includes a standard area where the yield parameters meet the card control indicators and a defective area where the yield parameters do not meet the card control indicators;
[0058] A model module 300 is used to select and locate the defect area in each of the grain distribution maps, and to learn and train the defect features in the image through a convolutional network deep learning model based on the defect classification parameters to obtain a defect classification detection model related to the grain distribution map;
[0059] The classification module 400 is used to read the unclassified test document uploaded from the test machine through the MES system, and generate a distribution map of the grains to be tested based on the grain coordinate parameters and yield parameters in the unclassified test document, and import the distribution map of the grains to be tested into the defect classification detection model for analysis to obtain the defect classification parameters corresponding to the unclassified test document.
[0060] Preferably, in this embodiment, the model module 300 is specifically used for:
[0061] Providing a second classified sample set, and importing each sample in the second classified sample set into a convolutional network deep learning model for testing, so as to obtain model accuracy by comparing the test results with the defect classification parameters in the classified sample set;
[0062] If the model accuracy is less than a preset value, multiple classified sample sets are provided in sequence to perform learning and training on the defect classification detection model until a defect classification detection model whose model accuracy meets the preset value is obtained.
[0063] Preferably, in this embodiment, the wafer defect monitoring and classification system further includes:
[0064] The preprocessing module is used to process the size of the grain distribution map and perform smoothing and denoising on the grain distribution map.
[0065] Preferably, in this embodiment, the defect classification parameters include a plurality of defect classifications corresponding to the distribution areas and distribution shapes of the defect areas;
[0066] The model module 300 is also used to: if the model accuracy is less than a preset value, provide a high defect classification sample set corresponding to the defect classification less than the preset value, so as to learn and train the defect classification detection model based on the high defect classification sample set.
[0067] The third embodiment of the present application provides a computer, which may include a processor 81 and a memory 82 storing computer program commands. It can be understood that the principles mentioned in the wafer defect monitoring and classification system in this embodiment correspond to the wafer defect monitoring and classification method in the first embodiment of the present application. The relevant principles not described can be referred to in detail in the first embodiment, and will not be repeated here.
[0068] Specifically, the processor 81 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
[0069] Among them, the memory 82 may include a large-capacity memory for data or commands. By way of example and not limitation, the memory 82 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 82 may include a removable or non-removable (or fixed) medium. Where appropriate, the memory 82 may be inside or outside a data processing device. In a specific embodiment, the memory 82 is a non-volatile memory. In a specific embodiment, the memory 82 includes a read-only memory (ROM) and a random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (Programmable Read-Only Memory, PROM for short), an erasable PROM (Erasable ProgrammableRead-Only Memory, EPROM for short), an electrically erasable PROM (Electrically Erasable ProgrammableRead-Only Memory, EEPROM for short), an electrically alterable ROM (Electrically Alterable Read-Only Memory, EAROM for short) or a flash memory (FLASH) or a combination of two or more of these. Under appropriate circumstances, the RAM can be a static random access memory (SRAM) or a dynamic random access memory (DRAM), wherein the DRAM can be a fast page mode dynamic random access memory (FPMDRAM), an extended data output dynamic random access memory (EDODRAM), a synchronous dynamic random access memory (SDRAM), etc.
[0070] The memory 82 may be used to store or cache various data files required for processing and / or communication, as well as possible computer program commands executed by the processor 81 .
[0071] The processor 81 implements any one of the wafer defect monitoring and classification methods in the above embodiments by reading and executing computer program commands stored in the memory 82 .
[0072] In some embodiments, the computer may further include a communication interface 83 and a bus 80. Figure 4 As shown, the processor 81, the memory 82, and the communication interface 83 are connected via a bus 80 and communicate with each other.
[0073] The communication interface 83 is used to implement communication between the modules, devices, units and / or equipment in the embodiment of the present application. The communication interface 83 can also implement data communication with other components such as: external devices, image / data acquisition equipment, databases, external storage, and image / data processing workstations.
[0074] The bus 80 includes hardware, software or both, and couples the components of the computer to each other. The bus 80 includes but is not limited to at least one of the following: a data bus, an address bus, a control bus, an expansion bus, and a local bus. By way of example and not limitation, bus 80 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses or a combination of two or more of these. Where appropriate, bus 80 may include one or more buses. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.
[0075] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0076] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A wafer defect monitoring and classification method, characterized in that: The following steps are involved: Providing a first classified sample set including a plurality of wafer samples, and setting a card control index, wherein the first classified sample set includes a defect classification parameter corresponding to each wafer, a grain coordinate parameter, and a yield parameter corresponding to each of the grain coordinate parameters; Generate a corresponding grain distribution map based on the grain coordinate parameters, yield parameters and card control indicators corresponding to each wafer, wherein the grain distribution map includes a standard area where the yield parameters meet the card control indicators and a defective area where the yield parameters do not meet the card control indicators; Select and locate the defective area in each of the grain distribution maps, and learn and train the defect features in the image through a convolutional network deep learning model based on the defect classification parameters to obtain a defect classification detection model related to the grain distribution map; The unclassified test document uploaded from the test machine is read through the MES system, and a distribution map of the grains to be tested is generated based on the grain coordinate parameters and yield parameters in the unclassified test document. The distribution map of the grains to be tested is imported into the defect classification detection model for analysis to obtain defect classification parameters corresponding to the unclassified test document.
2. The wafer defect monitoring and classification method according to claim 1, characterized in that: The steps of obtaining a defect classification detection model related to the grain distribution map specifically include: Providing a second classified sample set, and importing each sample in the second classified sample set into a convolutional network deep learning model for testing, so as to obtain model accuracy by comparing the test results with the defect classification parameters in the classified sample set; If the model accuracy is less than a preset value, multiple classified sample sets are provided in sequence to perform learning and training on the defect classification detection model until a defect classification detection model whose model accuracy meets the preset value is obtained.
3. The wafer defect monitoring and classification method according to claim 1, characterized in that: Before the step of selecting and locating the defective regions in each of the grain distribution maps, the method further comprises: The size of the grain distribution map is processed, and the grain distribution map is smoothed and denoised.
4. The wafer defect monitoring and classification method according to claim 1, characterized in that: The defect classification parameters include a plurality of defect classifications corresponding to the distribution area and distribution shape of the defect area; If the model accuracy is less than a preset value, the steps of sequentially providing a plurality of classified sample sets to perform learning and training on the defect classification detection model specifically include: If the model accuracy is less than a preset value, a high defect classification sample set corresponding to the defect classification less than the preset value is provided, so as to perform learning and training on the defect classification detection model based on the high defect classification sample set.
5. A wafer defect monitoring and classification system, characterized in that: include: A sample module, used to provide a first classified sample set including a plurality of wafer samples and set a card control index, wherein the first classified sample set includes a defect classification parameter corresponding to each wafer, a grain coordinate parameter and a yield parameter corresponding to each of the grain coordinate parameters; An image module, for generating a corresponding grain distribution map based on the grain coordinate parameters, yield parameters and card control indicators corresponding to each wafer, wherein the grain distribution map includes a standard area where the yield parameters meet the card control indicators, and a defective area where the yield parameters do not meet the card control indicators; A model module, used to select and locate the defect area in each of the grain distribution maps, and to learn and train the defect features in the image through a convolutional network deep learning model based on the defect classification parameters, so as to obtain a defect classification detection model related to the grain distribution map; The classification module is used to read the unclassified test document uploaded from the test machine through the MES system, and generate a distribution map of the grains to be tested based on the grain coordinate parameters and yield parameters in the unclassified test document, and import the distribution map of the grains to be tested into the defect classification detection model for analysis to obtain the defect classification parameters corresponding to the unclassified test document.
6. The wafer defect monitoring and classification system according to claim 5, characterized in that: The model module is specifically used for: Providing a second classified sample set, and importing each sample in the second classified sample set into a convolutional network deep learning model for testing, so as to obtain model accuracy by comparing the test results with the defect classification parameters in the classified sample set; If the model accuracy is less than a preset value, multiple classified sample sets are provided in sequence to perform learning and training on the defect classification detection model until a defect classification detection model whose model accuracy meets the preset value is obtained.
7. The wafer defect monitoring and classification system according to claim 5, characterized in that: The wafer defect monitoring and classification system further comprises: The preprocessing module is used to process the size of the grain distribution map and perform smoothing and denoising on the grain distribution map.
8. A computer comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the wafer defect monitoring and classification method according to any one of claims 1 to 4 is implemented.
9. A storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the wafer defect monitoring and classification method as described in any one of claims 1 to 4 is implemented.