eMCP Chip Aging Test Device and Its Test Method

Abstract

This application proposes an eMCP chip aging test device and a test method thereof, which sets an embedded system host that is respectively connected to the eMMC part and the LPDDR part. First, the target test scenario is determined, and the target test performance parameters are determined according to the target test scenario; the embedded system host performs a test operation on the LPDDR part according to the target test performance parameters, and stores the first test result of the LPDDR part in a database or external memory; the eMMC controller performs a test operation on the Nand Flash according to the target test performance parameters to obtain a second test result of the eMMC part; during the test operation, the embedded system host sends the first test result to the eMMC controller, and the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash. This application can intuitively reflect the test results of the eMCP product, which is conducive to the tracking of subsequent product test results. It can also reduce the binning cost and reduce the impact of the aging test on the product life.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to an eMCP chip aging test device and a test method thereof. Background Art

[0002] In related technologies, eMCP is a memory device that combines eMMC and LPDDR in a package. Although the two products are packaged together, they operate independently. Therefore, during mass production testing, eMMC and LPDDR are also tested independently. eMMC is a non-volatile storage product, so during testing, test results can be stored in the Nand itself and will not be lost after a power outage. However, the data stored in the LPDDR will be lost after a power outage, so it cannot save the product test results.

[0003] After packaging eMMC and LPDDR together, the two independent products should be considered the same. A test failure for either product should be considered a test failure for the eMCP. However, because LPDDR and eMMC are tested independently and the results are independent, testing requires testing the eMMC and LPDDR separately and analyzing the eMMC and LPDDR test results for binning. This method does not provide a direct representation of the eMCP product test results, increases testing costs, and performing separate aging tests also shortens the product lifespan. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes an eMCP chip aging test device and testing method. These devices are designed to intuitively display the test results of eMCP products, facilitate tracking of subsequent product test results, reduce binning costs, and mitigate the impact of aging testing on product lifespan.

[0005] In a first aspect, an embodiment of the present application provides a testing method for an eMCP chip aging test device, wherein the eMCP chip aging test device includes an embedded system host and an eMCP chip, wherein the eMCP chip includes an eMMC part and an LPDDR part, the eMMC part includes an eMMC controller and a Nand Flash, and the embedded system host is communicatively connected to the eMMC part and the LPDDR part respectively; the method includes:

[0006] Determining a target test scenario, and determining target test performance parameters based on the target test scenario;

[0007] The embedded system host performs a test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part in a database or an external memory;

[0008] The eMMC controller performs a test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part;

[0009] During the test operation, the embedded system host sends the first test result to the eMMC controller, and the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash.

[0010] According to some embodiments of the present application, determining a target test performance parameter according to the target test scenario includes:

[0011] Determine read / write speed requirements and random read / write performance requirements based on the scenario type of the target test scenario;

[0012] Determine target test performance parameters according to the read / write speed requirements and the random read / write performance requirements;

[0013] The scenario type of the target test scenario includes at least one of the following: a mobile device test scenario type, an automotive electronics test scenario type, and an industrial equipment test scenario type.

[0014] According to some embodiments of the present application, when multiple test operations are performed on the LPDDR part and the eMMC part, the method further includes:

[0015] In the case of the same scenario type, for the LPDDR part, comparing the current first test result and the previous first test result, obtaining a first incremental difference result between the current first test result and the previous first test result, and storing the first incremental difference result in a database or an external memory;

[0016] In the case of the same scenario type, for the eMMC part, the current second test result and the previous second test result are compared to obtain a second difference increment result between the current second test result and the previous second test result.

[0017] According to some embodiments of the present application, the eMMC controller integrates the first test result and the second test result, including:

[0018] The eMMC controller obtains the first incremental difference result and the second incremental difference result under the same category of the scenario type;

[0019] Integrating the first incremental difference result and the second incremental difference result to obtain a combined incremental difference result;

[0020] The merged difference increment result is written into the Nand Flash to update the integrated test result stored in the Nand Flash.

[0021] According to some embodiments of the present application, the eMMC part further includes SRAM, and the eMMC controller is communicatively connected to the SRAM; the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash, including:

[0022] The embedded system host accesses the eMMC part through the EMDC interface and writes the first test result into the SRAM;

[0023] The eMMC controller integrates the first test result and the second test result written into the SRAM, and writes the integrated test result into the Nand Flash.

[0024] According to some embodiments of the present application, when there are multiple target test scenarios, the method further includes:

[0025] In the current target test scenario, simultaneously starting the test operation on the LPDDR part and the eMMC part;

[0026] When the LPDDR part completes the test operation under the current target test scenario but the eMMC part has not completed the test operation under the current target test scenario, the eMMC part is kept to continue executing the test operation under the current target test scenario, and at the same time, the embedded system host writes the first test result to the SRAM of the eMMC part, and starts the test operation of the LPDDR part under the next target test scenario.

[0027] According to some embodiments of the present application, after initiating the test operation on the LPDDR part in the next target test scenario, the method further includes:

[0028] When the eMMC part completes the test operation under the current target test scenario, the eMMC controller integrates the first test result and the second test result written to the SRAM, while the embedded system host keeps performing the test operation on the LPDDR part under the next target test scenario.

[0029] According to some embodiments of the present application, after the embedded system host sends the first test result to the eMMC controller, the method further includes:

[0030] When the eMMC controller successfully receives the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception success instruction to the embedded system host;

[0031] When the eMMC controller does not receive the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception failure instruction to the embedded system host;

[0032] In addition, after the eMMC controller integrates the first test result and the second test result and writes the integrated test result into the Nand Flash, the method further includes:

[0033] The eMMC controller generates a result merging completion instruction, and sends the result merging completion instruction to the embedded system host.

[0034] In a second aspect, an embodiment of the present application provides an eMCP chip aging test device, based on the testing method of the eMCP chip aging test device of the first aspect above; the eMCP chip aging test device comprises:

[0035] The eMCP chip includes an eMMC part and an LPDDR part, wherein the eMMC part includes an eMMC controller, NandFlash and SRAM, and the eMMC controller is communicatively connected to the NandFlash and the SRAM respectively;

[0036] The embedded system host is communicatively connected with the eMMC part and the LPDDR part respectively.

[0037] According to some embodiments of the present application, the embedded system host is connected to the eMMC part through an EMDC interface, and the embedded system host is connected to the LPDDR part through a DDR interface or an SDRAM interface.

[0038] In a third aspect, an embodiment of the present application provides a control device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the test method of the eMCP chip aging test device of the first aspect mentioned above when running the computer program.

[0039] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the test method of the eMCP chip aging test device as described in the first aspect above.

[0040] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device performs the test method of the eMCP chip aging test device as described in the first aspect above.

[0041] According to the technical solution of the embodiment of the present application, there are at least the following beneficial effects: the embodiment of the present application sets up an embedded system host, which is communicated with the eMMC part and the LPDDR part respectively. First, the embodiment of the present application determines the target test scenario and determines the target test performance parameters according to the target test scenario; then, the embedded system host performs a test operation on the LPDDR part according to the target test performance parameters, and stores the first test result of the LPDDR part in a database or an external memory; then, the eMMC controller performs a test operation on the Nand Flash according to the target test performance parameters to obtain a second test result of the eMMC part; wherein, during the test operation, the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash. Therefore, the embodiment of the present application can test the eMMC part and the LPDDR part of the eMCP at the same time and in the same environment, which can solve the cost and product life issues; in addition, the test results of the LPDDR part can be integrated into the test results of the eMMC part and saved to Nand Flash, so that the test results of the entire product can be bound to the product. As long as the product is not damaged, the test results will be saved, which is conducive to the tracking of subsequent product test results and reduces the binning cost.

[0042] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0044] Figure 1 This is a schematic diagram of the hardware architecture of an eMCP chip aging test device provided by one embodiment of the present application;

[0045] Figure 2 This is a flow chart of a testing method for an eMCP chip aging testing device provided by one embodiment of the present application;

[0046] Figure 3 yes Figure 2 Flowchart of sub-steps of step S210;

[0047] Figure 4 This is a flow chart of obtaining difference increment results in the case of multiple test operations provided by an embodiment of the present application;

[0048] Figure 5 This is a flow chart of integrating difference increment results in the case of multiple test operations provided by an embodiment of the present application;

[0049] Figure 6 yes Figure 2 Flowchart of sub-steps of step S240;

[0050] Figure 7 This is a flowchart provided by one embodiment of the present application in the case where the LPDDR part completes the test operation under the current target test scenario, but the eMMC part does not complete the test operation under the current target test scenario;

[0051] Figure 8 This is a flowchart provided by one embodiment of the present application after the eMMC part completes the test operation under the current target test scenario, but the eMMC part does not complete the test operation under the current target test scenario;

[0052] Figure 9 This is a data flow diagram of a test method for an eMCP chip aging test device provided by an embodiment of the present application;

[0053] Figure 10 This is a schematic diagram of a control device for executing a test method of an eMCP chip aging test device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0055] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0056] In the description of this application, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The terms "first" and "second" are used solely to distinguish technical features and are not to be construed as indicating or implying relative importance, or as implicitly specifying the number or order of the technical features indicated.

[0057] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0058] In some cases, an eMCP (Embedded Multi-Chip Package) is a memory package consisting of an eMMC (Embedded Multi Media Card) and LPDDR (Low Power Double Data Rate SDRAM). Although these two products are packaged together, they operate independently. Therefore, during mass production testing, eMMC and LPDDR are tested independently. eMMC is a non-volatile storage product, so during testing, test results can be stored in the Nand itself and will not be lost after a power outage. However, the data stored in the LPDDR will be lost after a power outage, so it cannot save the product's test results.

[0059] After packaging eMMC and LPDDR together, the two independent products should be considered the same. A test failure for either product should be considered a test failure for the eMCP. However, because LPDDR and eMMC are tested independently and the results are independent, testing requires testing the eMMC and LPDDR separately and analyzing the eMMC and LPDDR test results for binning. This method does not provide a direct representation of the eMCP product test results, increases testing costs, and performing separate aging tests also shortens the product lifespan.

[0060] Based on the above situation, the embodiments of the present application propose an eMCP chip aging test device and a testing method thereof, which are intended to intuitively reflect the test results of eMCP products, facilitate the tracking of subsequent product test results, and also reduce binning costs and reduce the impact of aging testing on product life.

[0061] The following further describes various embodiments of the eMCP chip aging test device of the present application in conjunction with the accompanying drawings.

[0062] like Figure 1 As shown, Figure 1 This is a schematic diagram of the hardware architecture of an eMCP chip aging test device provided in one embodiment of the present application.

[0063] In one embodiment, the eMCP chip 200 aging test device includes but is not limited to an embedded system host 100 and an eMCP chip 200, wherein the eMCP chip 200 includes an eMMC part 220 and an LPDDR part 210, and the eMMC part 220 includes but is not limited to an eMMC controller and Nand Flash, and the eMMC controller is communicatively connected to the Nand Flash; in addition, the embedded system host 100 is communicatively connected to the eMMC part 220 and the LPDDR part 210 respectively.

[0064] In one embodiment, the eMMC portion 220 also includes but is not limited to SRAM, and the eMMC controller is also in communication with the SRAM.

[0065] In one embodiment, the eMCP chip 200 aging test device further includes but is not limited to an external memory, and the embedded system host 100 is further communicatively connected to the external memory, wherein the external memory can be used to store data, such as test results.

[0066] In one embodiment, the embedded system host 100 may be provided with a database for storing data, such as test results.

[0067] In one embodiment, the embedded system host 100 is connected to the eMMC part 220 through an EMDC interface, and the embedded system host 100 is connected to the LPDDR part 210 through a DDR interface or an SDRAM interface.

[0068] It should be noted that eMMC is a standard specification for embedded memory that packages high-density NAND Flash and an eMMC controller into a single BGA chip. It has the following features:

[0069] Integration: eMMC integrates a Flash controller, which is responsible for memory management, including erase and write leveling, bad block management, ECC checking and other functions.

[0070] Simplified design: eMMC uses a unified MMC standard interface, so users do not need to worry about changes in internal Flash wafer process and technology.

[0071] Performance advantage: eMMC improves read and write speeds by using technologies such as Cache and Memory Array.

[0072] Save space: eMMC is packaged into a single chip, saving more space on the motherboard.

[0073] In addition, it should be noted that LPDDR is a low-power version of double data rate synchronous dynamic random access memory, whose features include:

[0074] Low power design: LPDDR has strict requirements on power consumption and performance.

[0075] Multi-bank: LPDDR memory modules contain multiple banks, and data can be transferred quickly between banks.

[0076] Double Data Rate: Similar to DDR, LPDDR can transmit data twice in each clock cycle, increasing the data transmission rate.

[0077] Based on the hardware structure of the eMCP chip aging test device of each of the above embodiments, various embodiments of the testing method of the eMCP chip aging test device of the present application are respectively proposed below.

[0078] like Figure 2 As shown, Figure 2 This is a flowchart of a testing method for an eMCP chip aging testing device provided by an embodiment of the present application; the testing method for the eMCP chip aging testing device may include but is not limited to step S210, step S220, step S230 and step S240.

[0079] Step S210: determining a target test scenario, and determining target test performance parameters according to the target test scenario;

[0080] Step S220: The embedded system host performs a test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part in a database or an external memory;

[0081] Step S230: The eMMC controller performs a test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part;

[0082] Step S240: During the test operation, the embedded system host sends the first test result to the eMMC controller. The eMMC controller integrates the first test result and the second test result, and writes the integrated test result to NandFlash.

[0083] In one embodiment, first, the embodiment of the present application determines the target test performance parameters according to the target test scenario; then, the embedded system host performs a test operation on the LPDDR part according to the target test performance parameters, and after the test is completed, the first test result of the LPDDR part is stored in a database or an external memory; at the same time, the eMMC part is tested in the form of a self-test, specifically, the eMMC controller performs a test operation on the Nand Flash according to the target test performance parameters, and after the test is completed, a second test result of the eMMC part is obtained; then, the embedded system host sends the first test result to the eMMC controller, and after receiving the first test result, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash.

[0084] It is worth noting that the embodiment of the present application can test the eMMC part and LPDDR part of the eMCP at the same time and environment, which can solve the cost and product life issues; in addition, the test results of the LPDDR part can be integrated into the test results of the eMMC part and saved to Nand Flash, so that the test results of the entire product can be bound to the product. As long as the product is not damaged, the test results will be saved, which is conducive to the tracking of subsequent product test results and reduces the binning cost.

[0085] In addition, if Figure 3 As shown, Figure 3 yes Figure 2 Flowchart of sub-steps of step S210; regarding the above-mentioned step S210, it may include but is not limited to step S310 and step S320.

[0086] Step S310: Determine read / write speed requirements and random read / write performance requirements based on the scenario type of the target test scenario; wherein the scenario type of the target test scenario includes at least one of the following: a mobile device test scenario type, an automotive electronics test scenario type, and an industrial equipment test scenario type;

[0087] Step S320: Determine target test performance parameters according to read / write speed requirements and random read / write performance requirements.

[0088] In one embodiment, since the read and write speed requirements and random read and write performance requirements corresponding to target test scenarios of different scenario types are different, the embodiment of the present application needs to first determine the read and write speed requirements and random read and write performance requirements based on the scenario type of the target test scenario, and then determine the target test performance parameters, such as read and write efficiency, error rate, etc., based on the read and write speed requirements and random read and write performance requirements.

[0089] It should be noted that for mobile device testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows:

[0090] Read and write speed requirements: Mobile devices (such as smartphones and tablets) typically require high eMMC read and write speeds, especially for launching applications, loading games, and playing HD videos. eMMC version 5.1 offers continuous read speeds of up to 400MB / s and continuous write speeds of up to 250MB / s.

[0091] Random read and write performance: Random read and write performance is also important in mobile devices, especially when processing large numbers of small files. eMMC version 5.1 can achieve up to 8K random read IOPS and 6K random write IOPS.

[0092] Application scenario: Mobile devices focus more on user experience, so low latency and high IOPS are key indicators.

[0093] In addition, it should be noted that for automotive electronics testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows:

[0094] Read / write speed requirements: Automotive electronic systems have relatively low requirements for eMMC read / write speeds, but place greater emphasis on reliability and durability. For example, vehicle infotainment and instrument cluster systems generally do not require extremely high read / write speeds, but must operate stably in extreme environments.

[0095] Random read and write performance: Automotive electronic systems have moderate requirements for random read and write performance, focusing primarily on data integrity and reliability.

[0096] Application scenarios: Automotive electronic systems focus more on long-term stability and safety rather than extreme performance.

[0097] In addition, it should be noted that for industrial equipment testing scenarios, the read and write speed requirements, random read and write performance requirements, and application scenarios are as follows:

[0098] Read / write speed requirements: The read / write speed requirements of industrial equipment for eMMC vary depending on the specific application. Some industrial automation equipment may require higher read / write speeds to process large amounts of data, but these are generally not as stringent as those for mobile devices.

[0099] Random read and write performance: Industrial equipment places greater emphasis on data integrity and low latency, especially in scenarios requiring real-time data processing.

[0100] Application scenarios: Industrial equipment usually operates in harsh environments, so high requirements are placed on the durability and reliability of eMMC.

[0101] In addition, if Figure 4 As shown, Figure 4 This is a flowchart of obtaining difference increment results under multiple test operations provided by an embodiment of the present application; the method also includes but is not limited to step S410 and step S420.

[0102] Step S410: Under the same scenario type, for the LPDDR part, compare the current first test result with the previous first test result to obtain a first incremental difference result between the current first test result and the previous first test result, and store the first incremental difference result in a database or an external memory;

[0103] Step S420: Under the same scenario type, for the eMMC part, compare the current second test result with the previous second test result to obtain a second difference increment result between the current second test result and the previous second test result.

[0104] In one embodiment, in order to reduce the amount of transmitted data and improve transmission efficiency and testing efficiency, the embodiment of the present application does not need to fully store the first test result and the second test result each time, but instead stores the difference data of the two test results, as follows:

[0105] For example, under the same category of scenario types, the embedded system host performs multiple test operations on the LPDDR part. For the first test result, the embedded system host will completely record all test data; and for each subsequent test operation, the current first test result and the previous first test result will be compared to obtain the data difference between the two, and then the first difference incremental result between the current first test result and the previous first test result will be obtained. Therefore, for each subsequent test operation, the embedded system host only needs to store and record the first difference incremental result with a smaller amount of data, thereby reducing the amount of transmitted data and improving transmission efficiency and test efficiency.

[0106] Similarly, for example, under the same category of scenario types, the eMMC part will perform multiple tests in the form of self-tests. For the first second test result, the eMMC controller will obtain complete test data, and for each subsequent test operation, the current second test result and the previous second test result will be compared to obtain the data difference between the two, and then the second difference incremental result between the current second test result and the previous second test result will be obtained. Therefore, for each subsequent test operation, the eMMC controller only needs to obtain the second difference incremental result with a smaller amount of data, thereby reducing the amount of transmitted data and improving transmission efficiency and testing efficiency.

[0107] It should be noted that the above-mentioned first incremental difference result or second incremental difference result can only be for the same category of scene types.

[0108] In addition, if Figure 5 As shown, Figure 5 This is a flowchart of integrating difference incremental results under multiple test operations provided by an embodiment of the present application; regarding the eMMC controller in the above step S240 integrating the first test result and the second test result, including but not limited to step S510, step S520 and step S530.

[0109] Step S510: The eMMC controller obtains a first incremental difference result and a second incremental difference result under the same category of scene types;

[0110] Step S520: Integrate the first incremental difference result and the second incremental difference result to obtain a merged incremental difference result;

[0111] Step S530: Write the merged difference increment result to Nand Flash to update the integrated test result stored in Nand Flash.

[0112] In one embodiment, in order to reduce the amount of transmitted data and improve transmission efficiency and test efficiency, the embodiment of the present application does not need to integrate the complete data of each first test result and the second test result. Instead, the first difference increment result and the second difference increment result can be integrated as follows:

[0113] In the same scenario type, if the first incremental difference result and the second incremental difference result are obtained, the eMMC controller will combine them to obtain a combined incremental difference result. The combined incremental difference result is then written to Nand Flash to update the integrated test result stored in Nand Flash. Therefore, for each subsequent test operation, the eMMC controller only needs to combine the first incremental difference result and the second incremental difference result, which have a smaller amount of data. This can reduce the amount of data transmitted and improve transmission efficiency and testing efficiency.

[0114] In addition, if Figure 6 As shown, Figure 6 yes Figure 2 Flowchart of sub-steps of step S240; regarding the above-mentioned step S240, including but not limited to step S610 and step S620.

[0115] Step S610: The embedded system host accesses the eMMC part through the EMDC interface and writes the first test result into SRAM;

[0116] In step S620 , the eMMC controller integrates the first test result and the second test result written into the SRAM, and writes the integrated test result into the Nand Flash.

[0117] In one embodiment, during the test process, after the embedded system host obtains the test result of the LPDDR part, it can access the eMMC through the interface and write the test result of the LPDDR part into the SRAM of the eMMC part. The eMMC controller integrates the first test result of the LPDDR part and the second test result of the eMMC part and writes them into the Nand Flash.

[0118] In addition, if Figure 7 As shown, Figure 7 This is a flowchart provided by an embodiment of the present application in the case where the LPDDR part completes the test operation under the current target test scenario, but the eMMC part does not complete the test operation under the current target test scenario; when there are multiple target test scenarios, the method also includes but is not limited to step S710, step S720 and step S730.

[0119] Step S710: In the current target test scenario, start testing operations on the LPDDR part and the eMMC part simultaneously;

[0120] Step S720: When the LPDDR part completes the test operation under the current target test scenario but the eMMC part does not complete the test operation under the current target test scenario, keep the eMMC part continuing to perform the test operation under the current target test scenario;

[0121] Step S730: At the same time, the embedded system host writes the first test result into the SRAM of the eMMC part, and starts the test operation of the LPDDR part in the next target test scenario.

[0122] In one embodiment, when the test time of the LPDDR part and the test time of the eMMC part are not equal, if the embedded system host writes the first test result to the SRAM after waiting for both the LPDDR part and the eMMC part to complete the test operation, the LPDDR part or the eMMC part that completed the test earlier will have an idle time. In this regard, in order to improve efficiency, the embodiment of the present application can be operated as follows:

[0123] In the current target test scenario, the test operation of the LPDDR part and the eMMC part is started at the same time; then, if the LPDDR part completes the test operation of the current target test scenario earlier than the eMMC part, the eMMC part will continue to perform the test operation of the current target test scenario; at the same time, the embedded system host and the LPDDR part do not need to wait for the eMMC part to complete the operation, but the embedded system host can first write the first test result to the SRAM of the eMMC part, and at the same time, start the test operation of the LPDDR part in the next target test scenario. Therefore, the embodiment of the present application can save the idle time caused by the unequal test time of the LPDDR part and the eMMC part, thereby improving the overall test efficiency.

[0124] In addition, if Figure 8 As shown, Figure 8 This is a flowchart provided by an embodiment of the present application after the eMMC part completes the test operation under the current target test scenario, but the eMMC part does not complete the test operation under the current target test scenario; after the above step S730, the method also includes but is not limited to step S810 and step S820.

[0125] Step S810: When the eMMC part completes the test operation under the current target test scenario, the eMMC controller integrates the first test result and the second test result written to SRAM;

[0126] Step S820: At the same time, the embedded system host continues to perform a test operation on the LPDDR part in the next target test scenario.

[0127] In one embodiment, after the eMMC portion completes the test operation under the current target test scenario, it does not need to wait for the LPDDR portion to complete the test operation under the next target test scenario. Instead, the eMMC controller can immediately integrate the first test result and the second test result written to the SRAM. In addition, at the same time, the embedded system host continues to perform the test operation of the LPDDR portion under the next target test scenario. That is, the eMMC controller's integration operation does not affect the test operation of the LPDDR portion under the next target test scenario. Therefore, the embodiment of the present application can improve overall testing efficiency.

[0128] In one embodiment, after the embedded system host sends the first test result to the eMMC controller, when the eMMC controller successfully receives the first test result sent by the embedded system host within a preset time period, the eMMC controller feeds back a result reception success instruction to the embedded system host.

[0129] Alternatively, in one embodiment, after the embedded system host sends the first test result to the eMMC controller, when the eMMC controller does not receive the first test result sent by the embedded system host within a preset time period, the eMMC controller feeds back a result reception failure instruction to the embedded system host.

[0130] In addition, in one embodiment, after the eMMC controller writes the integrated test results into the Nand Flash, the eMMC controller further generates a result merging completion instruction and sends the result merging completion instruction to the embedded system host.

[0131] Based on the test methods of the eMCP chip aging test device of each of the above embodiments, overall embodiments of the test methods of the eMCP chip aging test device of the present application are respectively proposed below.

[0132] In one embodiment, if Figure 1 and Figure 9As shown in the figure, during the eMCP burn-in test, the host (i.e., the embedded system host) connects to both the eMMC and LPDDR components via the EMDC and DDR interfaces. During the LPDDR burn-in test, the host operates the LPDDR component according to established rules. After the test is complete, the results are stored in external memory or a database. The eMMC component is tested through a self-test, with the eMMC controller performing read, write, and erase tests on the Nand Flash. After the test is complete, the test results are written to a specific location in the Nand Flash. Therefore, during the test, after the LPDDR host receives the test results, it can access the eMMC component via the EMDC interface and write the LPDDR test results to the eMMC SRAM. The eMMC controller then combines the LPDDR and eMMC test results and writes them to the Nand Flash.

[0133] The technical solutions of the embodiments of this application include the following technical effects:

[0134] First, testing the eMMC and LPDDR parts of the eMCP at the same time and in the same environment can solve the cost and product life issues.

[0135] Second, by integrating the LPDDR test results into the eMMC test results and saving them to NandFlash, the test results of the entire product can be bound to the product. As long as the product is not damaged, the test results will be saved, which is conducive to tracking subsequent product test results and reduces binning costs.

[0136] Based on the test methods of the eMCP chip aging test device of each of the above embodiments, various embodiments of the control device, eMCP chip aging test device, computer-readable storage medium and computer program product of the present application are respectively proposed below.

[0137] like Figure 10 As shown, Figure 10 Schematic diagram of a control device for executing a test method for an eMCP chip aging test device according to an embodiment of the present application. The control device 300 implemented in the present application includes: a processor 310, a memory 320, and a computer program stored in the memory 320 and executable on the processor 310, wherein: Figure 10 In the figure, a processor 310 and a memory 320 are taken as an example.

[0138] The processor 310 and the memory 320 may be connected via a bus or other means. Figure 10 The bus connection is taken as an example.

[0139] The memory 320 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 320 may include a high-speed random access memory and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 320 may optionally include a memory 320 remotely located relative to the processor 310, and these remote memories 320 may be connected to the control device 300 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0140] Those skilled in the art will understand that Figure 10 The device structure shown in the figure does not constitute a limitation on the control device 300, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0141] exist Figure 10 In the illustrated control device 300, processor 310 can be used to invoke a control program stored in memory 320 to implement the aforementioned test method for the eMCP chip burn-in test device. Specifically, the non-transient software program and instructions required to implement the aforementioned test method for the eMCP chip burn-in test device are stored in memory 320. When executed by processor 310, the aforementioned test method for the eMCP chip burn-in test device is performed.

[0142] It is worth noting that since the control device 300 of the embodiment of the present application can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the control device 300 of the embodiment of the present application can refer to the specific implementation methods and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0143] In addition, an embodiment of the present application further provides an eMCP chip aging test device, which includes the control device of the above embodiment.

[0144] It is worth noting that since the eMCP chip aging test device of the embodiment of the present application includes the control device of the above embodiment, and the control device of the above embodiment can execute the test method of the eMCP chip aging test device of any of the above embodiments, the specific implementation methods and technical effects of the eMCP chip aging test device of the embodiment of the present application can refer to the specific implementation methods and technical effects of the test methods of the eMCP chip aging test device of any of the above embodiments.

[0145] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the test method of the eMCP chip aging test device described above. Figures 2 to 9 The method steps in .

[0146] It is worth noting that since the computer-readable storage medium of the embodiment of the present application can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer-readable storage medium of the embodiment of the present application can refer to the specific implementation methods and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0147] In addition, an embodiment of the present application further provides a computer program product, including a computer program or computer instructions, the computer program or computer instructions being stored in a computer-readable storage medium, the processor of a computer device reading the computer program or computer instructions from the computer-readable storage medium, and the processor executing the computer program or computer instructions, so that the computer device executes the test method of the eMCP chip aging test device described above. For example, the above-described Figures 2 to 9 The method steps in .

[0148] It is worth noting that since the computer program product of the embodiment of the present application can execute the test method of the eMCP chip aging test device of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer program product of the embodiment of the present application can refer to the specific implementation methods and technical effects of the test method of the eMCP chip aging test device of any of the above-mentioned embodiments.

[0149] Those skilled in the art will appreciate that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, or any suitable combination thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0150] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0152] It should also be understood that the various implementation methods provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0153] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the art can also make various equivalent modifications or substitutions under the shared conditions that do not violate the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A testing method for an eMCP chip aging test device, characterized in that: The eMCP chip aging test device includes an embedded system host and an eMCP chip, wherein the eMCP chip includes an eMMC part and an LPDDR part, the eMMC part includes an eMMC controller and a Nand Flash, and the embedded system host is communicatively connected to the eMMC part and the LPDDR part respectively; the method includes: Determining a target test scenario, and determining target test performance parameters based on the target test scenario; The embedded system host performs a test operation on the LPDDR part according to the target test performance parameter, and stores a first test result of the LPDDR part in a database or an external memory; The eMMC controller performs a test operation on the Nand Flash according to the target test performance parameter to obtain a second test result of the eMMC part; During the test operation, the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash; The scenario type of the target test scenario includes at least one of the following: a mobile device test scenario type, an automotive electronics test scenario type, and an industrial equipment test scenario type; In addition, when multiple test operations are performed on the LPDDR part and the eMMC part, the method further includes: In the case of the same scenario type, for the LPDDR part, comparing the current first test result and the previous first test result, obtaining a first incremental difference result between the current first test result and the previous first test result, and storing the first incremental difference result in a database or an external memory; In the case of the same scenario type, for the eMMC part, comparing the current second test result and the previous second test result to obtain a second difference increment result between the current second test result and the previous second test result; In addition, the eMMC controller integrates the first test result and the second test result, including: The eMMC controller obtains the first incremental difference result and the second incremental difference result under the same category of the scenario type; Integrating the first incremental difference result and the second incremental difference result to obtain a combined incremental difference result; The merged difference increment result is written into the Nand Flash to update the integrated test result stored in the Nand Flash.

2. The method according to claim 1, characterized in that Determining the target test performance parameter according to the target test scenario includes: Determine read / write speed requirements and random read / write performance requirements based on the scenario type of the target test scenario; Target test performance parameters are determined according to the read and write speed requirements and the random read and write performance requirements.

3. The method according to claim 1, characterized in that The eMMC part further includes SRAM, and the eMMC controller is communicatively connected to the SRAM; the embedded system host sends the first test result to the eMMC controller, the eMMC controller integrates the first test result and the second test result, and writes the integrated test result to the Nand Flash, including: The embedded system host accesses the eMMC part through the EMDC interface and writes the first test result into the SRAM; The eMMC controller integrates the first test result and the second test result written into the SRAM, and writes the integrated test result into the Nand Flash.

4. The method according to claim 3, characterized in that In the case where there are multiple target test scenarios, the method further includes: In the current target test scenario, simultaneously starting the test operation on the LPDDR part and the eMMC part; When the LPDDR part completes the test operation under the current target test scenario but the eMMC part has not completed the test operation under the current target test scenario, the eMMC part is kept to continue executing the test operation under the current target test scenario, and at the same time, the embedded system host writes the first test result to the SRAM of the eMMC part, and starts the test operation of the LPDDR part under the next target test scenario.

5. The method according to claim 4, characterized in that After initiating the test operation on the LPDDR part in the next target test scenario, the method further includes: When the eMMC part completes the test operation under the current target test scenario, the eMMC controller integrates the first test result and the second test result written to the SRAM, while the embedded system host keeps performing the test operation on the LPDDR part under the next target test scenario.

6. The method according to claim 1, characterized in that After the embedded system host sends the first test result to the eMMC controller, the method further includes: When the eMMC controller successfully receives the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception success instruction to the embedded system host; When the eMMC controller does not receive the first test result sent by the embedded system host within a preset time, the eMMC controller feeds back a result reception failure instruction to the embedded system host; In addition, after the eMMC controller integrates the first test result and the second test result and writes the integrated test result into the Nand Flash, the method further includes: The eMMC controller generates a result merging completion instruction, and sends the result merging completion instruction to the embedded system host.

7. An eMCP chip aging test device, characterized in that: A testing method based on the eMCP chip aging testing device according to any one of claims 1 to 6; The eMCP chip aging test device includes: The eMCP chip includes an eMMC part and an LPDDR part, wherein the eMMC part includes an eMMC controller, NandFlash and SRAM, and the eMMC controller is communicatively connected to the NandFlash and the SRAM respectively; The embedded system host is communicatively connected with the eMMC part and the LPDDR part respectively.

8. The eMCP chip aging test device according to claim 7, characterized in that: The embedded system host is connected to the eMMC part through an EMDC interface, and the embedded system host is connected to the LPDDR part through a DDR interface or an SDRAM interface.

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