Chip packaging method and chip packaging structure
By encapsulating a single glass core unit and forming a uniform packaging layer and an asymmetric wiring layer on its peripheral side, the warping problem caused by thermal stress differences in semiconductor chip packaging is solved, and the reliability and stability of the chip are improved.
Patent Information
- Application Number
- CN202411816285.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-04
AI Technical Summary
In the prior art, during the packaging process of semiconductor chips, the thermal expansion coefficients of the material between the glass substrate and the packaging layer do not match, resulting in a difference in thermal stress, which may cause warping of the glass substrate and affect the reliability and stability of the chip.
By encapsulating a single glass core unit, a uniform first encapsulation layer is formed on its peripheral side, and an asymmetric first and second re-wiring layer are made on one side of the glass core unit. Through the electrical connection and filling of the glue layer at these levels, a stable chip encapsulation structure is formed.
This method not only provides mechanical protection for the glass core unit and reduces external physical damage, but also better controls the thermal expansion of the glass core unit, reduces thermal stress concentration and warping, and improves the reliability and stability of the packaging products.
Smart Images
Figure CN119764185A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a chip packaging method and a chip packaging structure. Background Art
[0002] In semiconductor technology, packaging is an important part of the production and processing of semiconductor integrated circuit chips. It can not only place, fix, seal and protect the chips, but also enhance the electrical and thermal performance. At the same time, it can also realize the transmission of data and signals between the internal and external circuits of the chip. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging method and a chip packaging structure.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging method, the chip packaging method comprising:
[0005] Providing a glass substrate, and cutting the glass substrate to obtain a plurality of independent glass core units, wherein the glass core unit includes a wiring layer running through the glass core unit;
[0006] Encapsulating at least one of the glass core units, and forming a first encapsulation layer on the periphery of the glass core unit;
[0007] Making a first redistribution layer electrically connected to the routing layer on one side of the glass core unit;
[0008] Manufacturing a chip layer on a side of the first redistribution layer away from the glass core unit, wherein the chip layer includes at least one chip electrically connected to the first redistribution layer;
[0009] A second redistribution layer electrically connected to the routing layer is fabricated on a side of the glass core unit away from the first redistribution layer, the second redistribution layer is electrically connected to the first redistribution layer through the routing layer, the first redistribution layer and the second redistribution layer are asymmetric structures, wherein the first redistribution layer and the second redistribution layer include at least one redistribution sublayer composed of a dielectric material and an electrode routing, and the first redistribution layer and the second redistribution layer are different in at least one of the number of redistribution sublayers, the type of dielectric material, the thickness of the dielectric material and the thickness of the routing.
[0010] In a possible implementation, the step of encapsulating at least one of the glass core units and forming a first encapsulation layer on the circumference of the glass core unit includes:
[0011] Providing a first carrier, manufacturing a first adhesive layer on one side of the first carrier, and bonding at least one of the glass core units to the first adhesive layer;
[0012] Performing packaging processing on the bonded glass core unit to form a first packaging material layer covering the glass core unit;
[0013] The first packaging material layer is ground until the surface of the glass core unit is exposed to obtain the first packaging layer.
[0014] In a possible implementation, the step of manufacturing a chip layer on a side of the first redistribution layer away from the glass core unit includes:
[0015] At least one chip is placed on a side of the first redistribution layer away from the glass core unit, wherein the electrode pins of the chip face the first redistribution layer and are electrically connected to the first redistribution layer;
[0016] A bottom filling glue layer is formed between the chip and the first redistribution layer to obtain the chip layer.
[0017] In a possible implementation, after the step of forming an underfill glue layer between the chip and the first redistribution layer to obtain the chip layer, the method further includes the step of making a second packaging layer, which includes:
[0018] Performing packaging processing on the first redistribution layer and the manufactured chip layer to form a second packaging material layer covering the chip layer and the first redistribution layer;
[0019] The second packaging material layer is ground to obtain a second packaging layer.
[0020] In a possible implementation, the step of manufacturing a second redistribution layer electrically connected to the routing layer on a side of the glass core unit away from the first redistribution layer includes:
[0021] Removing the first adhesive layer, and separating the glass core unit on which the chip layer is made from from the first carrier board;
[0022] Providing a second carrier, bonding the second carrier to the second packaging layer, or bonding the second carrier to a side of the chip layer away from the glass core unit;
[0023] A second redistribution layer electrically connected to the routing layer is manufactured on a side of the glass core unit away from the first redistribution layer.
[0024] In a possible implementation, after the step of manufacturing a second redistribution layer electrically connected to the routing layer on a side of the glass core unit away from the first redistribution layer, the method further includes:
[0025] Performing ball planting processing on a side of the second redistribution layer away from the glass core unit to obtain conductive balls electrically connected to the second redistribution layer;
[0026] When there are multiple glass core units, the packaging structure of the conductive balls is cut to obtain a chip packaging structure including one glass core unit, wherein the chip packaging structure includes at least one chip.
[0027] In a second aspect, an embodiment of the present application further provides a chip packaging structure, wherein the chip packaging structure is manufactured by the chip packaging method described in any one of the first aspects above, including:
[0028] A glass core unit, wherein the glass core unit includes a wiring layer passing through the glass core unit;
[0029] A first encapsulation layer, wherein the first encapsulation layer is located on a peripheral side of the glass core unit;
[0030] A first redistribution layer, the first redistribution layer is located on one side of the glass core unit, and the first redistribution layer is electrically connected to the routing layer;
[0031] A chip layer, the chip layer is located on a side of the first redistribution layer away from the glass core unit, and the chip layer includes at least one chip;
[0032] A second redistribution layer, wherein the second redistribution layer is located on a side of the glass core unit away from the first redistribution layer, the second redistribution layer is electrically connected to the routing layer, the first redistribution layer and the second redistribution layer are asymmetric structures, wherein the first redistribution layer and the second redistribution layer include at least one redistribution sublayer composed of a dielectric material and an electrode routing, and the first redistribution layer and the second redistribution layer are different in at least one of the number of redistribution sublayers, the type of dielectric material, the thickness of the dielectric material and the thickness of the routing.
[0033] In a possible implementation manner, the chip packaging structure further includes a second packaging layer;
[0034] The second packaging layer is located on the periphery of the first redistribution layer and the chip layer, or the second packaging layer covers the first redistribution layer and the chip layer.
[0035] In a possible implementation, the chip layer further includes an underfill glue, and the underfill glue is located between the chip and the first redistribution layer;
[0036] The chip packaging structure further includes a conductive ball electrically connected to the second redistribution layer, and the conductive ball is located on a side of the second redistribution layer away from the glass core unit.
[0037] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the chip packaging structure described in any one of the second aspects.
[0038] Based on any one of the above aspects, the embodiments of the present application provide a chip packaging method and a chip packaging structure. By encapsulating a single glass core unit, a uniform first plastic sealing layer is formed on its periphery. This can not only provide mechanical protection for the glass core unit and reduce external physical damage, but also better control the thermal expansion of each glass core unit when the temperature changes, so that the thermal stress is evenly distributed on the periphery of the glass core unit, reducing stress concentration and warping caused by mismatch of material thermal expansion coefficients, and reducing the influence of subsequently manufactured asymmetric structures (i.e., the first redistribution layer and the second redistribution layer) on warping, thereby improving the reliability and stability of the final packaged product. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0040] Figure 1 A schematic diagram of a process flow of a chip packaging method provided in an embodiment of the present application;
[0041] Figure 2 for Figure 1 The corresponding process diagram;
[0042] Figure 3 for Figure 1 Schematic diagram of the sub-step flow chart of step S120;
[0043] Figure 4 Another schematic diagram of a chip packaging method according to an embodiment of the present application;
[0044] Figure 5 for Figure 4 The corresponding process diagram;
[0045] Figure 6 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 1 ;
[0046] Figure 7 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION
[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0048] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0050] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0051] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0052] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0053] The inventors found that in the relevant chip asymmetric manufacturing process, the glass substrate including multiple glass core units is usually first encapsulated on the entire surface, and then an asymmetric redistribution layer is made on the opposite sides of the glass substrate after the entire surface is encapsulated. However, due to the mismatch in the coefficient of thermal expansion (CTE) of the material between the glass substrate and the encapsulation layer, the glass substrate and / or the encapsulation layer may expand or contract to different degrees when the temperature changes, thereby generating a large difference in thermal stress, causing the glass substrate after the entire surface is encapsulated to warp. In addition, the asymmetric structure on the opposite sides of the glass substrate may aggravate the degree of warping. If the degree of warping is too large, it may cause damage to the chip, affecting product performance and reliability.
[0054] In addition, in the related art of encapsulating the entire surface of a glass substrate, in the encapsulation structure including a single glass core unit obtained by cutting, the peripheral side of the glass core unit is often exposed to the outside, which is easily subject to external physical damage and has low reliability.
[0055] To solve the problems in the prior art, please refer to Figure 1 and Figure 2 , the present application embodiment provides a chip packaging method, please refer to Figure 1 and Figure 2 , Figure 1 FIG. 1 is a flow chart of a chip packaging method. Figure 2 for Figure 1 The corresponding process diagram. Figure 1 and Figure 2 Each step of the chip packaging method is described in detail.
[0056] Step S110: providing a glass substrate, and cutting the glass substrate to obtain a plurality of independent glass core units.
[0057] In this step, the glass substrate may include a plurality of independent glass core units 110 and cutting paths between adjacent glass core units 110, and the glass substrate may be laser cut or wire cut based on the cutting paths to obtain a plurality of independent glass core units 110. The glass core unit 110 may include a through-glass hole penetrating the glass core unit 110 and a routing layer 111 located on the surface of the through-glass hole, and the extension direction of the through-glass hole may be perpendicular to the surface where the glass substrate is located. Specifically, the routing layer 111 may include a seed layer and a metal layer, the seed layer being located on the inner wall of the through-glass hole and at least a portion of the surface of the glass core unit 110, and the metal layer being located on the side of the seed layer away from the through-glass hole. In addition, the glass core unit 110 may also include an ABF filling layer, the ABF filling layer may be located in the through-glass hole and on the surface of the glass core unit 110, wherein the ABF filling layer at least partially exposes the routing layer 111. Exemplarily, the material of the ABF filling layer includes, but is not limited to, ABF (Ajinomoto Build-up Film) material.
[0058] Step S120: encapsulating at least one glass core unit, and forming a first encapsulation layer on the peripheral side of the glass core unit.
[0059] In this step, the material of the first packaging layer 120 includes but is not limited to epoxy molding compound (EMC). The first packaging layer 120 is used to provide mechanical protection and electrical insulation for the glass core unit 110 to improve the reliability of the final packaged product.
[0060] Step S130: manufacturing a first redistribution layer electrically connected to the routing layer on one side of the glass core unit.
[0061] In this step, the first redistribution layer 130 can reconstruct the electrical connection lines to improve the efficiency and flexibility of signal transmission.
[0062] Step S140: manufacturing a chip layer on a side of the first redistribution layer away from the glass core unit.
[0063] In this step, the chip layer 140 includes at least one chip 141 electrically connected to the first redistribution layer 130, and the electrode pins of the chip 141 face the first redistribution layer 130 and are electrically connected to the first redistribution layer 130. Exemplarily, the chip 141 includes a highly integrated chip such as a system-on-chip (SoC chip) and a high-bandwidth memory chip (HBM).
[0064] Step S150: manufacturing a second redistribution layer 150 electrically connected to the routing layer on a side of the glass core unit away from the first redistribution layer.
[0065] In this step, the second rewiring is electrically connected to the first rewiring layer 130 through the routing layer 111, wherein the first rewiring layer and the second rewiring layer are asymmetric structures, specifically, the first rewiring layer and the second rewiring layer include at least one rewiring sublayer composed of dielectric material and electrode routing, and the first rewiring layer and the second rewiring layer are different in at least one of the number of rewiring sublayers, the type of dielectric material, the thickness of dielectric material and the thickness of routing. Exemplarily, the second rewiring layer 150 can be an ABF rewiring layer, and the spacing between adjacent conductive routings of the second rewiring layer 150 is smaller than the spacing between adjacent conductive routings of the first rewiring layer 130, that is, the integration of the second rewiring layer 150 is greater than the integration of the first rewiring layer 130.
[0066] In this embodiment, by encapsulating a single glass core unit 110 and forming a uniform first plastic sealing layer on its periphery, not only can mechanical protection be provided for the glass core unit 110 and external physical damage be reduced, but also the thermal expansion of each glass core unit 110 can be better controlled when the temperature changes, so that the thermal stress is evenly distributed on the periphery of the glass core unit 110, reducing stress concentration and warping caused by mismatch of material thermal expansion coefficients, and reducing the influence of the subsequently manufactured asymmetric structure (i.e., the first redistribution layer 130 and the second redistribution layer) on the warping, thereby improving the reliability and stability of the final packaged product.
[0067] For some possible embodiments, please refer to Figure 3 , step S120 can be implemented by the following method.
[0068] Step S121: providing a first carrier board, manufacturing a first adhesive layer on one side of the first carrier board, and bonding at least one glass core unit 110 to the first adhesive layer.
[0069] In this step, the first carrier can be, but is not limited to, a glass carrier, a resin carrier, etc. The first adhesive layer can be made of a thermal peeling and / or laser peeling material, wherein the first adhesive layer can be removed by heating and / or laser treatment. Exemplarily, when the first carrier is a glass carrier, the first adhesive layer is made of a laser peeling material.
[0070] Step S122 : performing packaging processing on the bonded glass core unit 110 to form a first packaging material layer covering the glass core unit 110 .
[0071] In this step, the bonded glass core unit 110 is placed in a plastic encapsulation mold, and the plastic encapsulation material is pressed into the mold by injection molding to form a first encapsulation material layer covering the glass core unit 110. The first encapsulation material layer is demoulded after being cooled and solidified.
[0072] Step S123 : grinding the first packaging material layer until the surface of the glass core unit 110 is exposed to obtain the first packaging layer 120 .
[0073] In this step, the surface of the glass core unit 110 is exposed by grinding to facilitate the subsequent electrical connection between the first redistribution layer 130 and / or the second redistribution layer 150 and the routing layer 111 .
[0074] Furthermore, in step S130, at least one chip 141 may be placed on the side of the first redistribution layer 130 away from the glass core unit 110, with the electrode pins of the chip 141 facing the first redistribution layer 130 and electrically connected to the first redistribution layer 130. Next, a bottom filling glue layer is formed between the chip 141 and the first redistribution layer 130 to obtain the chip layer 140. Among them, a suitable bottom filling material may be selected according to the material properties (such as thermal expansion coefficient) of the chip 141 and the first redistribution layer 130, and the bottom filling material may be dotted between the chip 141 and the first redistribution layer 130, and finally filled in the gap between the chip 141 and the first redistribution layer 130 by heating, and the bottom filling glue layer is formed after the bottom filling material is cooled and solidified. The bottom filling glue layer can improve the mechanical connection strength between the chip 141 and the routing layer 111, and protect the chip 141 from physical loss.
[0075] In addition, after step S130, the first rewiring layer 130 and the manufactured chip layer 140 can also be packaged to form a second packaging material layer covering the chip layer 140 and the first rewiring layer 130, and the second packaging material layer is ground to obtain a second packaging layer. Specifically, the glass core unit 110 with the manufactured chip layer 140 is placed in a plastic packaging mold, and the plastic packaging material is pressed into the mold by injection molding to form a second packaging material layer covering the chip layer 140 and the first rewiring layer 130, and the second packaging material layer is demoulded after cooling and solidifying. Then, the second packaging material layer can be ground according to the actual needs of the product until the surface of the second packaging material layer is flat and meets the preset size range. Exemplarily, the second packaging material layer can be ground until the side of the chip layer 140 opposite to the electrode pin is exposed, at which time the surface of the chip layer 140 is flush with the surface of the second plastic packaging layer, effectively improving the heat dissipation performance of the chip 141. The second packaging layer can protect the chip layer 140 and the second redistribution layer 150 from water vapor intrusion, and improve the mechanical strength of the overall structure, thereby improving the reliability of the final packaged product.
[0076] It is not difficult to understand that the materials of the first packaging layer 120 and the second packaging layer can be the same or different. Preferably, the materials of the first packaging layer 120 and the second packaging layer are the same to avoid thermal stress differences caused by different thermal expansion coefficients of the first packaging layer 120 and the second packaging layer, thereby reducing the risk of cracking due to thermal stress differences.
[0077] Furthermore, in step S150, the first adhesive layer can be removed by heating and / or laser treatment to separate the glass core unit 110 with the chip layer 140 made thereon from the first carrier. Next, a second carrier is provided, and a second adhesive layer is made on one side of the second carrier using a thermal stripping and / or laser stripping material, and the second carrier is bonded to the second packaging layer through the second adhesive layer, or the second carrier is bonded to the side of the chip layer 140 away from the glass core unit 110, wherein the second carrier can be, but is not limited to, a glass carrier, a resin carrier, etc. Finally, a second redistribution layer 150 electrically connected to the routing layer 111 is made on the side of the glass core unit 110 away from the first redistribution.
[0078] For some possible embodiments, please refer to Figure 4 and Figure 5 After step S150, the chip packaging method provided in the embodiment of the present application may further include the following steps.
[0079] Step S160 : performing ball planting processing on a side of the second redistribution layer 150 away from the glass core unit 110 to obtain a conductive ball 160 electrically connected to the second redistribution layer 150 .
[0080] Specifically, the prefabricated conductive balls 160 can be transferred to the conductive bumps and / or conductive recesses on the side of the second redistribution layer 150 away from the glass core unit 110, so that the conductive balls 160 are electrically connected to the traces in the second redistribution layer 150. The conductive balls 160 can play a role of adhesion and diffusion when the chip packaging structure is welded with other electronic devices.
[0081] Step S170 : when there are multiple glass core units 110 , cutting the package structure with the conductive balls 160 to obtain a chip package structure including one glass core unit 110 .
[0082] Specifically, the packaging structure with the conductive balls 160 manufactured can be cut by laser cutting or wire cutting to obtain a chip packaging structure including a glass core unit 110 , wherein the chip packaging structure includes at least one chip 141 .
[0083] Based on the same inventive concept, please refer to Figure 6 The present application also provides a chip packaging structure 10 manufactured according to the chip packaging method in the above embodiment. The chip packaging structure 10 may include a glass core unit 110, a first packaging layer 120, a first redistribution layer 130, a chip layer 140 and a second redistribution layer 150.
[0084] The glass core unit 110 may include a through-glass hole penetrating the glass core unit 110 and a routing layer 111 located on the surface of the through-glass hole, and the extension direction of the through-glass hole may be perpendicular to the surface where the glass substrate is located. Specifically, the routing layer 111 may include a seed layer and a metal layer, the seed layer is located on the inner wall of the through-glass hole and at least a portion of the surface of the glass core unit 110, and the metal layer is located on the side of the seed layer away from the through-glass hole. In addition, the glass core unit 110 may also include an ABF filling layer, and the ABF filling layer may be located in the through-glass hole and on the surface of the glass core unit 110, wherein the ABF filling layer at least partially exposes the routing layer 111. Exemplarily, the material of the ABF filling layer includes, but is not limited to, ABF (Ajinomoto Build-up Film) material.
[0085] The first encapsulation layer 120 is located on the peripheral side of the glass core unit 110. The material of the first encapsulation layer 120 includes but is not limited to epoxy molding compound (EMC). The first encapsulation layer 120 can protect the glass core unit 110 from physical damage (such as vibration, impact, etc.) and environmental factors (such as temperature, dust, etc.), provide mechanical protection and electrical insulation for the glass core unit 110, and improve the reliability of the final encapsulated product.
[0086] The first redistribution layer 130 is located on one side of the glass core unit 110, and the first redistribution layer 130 is electrically connected to the routing layer 111. The chip layer 140 is located on the side of the first redistribution layer 130 away from the glass core unit 110, and the chip layer 140 includes at least one chip 141, and the electrode pins of the chip 141 face the first redistribution layer 130 and are electrically connected to the first redistribution layer 130. Exemplarily, the chips 141131 include highly integrated chips 141 such as a system-on-chip 141 (SoC chip 141) and a high-bandwidth memory chip 141 (HBM).
[0087] The second rewiring layer 150 is located on the side of the glass core unit 110 away from the first rewiring layer 130. The second rewiring layer 150 is electrically connected to the first rewiring layer 130 through the routing layer 111. The first rewiring layer 130 and the second rewiring layer 150 can reconstruct the electrical connection line to improve the efficiency and flexibility of signal transmission. Among them, the first rewiring layer and the second rewiring layer are asymmetric structures. Specifically, the first rewiring layer and the second rewiring layer include at least one rewiring sublayer composed of dielectric material and electrode routing. The first rewiring layer and the second rewiring layer are different in at least one of the number of rewiring sublayers, the type of dielectric material, the thickness of the dielectric material and the thickness of the routing. Exemplarily, the second rewiring layer 150 can be an ABF rewiring layer, and the spacing between adjacent conductive routings of the second rewiring layer 150 is smaller than the spacing between adjacent conductive routings of the first rewiring layer 130, that is, the integration of the second rewiring layer 150 is greater than the integration of the first rewiring layer 130.
[0088] In this embodiment, a single glass core unit is encapsulated and a uniform first plastic sealing layer is formed on its periphery, which can not only provide mechanical protection for the glass core unit and reduce external physical damage, but also better control the thermal expansion of each glass core unit when the temperature changes, so that the thermal stress is evenly distributed on the periphery of the glass core unit, reducing stress concentration and warping caused by mismatch of material thermal expansion coefficients, and reducing the influence of the subsequently manufactured asymmetric structure (i.e., the first redistribution layer and the second redistribution layer) on the warping, thereby improving the reliability and stability of the final packaged product.
[0089] For further information, please refer to Figure 7 The chip packaging structure 10 further includes a second packaging layer 170, which is located on the peripheral side of the first redistribution layer 130 and the chip layer 140, that is, the surface of the second packaging layer 170 is flush with the surface of the chip layer 140 to improve the heat dissipation performance of the chip 141. Alternatively, in order to improve the mechanical strength of the chip layer 140, the second packaging layer 170 can cover the first redistribution layer 130 and the chip layer 140. The chip layer 140 further includes a bottom filling glue 142, which is located between the chip 141 and the first redistribution layer 130. The bottom filling glue 142 can improve the mechanical connection strength between the chip 141 and the routing layer 111, and protect the chip 141 from physical loss.
[0090] Please refer again Figure 7 The chip packaging structure 10 also includes a conductive ball 160 electrically connected to the second redistribution layer 150. The conductive ball 160 is located on a side of the second redistribution layer 150 away from the glass core unit 110. The conductive ball 160 can play a role of adhesion and diffusion when the chip packaging structure 10 is welded with other electronic devices.
[0091] In addition, an embodiment of the present application also provides an electronic device, including a chip packaging structure 10 manufactured by the chip packaging method of any one of the above embodiments, or a chip packaging structure 10 of any one of the above embodiments.
[0092] In summary, the embodiment of the present application provides a chip packaging method and a chip packaging structure 10, which encapsulates a single glass core unit 110 and forms a uniform first plastic sealing layer on its periphery. It can not only provide mechanical protection for the glass core unit 110 and reduce external physical damage, but also better control the thermal expansion of each glass core unit 110 when the temperature changes, so that the thermal stress is evenly distributed on the periphery of the glass core unit 110, reducing stress concentration and warping caused by mismatch of material thermal expansion coefficients, and reducing the influence of the subsequently manufactured asymmetric structure (i.e., the first redistribution layer 130 and the second redistribution layer) on the warping, thereby improving the reliability and stability of the final packaged product.
[0093] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging method, characterized in that: The method comprises: Providing a glass substrate, and cutting the glass substrate to obtain a plurality of independent glass core units, wherein the glass core unit includes a wiring layer running through the glass core unit; Encapsulating at least one of the glass core units, and forming a first encapsulation layer on the periphery of the glass core unit; Making a first redistribution layer electrically connected to the routing layer on one side of the glass core unit; Manufacturing a chip layer on a side of the first redistribution layer away from the glass core unit, wherein the chip layer includes at least one chip electrically connected to the first redistribution layer; A second redistribution layer electrically connected to the routing layer is fabricated on a side of the glass core unit away from the first redistribution layer, the second redistribution layer is electrically connected to the first redistribution layer through the routing layer, the first redistribution layer and the second redistribution layer are asymmetric structures, wherein the first redistribution layer and the second redistribution layer include at least one redistribution sublayer composed of a dielectric material and an electrode routing, and the first redistribution layer and the second redistribution layer are different in at least one of the number of redistribution sublayers, the type of dielectric material, the thickness of the dielectric material and the thickness of the routing.
2. The chip packaging method according to claim 1, characterized in that: The step of encapsulating at least one of the glass core units and forming a first encapsulation layer on the circumference of the glass core unit comprises: Providing a first carrier, manufacturing a first adhesive layer on one side of the first carrier, and bonding at least one of the glass core units to the first adhesive layer; Performing packaging processing on the bonded glass core unit to form a first packaging material layer covering the glass core unit; The first packaging material layer is ground until the surface of the glass core unit is exposed to obtain the first packaging layer.
3. The chip packaging method according to claim 1, characterized in that: The step of manufacturing a chip layer on a side of the first redistribution layer away from the glass core unit comprises: At least one chip is placed on a side of the first redistribution layer away from the glass core unit, wherein the electrode pins of the chip face the first redistribution layer and are electrically connected to the first redistribution layer; A bottom filling glue layer is formed between the chip and the first redistribution layer to obtain the chip layer.
4. The chip packaging method according to claim 3, characterized in that: After the step of forming a bottom filling glue layer between the chip and the first redistribution layer to obtain the chip layer, the method further includes the step of making a second packaging layer, which step includes: Performing packaging processing on the first redistribution layer and the manufactured chip layer to form a second packaging material layer covering the chip layer and the first redistribution layer; The second packaging material layer is ground to obtain a second packaging layer.
5. The chip packaging method according to claim 4, characterized in that: The step of manufacturing a second redistribution layer electrically connected to the routing layer on a side of the glass core unit away from the first redistribution layer comprises: Removing the first adhesive layer, and separating the glass core unit on which the chip layer is made from from the first carrier board; Providing a second carrier, bonding the second carrier to the second packaging layer, or bonding the second carrier to a side of the chip layer away from the glass core unit; A second redistribution layer electrically connected to the routing layer is manufactured on a side of the glass core unit away from the first redistribution layer.
6. The chip packaging method according to claim 5, characterized in that: After the step of manufacturing a second redistribution layer electrically connected to the routing layer on a side of the glass core unit away from the first redistribution layer, the method further comprises: Performing ball planting processing on a side of the second redistribution layer away from the glass core unit to obtain conductive balls electrically connected to the second redistribution layer; When there are multiple glass core units, the packaging structure of the conductive balls is cut to obtain a chip packaging structure including one glass core unit, wherein the chip packaging structure includes at least one chip.
7. A chip packaging structure, characterized in that: The chip packaging structure is manufactured by the chip packaging method according to any one of claims 1 to 6, including: A glass core unit, wherein the glass core unit includes a wiring layer passing through the glass core unit; A first encapsulation layer, wherein the first encapsulation layer is located on a peripheral side of the glass core unit; A first redistribution layer, the first redistribution layer is located on one side of the glass core unit, and the first redistribution layer is electrically connected to the routing layer; A chip layer, the chip layer is located on a side of the first redistribution layer away from the glass core unit, and the chip layer includes at least one chip; A second redistribution layer, wherein the second redistribution layer is located on a side of the glass core unit away from the first redistribution layer, the second redistribution layer is electrically connected to the routing layer, the first redistribution layer and the second redistribution layer are asymmetric structures, wherein the first redistribution layer and the second redistribution layer include at least one redistribution sublayer composed of a dielectric material and an electrode routing, and the first redistribution layer and the second redistribution layer are different in at least one of the number of redistribution sublayers, the type of dielectric material, the thickness of the dielectric material and the thickness of the routing.
8. The chip packaging structure according to claim 7, characterized in that: The chip packaging structure also includes a second packaging layer; The second packaging layer is located on the periphery of the first redistribution layer and the chip layer, or the second packaging layer covers the first redistribution layer and the chip layer.
9. The chip packaging structure according to claim 7, characterized in that: The chip layer further comprises an underfill glue, wherein the underfill glue is located between the chip and the first redistribution layer; The chip packaging structure further includes a conductive ball electrically connected to the second redistribution layer, and the conductive ball is located on a side of the second redistribution layer away from the glass core unit.
10. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 7 to 9.