Virtual impedance adjustment-based low-voltage ride-through control method for network-forming inverter

Abstract

According to the virtual impedance adjustment-based low-voltage ride-through control method for the grid-forming type inverter, the voltage source characteristics of the inverter are maintained by locking a power loop during a fault period so as to support a power grid; the virtual impedance input in the fault initial transient stage is determined according to the national standard injected reactive current requirement and the fault initial stage impact current limitation, and after the fault initial transient stage is ended, the virtual resistor is quitted to enter the fault steady-state stage, so that the inverter injects the reactive current meeting the national standard requirement in the fault steady-state stage, and the inverter is controlled to be in the fault steady-state stage. And determining the virtual impedance of the stage according to the impact current limitation in the fault ending transient stage, exiting the virtual impedance of the system after the fault ending transient stage is ended, and unlocking the power ring. According to the method, the fault current is limited in the fault starting transient stage, the current decay time is shortened, the fault current is limited in the fault steady state stage, reactive current meeting the national standard requirement is injected, and finally the impact current caused by fault recovery is limited in the fault ending transient stage.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy utilization, and in particular to a low voltage ride-through control method for a grid-connected inverter based on virtual impedance regulation. Background Art

[0002] Developing new energy is a necessary way to deal with environmental pollution and the fossil energy crisis. Connecting new energy to the grid through inverters can solve the energy crisis. Grid-connected inverters have voltage source characteristics, can provide voltage and frequency support for the system, and improve the stability of weak grid systems. Therefore, they have great application potential in systems with high penetration rates of new energy. However, when a short circuit occurs in the system, unlike traditional synchronous generators, the inverter will be locked or disconnected from the grid due to excessive fault current, further expanding the scope of system failures.

[0003] In the context of grid-type inverters exiting due to overcurrent due to system faults after being connected to the grid, it is of great significance to adopt low voltage ride through control (LVRT) to prevent the inverter from exiting due to overcurrent and ensure its safe and stable operation. Existing literature mainly uses three methods to achieve low voltage ride through control of grid-type inverters. The first is to switch the grid-type control to the grid-following control during the fault period, and adjust the power reference value or current reference value to limit the fault current; the second is to modify the inverter voltage loop reference value so that the inverter output voltage can meet the fault current requirements; the third is to limit the fault current by increasing the equivalent impedance of the system.

[0004] However, the existing grid-connected inverter low voltage ride-through control methods have certain defects and shortcomings, mainly focusing on: The traditional control method is to switch the grid-forming control to the grid-following control during the fault period. However, this method requires a phase-locked loop to keep synchronization with the grid. Due to the strength of the grid, it is not suitable for weak grids. During the fault period, it only considers limiting the steady-state current and meeting the national standard reactive current injection, without limiting the impact current caused by the fault. The low voltage ride-through control method using pure virtual reactance can maintain the voltage source characteristics. The design principle of the virtual reactance is based on the maximum current withstand value limit principle of the steady-state current. During the fault period, the steady-state current can be limited and the reactive current value injected into the grid can be increased. However, this method does not consider the impact current caused by the initial stage of the fault, which will cause the inverter to lock out due to excessive impact current. In addition, the input of virtual reactance reduces the system impedance ratio and increases the fault current decay time. The virtual impedance of the low voltage ride-through control method using fixed virtual impedance is designed according to the impact current and steady-state current limit targets, and the virtual impedance is maintained unchanged during the fault period. This method can limit the impact current at the initial stage of the fault and limit the steady-state current in the steady-state stage of the fault, because the impact current limit maintains the system high impedance ratio, which will reduce the reactive current injected into the grid by the inverter. Summary of the invention The present invention proposes a low voltage ride-through control method for a grid-type inverter based on virtual impedance regulation, which can at least solve one of the technical problems in the background technology.

[0005] To achieve the above object, the present invention adopts the following technical solutions: A low voltage ride-through control method for a grid-type inverter based on virtual impedance regulation is based on a grid-type inverter system. The grid-type inverter system includes a grid-type inverter controlled by a virtual synchronous generator, a low voltage ride-through controller, a virtual impedance loop, a line impedance, and a large power grid. The grid-type inverter provides voltage and frequency support for the large power grid. When a low voltage fault occurs, the inverter will have a large current and power angle divergence. The low voltage ride-through control method is performed according to the following steps: Step 1: Detect the grid connection point voltage. When the grid connection point voltage is lower than the specified value, it indicates that the system has a fault. At this time, the power loop of the inverter is locked. In the fault steady-state stage, the inverter injects current I F : (1) In formula (1), E is the electromotive force of the grid-type inverter, δ is the phase of the electromotive force of the grid-type inverter, φ = γ - φ k , γ is the phase difference between the electromotive force and the grid voltage after the fault ∆ The phase angle of U is determined by the grid voltage and electromotive force phase. R v and X v is a virtual resistance and a virtual reactance. U g is the grid connection point voltage.

[0006] According to the national standard requirements, the reactive current injected into the grid is obtained I Q : (2) In formula (2), I q0 is the reactive current injected into the grid during normal periods, Δ I q is the reactive current increment required by the national standard. The current in the steady-state stage of the fault can be obtained by equation (2): (3) In addition to meeting the national standard reactive current requirements, it is also necessary to ensure that the inverter current does not exceed the limit. Assuming that the maximum effective current that the inverter can withstand for a long time is (1+K s )I N , K s It is the coefficient that represents the current that the inverter can withstand for a long time. s )I N When the fault steady-state current is greater than (1+ K s ) I N When the fault steady-state current is limited to (1+ K s ) I N , to ensure that the inverter will not be locked out due to overcurrent, thus obtaining the virtual reactance X Q for: (4) In the transient stage of fault initiation, firstly, the inverter is guaranteed to inject reactive current into the grid when the virtual resistance is withdrawn, so the power factor angle can be obtained to be less than 0. Based on this requirement, the system impedance angle is calculated. φ k > γ , so the system impedance ratio range is: (5) Under the premise of ensuring that the inverter does not absorb reactive current, the fault current decay time is reduced to the minimum and the system impedance ratio is set as the upper limit, expressed as Z r1 .

[0007] Considering the fault current decay time, it is also necessary to verify the effect of the designed impedance ratio in limiting the impact current. The maximum impact current can be obtained by differentiating the time domain expression of the fault current, but since the result after differentiation is a transcendental equation, it is difficult to calculate the maximum value. Therefore, this paper makes a reasonable simplified approximation to obtain the maximum value. After the fault occurs, the time domain expression of the fault current is obtained by the three-element method: (6) Where: ω is the angular frequency of the system, i o_initial (t) is the fault current when the fault occurs, I ois the current expression when the system is operating normally. Because the grid voltage amplitude drops and the inverter power circuit is locked, the inverter and grid frequencies are the same. Because the system is in normal working state, the input virtual impedance is unknown, so the phase is uncertain. Theoretically, the two are in the peak-to-valley difference of the function. When the difference is the largest, considering the serious situation, it is considered that the inverter current before the fault is the rated current, and the current during the fault is (1+ K s )I N From the conclusion of the power system short-circuit current analysis, it can be seen that the impact current is roughly located at the peak of the steady-state current after the system fault, that is, 0.01s after the fault, so the impact current can be expressed as: (7) Formula (7) is the inrush current at the transient state stage of the fault initialization. The maximum inrush current amplitude that the inverter can withstand is set to √2(1+ K t )I N , K t It is the short-time current withstand coefficient of the inverter. In order to ensure that the inverter will not be disconnected from the grid due to the impact current, and according to the requirements of different application scenarios, K % safety margin, it can be determined that the system impedance ratio that meets the impulse current requirements is: (8) If the impedance ratio obtained from equation (5) does not satisfy equation (8), it means that the impedance ratio Z r1 If the inrush current cannot be limited, the impedance ratio is set to the lower limit of equation (8), expressed as Z r2 To ensure that the inverter will not exit due to excessive inrush current.

[0008] Z r1 Less than Z r2 If the designed system impedance ratio does not meet the impulse current requirement, then according to Z r2 To design the system impedance ratio, safety is given priority. r1 Greater than or equal to Z r2 When the transient state at the beginning of the fault is reached, the impact current is limited, the decay time is reduced, and the reactive current is not absorbed after the transient state at the beginning of the fault ends. In summary, the system impedance ratio is: (9) At this point, the system impedance ratio in the transient stage of the fault initiation has been determined as formula (9), and the virtual reactance determined in the steady-state stage of the fault may not satisfy formula (9). In this case, it is necessary to adjust the virtual impedance. There are two adjustment methods. The first is to ensure that the system impedance modulus remains unchanged, and adjust the virtual resistance and virtual reactance respectively to satisfy formula (9). The second is to ensure that the virtual reactance remains unchanged and increase the virtual resistance to satisfy formula (9). In this article, the second method is selected because the first method requires switching the virtual resistance and virtual reactance at the same time after the transient stage of the fault initiation ends, which increases the difficulty and complexity of control. Therefore, in the transient stage of the fault initiation, the virtual reactance and virtual resistance put into operation are: (10) Step 2: When the difference between adjacent fault current sampling values ​​is less than the set value, it indicates that the transient stage of the fault is over, and it is necessary to design a virtual resistor to exit. The exit function is set as formula (11), and the virtual resistor is exited at this time; (11) In formula (11) t F This is the moment when voltage drops occur. τ F is the current decay time, regulating K 1Change the resistance exit speed; after the virtual resistance exits, the virtual impedance module only invests X Q .

[0009] Step 3: When the grid connection point voltage is higher than the specified value, it indicates that the fault is over; after the fault is removed, the grid connection point voltage will return to normal voltage and the circuit state will change; because only virtual reactance is put into use in the steady-state stage of the fault, the impedance ratio of the system is very small, resulting in slow decay of the non-periodic component. When the periodic component reaches its peak value, a surge current will appear; the surge current after the fault is removed is also solved by the three-element method i Rmax : (12) This process needs to limit the impact current, and the maximum impact current that the inverter can withstand is recorded as At the same time, to ensure safety, a 10% safety margin is considered to obtain the system impedance constraint range Z r3 : (13) In order to avoid the control complexity caused by excessive virtual impedance switching, the virtual reactance is kept unchanged in this stage, and the virtual resistance is determined according to formula (14): R R : (14) When the difference between the adjacent sampling values ​​of the system current is less than the set value, it means that the fault has ended and the transient stage has ended. It is necessary to design the virtual impedance to exit, and set the exit function as formula (15) and formula (16); (15) (16) In the formula t R This is the moment when voltage drops occur. τ R is the current decay time, regulating K 2. Change the resistance exit speed; after the virtual impedance exits, the system returns to normal and the power reference is modified to the reference value before the fault.

[0010] On the other hand, the present invention further discloses a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the above method.

[0011] On the other hand, the present invention further discloses a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the above method.

[0012] It can be seen from the above technical scheme that the low voltage ride-through control method of the grid-type inverter based on virtual impedance adjustment of the present invention can provide support for the power grid during a fault, limit the impact current and steady-state current, ensure that the inverter will not be locked out due to overcurrent, and inject reactive current that meets the national standard requirements during the steady-state stage of the fault, thereby improving the safety and stability of the grid-type inverter during a fault.

[0013] Compared with the existing method, the beneficial effects of the present invention are: The present invention aims at the problem that the grid-type inverter is locked out due to overcurrent during a fault. Different from the existing grid-following control method and the voltage reference value modification method, the present invention adopts a grid-type low voltage ride-through control method based on virtual impedance adjustment, and realizes voltage and frequency support for the power grid during the fault by locking the power loop. It is independent of the strength of the power grid and has higher reliability. During the fault, the virtual impedance of the transient stage at the beginning of the fault and the transient stage at the end of the fault are designed according to the impact current constraint, the virtual impedance of the steady-state stage of the fault is designed according to the national standard reactive current requirements, and the virtual impedance switching of each stage is realized. The impact current can be limited in the transient stage at the beginning of the fault and the transient stage at the end of the fault, and the fault steady-state current can be limited in the steady-state stage of the fault, and reactive current that meets the national standard requirements can be injected into the power grid. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1is a control structure diagram of a grid-type inverter of the present invention; Figure 2 It is a three-phase short-circuit fault stage division diagram of the present invention; Figure 3 is a virtual impedance diagram of low voltage control of the present invention; Figure 4 is a low voltage ride through control flow chart of the present invention; Figure 5 It is the hardware-in-the-loop experimental platform of the present invention; Figure 6a This is the current waveform when the voltage drops to 0.9 pu using pure virtual reactance in the present invention; Figure 6b It is the impulse current waveform when the voltage drops to 0.9pu using pure virtual reactance in the present invention; Figure 6c It is the injected reactive current waveform when the voltage drops to 0.9pu and a pure virtual reactance is used in the present invention; Figure 7a It is the current waveform when the voltage drops to 0.9pu and a fixed virtual impedance is used in the present invention; Figure 7b It is the injected reactive current waveform when the voltage drops to 0.9pu and a fixed virtual impedance is used in the present invention; Figure 8a This is the current waveform of the present invention when the voltage drops to 0.9 pu and the strategy of this invention is adopted; Figure 8b This is the impulse current waveform at the fault initiation stage when the voltage drops to 0.9 pu using the strategy of this invention; Figure 8c This is the impulse current waveform of the fault transient stage when the voltage drops to 0.9pu using the strategy of this invention; Figure 8d This is the injected reactive current waveform when the voltage drops to 0.9 pu using the strategy of this invention; Figure 9a This is the current waveform of the present invention when the voltage drops by 0.3pu and the strategy of this invention is adopted; Figure 9b This is the impulse current waveform at the fault initiation stage when the voltage drops to 0.3pu using the strategy of this invention; Fig.9c It is the impulse current waveform of the fault transient stage when the voltage drops to 0.3pu and the strategy of this invention is adopted; Figure 9d This is the injected reactive current waveform when the voltage drops to 0.3 pu using the strategy of this invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0016] The low voltage ride-through control method for grid-type inverters based on virtual impedance adjustment described in this embodiment takes into account aspects such as the inverter's ability to support the grid during a fault, the fault impact current and steady-state current limiting capabilities, and reactive current injection that meets national standards during the fault steady-state stage, and calculates the virtual impedance at each stage of the fault, respectively, and respectively switches on and off at each stage, and determines the power loop unlocking time after the fault ends to prevent the inverter from excessively absorbing reactive current from the grid. This ensures that the inverter will not be locked out due to overcurrent during a fault, thereby improving its safety and power supply reliability.

[0017] Figure 1 This is a control structure diagram of a grid-type inverter. The system consists of a grid-type inverter, an LC filter, a line impedance, and a grid. The inverter uses VSG control to provide voltage and frequency support for the grid. R g , L g is the resistance and inductance from the inverter to the grid, assuming . U g is the grid voltage, P m , Q ref are the reference active power and reactive power respectively. P o , Q o are the inverter output active power and reactive power respectively, J , D They are inertia factor and damping factor respectively. The active frequency loop and reactive voltage loop provide voltage and frequency references for the inverter respectively. The virtual impedance loop provides the function of voltage drop, but without power loss. The voltage and current loop tracks the voltage reference value output by the virtual impedance loop. When a three-phase short circuit fault occurs in a large power grid, if no corresponding measures are taken, the current injected by the inverter into the power grid will increase, and the inverter will diverge in power angle. When the virtual impedance control method is used to limit the fault current, the virtual impedance can be designed according to the regulations to reduce the inverter output voltage and thereby reduce the inverter current. The present invention locks the power loop during the fault to avoid power divergence, and designs the virtual impedance of each stage according to the impact current, steady-state current limiting requirements and national standard reactive current injection requirements, and then puts them into the system respectively.

[0018] Figure 2The present invention proposes a fault stage division for three-phase short-circuit faults and corresponding system requirements for each stage. After the fault begins, it enters the fault start transient stage. In this stage, it is necessary to limit the impact current caused by voltage drop, and at the same time reduce the fault transient time. After the current decay is completed, it enters the fault steady-state stage. In this stage, it is necessary to limit the fault current and inject reactive current into the power grid in accordance with national standards. After the voltage is restored, the system enters the fault end transient stage. In this stage, it is necessary to limit the impact current caused by voltage recovery.

[0019] Figure 3 is the virtual impedance value used by the control strategy of the present invention during the fault period. When a fault occurs, the virtual resistance R0 and the virtual reactance X are used. Q After the transient phase of the fault is over, the virtual resistor is withdrawn and the fault steady state phase is entered. When the grid voltage is restored, the virtual resistor R R , and enter the fault end transient stage. When this stage ends, the virtual resistance and virtual reactance are exited at the same time.

[0020] In view of various problems that may occur when a grid-connected inverter fails, the present invention designs the following Figure 4 The control flow chart shows that during the fault period, the fault stages are distinguished according to voltage judgment and current judgment, and the corresponding virtual impedance is designed in each stage to meet the requirements. The low voltage ride-through control method is carried out in the following steps: Step 1: Detect the grid connection point voltage. When the grid connection point voltage is lower than the specified value, it indicates that the system has a fault. At this time, the power loop of the inverter is locked, that is, the input power difference of the active-frequency loop and the reactive-voltage loop is set to 0, to ensure that the inverter electromotive force remains unchanged and the power angle does not diverge. Establish the fault steady-state stage, and the inverter injects current I F : (1) In formula (1), E is the electromotive force of the grid-type inverter, δ is the phase of the grid-type inverter electromotive force, X g is the line reactance from the inverter to the grid connection point, φ = γ - φ k , γ is the phase difference between the electromotive force and the grid voltage after the fault ∆ The phase angle of U is determined by the grid voltage and electromotive force phase. R v and X v is a virtual resistance and a virtual reactance. U g is the grid connection point voltage.

[0021] According to the national standard requirements, the reactive current injected into the grid during the fault steady state stage is obtained I Q : (2) In formula (2), I q0 is the reactive current injected into the grid during normal periods, Δ I q is the reactive current increment required by the national standard. The current in the steady-state stage of the fault can be obtained by equation (2): (3) In addition to meeting the national standard reactive current requirements, it is also necessary to ensure that the inverter current does not exceed the limit. Assuming that the maximum effective current that the inverter can withstand for a long time is (1+K s )I N , K s It is the coefficient that represents the current that the inverter can withstand for a long time. s )I N When the fault steady-state current is greater than (1+ K s ) I N When the fault steady-state current is limited to (1+ K s ) I N , to ensure that the inverter will not be locked out due to overcurrent, thus obtaining the virtual reactance X Q for: (3) In the transient stage of fault initiation, firstly, the inverter is guaranteed to inject reactive current into the grid when the virtual resistance is withdrawn, so the power factor angle can be obtained to be less than 0. Based on this requirement, the system impedance angle is calculated. φ k > γ , so the system impedance ratio range is: (5) Under the premise of ensuring that the inverter does not absorb reactive current, the fault current decay time is reduced to the minimum and the system impedance ratio is set as the upper limit, expressed as Z r1 .

[0022] Considering the fault current decay time, it is also necessary to verify the effect of the designed impedance ratio in limiting the impact current. The maximum impact current can be obtained by differentiating the time domain expression of the fault current, but since the result after differentiation is a transcendental equation, it is difficult to calculate the maximum value. Therefore, this paper makes a reasonable simplified approximation to obtain the maximum value. After the fault occurs, the time domain expression of the fault current is obtained by the three-element method: (6) Where: ω is the angular frequency of the system, i o_initial (t) is the fault current when the fault occurs, I o is the current expression when the system is operating normally. Because the grid voltage amplitude drops and the inverter power circuit is locked, the inverter and grid frequencies are the same. Because the system is in normal working state, the input virtual impedance is unknown, so the phase is uncertain. Theoretically, the two are in the peak-to-valley difference of the function. When the difference is the largest, considering the serious situation, it is considered that the inverter current before the fault is the rated current, and the current during the fault is (1+ K s )I N From the conclusion of the power system short-circuit current analysis, it can be seen that the impact current is roughly located at the peak of the steady-state current after the system fault, that is, 0.01s after the fault, so the impact current can be expressed as: (7) Formula (7) is the inrush current at the transient state stage of the fault initialization. The maximum inrush current amplitude that the inverter can withstand is set to √2(1+ K t )I N , K t It is the short-time current withstand coefficient of the inverter. In order to ensure that the inverter will not be disconnected from the grid due to the impact current, and according to the requirements of different application scenarios, K % safety margin, it can be determined that the system impedance ratio that meets the impulse current requirements is: (8) If the impedance ratio obtained from equation (5) does not satisfy equation (8), it means that the impedance ratio Z r1 If the inrush current cannot be limited, the impedance ratio is set to the lower limit of equation (8), expressed as Z r2 To ensure that the inverter will not exit due to excessive inrush current.

[0023] Z r1 Less than Z r2 If the designed system impedance ratio does not meet the impulse current requirement, then according to Z r2To design the system impedance ratio, safety is given priority. r1 Greater than or equal to Z r2 When the transient state at the beginning of the fault is reached, the impact current is limited, the decay time is reduced, and the reactive current is not absorbed after the transient state at the beginning of the fault ends. In summary, the system impedance ratio is: (9) At this point, the system impedance ratio in the transient stage of the fault initiation has been determined as formula (9), and the virtual reactance determined in the steady-state stage of the fault may not satisfy formula (9). In this case, it is necessary to adjust the virtual impedance. There are two adjustment methods. The first is to ensure that the system impedance modulus remains unchanged, and adjust the virtual resistance and virtual reactance respectively to satisfy formula (9). The second is to ensure that the virtual reactance remains unchanged and increase the virtual resistance to satisfy formula (9). In this article, the second method is selected because the first method requires switching the virtual resistance and virtual reactance at the same time after the transient stage of the fault initiation ends, which increases the difficulty and complexity of control. Therefore, in the transient stage of the fault initiation, the virtual reactance and virtual resistance put into operation are: (10) Step 2: When the difference between adjacent fault current sampling values ​​is less than the set value, it indicates that the transient stage of the fault is over, and it is necessary to design a virtual resistor to exit. The exit function is set as formula (11), and the virtual resistor is exited at this time; (11) In formula (11) t F This is the moment when voltage drops occur. τ F is the current decay time, regulating K 1Change the resistance exit speed; after the virtual resistance exits, the virtual impedance module only invests X Q .

[0024] Step 3: When the grid connection point voltage is higher than the specified value, it indicates that the fault is over; after the fault is removed, the grid connection point voltage will return to normal voltage and the circuit state will change; because only virtual reactance is put into use in the steady-state stage of the fault, the impedance ratio of the system is very small, resulting in slow decay of the non-periodic component. When the periodic component reaches its peak value, a surge current will appear; the surge current after the fault is removed is also solved by the three-element method i Rmax : (12) This process needs to limit the impact current, and the maximum impact current that the inverter can withstand is recorded as At the same time, to ensure safety, a 10% safety margin is considered to obtain the system impedance constraint range Z r3 : (13) In order to avoid the control complexity caused by excessive virtual impedance switching, the virtual reactance is kept unchanged in this stage, and the virtual resistance is determined according to formula (14): R R : (14) After the fault ends, it is necessary to consider unlocking the power loop. The common power loop unlocking time is to unlock when the fault ends or to unlock after the virtual impedance exits. The first solution restores the reactive power reference to the value before the fault when the fault ends. However, since the specified reactive power is injected into the grid during the steady-state phase of the fault, the reactive power reference value will be less than the reactive power output value, causing the inverter voltage to decrease and be lower than the grid connection point voltage, resulting in reactive power reverse transmission problems at the grid connection point. Therefore, this article adopts the solution of unlocking the power loop after the virtual impedance exits. After the virtual impedance exits, the system returns to normal and the power reference is modified to the reference value before the fault.

[0025] When the difference between the adjacent sampling values ​​of the system current is less than the set value, it means that the fault has ended and the transient stage has ended. It is necessary to design the virtual impedance to exit, and set the exit function as formula (15) and formula (16); (15) (16) In the formula t R This is the moment when voltage drops occur. τ R is the current decay time, regulating K 2. Change the resistance exit speed; after the virtual impedance exits, the system returns to normal and the power reference is modified to the reference value before the fault.

[0026] In order to verify the effectiveness and superiority of the proposed low voltage ride-through control strategy, a semi-physical real-time simulation experimental platform for grid-connected inverters is constructed. Figure 5 shown.

[0027] Simulation 1: Comparison of different LVRT control strategies: Taking the grid voltage drop of 0.9pu as an example, different LVRT control strategies are adopted to compare from three aspects: limiting the impact current, limiting the steady-state current, and reactive current injection.

[0028] Figure 6a and 6b These are the fault current and impact current diagrams of the pure virtual reactance control method. The control design can successfully limit the fault steady-state current, but in the transient stage at the beginning of the fault, the pure virtual reactance design cannot limit the impact current and the decay time is very long. Excessive impact current will cause the inverter to lock out due to overcurrent. Figure 6c It is the reactive current injected into the grid during a fault. Pure virtual reactance can increase the reactive current injected into the grid, but it will unlock the power loop when the fault ends, causing the problem of absorbing reactive current for a long time.

[0029] Figure 7a and 7b The fault current of the fixed virtual impedance control method and the reactive current injected into the grid during the fault are shown in the figure. During the fault, the fixed virtual impedance method can successfully limit the steady-state current and the impact current, and can ensure that the inverter will not be locked out due to overcurrent during the fault. Since the fixed virtual impedance is designed based on limiting the steady-state current and the impact current and maintaining a high impedance ratio, the reactive current injected into the grid is very small and does not meet the national standard requirements. In addition, the power loop is unlocked at the end of the fault, causing the problem of absorbing reactive current for a long time.

[0030] Figure 8a , 8b ) and 8c are the fault current and impact current diagrams of the LVRT control strategy proposed in this paper, respectively. The impact current can be limited in both the transient stage at the beginning of the fault and the transient stage at the end of the fault, ensuring that the inverter will not be locked out due to overcurrent. Figure (d) shows that the reactive current injected into the grid in the steady-state stage of the fault meets the national standard requirements, and at the end of the fault, because the power loop is unlocked after the system returns to normal, there will be no problem of absorbing reactive power for a long time.

[0031] Table 1 Simulation results of different strategies under three-phase short circuit

[0032] Table 1 shows the comparison of the constant virtual impedance method, pure virtual reactance method, and method based on adjusting virtual impedance in terms of inrush current, current decay time, and reactive current injection during a three-phase short circuit. According to the table analysis, the LVRT strategy based on adjusting virtual impedance can limit the inrush current, reduce the fault current decay time, and inject reactive current into the grid according to the national standard requirements.

[0033] Simulation 2: LVRT control strategy verification with different voltage drops: In order to verify the effectiveness of the low voltage ride-through strategy proposed in this paper under different voltage drop levels, the grid voltage drops by 0.3pu. Figure 9a , 9b 9c and 9d are the fault current and impulse current diagrams of the LVRT control strategy proposed in this paper, which can limit the impulse current in both the transient stage of the fault start and the transient stage of the fault end, ensuring that the inverter will not be locked out due to overcurrent. Figure 9dIt means that the reactive current injected into the grid during the steady-state stage of the fault meets the national standard requirements, and when the fault ends, there will be no problem of long-term reactive power absorption because the power loop is unlocked after the system returns to normal.

[0034] On the other hand, the present invention further discloses a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the above method.

[0035] On the other hand, the present invention further discloses a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the above method.

[0036] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any of the low voltage ride-through control methods for a grid-connected inverter based on virtual impedance adjustment in the above embodiments.

[0037] It is understandable that the system, device and storage medium provided in the embodiments of the present invention correspond to the method provided in the embodiments of the present invention, and the explanation, examples and beneficial effects of the relevant contents can refer to the corresponding parts in the above methods.

[0038] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0039] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0040] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0041] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low voltage ride-through control method for a grid-type inverter based on virtual impedance regulation, based on a grid-type inverter system, wherein the grid-type inverter system comprises a grid-type inverter controlled by a virtual synchronous generator, a low voltage ride-through controller, a virtual impedance loop, a line impedance, and a large power grid; characterized in that: The grid-type inverter supports the voltage and frequency of the large power grid. When a low voltage fault occurs, the inverter will have a large current and power angle divergence. The low voltage ride-through control method is performed according to the following steps: Step 1: Detect the grid connection point voltage. When the grid connection point voltage is lower than the specified value, it indicates that the system has a fault. At this time, the power loop of the inverter is locked. In the fault steady-state stage, the inverter injects current I F : (1) In formula (1), E is the electromotive force of the grid-type inverter, δ is the phase of the electromotive force of the grid-type inverter, φ = γ - φ k , γ is the phase difference between the electromotive force and the grid voltage after the fault ∆ The phase angle of U is determined by the grid voltage and electromotive force phase. R v and X v is a virtual resistance and a virtual reactance. U g is the grid connection point voltage; According to the national standard requirements, the reactive current injected into the grid is obtained I Q : (2) In formula (2), I q0 is the reactive current injected into the grid during normal periods, Δ I q is the reactive current increment required by the national standard. The current in the steady-state stage of the fault is obtained by formula (2): (3) Assume that the maximum effective current that the inverter can withstand for a long time is (1+K s )I N , K s It is the coefficient representing the current that the inverter can withstand for a long time; when the fault current is less than (1+K s )I N When the fault steady-state current is greater than (1+ K s ) I N When the fault steady-state current is limited to (1+ K s ) I N , to ensure that the inverter will not be locked out due to overcurrent, thus obtaining the virtual reactance X Q for: (4) In the transient stage of fault initiation, firstly ensure that the inverter injects reactive current into the grid when the virtual resistance is withdrawn, and the power factor angle is less than 0. Then, the system impedance angle is calculated based on this requirement. φ k > γ , the system impedance ratio range is: (5) Under the premise of ensuring that the inverter does not absorb reactive current, the fault current decay time is reduced to the minimum and the system impedance ratio is set as the upper limit, expressed as Z r1 ; After the fault occurs, the time domain expression of the fault current is obtained by the three-element method: (6) Where: ω is the angular frequency of the system, i o_initial (t) is the fault current when the fault occurs, I o is the current expression when the system is operating normally; From the conclusion of the power system short-circuit current analysis, it can be seen that the impact current is roughly located at the peak of the steady-state current after the system fault, that is, 0.01s after the fault, so the impact current is expressed as: (7) Formula (7) is the impact current in the transient state stage of the fault initialization; the maximum impact current amplitude that the inverter can withstand is set to √2(1+ K t )I N , K t It is the short-time current withstand coefficient of the inverter. In order to ensure that the inverter will not exit the grid due to the impact current, and according to the requirements of different application scenarios, K % safety margin, the system impedance ratio that meets the impulse current requirement is determined as: (8) If the impedance ratio obtained from equation (5) does not satisfy equation (8), it means that the impedance ratio Z r1 If the inrush current cannot be limited, the impedance ratio is set to the lower limit of equation (8), expressed as Z r2 To ensure that the inverter will not exit due to excessive inrush current; Z r1 Less than Z r2 If the designed system impedance ratio does not meet the impulse current requirement, then according to Z r2 To design the system impedance ratio, safety is given priority; when Z r1 Greater than or equal to Z r2 When the impulse current is limited in the transient stage of the fault, the decay time is reduced, and the reactive current is not absorbed after the transient state of the fault ends. In summary, the system impedance ratio is: (9) At this time, the system impedance ratio at the transient stage of the fault has been determined as formula (9), and the virtual reactance determined at the steady-state stage of the fault may not satisfy formula (9); in this case, the virtual impedance is adjusted to ensure that the virtual reactance remains unchanged, and the virtual resistance is increased to satisfy formula (9); at the transient stage of the fault, the virtual reactance and virtual resistance are: (10) Step 2: When the difference between adjacent fault current sampling values ​​is less than the set value, it indicates that the transient stage of the fault is over, and it is necessary to design a virtual resistor to exit. The exit function is set as formula (11), and the virtual resistor is exited at this time; (11) In formula (11) t F This is the moment when voltage drops occur. τ F is the current decay time, regulating K 1Change the resistance exit speed; after the virtual resistance exits, the virtual impedance module only invests X Q .

2. The low voltage ride through control method of a grid-connected inverter based on virtual impedance adjustment according to claim 1, characterized in that: It also includes step three: when the grid connection point voltage is higher than the specified value, it indicates that the fault is over; after the fault is removed, the grid connection point voltage will return to normal voltage and the circuit state will change; because only virtual reactance is put into use in the steady-state stage of the fault, the impedance ratio of the system is very small, resulting in slow decay of the non-periodic component, and when the periodic component reaches the peak value, an impact current will appear; similarly, the impact current after the fault is removed is solved by the three-element method i Rmax : (12) This process needs to limit the impact current, and the maximum impact current that the inverter can withstand is recorded as At the same time, to ensure safety, a 10% safety margin is considered to obtain the system impedance constraint range Z r3 : (13) In order to avoid the control complexity caused by excessive virtual impedance switching, the virtual reactance is kept unchanged in this stage, and the virtual resistance is determined according to formula (14): R R : (14) When the difference between the adjacent sampling values ​​of the system current is less than the set value, it means that the fault has ended and the transient stage has ended. It is necessary to design the virtual impedance to exit, and set the exit function as formula (15) and formula (16); (15) (16) In the formula t R This is the moment when voltage drops occur. τ R is the current decay time, regulating K 2. Change the resistance withdrawal speed; After the virtual impedance is exited, the system returns to normal and the power reference is modified to the reference value before the fault.

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