Device and method for controlling soft start of switching power supply, BUCK converter and chip

Abstract

The present disclosure provides a device and method for controlling the soft start of a switching power supply, a BUCK converter and a chip. The device includes: an error amplification module, which compares the feedback voltage with the reference voltage to output an error signal; a loop zero-pole compensation module, which generates the zero and pole required for the voltage loop through the start capacitor; during soft start, the output voltage soft start rising slope and start time are controlled by the start capacitor; an error output clamping module, which clamps the error signal to the voltage of the start capacitor; a comparator control module, which compares the voltage of the start capacitor with the reference voltage to determine the soft start time according to the comparison result; a selection switching module, which switches between the start capacitor charging stage at the beginning of the soft start and the clamping monitoring stage of the error signal at the end of the soft start according to the comparison result of the comparator control module. The present disclosure realizes the time-sharing multiplexing of the start capacitor in the voltage regulation loop of the switching power supply.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of integrated circuits, and relates to a soft start circuit, and in particular to a device and method for controlling the soft start of a switching power supply, a BUCK converter, and a chip. Background Art

[0002] At present, with the rapid development of information electronics, the demand for electronic products in daily life is also growing rapidly, among which the research and design of high-performance power management chips are becoming more and more important. Compared with linear regulated power supplies, switching power supplies have very high conversion efficiency (generally more than 90%), especially in applications with large input and output voltage differences, the efficiency advantage is very obvious. This will greatly promote portable electronic products to improve their battery efficiency, extend the battery power supply time and service life, and is also very consistent with the current sustainable development direction of energy conservation and environmental protection.

[0003] In some specific applications, the output voltage is required to slowly rise to the target voltage at a set slope during the enable startup phase. During operation, the output voltage fluctuation of the switching power supply is required to be small, which requires the switching power supply to have a certain transient response speed. In addition, while meeting the hard indicators, the cost of the chip also needs to be controlled to a certain extent. Summary of the invention

[0004] The present disclosure provides a device and method for controlling the soft start of a switching power supply, a BUCK converter and a chip, which are used to avoid the increase of chip area caused by an additional soft start capacitor and to enable different outputs to slowly rise to a target voltage with a fixed set slope.

[0005] In a first aspect, an embodiment of the present disclosure provides a device for controlling the soft start of a switching power supply. The device includes: an error amplification module, configured to compare a feedback voltage based on the output voltage of the switching power supply with a reference voltage to output an error signal; a loop zero-pole compensation module, including a startup capacitor, and configured to generate the zero and pole required for the voltage loop through the startup capacitor, and to control the soft start rising slope and start time of the output voltage through the startup capacitor during the soft start phase; an error output clamping module, configured to clamp the error signal to the voltage of the startup capacitor; a comparator control module, configured to compare the voltage of the startup capacitor with the reference voltage to determine the soft start time according to the comparison result; and a selection switching module, configured to switch between the charging phase of the startup capacitor at the beginning of the soft start and the clamp monitoring phase of the error signal at the end of the soft start according to the comparison result of the comparator control module.

[0006] In an implementation of the first aspect, the loop zero-pole compensation module further includes a first resistor, wherein the first resistor is electrically coupled to the startup capacitor, and the zero and pole required for the voltage loop are generated by connecting resistors and capacitors in series and in parallel.

[0007] In an implementation of the first aspect, the loop zero-pole compensation module also includes a first capacitor, wherein the first capacitor is electrically coupled to the first resistor, and forms a loop zero-pole compensation network with the first resistor and the startup capacitor, and the first capacitor is configured to filter the error signal output by the error amplification module.

[0008] In an implementation of the first aspect, the error output clamp module includes a high-voltage clamp comparator and an NMOS tube, wherein the positive end of the high-voltage clamp comparator inputs the error signal, and the negative end inputs a preset high clamp voltage or the voltage of the startup capacitor, wherein the output end of the high-voltage clamp comparator is electrically coupled to the gate of the NMOS tube to form a high-voltage clamp control circuit for controlling the error signal voltage.

[0009] In an implementation of the first aspect, the selection switching module includes a first switching switch group and a second switching switch group, the first switching switch group and the second switching switch group both have a two-to-one switching mode, wherein the first selection end of the first switching switch group is electrically coupled to one end of the first resistor, the second selection end inputs a soft start charging current, and the common end is electrically coupled to the charging end of the startup capacitor, wherein the first selection end of the second switching switch group inputs a preset high clamp voltage, the second selection end is electrically coupled to the charging end of the startup capacitor, and the common end is electrically coupled to the negative end of the high-voltage clamp comparator.

[0010] In an implementation of the first aspect, in response to the start of soft start, the comparison result received by the first switching switch group and the second switching switch group is a first level signal, and the second selection end of the first switching switch group and the second switching switch group is connected to the common end; in response to the end of soft start, the comparison result received by the first switching switch group and the second switching switch group is a second level signal, and the first selection end of the first switching switch group and the second switching switch group is connected to the common end.

[0011] In an implementation of the first aspect, in response to the second selection end of the first switching switch group and the second switching switch group being turned on with the common end, the negative end input of the high-voltage clamp comparator is the voltage of the startup capacitor, and the output end is controlled to be the voltage of the startup capacitor, and at the same time, the soft start charging current starts to charge the startup capacitor so that the voltage of the startup capacitor slowly rises with a fixed slope, and the output voltage will completely follow the rising slope of the voltage of the startup capacitor; in response to the first selection end of the first switching switch group and the second switching switch group being turned on with the common end, the negative end of the high-voltage clamp comparator inputs the preset high clamp voltage, and the preset high clamp voltage is used to monitor the jump of the error signal, and at the same time, the startup capacitor is electrically coupled with the first resistor to re-constitute a loop zero-pole compensation network.

[0012] In a second aspect, an embodiment of the present disclosure provides a method for controlling the soft start of a switching power supply. The method includes: comparing the voltage of a startup capacitor with a reference voltage to determine the soft start time according to the comparison result; switching between the charging phase of the startup capacitor at the beginning of the soft start and the clamping monitoring phase of the error signal at the end of the soft start according to the comparison result; comparing the feedback voltage based on the output voltage of the switching power supply with the reference voltage to output an error signal; and in the soft start phase, clamping the error signal to the voltage of the startup capacitor, and using the startup capacitor to control the soft start rising slope and start time of the output voltage; and at the end of the soft start, using a preset high clamp voltage to monitor the jump of the error signal, and generating the zero and pole required for the voltage loop through the startup capacitor.

[0013] In a third aspect, an embodiment of the present disclosure provides a BUCK converter. The BUCK converter comprises: the device as described above; a pulse width modulation module, configured to receive the error signal and the ramp signal from the device, and compare the error signal with the ramp signal to generate a set logic signal; a duty cycle generation module, configured to receive the set logic signal from the pulse width modulation module, and generate a duty cycle control signal based on the set logic signal; a switch drive control module, configured to receive the duty cycle control signal from the duty cycle generation module, and generate a switch drive signal based on the duty cycle control signal; and a power switch module, configured to receive the switch drive signal from the switch drive control module, and output the output voltage based on the switch drive signal.

[0014] In a fourth aspect, an embodiment of the present disclosure provides a chip, wherein the chip includes the BUCK converter as described above.

[0015] According to the device and method for controlling the soft start of a switching power supply, the BUCK converter and the chip described in the present disclosure, time-sharing multiplexing of the start capacitor is achieved. That is, in the soft start phase, the start capacitor is used as a soft start capacitor; and after the startup is completed, it is used again as the zero-pole compensation of the voltage regulation loop. Therefore, the soft start scheme disclosed in the present disclosure can save a large internal capacitor, thereby saving chip area. At the same time, it can be achieved that the switching power supply system can slowly rise to the target voltage at a fixed slope during the soft start phase at different output voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a schematic diagram of the structural connection of a device for controlling soft starting of a switching power supply according to an embodiment of the present disclosure.

[0017] Figure 2 Shown is a circuit schematic diagram of a device for controlling soft start of a switching power supply according to an embodiment of the present disclosure.

[0018] Figure 3 A schematic diagram of switch switching at the start of soft start of the device for controlling soft start of a switching power supply according to an embodiment of the present disclosure is shown.

[0019] Figure 4 A schematic diagram of switch switching at the end of soft start of the device for controlling soft start of a switching power supply according to an embodiment of the present disclosure is shown.

[0020] Figure 5 Shown is a flow chart of a soft start method according to an embodiment of the present disclosure.

[0021] Figure 6 Shown is a schematic structural diagram of the BUCK converter described in an embodiment of the present disclosure.

[0022] Figure 7 Shown is a schematic diagram of the structural connection of the BUCK converter described in an embodiment of the present disclosure.

[0023] Figure 8 Shown is a circuit principle block diagram of the BUCK converter described in an embodiment of the present disclosure.

[0024] Fig. 9 Shown is a working waveform diagram of the BUCK converter described in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0026] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present disclosure in a schematic manner, and thus the illustrations only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] The soft start method generally generates a slowly rising voltage by charging the soft start capacitor through a current. This voltage is used to control the output voltage of the error amplifier in the voltage regulation loop to rise slowly, thereby realizing the soft start function. This method has two problems because the slowly rising voltage and the feedback reference are directly superimposed in a specific way. First, an additional soft start capacitor is required. If a soft start time of 1ms is to be generated, this capacitor is often large (for example, if the output voltage is 1V and the charging current is 25nA, the required soft start capacitor needs to be at least 25pF), which will increase the chip area. Second, because the input stage of the error amplifier has different DC transconductance for different common-mode voltages, the output voltage of the soft start stage controlled by it cannot be achieved to rise slowly to the target voltage at a set fixed slope for different output voltages (or different feedback references).

[0028] The device for controlling the soft start of a switching power supply disclosed in the present disclosure can be applied to the ACOT (Adaptive Constant On-Time) architecture, and can accurately control the output voltage start slope and start time of the soft start. At the same time, part of the compensation capacitor of the main loop, i.e., the start capacitor, can be reused to better reduce the chip capacitor area.

[0029] In the soft start circuit of a switching power supply suitable for constant on-time (ACOT) control according to an embodiment of the present disclosure, by multiplexing the compensation capacitor of the error amplification link in the voltage regulation loop and combining it with the high clamping control of the error amplification output, it is possible to achieve a fixed rising slope that can be set from 0V to a normal output voltage regardless of the output voltage.

[0030] During the soft start period, the compensation capacitor of part of the error amplifier output loop is started as the control output voltage and rises at a set fixed slope. A small current is used to charge this part of the compensation capacitor to generate a voltage with a slow ramp rise, which is used as the high clamp voltage of the error amplifier output and controlled by the high clamp op amp loop. The comparator compares this voltage with the feedback reference voltage. When this voltage rises to the reference voltage, the comparator output SSOK logic becomes high, and the two two-choice switch arrays are controlled to return this part of the compensation capacitor to the error amplifier output loop, and the high clamp voltage of the error amplifier output is switched to the high clamp voltage. Due to the characteristics of the ACOT (adaptive on-time) control method, the error amplifier output voltage is about the reference voltage at this time, so the switching of the two-choice switch will not cause fluctuations in the output voltage of the BUCK, and a smooth transition can be achieved.

[0031] The technical solutions in the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present disclosure.

[0032] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram showing the structural connection of a device for controlling soft starting of a switching power supply according to an embodiment of the present disclosure. Figure 1 As shown, this embodiment provides a device 1 for controlling soft start of a switching power supply, which includes: an error amplification module 11, a loop zero-pole compensation module 12, an error output clamping module 13, a comparator control module 14 and a selection switching module 15.

[0033] The error amplification module 11 is configured to compare a feedback voltage based on the output voltage of the switching power supply with a reference voltage to output an error signal.

[0034] The loop zero-pole compensation module 12 includes a startup capacitor and is configured to generate the zero and pole required by the voltage loop through the startup capacitor, and to control the soft start rising slope and startup time of the output voltage through the startup capacitor during the soft start phase.

[0035] The error output clamping module 13 is configured to clamp the error signal to the voltage of the startup capacitor.

[0036] The comparator control module 14 is configured to compare the voltage of the start capacitor with the reference voltage to determine the soft start time according to the comparison result.

[0037] The selection switching module 15 is configured to switch between the charging stage of the startup capacitor at the beginning of soft start and the clamping monitoring stage of the error signal at the end of soft start according to the comparison result of the comparator control module.

[0038] In one embodiment, the loop zero-pole compensation module further includes a first resistor. The first resistor is electrically coupled to the startup capacitor, and generates the zero and pole required by the voltage loop through resistors and capacitors connected in series and parallel.

[0039] See also Figure 2 , Figure 2 FIG. 1 is a circuit diagram of a device for controlling soft start of a switching power supply according to an embodiment of the present disclosure. Figure 2 As shown, the loop zero-pole compensation module 12 further includes a first resistor R1. The first resistor R1 is electrically coupled to the startup capacitor C2, and the zero and pole required for the voltage loop are generated by connecting the resistor and capacitor in series and in parallel.

[0040] In one embodiment, the loop zero-pole compensation module further includes a first capacitor. The first capacitor is electrically coupled to the first resistor, and forms a loop zero-pole compensation network with the first resistor and the startup capacitor, and the first capacitor is configured to filter the error signal output by the error amplification module.

[0041] like Figure 2 As shown, the loop zero-pole compensation module 12 further includes a first capacitor C1. The first capacitor C1 is electrically coupled to the first resistor R1, and forms a loop zero-pole compensation network with the first resistor R1 and the start-up capacitor C2. The first capacitor C1 is configured to filter the error signal VEA output by the error amplification module 11.

[0042] In one embodiment, the error output clamp module includes a high-voltage clamp comparator and an NMOS tube. The positive terminal of the high-voltage clamp comparator inputs the error signal, and the negative terminal inputs a preset high clamp voltage or the voltage of the startup capacitor. The output terminal of the high-voltage clamp comparator is electrically coupled to the gate of the NMOS tube to form a high-voltage clamp control circuit for controlling the error signal voltage.

[0043] like Figure 2 As shown, the error output clamp module 13 includes a high-voltage clamp comparator and an NMOS tube NM. The positive terminal of the high-voltage clamp comparator inputs the error signal VEA, and the negative terminal inputs the preset high clamp voltage Vhclamp or the voltage VC2 of the startup capacitor C2. The output terminal of the high-voltage clamp comparator is electrically coupled to the gate of the NMOS tube NM to form a high-voltage clamp control circuit for controlling the error signal voltage.

[0044] In one embodiment, the selection switching module includes a first switching switch group and a second switching switch group, and the first switching switch group and the second switching switch group both have a two-choose-one switching mode. The first selection end of the first switching switch group is electrically coupled to one end of the first resistor, the second selection end inputs a soft start charging current, and the common end is electrically coupled to the charging end of the startup capacitor. The first selection end of the second switching switch group inputs a preset high clamp voltage, the second selection end is electrically coupled to the charging end of the startup capacitor, and the common end is electrically coupled to the negative end of the high voltage clamp comparator.

[0045] like Figure 2 As shown, the selection switching module 15 includes a first switching switch group 151 and a second switching switch group 152. The first switching switch group 151 and the second switching switch group 152 are both in a two-choose-one switching mode. The first selection terminal S1 of the first switching switch group 151 is electrically coupled to one end of the first resistor R1, the second selection terminal S2 inputs the soft start charging current Iss, and the common terminal is electrically coupled to the charging end of the startup capacitor C2. The first selection terminal S1 of the second switching switch group 152 inputs the preset high clamp voltage Vhclamp, the second selection terminal S2 is electrically coupled to the charging end of the startup capacitor C2, and the common terminal is electrically coupled to the negative end of the high voltage clamp comparator.

[0046] In one embodiment, in response to the start of soft start, the comparison results received by the first switch group and the second switch group are first level signals, and the second selection terminals of the first switch group and the second switch group are connected to the common terminal.

[0047] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of switch switching at the start of soft start of the device for controlling soft start of a switching power supply according to an embodiment of the present disclosure. Figure 3 As shown, in response to the start of soft start, the comparison result SSOK received by the first switching switch group 151 and the second switching switch group 152 is a first level signal (for example, a low level signal), and the second selection terminal S2 of the first switching switch group 151 and the second switching switch group 152 is connected to the common terminal.

[0048] In one embodiment, in response to the end of the soft start, the comparison results received by the first switch group and the second switch group are second level signals, and the first selection terminals of the first switch group and the second switch group are connected to the common terminal.

[0049] See also Figure 4 , Figure 4 FIG. 1 is a schematic diagram of switch switching at the end of soft start of the device for controlling soft start of a switching power supply according to an embodiment of the present disclosure. Figure 4 As shown, in response to the end of the soft start, the comparison result SSOK received by the first switching switch group 151 and the second switching switch group 152 is a second level signal (for example, a high level signal), and the first selection terminal S1 of the first switching switch group 151 and the second switching switch group 152 is connected to the common terminal.

[0050] In one embodiment, in response to the second selection terminals of the first switching switch group and the second switching switch group being turned on to the common terminal, the negative terminal input of the high-voltage clamp comparator is the voltage of the startup capacitor, and the output terminal is controlled to be the voltage of the startup capacitor. At the same time, the soft start charging current starts to charge the startup capacitor, so that the voltage of the startup capacitor slowly rises with a fixed slope, and the output voltage will completely follow the rising slope of the voltage of the startup capacitor.

[0051] In response to the first selection terminal and the common terminal of the first switching switch group and the second switching switch group being turned on, the negative terminal of the high-voltage clamp comparator inputs the preset high clamp voltage, and the preset high clamp voltage is used to monitor the jump of the error signal; at the same time, the startup capacitor is electrically coupled with the first resistor to re-constitute a loop zero-pole compensation network.

[0052] Combination Figures 1 to 4 The specific implementation principle of the device for controlling the soft start of a switching power supply disclosed in the present invention is as follows.

[0053] The error amplification module 11 includes an error amplifier AMP (Automatic Mixed Precision), which is used to compare the output voltage of the loop with a reference voltage in real time to generate an error signal VEA.

[0054] The loop zero-pole compensation module 12 is configured to construct the loop zero-pole compensation network, which mainly includes the first resistor R1 / the first capacitor C1 / the start capacitor C2, and the series-parallel combination generates the zero and pole required for the control voltage loop for loop stability. At the same time, the start capacitor C2 is reused as a capacitor for controlling the output voltage soft start rising slope and start time during the soft start phase.

[0055] The error output clamping module 13 is mainly the error signal VEA. In the soft start phase, the high clamping BUF clamps VEA to the voltage controlled by the start capacitor C2 in real time through the unit gain negative feedback.

[0056] The comparator control module 14 includes an SS comparator control, the positive input is a voltage VC2 generated by charging the start capacitor C2 with a fixed current Iss, and the negative input is the feedback reference voltage of the loop. The soft start time is determined by comparing VC2 and Vref. When VC2 is greater than Vref, the SS comparator outputs a logic high, indicating that the soft start phase is over. The soft start time is approximately TSS=C2*Vref / Iss, and the soft start slope is approximately Iss / C2. For a reliable design, the soft start time is much greater than the design bandwidth of the voltage loop.

[0057] The selection switching module 15 includes two groups of analog two-choice controls, such as S1 / S2 in the dotted box of the first switching switch group 151 and the second switching switch group 152. The switch is controlled by the SS comparator input logic. At the beginning of the soft start, the SS comparator output SSOK is logic low, S2 is selected to be turned on, and S1 is turned off. At this time, the negative input of the high clamp BUF is the startup capacitor C2 voltage VC2, and the BUF output potential is precisely controlled to be the VC2 voltage. At the same time, the first resistor R1 is disconnected from the startup capacitor C2, and Iss begins to charge the startup capacitor C2 to generate a voltage VC2 with a fixed rising slope. At the end of the soft start, the SS comparator output SSOK is logic high, S2 is selected to be turned off, and S1 is turned on. At this time, the negative input of the high clamp BUF is switched to the designed clamping voltage Vclamp, and the VEA fluctuation is monitored, which is conducive to speeding up the loop response and avoiding the problem that the VEA fluctuation is too high, it takes too long to return to VC2, and the response is too slow. At the same time, the first resistor R1 is reconnected to the first capacitor C1 to serve as zero and pole compensation of the voltage loop, and Iss stops charging the start capacitor C2.

[0058] See also Figure 5 , Figure 5 FIG. 1 is a flow chart of a soft start method according to an embodiment of the present disclosure. Figure 5 As shown, this embodiment provides a method for controlling the soft start of a switching power supply. In some embodiments, the method is applied to the device for controlling the soft start of a switching power supply as described in the above embodiments, and the device includes a starting capacitor. The method includes the following steps S51 to S54.

[0059] In step S51, the voltage of the start capacitor is compared with a reference voltage to determine a soft start time according to the comparison result.

[0060] In step S52, according to the comparison result, switching is performed between the charging stage of the startup capacitor at the beginning of soft start and the clamping monitoring stage of the error signal at the end of soft start.

[0061] In step S53 , a feedback voltage based on the output voltage of the switching power supply is compared with the reference voltage to output an error signal.

[0062] In step S54, during the soft start phase, the error signal is clamped to the voltage of the start capacitor, and the start capacitor is used to control the soft start rising slope and start time of the output voltage; and at the end of the soft start, the jump of the error signal is monitored using a preset high clamp voltage, and the zero and pole required for the voltage loop are generated through the start capacitor.

[0063] See also Figure 6 , Figure 6 FIG. 1 is a schematic diagram of the structure of a BUCK converter according to an embodiment of the present disclosure. Figure 6 As shown, this embodiment provides a BUCK converter, which includes the device for controlling the soft start of a switching power supply as described in the above embodiment, a pulse width modulation module 16, a duty cycle generation module 17, a switch drive control module 18, and a power switch module 19.

[0064] The pulse width modulation module 16 is configured to receive the error signal and the ramp signal from the device, and compare the error signal with the ramp signal to generate a set logic signal. The duty cycle generation module 17 is configured to receive the set logic signal from the pulse width modulation module, and generate a duty cycle control signal based on the set logic signal. The switch drive control module 18 is configured to receive the duty cycle control signal from the duty cycle generation module, and generate a switch drive signal based on the duty cycle control signal. In addition, the power switch module 19 is configured to receive the switch drive signal from the switch drive control module, and output the output voltage based on the switch drive signal.

[0065] See also Figure 7 , Figure 7 FIG. 1 is a schematic diagram showing the structural connection of the BUCK converter according to an embodiment of the present disclosure. Figure 7As shown, in one embodiment, the modules of the device for controlling the soft start of a switching power supply constitute the voltage regulation loop of the BUCK converter. In addition to the error amplification module 11, the loop zero-pole compensation module 12, the error output clamping module 13, the comparator control module 14 and the selection switching module 15 in the device for controlling the soft start of a switching power supply 1, the BUCK converter also includes a pulse width modulation module 16, a duty cycle generation module 17, a switch drive control module 18, a power switch module 19, and an external inductor L and an output capacitor C. The pulse width modulation module 16, the duty cycle generation module 17, the switch drive control module 18, the power switch module 19, the external inductor L and the output capacitor C are electrically coupled in sequence.

[0066] The error signal output end of the device is electrically coupled to the input end of the pulse width modulation module 16, and the error signal is sequentially converted through the pulse width modulation module 16, the duty cycle generation module 17, the switch drive control module 18, the power switch module 19, and the external inductor L and the output capacitor C to output the output voltage of the switching power supply.

[0067] See also Figure 8 , Figure 8 FIG. 1 is a circuit diagram of a BUCK converter according to an embodiment of the present disclosure. Figure 8 As shown, in combination with the error amplification module 11, the loop zero-pole compensation module 12, the error output clamping module 13, the comparator control module 14 and the selection switching module 15 as well as the pulse width modulation module 16, the duty cycle generation module 17, the switch drive control module 18, and the specific implementation form of the power switch module 19, the BUCK converter includes an error AMP 11, a main pole compensation network 12 (R1 / C1 / C2) (wherein, the necessary components are R1 / C2, and the optional component is C1, and generally, these three components will exist in the design), a high clamp BUF 13 (BUF, that is, BUFFER is actually also an operational amplifier), an SS comparator 14 (SS refers to SOFT START, soft start), a soft start switch 15 (soft start charging current Iss and two two-choice switch array control), a pulse width modulation CMP 16 (compare, comparator), a duty cycle DUTY generation module 17, a switch drive control logic 18, a power switch 19 (a high-side switch HS and a low-side switch LS), and an external inductor L and an output capacitor C.

[0068] Figure 8 The part from "pulse width modulation CMP 16" to "LC output circuit composed of external inductor L and output capacitor C" is a known technology in the art and will not be described in detail here.

[0069] like Figure 8 As shown, the RESET logic controls the on-time of the current cycle by controlling the DUTY reset (DUTY=L). DUTY=L controls the power switch HS to be turned off and LS to be turned on. The SET logic controls the off-time of the current cycle by controlling the DUTY set (DUTY=H). DUTY=H controls the power switch HS to be turned on and LS to be turned off.

[0070] See also Fig. 9 , Fig. 9 FIG. 2 shows the working waveform of the BUCK converter according to the embodiment of the present disclosure. Fig. 9 As shown, before the switching power supply is enabled, EN=L, and the voltage of the start capacitor C2 is discharged to 0V.

[0071] The positive terminal of the SS comparator inputs the voltage VC2 of the startup capacitor C2, and the negative terminal inputs the feedback reference voltage Vref (the feedback reference can be changed with the output voltage). At this time, the SS comparator outputs the logic SSOK=L. Control the two two-choice switch arrays, S1 is closed, and S2 is turned on. The negative terminal of the high clamp BUF is connected to the voltage VC2 of the startup capacitor C2, and the positive terminal is connected to the output VEA of the error AMP. At the same time, its output and the gate terminal of NM are short-circuited to form a high-voltage clamp control circuit for controlling the VEA voltage. The soft start charging current Iss charges the startup capacitor C2, so that the VC2 voltage slowly rises at a fixed slope Iss / C2.

[0072] In the soft start phase, as mentioned above, the SS comparator SSOK outputs a logic low, and the output of the error AMP is controlled by the high clamp BUF, that is, at this time, the high clamp BUF accurately controls the maximum output voltage of the output voltage VEA of the error AMP. At this time, the output feedback voltage Vfb slowly rises from 0V, and Vfb is always less than Vref. Therefore, the error AMP (positive terminal connected to the output feedback reference Vref, negative terminal connected to the output feedback voltage Vfb), the output voltage VEA will always be accurately controlled by the high clamp BUF, so that the VEA voltage will slowly rise with the VC2 voltage. Before the error AMP input Vfb does not exceed Vref, the output voltage VEA is controlled by the high clamp BUF.

[0073] Pulse width modulation CMP, the negative terminal is connected to the periodic RAMP voltage (where the RAMP voltage is as Fig. 9 The triangular wave signal around VEA shown in the figure can have a period of the switching frequency), and the positive terminal voltage VEA is used to generate SET logic by comparing RAMP and VEA cycle by cycle, thereby controlling the duty cycle DUTY of the switching power supply. In the soft start stage, Fig. 9As shown, VEA rises slowly, and the RAMP voltage can be reduced below VEA earlier. The SS comparator output SET logic can set SET=H earlier, control DUTY=H to drive the power switch HS to turn on, and LS to turn off. That is, as VEA rises, the duty cycle DUTY of the working cycle slowly increases cycle by cycle until DUTY stabilizes at the stable value set by the target voltage at the end of the soft start.

[0074] In the soft start phase, SSOK=L, DUTY will increase cycle by cycle as VEA slowly rises until the voltage VC2 exceeds the reference voltage Vref. When VC2 is greater than Vref, the SS comparator outputs logic SSOK=H, indicating that the soft start phase is completed, and the entire soft start time is Tss=Vref*C2 / Iss. In order to ensure stable operation during the soft start phase, Tss is required to be much larger than the loop response bandwidth time of the entire switching power supply. At this point, the output voltage will completely follow the rising slope of the voltage VC2 of capacitor C2 (or 1 / K times, K can be set by the output feedback resistor ratio) and slowly rise in a ramp until the target voltage is reached.

[0075] At the end of soft start, SSOK = H, controlling the two-choice switch array, S1 is turned on, and S2 is turned off. At this time, the negative terminal of the high clamp BUF is connected from VC2 to the preset high clamp voltage Vhcalmp (where Vhclamp is a voltage higher than VEA in steady-state operation), which is used to monitor the jump of VEA and speed up the response speed of the voltage regulation loop. The high clamp BUF ends the soft start work and officially enters the real-time monitoring of the size of the error AMP output voltage VEA. When the power supply output jumps, it can be used to monitor and limit the maximum fluctuation voltage of VEA, which is conducive to accelerating the rapid response of the power supply output.

[0076] The compensation network R1 and C2 of the error amplification link are short-circuited to serve as the zero-pole compensation of the entire voltage regulation loop and to adjust the zero-pole distribution of the voltage regulation loop. R1 / C1 / C2 together form the zero-pole compensation of the power supply loop, which is a known technology.

[0077] During the entire soft-start phase, VEA and VC2 are controlled by a unity-gain negative feedback loop consisting of a high-clamp BUF and NM. In addition, in the actual circuit design, the SS comparator and high-clamp BUF have low input offset, so during the soft-start phase and at the end of the soft-start, the voltages of VEA and VC2 can be basically guaranteed to be equal, without causing large output voltage fluctuations at the end to affect the stability of the power supply system.

[0078] In practical applications, the voltage regulation loop is suitable for an ACOT architecture. Specifically, the present disclosure is suitable for a soft start circuit of a switching power supply controlled by a constant on-time (ACOT). By reusing the compensation capacitor of the error amplification link in the voltage regulation loop and combining the high clamping control of the error amplification output, it is possible to set a fixed rising slope from 0V to a normal output voltage regardless of the output voltage.

[0079] During the soft start period of the ACOT controlled switching power supply, the compensation capacitor of part of the error amplifier output loop is started as the control output voltage and rises at a set fixed slope. A small current is used to charge the startup capacitor as the compensation capacitor to generate a voltage with a slow ramp rise, which is used as the high clamp voltage of the error amplifier output and controlled by the high clamp op amp loop. The SS comparator compares this voltage VC2 with the feedback reference voltage Vref. When VC2 rises to Vref, the SS comparator output SSOK logic becomes high. After SSOK=H, the two two-choice switch arrays are controlled, S1 is closed, S2 is turned on, and the startup capacitor C2 is returned to the error amplifier output loop respectively, and the high clamp voltage of the error amplifier output is switched to Vh_clamp. Due to the stick-following characteristics of the ACOT (adaptive on-time) control method, the error amplifier output voltage is about the size of the reference voltage VREF at this time, so the switching of the two-choice switch will not cause fluctuations in the output voltage of the BUCK, and a smooth transition can be achieved.

[0080] Therefore, the present disclosure performs time-division multiplexing of the start capacitor C2, that is, in the soft start phase, the start capacitor C2 is used as a soft start capacitor; and after the start is completed, it is used again as the zero-pole compensation of the voltage regulation loop. In this way, a large internal capacitor can be saved, saving chip area. At the same time, it can be achieved that the power supply system can slowly rise to the target voltage at a fixed slope during the soft start phase when the output voltage is different. The start capacitor C2 can control the rising slope and start time of the output voltage during the soft start phase. After the soft start is completed, it is used as the zero-pole compensation of the entire voltage loop, and the loop compensation is related to the definition of the entire power supply system.

[0081] The present disclosure also provides a chip, wherein the chip includes the BUCK converter described in the above embodiment.

[0082] In practical applications, the present disclosure realizes a high-efficiency and low-cost BUCK converter. Through simulation / actual measurement verification, under the application conditions of input Vin=5V, output Vout=0.5V-1.5V, and load Iout=3A, the BUCK converter can always achieve a slow rise in output voltage with a fixed slope ramp under different output voltages, and has the advantage of fast response.

[0083] The protection scope of the soft start method described in the embodiment of the present disclosure is not limited to the execution order of the steps listed in the embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present disclosure are included in the protection scope of the present disclosure.

[0084] The device for controlling the soft start of a switching power supply described in the present disclosure can implement the soft start method described in the present disclosure, but the device for implementing the soft start method described in the present disclosure includes but is not limited to the structure of the device for controlling the soft start of a switching power supply listed in this embodiment. All structural deformations and replacements of the prior art made according to the principles of the present disclosure are included in the protection scope of the present disclosure.

[0085] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices or methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.

[0086] The modules / units described as separate components may or may not be physically separated, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, the functional modules / units in the various embodiments of the present disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0087] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0088] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0089] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.

Claims

1. A device for controlling soft start of a switching power supply, characterized in that: include: an error amplification module configured to compare a feedback voltage based on the output voltage of the switching power supply with a reference voltage to output an error signal; A loop zero-pole compensation module, comprising a startup capacitor, and configured to generate zeros and poles required for a voltage loop through the startup capacitor, and to control a soft-start rising slope and a startup time of the output voltage through the startup capacitor during a soft-start phase; an error output clamping module, configured to clamp the error signal to the voltage of the startup capacitor; a comparator control module, configured to compare the voltage of the startup capacitor with the reference voltage to determine a soft start time according to a comparison result; as well as The selection switching module is configured to switch between the charging stage of the startup capacitor at the beginning of soft start and the clamping monitoring stage of the error signal at the end of soft start according to the comparison result of the comparator control module.

2. The device according to claim 1, characterized in that The loop zero-pole compensation module also includes a first resistor, The first resistor is electrically coupled to the startup capacitor, and the zero point and pole required by the voltage loop are generated by connecting resistors and capacitors in series and in parallel.

3. The device according to claim 2, characterized in that The loop zero-pole compensation module also includes a first capacitor, The first capacitor is electrically coupled to the first resistor, and forms a loop zero-pole compensation network with the first resistor and the startup capacitor. The first capacitor is configured to filter the error signal output by the error amplification module.

4. The device according to claim 2, characterized in that The error output clamp module includes a high voltage clamp comparator and an NMOS tube. The positive terminal of the high-voltage clamp comparator inputs the error signal, and the negative terminal inputs the preset high clamp voltage or the voltage of the start-up capacitor. The output end of the high-voltage clamping comparator is electrically coupled to the gate of the NMOS tube to form a high-voltage clamping control circuit for controlling the error signal voltage.

5. The device according to claim 4, characterized in that The selection switch module includes a first switch group and a second switch group, and the first switch group and the second switch group both have a two-choose-one switching mode. The first selection end of the first switch group is electrically coupled to one end of the first resistor, the second selection end inputs the soft start charging current, and the common end is electrically coupled to the charging end of the start capacitor. The first selection terminal of the second switch group inputs a preset high clamp voltage, the second selection terminal is electrically coupled to the charging terminal of the startup capacitor, and the common terminal is electrically coupled to the negative terminal of the high voltage clamp comparator.

6. The device according to claim 5, characterized in that In response to the start of the soft start, the comparison results received by the first switch group and the second switch group are first level signals, and the second selection terminals of the first switch group and the second switch group are connected to the common terminal; In response to the end of the soft start, the comparison results received by the first switch group and the second switch group are second level signals, and the first selection terminals of the first switch group and the second switch group are connected to the common terminal.

7. The device according to claim 6, characterized in that In response to the second selection terminals of the first switching switch group and the second switching switch group being turned on with the common terminal, the negative terminal input of the high-voltage clamp comparator is the voltage of the startup capacitor, and the output terminal is controlled to be the voltage of the startup capacitor, and at the same time, the soft start charging current starts to charge the startup capacitor, so that the voltage of the startup capacitor slowly rises with a fixed slope, and the output voltage will completely follow the rising slope of the voltage of the startup capacitor; In response to the first selection terminal of the first switching switch group and the second switching switch group being turned on with the common terminal, the negative terminal of the high-voltage clamp comparator inputs the preset high clamp voltage, and the preset high clamp voltage is used to monitor the jump of the error signal. At the same time, the startup capacitor is electrically coupled with the first resistor to re-constitute a loop zero-pole compensation network.

8. A method for controlling soft start of a switching power supply, characterized in that: include: comparing the voltage of the starting capacitor with a reference voltage to determine a soft start time according to the comparison result; According to the comparison result, switching is performed between a charging stage of the startup capacitor at the beginning of soft starting and a clamping monitoring stage of the error signal at the end of soft starting; comparing a feedback voltage based on the output voltage of the switching power supply with the reference voltage to output an error signal; as well as In the soft start phase, the error signal is clamped to the voltage of the start capacitor, and the start capacitor is used to control the soft start rising slope and start time of the output voltage; as well as At the end of the soft start, the error signal jump is monitored using a preset high clamp voltage to generate the zero and pole required for the voltage loop through the start capacitor.

9. A BUCK converter, characterized in that: include: The device according to any one of claims 1 to 7; a pulse width modulation module configured to receive the error signal from the device and receive a ramp signal, and compare the error signal with the ramp signal to generate a set logic signal; a duty cycle generation module configured to receive the set logic signal from the pulse width modulation module and generate a duty cycle control signal based on the set logic signal; a switch driving control module, configured to receive the duty cycle control signal from the duty cycle generating module, and generate a switch driving signal based on the duty cycle control signal; as well as The power switch module is configured to receive the switch drive signal from the switch drive control module and output the output voltage based on the switch drive signal.

10. A chip, characterized in that: It comprises the BUCK converter according to claim 9.

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