A PWM dead time generation method and device based on FPGA

Abstract

This invention relates to a method and apparatus for generating PWM dead time based on an FPGA. The invention includes generating a PWM signal for driving a half-bridge circuit; resetting registers in the FPGA to an initial state in response to the PWM signal being low; configuring and delaying the rising edge of the PWM signal for a predetermined delay time to generate a dead time; allowing the PWM signal to pass directly through the loop of the half-bridge circuit in response to the PWM signal being low; and outputting the PWM signal after the predetermined delay time in response to the PWM signal being high, thereby achieving dead time control. This invention enables high-precision dead time control and consumes fewer logic resources.

Description

Technical Field

[0001] The present invention relates to the field of motor drive technology, and in particular to a PWM dead time generation method and device based on FPGA. Background Art

[0002] PWM (Pulse Width Modulation) dead time refers to the delay time set when driving two adjacent power semiconductor switches to prevent them from being turned on or off at the same time. This delay ensures that one switch is turned off before the other is turned on, avoiding short circuit problems and current surges, while improving circuit reliability and efficiency.

[0003] At present, the mainstream PWM dead time generation methods mainly include the following: 1. Hardware circuit implementation This is achieved through a dedicated dead time generation circuit. For example, some circuit designs include components such as a comparator, a D flip-flop, an up-down counter, and a time constant circuit. The comparator compares the drain voltage of the low-side switch with the reference voltage, and the D flip-flop receives the comparison signal and outputs the comparison signal using the on-pulse signal of the low-side switch as the trigger clock signal. The up-down counter counts according to the comparison signal output by the D flip-flop and outputs an indication signal, and the time constant circuit generates the dead time according to the indication signal. This method can generate a better dead time and adjust it adaptively.

[0004] 2. DSP Implementation In a digital signal processor (DSP), the input mode, polarity selection, and output mode are set by configuring the dead-band control register (DBCTL). Specifically, when the switch corresponding to the input mode is closed, the rising edge delay or falling edge delay of different signal sources is determined, thereby achieving dead-band time control.

[0005] 3. FPGA Implementation Utilize field programmable gate array (FPGA) to generate PWM dead time. For example, in patent CN104734678A, the following method is adopted: in a timing loop, the clock source is H MHz, and each time a loop is run, in order to realize the dead time generation, first determine the rising edge of the signal, and when the rising edge is determined, set the delay parameter M, and then output a low level; each loop decrements the delay parameter M by 1 until the parameter is zero and outputs a high level. Since the time of each loop is determined, the delay output, i.e., the dead time, is realized.

[0006] However, the traditional PWM dead time generation method based on ARM or DSP has the problems of low precision and complex control method. Especially in high-frequency PWM signal control scenarios, the response speed and accuracy of the traditional method are difficult to meet the requirements. Summary of the invention

[0007] To this end, the present invention provides a PWM dead time generation method and device based on FPGA. Compared with other FPGA technologies, the present invention can achieve high-precision dead time control and occupy less logic resources.

[0008] In order to solve the above technical problems, the present invention provides a PWM dead time generation method based on FPGA, comprising: Generate a PWM signal for driving a half-bridge circuit; In response to the PWM signal being at a low level, resetting the registers in the FPGA to an initial state; Configuring and delaying the rising edge of the PWM signal to a predetermined time so as to generate a dead time; In response to the PWM signal being at a low level, the PWM signal is directly passed through a loop of the half-bridge circuit; In response to the PWM signal being at a high level, the PWM signal is output after the predetermined delay time, so as to realize dead zone control.

[0009] In one embodiment of the present invention, a PWM signal for driving a half-bridge circuit is generated by using an FPGA, including: The periodic high and low level output of the PWM signal is realized through the timer and the output comparator; When the counter value is lower than the set comparison value, the output is high level; When the counter value is greater than or equal to the set comparison value, the output is low.

[0010] In one implementation manner of the present invention, the low level and the high level represent "0" and "1" states respectively.

[0011] In one embodiment of the present invention, configuring and making the rising edge of the PWM signal pass through a predetermined delay time to generate a dead time includes: The predetermined delay time is set by configuring registers or calling counting resources inside the FPGA.

[0012] The present invention also provides a PWM dead time generating device based on FPGA, comprising: A PWM signal output module, used for generating a PWM signal for driving a half-bridge circuit; A low-level reset module, used for resetting the registers in the FPGA to an initial state in response to the PWM signal being at a low level; A hysteresis time delay module, used for making the PWM signal directly pass through the loop of the half-bridge circuit in response to the PWM signal being at a low level; The multi-channel switching module is used to respond to the PWM signal being at a high level and output the PWM signal after the predetermined delay time to achieve dead zone control.

[0013] In one embodiment of the present invention, the PWM signal output module includes a timer, an output comparator and a counter; The periodic high and low level output of the PWM signal is realized through the timer and the output comparator; When the counter value is lower than the set comparison value, the output is high level; When the counter value is greater than or equal to the set comparison value, the output is low.

[0014] In one implementation of the present invention, the PWM signal output module includes a 555 timer or a PWM unit inside an FPGA.

[0015] In one implementation of the present invention, the level output by the PWM signal output module includes a voltage signal of GND, 1.8V, 2.5V, 3.3V or 5V.

[0016] In one embodiment of the present invention, the low-level reset module includes a transistor, which is used to achieve a short power outage when a low-level signal is detected, and restore the register and the operation unit to a power supply state after the power supply is restored.

[0017] In one embodiment of the present invention, the multi-way switching module has a latching function, and selects different transmission paths by selecting switches, so that the "0" signal passes through the loop directly, and the "1" signal is output after passing through the lag time delay module, thereby realizing dead zone control between the upper and lower bridge arms.

[0018] The above technical solution of the present invention has the following advantages compared with the prior art: The FPGA-based PWM dead time generation method and device described in the present invention effectively improves the dead time control accuracy of the PWM signal, significantly reduces the delay in the dead time generation process, and can adapt to higher frequency PWM control requirements. At the same time, the method complexity is reduced, the FPGA resource occupancy is lower, and the efficiency and reliability of the system operation are increased.

[0019] The present invention adopts a low-level reset module, which automatically triggers the reset of registers and operation units when the PWM signal enters a low-level state, so that the storage unit is restored to the initial state in each PWM cycle. This reset mechanism avoids the interference of the current cycle signal caused by the residual data of the previous cycle, and ensures the stability and consistency of the PWM signal output. At the same time, the low-level reset module has a simple structure and can be implemented through transistors or FPGA logic, which greatly improves the efficiency and reliability of the reset function. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0021] Figure 1 The invention discloses a method and device for generating PWM dead time based on FPGA and a principle diagram.

[0022] Figure 2 It is a module connection diagram of the FPGA-based PWM dead time generating device of the present invention.

[0023] Figure 3 This is a dead zone generation effect diagram of the present invention (wherein the Y axis is the PWM amplitude (0-1) and the horizontal axis is time). DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0025] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0026] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0027] Example 1 A PWM dead time generation method based on FPGA in this embodiment includes: S1. Generate a PWM signal for driving a half-bridge circuit.

[0028] Specifically, the periodic high and low level output of the PWM signal is realized through the timer and the output comparator; When the counter value is lower than the set comparison value, the output is high level; When the counter value is greater than or equal to the set comparison value, the output is low.

[0029] The low level and the high level represent "0" and "1" states, respectively.

[0030] It can be understood that the PWM signal is used to control the upper and lower arms of the half-bridge. The complementary PWM signal can drive the upper and lower arms to conduct alternately. In order to avoid the upper and lower arms being turned on at the same time, forming a "straight-through" short circuit, it is necessary to add a delay to the upper arm signal when the lower arm is turned off. Usually, when the shutdown signal falls, the rising edge that arrives at the same time is delayed for a certain period of time, that is, the dead time.

[0031] S2. In response to the PWM signal being at a low level, resetting the registers in the FPGA to an initial state.

[0032] When the PWM signal is low, the registers in the FPGA are reset. This reset ensures that the storage unit returns to the initial state at the beginning of each PWM cycle to prevent the residual data of the previous cycle from affecting the new cycle signal. This reset can be achieved through simple circuits such as transistors. When the PWM signal enters a low level, the reset circuit triggers a short power outage, returning the registers and operation units to their initial state.

[0033] S3. Configure and make the rising edge of the PWM signal pass through a predetermined delay time to generate a dead time.

[0034] FPGA can achieve precise delay setting through counting resources; by configuring the delay value through registers, the dead time can be flexibly adjusted to meet different application requirements.

[0035] S4, in response to the PWM signal being at a low level, allowing the PWM signal to directly pass through a loop of the half-bridge circuit; In response to the PWM signal being at a high level, the PWM signal is output after the predetermined delay time, so as to realize dead zone control.

[0036] When the PWM signal rises to a high level, the upper bridge arm is turned on. In order to ensure that the upper and lower bridge arms are not turned on at the same time, a delay is added. The delay controls the time when the upper bridge arm is turned on, so that the upper bridge arm is turned on after the lower bridge arm is turned off, forming a dead zone.

[0037] Example 2 This embodiment provides a PWM dead time generating device based on FPGA, comprising: A PWM signal output module, used for generating a PWM signal for driving a half-bridge circuit; A low-level reset module, used for resetting the registers in the FPGA to an initial state in response to the PWM signal being at a low level; A hysteresis time delay module, used for making the PWM signal directly pass through the loop of the half-bridge circuit in response to the PWM signal being at a low level; The multi-channel switching module is used to respond to the PWM signal being at a high level and output the PWM signal after the predetermined delay time to achieve dead zone control.

[0038] Specifically, the PWM signal output module includes a timer, an output comparator and a counter; The periodic high and low level output of the PWM signal is realized through the timer and the output comparator; When the counter value is lower than the set comparison value, the output is high level; When the counter value is greater than or equal to the set comparison value, the output is low.

[0039] Specifically, the PWM signal output module includes a 555 timer or a PWM unit inside the FPGA.

[0040] Specifically, the level output by the PWM signal output module includes a voltage signal of GND, 1.8V, 2.5V, 3.3V or 5V.

[0041] Specifically, the low-level reset module includes a transistor, which is used to achieve a short power outage when a low-level signal is detected, and restore the register and the operation unit to the power supply state after the power supply is restored. The low-level reset module can ensure that after sending a "1" signal, when the next PWM cycle arrives, all storage units are in the initial normal state.

[0042] Specifically, the multi-channel switching module has a latching function, and selects different transmission paths by selecting switches, so that the "0" signal passes through the loop directly, and the "1" signal is output after passing through the lag time delay module, thereby realizing dead zone control between the upper and lower bridge arms.

[0043] Inside the FPGA, the multi-way switching module uses multiple registers to achieve the signal latching function by controlling the time of register read and write permissions. In the actual circuit, the same latching function can be achieved through the "74" series chips. The logic design of the multi-way switching module is simple and reliable, so that the "0" signal can pass through the loop directly, and the "1" signal must be output through the delay module, thus forming an accurate dead time and eliminating complex loop judgments. In the half-bridge structure, the hardware enable interlocking structure is used to further ensure that the dead zone control under any failure condition is safe and reliable, avoiding the risk of "logical" short circuits.

[0044] In addition, by using the delay module inside the FPGA or configuring the clock signal through the register, the clock signal of the FPGA can be set as a timer, so that the operating conditions of the FPGA are controlled by the timer, thereby forming an accurate delay module. If a 555 timer chip and its peripheral circuits are used, similar timing functions can also be achieved. By reasonably configuring the registers of the delay module, it can be ensured that the transmission speed of each signal branch and the synchronization of the target module meet the design requirements.

[0045] In the original two-way complementary PWM signal, since there is no dead time, the signal is used as both a selection switch signal and an output signal. In this design, the high-level "1" signal passes through a delay module containing a reset device to form a dead time, thereby ensuring reliable isolation between the upper and lower bridge arms.

[0046] By generating PWM signals through FPGA and introducing precise delay in the signal transmission path, the dead time when the upper and lower bridge arms are switched can be precisely controlled. By using the timer and counting resources inside the FPGA, nanosecond-level delay adjustment can be achieved to meet the precise control requirements of different application scenarios. This precise dead time control avoids the direct-through phenomenon when the upper and lower bridge arms are switched, thereby effectively preventing the risk of short circuit and ensuring the stability and safety of the circuit.

[0047] Reference Figure 1 As shown, the left side is a single dead zone signal output, and the input is a PWM signal ("0" represents a low level, and "1" represents a high level). The signal path is controlled by a selection switch (SEL).

[0048] When the input is "0", the signal passes directly; when the input is "1", the signal is output after passing through the hysteresis time delay module, thereby generating a delay at the beginning of the high level, forming a dead time. This circuit is used in applications that require single-channel control, and dead time control is achieved by delaying the arrival of the rising edge of the signal.

[0049] The right side shows the dual-channel upper and lower bridge arm dead zone signal output, and the input is two complementary PWM signals, which are used for the upper and lower bridge arms respectively. The signal selection and enable are performed through the dual-channel selection switch (SEL and En). The "0" signal passes directly, and the "1" signal is output after passing through the delay module to ensure that the high-level switching of the two bridge arms does not overlap. The hardware enable interlock structure is introduced to ensure the dead zone control between the upper and lower bridge arms under any failure conditions, avoiding short circuits.

[0050] Figure 2 The module connection diagram of the FPGA-based PWM dead time generator is shown. It includes a data conversion module, a hysteresis time delay module, a low-level reset module, and a multi-channel switching module, among which: The data conversion module (Cast) is used to convert the format of the input signal to meet the standards of FPGA internal processing.

[0051] The hysteresis time delay module is used to introduce dead time when the signal is switched. By adding a delay at the rising edge of the high level, the high level of the upper and lower bridge arms is avoided to exist at the same time.

[0052] Low-level reset module (RST): When a reset signal is required, this module resets all registers and counting units to the initial state to ensure that the signal processing of the next cycle is not affected by the previous cycle.

[0053] The multiplexer module uses a multi-way selector switch to select different signal paths. The "sel" signal controls the switching of the signal path, so that the "0" signal is directly output, while the "1" signal is output through the delay module, thus generating a dead time.

[0054] Figure 3 The dead zone generation effect is shown, which is used to show the waveform performance of the PWM signal in different states. The coordinate axes in the figure are as follows: Y axis (PWM amplitude): represents the level state of the PWM signal, "0" represents a low level, and "1" represents a high level. X axis (time): used to show the periodic changes of the PWM signal.

[0055] In the waveform diagram, it can be seen that when the PWM signal switches to a high level, there is an obvious delay, which indicates the effect of the dead time. This delay control ensures that the upper and lower bridge arms are not turned on at the same time when the high level is switched, avoiding a direct short circuit. The two waveforms represent complementary PWM signals. It can be seen that after the high level of one signal drops to a low level, there is a delay on the rising edge of the other signal, which is the performance of the dead time.

[0056] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0057] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0058] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0059] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0060] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A PWM dead time generation method based on FPGA, characterized in that: include: Generate a PWM signal for driving a half-bridge circuit; In response to the PWM signal being at a low level, resetting the registers in the FPGA to an initial state; Configuring and delaying the rising edge of the PWM signal to a predetermined time so as to generate a dead time; In response to the PWM signal being at a low level, the PWM signal is directly passed through a loop of the half-bridge circuit; In response to the PWM signal being at a high level, the PWM signal is output after the predetermined delay time, so as to realize dead zone control.

2. The FPGA-based PWM dead time generation method according to claim 1, characterized in that: Use FPGA to generate PWM signals for driving half-bridge circuits, including: The periodic high and low level output of the PWM signal is realized through the timer and the output comparator; When the counter value is lower than the set comparison value, the output is high level; When the counter value is greater than or equal to the set comparison value, the output is low.

3. The FPGA-based PWM dead time generation method according to claim 2, characterized in that: The low level and the high level represent "0" and "1" states, respectively.

4. The FPGA-based PWM dead time generation method according to claim 1, characterized in that: Configuring and delaying the rising edge of the PWM signal to generate a dead time includes: The predetermined delay time is set by configuring registers or calling counting resources inside the FPGA.

5. A PWM dead time generating device based on FPGA, characterized in that: include: A PWM signal output module, used for generating a PWM signal for driving a half-bridge circuit; A low-level reset module, used for resetting the registers in the FPGA to an initial state in response to the PWM signal being at a low level; A hysteresis time delay module, used for making the PWM signal directly pass through the loop of the half-bridge circuit in response to the PWM signal being at a low level; The multi-channel switching module is used to respond to the PWM signal being at a high level and output the PWM signal after the predetermined delay time to achieve dead zone control.

6. The FPGA-based PWM dead time generating device according to claim 5, characterized in that: The PWM signal output module includes a timer, an output comparator and a counter; The periodic high and low level output of the PWM signal is realized through the timer and the output comparator; When the counter value is lower than the set comparison value, the output is high level; When the counter value is greater than or equal to the set comparison value, the output is low.

7. The FPGA-based PWM dead time generating device according to claim 5, characterized in that: The PWM signal output module includes a 555 timer or a PWM unit inside the FPGA.

8. The FPGA-based PWM dead time generating device according to claim 5, characterized in that: The levels output by the PWM signal output module include voltage signals of GND, 1.8V, 2.5V, 3.3V or 5V.

9. The FPGA-based PWM dead time generating device according to claim 5, characterized in that: The low-level reset module includes a transistor, which is used to achieve a short power outage when a low-level signal is detected, and restore the register and the operation unit to a power supply state after the power supply is restored.

10. The FPGA-based PWM dead time generating device according to claim 5, characterized in that: The multi-channel switching module has a latching function, and selects different transmission paths by selecting switches, so that the "0" signal passes through the loop directly, and the "1" signal is output after passing through the hysteresis time delay module, thereby realizing the dead zone control between the upper and lower bridge arms.

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