A DC-DC converter
By introducing a charge pump module and output circuit into the DC-DC converter, the gate charge of the power transistor is recycled, and the problem of high switching losses of the DC-DC converter in the prior art is solved, achieving higher operating efficiency and lower losses.
Patent Information
- Application Number
- CN202411899958.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-04
AI Technical Summary
The existing DC-DC converters have high switching losses when switching the switch state, resulting in an increase in the use area and cost of the overall module.
By introducing a charge pump module and an output circuit into the DC-DC converter, the gate charge of the power transistor is circulated to reduce charge and energy loss by utilizing the switch combination and energy storage capacitor group.
It improves the operating efficiency of DC-DC converters, reduces switching losses, reduces overall system losses, and improves the ability to conduct on-resistance.
Smart Images
Figure CN119765907A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power conversion circuits, and in particular to a DC-DC converter. Background Art
[0002] As an important voltage conversion module, the DC-DC converter can convert a given voltage signal into the result required by the user and is widely used in various types of power management chips. Compared with another type of voltage conversion unit: low-dropout regulator (LDO), the DCDC converter has a higher voltage conversion efficiency. Due to its high efficiency, pursuing higher efficiency and reducing losses is an important direction for designing and improving DCDC (DC-DC) modules.
[0003] The losses of DCDC converters are mainly divided into two categories: conduction loss and switching loss. Conduction loss mainly occurs in the process of linear change of inductor current, which is related to parasitic resistances such as transmission switch, external inductor, and package routing. Switching loss mainly occurs when the inductor current increases or decreases due to switch switching, which is usually related to the parasitic capacitance of the transmission switch and the scale of the circuit driving the switch. When switching power, traditional DCDC converters change the voltage drop across the inductor, thereby changing the charge and discharge state of the inductor. In order to pursue lower conduction loss, a larger size is often used in the power switch part, which reduces its on-resistance while increasing parasitic capacitance and switching loss during the switching process, increasing the use area of the overall module, and ultimately leading to an increase in cost. Summary of the invention
[0004] In view of this, the present invention provides a DC-DC converter to solve the problem of high switching loss when the existing DC-DC converter switches the switch state.
[0005] The present invention provides a DC-DC converter, comprising: a charge pump module and an output circuit, wherein the output circuit comprises a first power transistor and a second power transistor, the first power transistor connects or disconnects an input voltage and a switch node according to a first drive signal of its gate, and the second power transistor connects or disconnects a ground terminal and the switch node according to a second drive signal of its gate; the charge pump module comprises a switch combination and an energy storage capacitor group; when the first drive signal is switched from a high level to a low level, the charge of the gate of the first power transistor is stored in the energy storage capacitor group through the switch combination, and / or, when the second drive signal is switched from a high level to a low level, the charge of the gate of the second power transistor is stored in the energy storage capacitor group through the switch combination; when the first drive signal is switched from a low level to a high level, the charge in the energy storage capacitor group is transported to the gate of the first power transistor through the switch combination, and / or, when the second drive signal is switched from a low level to a high level, the charge in the energy storage capacitor group is transported to the gate of the second power transistor through the switch combination.
[0006] In the DC-DC converter provided by the present invention, when the first power transistor and the second power transistor switch the switch state based on the first drive signal and the second drive signal respectively, the switch combination switches the switch state, and stores the excess charge of the gate of the first power transistor or the second power transistor in the energy storage capacitor group; and when the first power transistor and the second power transistor need to switch the switch state based on the gate drive voltage, the switch combination switches the switch state again, and transmits the charge stored in the energy storage capacitor group to the gate of the first power transistor or the second power transistor, thereby increasing the drive voltage of the corresponding power transistor, recycling the gate charge of the first power transistor and the second power transistor through the charge pump, reducing the charge and energy loss of the DC-DC converter, and improving the operation efficiency.
[0007] In an optional embodiment, the first power transistor includes a first PMOS transistor, and the second power transistor includes a first NMOS transistor. When the first drive signal is at a low level, the first power transistor connects the input voltage and the switch node, and when the first drive signal is at a high level, the first power transistor disconnects the input voltage and the switch node; when the second drive signal is at a high level, the second power transistor connects the ground terminal and the switch node, and when the second drive signal is at a low level, the second power transistor disconnects the ground terminal and the switch node; when the first power transistor is turned on, the second power transistor is disconnected; when the second power transistor is turned on, the first power transistor is disconnected; the output circuit also includes: an inductor connected between the voltage output terminal and the switch node; and an output capacitor connected between the voltage output terminal and the ground terminal.
[0008] In an optional embodiment, the energy storage capacitor group includes a first energy storage capacitor and a second energy storage capacitor, wherein, when the first drive signal is switched from a high level to a low level, the charge of the gate of the first power transistor is stored in the first energy storage capacitor through a switch combination, and / or, after the second drive signal is switched from a high level to a low level, the charge of the gate of the second power transistor is stored in the second energy storage capacitor through a switch combination; when the first drive signal is switched from a low level to a high level, the charge in the first energy storage capacitor or the second energy storage capacitor is transferred to the gate of the first power transistor through the switch combination, and / or, when the second drive signal is switched from a low level to a high level, the charge in the first energy storage capacitor or the second energy storage capacitor is transferred to the gate of the second power transistor through the switch combination.
[0009] In the DC-DC converter provided by the present invention, the first energy storage capacitor stores the charge of the gate of the first power transistor, and the second energy storage capacitor stores the charge of the gate of the second power transistor. The first energy storage capacitor and the second energy storage capacitor are independently arranged so that the charge storage and release processes of the gates of the two power transistors do not interfere with each other.
[0010] In an optional embodiment, the switch combination includes a first switch combination, a second switch combination, a third switch combination and a fourth switch combination, wherein the first switch combination selectively connects the first connection end of the first energy storage capacitor to the power supply end or the ground end; the second switch combination selectively connects the second connection end of the first energy storage capacitor to the gate of the first power transistor or the gate of the second power transistor; the third switch combination selectively connects the first connection end of the second energy storage capacitor to the power supply end or the ground end; and the fourth switch combination selectively connects the second connection end of the second energy storage capacitor to the gate of the first power transistor or the gate of the second power transistor.
[0011] In an optional embodiment, when the first drive signal is switched from a high level to a low level, the fourth switch combination connects the second connection end of the second energy storage capacitor to the gate of the first power transistor, and the third switch combination connects the first connection end of the second energy storage capacitor to the ground terminal, at which time the charge of the gate of the first power transistor is stored in the second energy storage capacitor, and / or, when the second drive signal is switched from a high level to a low level, the second switch combination connects the second connection end of the first energy storage capacitor to the gate of the second power transistor, and the first switch combination connects the first connection end of the first energy storage capacitor to the ground terminal, at which time the charge of the gate of the second power transistor is stored in the first switch combination. In an energy storage capacitor; when the first drive signal is switched from a low level to a high level, the fourth switch combination connects the second connection end of the second energy storage capacitor to the gate of the second power transistor, and the third switch combination connects the first connection end of the second energy storage capacitor to the power supply end, at which time the charge of the second energy storage capacitor is delivered to the gate of the second power transistor, and / or, when the second drive signal is switched from a low level to a high level, the second switch combination connects the second connection end of the first energy storage capacitor to the gate of the first power transistor, and the first switch combination connects the first connection end of the first energy storage capacitor to the power supply end, at which time the charge in the first energy storage capacitor is delivered to the gate of the first power transistor.
[0012] In an optional embodiment, the first switch combination includes a second NMOS transistor and a second PMOS transistor; the second switch combination includes a third PMOS transistor and a fourth PMOS transistor; the third switch combination includes a fifth PMOS transistor and a third NMOS transistor; and the fourth switch combination includes a sixth PMOS transistor and a seventh PMOS transistor.
[0013] In an optional embodiment, the DC-DC converter also includes: a first inverter and a second inverter connected in series between the signal input terminal and the gate of the first power transistor, and the output terminal of the second inverter outputs the first drive signal; a third inverter and a fourth inverter connected in series between the signal input terminal and the gate of the second power transistor, and the output terminal of the fourth inverter outputs the second drive signal; the first inverter and the third inverter input the control signal through the signal input terminal.
[0014] The DC-DC converter provided by the present invention can flexibly adjust the level logic of the control signal by setting a plurality of inverters, thereby driving different types of transistors to realize charge transmission.
[0015] In an optional embodiment, the control end of the second NMOS transistor is connected to the control end of the second PMOS transistor and the output end of the first inverter, the first end of the second PMOS transistor is connected to the power supply, and the second end of the second PMOS transistor is connected to the first end of the second NMOS transistor and the first connection end of the first energy storage capacitor; the second end of the second NMOS transistor is grounded; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the second NMOS transistor is turned on and the second PMOS transistor is turned off, connecting the first connection end of the first energy storage capacitor to the ground end; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the second PMOS transistor is turned on and the second NMOS transistor is turned off, connecting the first connection end of the first energy storage capacitor to the power supply end.
[0016] In an optional embodiment, the control end of the third PMOS transistor is connected to the output end of the first inverter, the first end of the third PMOS transistor is connected to the second connection end of the first energy storage capacitor and the first end of the fourth PMOS transistor, and the second end of the third PMOS transistor is connected to the gate of the first power transistor; the control end of the fourth PMOS transistor inputs a control signal, and the second end of the fourth PMOS transistor is connected to the gate of the second power transistor; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the third PMOS transistor is turned on and the fourth PMOS transistor is turned off, connecting the second connection end of the first energy storage capacitor to the gate of the second power transistor; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the third PMOS transistor is turned off and the fourth PMOS transistor is turned on, connecting the second connection end of the first energy storage capacitor to the gate of the first power transistor.
[0017] In an optional embodiment, the control end of the fifth PMOS transistor is connected to the control end of the third NMOS transistor and the output end of the third inverter, the first end of the fifth PMOS transistor is connected to the power supply, and the second end of the fifth PMOS transistor is connected to the first end of the third NMOS transistor and the first connection end of the second energy storage capacitor; the second end of the third NMOS transistor is grounded; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the third NMOS transistor is turned on and the fifth PMOS transistor is turned off, connecting the first connection end of the second energy storage capacitor to the ground end; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the third NMOS transistor is turned off and the fifth PMOS transistor is turned on, connecting the first connection end of the second energy storage capacitor to the power supply end.
[0018] In an optional embodiment, a control signal is input to the control end of the sixth PMOS transistor, the first end of the sixth PMOS transistor is connected to the gate of the first power transistor, and the second end of the sixth PMOS transistor is connected to the first end of the seventh PMOS transistor and the second connection end of the second energy storage capacitor; the control end of the seventh PMOS transistor is connected to the output end of the third inverter, and the second end of the seventh PMOS transistor is connected to the gate of the second power transistor; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the sixth PMOS transistor is turned off and the seventh PMOS transistor is turned on, and the second connection end of the second energy storage capacitor is connected to the gate of the second power transistor; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the sixth PMOS transistor is turned on and the seventh PMOS transistor is turned off, and the second connection end of the second energy storage capacitor is connected to the gate of the first power transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0020] Figure 1 It is a composition diagram of a DC-DC converter in the related art;
[0021] Figure 2 is a composition diagram of a DC-DC converter according to an embodiment of the present invention;
[0022] Figure 3 is a specific circuit structure diagram of an output circuit according to an embodiment of the present invention;
[0023] Figure 4 is a composition diagram of an energy storage capacitor bank according to an embodiment of the present invention;
[0024] Figure 5 is a composition diagram of a charge pump module according to an embodiment of the present invention;
[0025] Figure 6 is a specific circuit structure diagram of a DC-DC converter according to an embodiment of the present invention;
[0026] Figure 7 is another specific circuit structure diagram of a DC-DC converter according to an embodiment of the present invention;
[0027] Figure 84 is a waveform diagram of the working process of the DC-DC converter according to an embodiment of the present invention. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0029] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0030] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0031] In the present invention, words such as "connect", "connected", "connect", "coupled", "interconnected" and the like indicating electrical connection, unless otherwise specified, indicate direct or indirect electrical connection. The direct electrical connection indicates a direct connection between two or more objects without any intervening objects, and the indirect electrical connection indicates an electrical connection between two or more objects with one or more objects (such as electrical components or electrical units such as resistors, capacitors, inductors, switches, filters, etc.) intervening.
[0032] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0033] Traditional DC-DC converters, such as Figure 1As shown, PULSE is the gate pulse signal, BUF1 and BUF2 are forward drive modules, PM1 is PMOS, and NM1 is NMOS. Under normal circumstances, the switching of PM1 and NM1 is controlled by the PULSE signal: when PULSE pulls PM1 low to turn on, the potential of the LX point is raised, and the inductor L1 enters the charging state; when the PULSE is pulled high, PM1 is turned off, the DCDC converter enters the dead zone working state, and the internal parasitic body diode of NM1 is turned on; then NM1 is turned on, the potential of the LX point is pulled low, and the inductor L1 enters the power-off state. However, the conduction loss of the traditional DC-DC converter mainly occurs in the process of linear change of the inductor current, which is related to the parasitic resistance of the transmission switch, external inductor, package routing, etc.; while the switching loss mainly occurs at the moment when the inductor current increases or decreases due to the switching, which is usually related to the parasitic capacitance of the transmission switch and the scale of the circuit driving the switch. When switching power, traditional DCDC converters change the voltage drop across the inductor, thereby changing the charging and discharging state of the inductor. In order to pursue lower conduction losses, larger sizes are often used in the power switch part, which reduces its on-resistance while also increasing parasitic capacitance and switching losses during the switching process, increasing the overall module usage area, and ultimately leading to an increase in cost.
[0034] To this end, this embodiment provides a DC-DC converter, such as Figure 2 As shown, it includes: a charge pump module 1 and an output circuit 2. The output circuit 2 includes a first power transistor 21 and a second power transistor 22. The first power transistor 21 connects or disconnects the input voltage VDD and the switch node LX according to a first drive signal of its gate, and the second power transistor 22 connects or disconnects the ground terminal GND and the switch node LX according to a second drive signal of its gate. The charge pump module 1 includes a switch combination 11 and an energy storage capacitor group 12.
[0035] Specifically, Figure 2 In the embodiment, the level state of the first driving signal is used to control the on-off state of the first power transistor 21, and the level state of the second driving signal is used to control the on-off state of the second power transistor 22. When the first driving signal is switched from a high level to a low level, the switch combination 11 switches the switch state synchronously, so that the excess charge on the gate of the first power transistor 21 is stored in the energy storage capacitor group 12 through the switch combination 11; the excess charge on the gate of the second power transistor 22 is stored in the energy storage capacitor group 12 through the switch combination 11.
[0036] Specifically, Figure 2In the embodiment, when the first drive signal is switched from a low level to a high level, in order to increase the drive voltage of the gate of the first power transistor 21, the switch combination 11 synchronously switches the switch state based on the first drive signal, so that the energy storage capacitor group 12 transfers the internally stored charge to the gate of the first power transistor 21, and raises the gate level of the first power transistor 21 based on the first drive signal; when the second drive signal is switched from a low level to a high level, in order to increase the drive voltage of the gate of the second power transistor 22, the switch combination 11 synchronously switches the switch state based on the second drive signal, so that the energy storage capacitor group 12 transfers the internally stored charge to the gate of the second power transistor 22, and raises the gate level of the second power transistor 22 based on the second drive signal.
[0037] It should be noted that those skilled in the art may adopt other connection methods to implement the above-mentioned charge pump function in the DC-DC converter, so that the DC-DC converter output circuit recycles the gate charge and raises the gate drive level when switching the switch state.
[0038] That is to say, the excess charge on the gate of the first power transistor 21 can be stored in the energy storage capacitor group 12 alone, the excess charge on the gate of the second power transistor 22 can be stored in the energy storage capacitor group 12 alone, or the excess charge on the gates of the first power transistor 21 and the second power transistor 22 can be stored in the energy storage capacitor group 12 at the same time. The charge stored in the energy storage capacitor group 12 can be delivered to the gate of the first power transistor 21 alone, the charge stored in the energy storage capacitor group 12 can be delivered to the gate of the second power transistor 22 alone, or the charge stored in the energy storage capacitor group 12 can be delivered to the gate of the first power transistor 21 and the gate of the second power transistor 22 at the same time. The switch combination 11 can adopt a combination of various switches in the prior art, as long as the energy storage and release functions of the energy storage capacitor group 12 mentioned above can be realized.
[0039] In the case of a larger switch area, each switching action of the DC-DC converter of this embodiment will cause a large amount of switch charge to flow, thereby causing a large switching loss. When the gate potential turns high, this part of the switch charge flows into the gate parasitic capacitance of the switch via the power supply. When the gate potential changes again, the original method of directly discharging the charge into the ground is changed, and the gate charge is recycled into the energy storage capacitor group for reuse, and together with the power supply, the next switch switching action is supported, thereby achieving gate charge recycling and reuse, reducing the loss of charge and energy. In addition to increasing the gate switch area, this embodiment can also increase the gate potential. When the gate potential changes from off to on again, the last collected charge is reused to a potential that breaks through the power supply voltage limit using the charge pump, and the switching loss at this time does not increase. A higher gate potential means a lower on-resistance, thereby reducing the loss of the overall system and improving the overall operating efficiency of the DC-DC converter.
[0040] In the DC-DC converter provided in this embodiment, when the first power transistor and the second power transistor switch the switch state based on the first drive signal and the second drive signal respectively, the switch combination switches the switch state, and stores the excess charge of the gate of the first power transistor or the second power transistor in the energy storage capacitor group, and when the first power transistor and the second power transistor need to switch the switch state based on the gate drive voltage, the switch combination switches the switch state again, and transmits the charge stored in the energy storage capacitor group to the gate of the first power transistor or the second power transistor, thereby increasing the drive voltage of the corresponding power transistor, and recycling the gate charge of the first power transistor and the second power transistor through the charge pump, thereby reducing the charge and energy loss of the DC-DC converter and improving the operating efficiency.
[0041] In some optional embodiments, such as Figure 3 As shown, the first power transistor 21 includes a first PMOS transistor PM1 , and the second power transistor 22 includes a first NMOS transistor NM1 .
[0042] Specifically, Figure 3In the embodiment, when the first driving signal is at a low level, the first power transistor 21 is turned on to connect the input voltage VDD and the switch node LX, and when the first driving signal is at a high level, the first power transistor 21 disconnects the input voltage VDD and the switch node LX; when the second driving signal is at a high level, the second power transistor 22 connects the ground terminal GND and the switch node LX, and when the second driving signal is at a low level, the second power transistor 22 disconnects the ground terminal GND and the switch node LX; when the first power transistor 21 is turned on, the second power transistor 22 is turned off; when the second power transistor 22 is turned on, the first power transistor 21 is turned off. The first power transistor 21 and the second power transistor 22 will not be turned on at the same time, and there will be a period of time when both are turned off at the same time.
[0043] Specifically, Figure 3 In the embodiment, the output circuit 2 further includes: an inductor L1 connected between the voltage output terminal and the switch node LX; an output capacitor C1 connected between the voltage output terminal and the ground terminal GND, and the voltage output terminal is connected to one end of the load resistor R1.
[0044] It should be noted that the output circuit in this embodiment has the same working principle as the output power stage of a conventional DC-DC converter, which will not be described in detail here.
[0045] In some optional embodiments, such as Figure 4 As shown, the energy storage capacitor group 12 includes a first energy storage capacitor C2 and a second energy storage capacitor C3. Of course, in other embodiments, there may be only one energy storage capacitor.
[0046] Specifically, Figure 4 In the embodiment, when the first drive signal is switched from a high level to a low level, the charge of the gate of PM1 is stored in the first energy storage capacitor C2 through the switch combination 11, and when the second drive signal is switched from a high level to a low level, the charge of the gate of NM1 is stored in the second energy storage capacitor C3 through the switch combination 11; when the first drive signal is switched from a low level to a high level, the charge in the first energy storage capacitor C2 or the second energy storage capacitor C3 is delivered to the gate of PM1 through the switch combination 11, and when the second drive signal is switched from a low level to a high level, the charge in the first energy storage capacitor C2 or the second energy storage capacitor C3 is delivered to the gate of NM1 through the switch combination 11. Those skilled in the art can set the on-off logic of the switch combination 11 as needed, so as to control the charge in the first energy storage capacitor C2 or the second energy storage capacitor C3 to be delivered to the gate of the corresponding power transistor respectively.
[0047] In some optional embodiments, such as Figure 5As shown, the switch combination 11 includes a first switch combination 111, a second switch combination 112, a third switch combination 113 and a fourth switch combination 114, wherein the first switch combination 111 selectively connects the first connection end of the first energy storage capacitor C2 to the power supply end or the ground end; the second switch combination 112 selectively connects the second connection end of the first energy storage capacitor C2 to the gate of PM1 or the gate of NM1; the third switch combination 113 selectively connects the first connection end of the second energy storage capacitor C3 to the power supply end or the ground end; and the fourth switch combination 114 selectively connects the second connection end of the second energy storage capacitor C3 to the gate of PM1 or the gate of NM1.
[0048] Specifically, Figure 5 In the embodiment, when the control signal is switched from a high level to a low level, the first drive signal and the second drive signal are switched from a high level to a low level, the third switch combination 113 controls the first connection end of the second energy storage capacitor C3 to be grounded, and then the fourth switch combination 114 controls the charge of the gate of PM1 to be stored in the second energy storage capacitor C3; similarly, after the first switch combination 111 controls the first connection end of the first energy storage capacitor C2 to be grounded, the second switch combination 112 controls the charge of the gate of NM1 to be stored in the first energy storage capacitor C2.
[0049] Specifically, Figure 5 In the embodiment, when the control signal is switched from a high level to a low level, and the first drive signal and the second drive signal are switched from a high level to a low level, after the first switch combination 111 controls the first connection end of the first energy storage capacitor C2 to be connected to VDD, the charge of the first connection end of the first energy storage capacitor C2 is superimposed with VDD on the basis of the original stored charge, and the charge in the first energy storage capacitor C2 is transmitted to the gate of PM1 through the second switch combination 112, thereby increasing the gate voltage of PM1 to a voltage higher than the first drive signal voltage; similarly, after the third switch combination 113 controls the first connection end of the second energy storage capacitor C3 to be connected to VDD, the charge of the first connection end of the second energy storage capacitor C3 is superimposed with VDD on the basis of the original stored charge, and the charge in the second energy storage capacitor C3 is transmitted to the gate of NM1 through the fourth switch combination 114, thereby increasing the gate voltage of NM1 to a voltage higher than the second drive signal voltage.
[0050] In some optional embodiments, such as Figure 6As shown, the first switch combination 111 includes a second NMOS transistor NM2 and a second PMOS transistor PM2; the second switch combination 112 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4; the third switch combination 113 includes a fifth PMOS transistor PM5 and a third NMOS transistor NM3; the fourth switch combination 114 includes a sixth PMOS transistor PM6 and a seventh PMOS transistor PM7. Each MOS transistor in each switch combination is used as a switch.
[0051] For example, Figure 6 In the embodiment, the control signal is the input signal of the entire DC-DC converter, and the first drive signal and the second drive signal have the same level logic as the control signal at the same time, and the third drive signal and the fourth drive signal have opposite level logic as the control signal at the same time. The control end of the first switch combination 111 receives the third drive signal, the two control ends of the second switch combination 112 respectively receive the control signal and the third drive signal with opposite level logics, the control end of the third switch combination 113 receives the fourth drive signal, and the two control ends of the fourth switch combination 114 respectively receive the control signal and the fourth drive signal with opposite level logics.
[0052] For example, Figure 6 In the embodiment, when the control signal is switched from a high level to a low level, the first drive signal and the second drive signal are switched from a high level to a low level, and the third drive signal and the fourth drive signal are switched from a low level to a high level, NM3 is turned on and PM5 is turned off, so that the lower plate (i.e., the first connection end) of the second energy storage capacitor C3 is grounded. At this time, PM6 is turned on and PM7 is turned off, and the charge of the gate of PM1 is stored in the second energy storage capacitor C3 through PM6; when the control signal is switched from a low level to a high level, the first drive signal and the second drive signal are turned on and off. After the signal is switched from low level to high level, and the third drive signal and the fourth drive signal are switched from high level to low level, PM5 is turned on and NM3 is turned off, so that the lower plate (i.e., the first connection end) of the second energy storage capacitor C3 is connected to VDD, and the voltage of the upper plate (i.e., the second connection end) of the second energy storage capacitor C3 is VDD based on the original charge voltage. At this time, PM7 is turned on and PM6 is turned off, and the charge in the second energy storage capacitor C3 is transmitted to the gate of NM1 through PM7, thereby increasing the gate voltage of NM1 to be higher than the second drive signal voltage.
[0053] For example, Figure 6In the embodiment, when the control signal is switched from a high level to a low level, the first drive signal and the second drive signal are switched from a high level to a low level, and the third drive signal and the fourth drive signal are switched from a low level to a high level, NM2 is turned on and PM2 is turned off, so that the lower plate (i.e., the first connection end) of the first energy storage capacitor C2 is grounded. At this time, PM4 is turned on and PM3 is turned off, and the charge of the gate of NM1 is stored in the first energy storage capacitor C2 through PM4; when the control signal is switched from a low level to a high level, the first drive signal and the second drive signal are turned on and PM2 is turned off. After the signal is switched from low level to high level, and the third drive signal and the fourth drive signal are switched from high level to low level, PM2 is turned on and NM2 is turned off, so that the lower plate (i.e., the first connection end) of the first energy storage capacitor C2 is connected to VDD, and the voltage of the upper plate (i.e., the second connection end) of the first energy storage capacitor C2 is VDD based on the original charge voltage. At this time, PM3 is turned on and PM4 is turned off, and the charge in the first energy storage capacitor C2 is transported to the gate of PM1 through PM3, thereby increasing the gate voltage of PM1 to be higher than the first drive signal voltage.
[0054] It should be noted that those skilled in the art can adjust the level logic of each driving signal according to the type of each transistor, so that the DC-DC converter has the above functions.
[0055] In some optional embodiments, such as Figure 7 The DC-DC converter shown also includes: a first inverter INV1 and a second inverter INV2 connected in series between the signal input terminal and the gate of the first power transistor, and the output terminal of the second inverter INV2 outputs a first drive signal; a third inverter INV3 and a fourth inverter INV4 connected in series between the signal input terminal and the gate of the second power transistor, and the output terminal of the fourth inverter INV4 outputs a second drive signal; the first inverter INV1 and the third inverter INV3 input a control signal PULSE through the signal input terminal.
[0056] Figure 7In the embodiment, the control end of the second NMOS transistor NM2 is connected to the control end of the second PMOS transistor PM2 and the output end of the first inverter INV1, the first end of the second PMOS transistor PM2 is connected to the power supply, and the second end of the second PMOS transistor PM2 is connected to the first end of the second NMOS transistor NM2 and the first connection end of the first energy storage capacitor C2; the second end of the second NMOS transistor NM2 is grounded; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the second NMOS transistor NM2 is turned on and the second PMOS transistor PM2 is turned off, and the first connection end of the first energy storage capacitor C2 is connected to the ground end; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the second PMOS transistor PM2 is turned on and the second NMOS transistor NM2 is turned off, and the first connection end of the first energy storage capacitor C2 is connected to the power supply end.
[0057] Figure 7 In the embodiment, the control end of the third PMOS transistor PM3 is connected to the output end of the first inverter INV1, the first end of the third PMOS transistor PM3 is connected to the second connection end of the first energy storage capacitor C2 and the first end of the fourth PMOS transistor PM4, and the second end of the third PMOS transistor PM3 is connected to the gate of PM1; the control end of the fourth PMOS transistor PM4 inputs a control signal, and the second end of the fourth PMOS transistor PM4 is connected to the gate of NM1; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the third PMOS transistor PM3 is turned on and the fourth PMOS transistor PM4 is turned off, and the second connection end of the first energy storage capacitor C2 is connected to the gate of NM1; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the third PMOS transistor PM3 is turned off and the fourth PMOS transistor PM4 is turned on, and the second connection end of the first energy storage capacitor C2 is connected to the gate of PM1.
[0058] Figure 7In the embodiment, the control end of the fifth PMOS transistor PM5 is connected to the control end of the third NMOS transistor NM3 and the output end of the third inverter INV3, the first end of the fifth PMOS transistor PM5 is connected to the power supply, and the second end of the fifth PMOS transistor PM5 is connected to the first end of the third NMOS transistor NM3 and the first connection end of the second energy storage capacitor C3; the second end of the third NMOS transistor NM3 is grounded; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the third NMOS transistor NM3 is turned on and the fifth PMOS transistor PM5 is turned off, and the first connection end of the second energy storage capacitor C3 is connected to the ground end; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the third NMOS transistor NM3 is turned off and the fifth PMOS transistor PM5 is turned on, and the first connection end of the second energy storage capacitor C3 is connected to the power supply end.
[0059] Figure 7 In the embodiment, a control signal is input to the control end of the sixth PMOS transistor PM6, a first end of the sixth PMOS transistor PM6 is connected to the gate of PM1, a second end of the sixth PMOS transistor PM6 is connected to the first end of the seventh PMOS transistor PM7 and the second connection end of the second energy storage capacitor C3; a control end of the seventh PMOS transistor PM7 is connected to the output end of the third inverter INV3, and a second end of the seventh PMOS transistor PM7 is connected to the gate of NM1; when the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the sixth PMOS transistor PM6 is turned off and the seventh PMOS transistor PM7 is turned on, and the second connection end of the second energy storage capacitor C3 is connected to the gate of NM1; when the control signal is switched from a low level to a high level, after the first drive signal is switched from a low level to a high level, the sixth PMOS transistor PM6 is turned on and the seventh PMOS transistor PM7 is turned off, and the second connection end of the second energy storage capacitor C3 is connected to the gate of PM1.
[0060] Specifically, Figure 7 In the embodiment, when the whole system is in sleep mode, both the High side (ie PM1) and the Low side (ie NM1) are in off state. At this time, the gate signal of PM1 is high, the gate signal of NM1 is low, and the current of the inductor L1 is zero.
[0061] Specifically, Figure 7In the embodiment, when the system enters the charging mode, the control signal PULSE is at a low level and PM6 is turned on. At this time, the control signal PULSE is reversed by the third inverter INV3 and the fourth inverter INV4, so that the second drive signal of the gate of NM1 is also at a low level, so that NM1 is turned off; the third inverter INV3 reverses the control signal PULSE and outputs it as high, so that NM3 is turned on, PM5 and PM7 are turned off, and the lower plate (i.e., the first connection end) of the second energy storage capacitor C3 is grounded, and the upper plate (i.e., the second connection end) of C2 is connected to the drain of PM6. At this time, the first drive signal of the gate of PM1 is also at a low level after being reversed by the first inverter INV1 and the second inverter INV2. The first drive signal controls PM1 to turn on and pulls the gate of PM1 down. The excess charge of the gate of PM1 is temporarily stored in the second energy storage capacitor C3 through PM6. The inductor current flows from VDD to PM1 to LX to L1 to C1 and R1, and the current of the inductor L1 continues to increase; then PM1 is turned off, NM1 is also turned off, and the system enters the dead time.
[0062] Specifically, Figure 7 In the process, the control signal PULSE is switched to a high level, PM6 is turned off, and the second drive signal pulls up the gate of NM1 to control NM1 to turn on. Since the output of the third inverter INV3 is low at this time, NM3 is turned off, PM5 and PM7 are turned on, and the potential of the lower plate (i.e., the first connection end) of the second energy storage capacitor C3 is pulled up to VDD. The charge in the second energy storage capacitor C3 is transmitted to the gate of NM1 through PM7 under the action of VDD. The extra charge on the gate of NM1 causes the potential of the gate of NM1 to be pulled up on the basis of the second drive signal. The current of the inductor L1 flows from L1 to R1 to GND to NM1 and then back to L1.
[0063] Specifically, Figure 7 Similarly, when the control signal PULSE switches from a high level to a low level, PM4 is turned on, the output of the first inverter INV1 is high, so that NM2 is turned on, PM2 and PM3 are turned off, the lower plate (i.e., the first connection end) of the first energy storage capacitor C2 is grounded, and the upper plate (i.e., the second connection end) of the first energy storage capacitor C2 is connected to the drain of PM4. At this time, the control signal PULSE is reversed by the third inverter INV3 and the fourth inverter INV4, so that the second drive signal of the gate of NM1 is also low, NM1 is turned off and the gate of NM1 is pulled down, and the excess charge of the gate of NM1 is temporarily stored in the first energy storage capacitor C2 through PM4.
[0064] Specifically, Figure 7In the process, when the control signal PULSE is switched from a low level to a high level, PM4 is turned off. After the control signal PULSE is reversed by the first inverter INV1 and the second inverter INV2, the first drive signal of the gate of PM1 is also high, so that PM1 is turned off; the output of the first inverter INV1 is low, so that NM2 is turned off, PM2 and PM3 are turned on, and the potential of the lower plate (i.e., the first connection end) of the first energy storage capacitor C2 is pulled up to VDD. The charge in the first energy storage capacitor C2 is transferred to the gate of PM1 through PM3 under the action of VDD. The extra charge on the gate of PM1 causes the potential of the gate of PM1 to be pulled up on the basis of the first drive signal to maintain the off state.
[0065] For example, Figure 8 : is a diagram of the main signal changes in the ideal working state of the DC-DC converter, wherein PDRV1 is the gate level of PM1 of the traditional DC-DC converter, NDRV1 is the gate level of NM1 of the traditional DC-DC converter, PDRV2 is the gate level of PM1 of the DC-DC converter of this embodiment, NDRV2 is the gate level of NM1 of the DC-DC converter of this embodiment, C2 is the potential difference between the two plates of the first energy storage capacitor C2, C3 is the potential difference between the two plates of the second energy storage capacitor C3, LX is the potential change of the LX point, IL0 is the inductor current change waveform: during the inductor discharge period, this embodiment collects the charges when NDRV and PDRV are pulled low, and reuses them again when PDRV and NDRV are pulled high. Compared with the traditional structure, PDRV and NDRV will have an obvious level rise when the gate is high.
[0066] This embodiment reuses the gate charge of the High side end when it is turned on and the Low side end when it is turned off, temporarily stores the gate charge at each switch switching and uses it to drive the next switch cycle, so that the gate charge can be recycled, which significantly reduces the switching loss. This embodiment also increases the gate voltage of the High side end and the Low side end: by reusing the gate charge of the High side end and the Low side end and using the charge pump technology to increase the gate voltage when the High side end and the Low side end are turned high, the on-resistance capability is improved, and the charge pump technology is used to increase the gate voltage to a level higher than the power supply voltage, so that the PMOS and NMOS tubes on both sides can be more fully turned on. This method not only reduces the conduction loss, but also improves the current transmission efficiency of the system. In addition, the higher gate drive voltage improves the performance of the converter under heavy load conditions, which helps to maintain a lower on-state voltage drop and higher efficiency, especially in the process of handling high current applications.
[0067] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.
Claims
1. A DC-DC converter, characterized in that: include: Charge pump module and output circuit, wherein: The output circuit includes a first power transistor and a second power transistor, the first power transistor connects or disconnects the input voltage and the switch node according to a first drive signal of the gate thereof, and the second power transistor connects or disconnects the ground terminal and the switch node according to a second drive signal of the gate thereof; The charge pump module includes a switch combination and an energy storage capacitor group; When the first drive signal is switched from a high level to a low level, the charge of the gate of the first power transistor is stored in the energy storage capacitor group through the switch combination, and / or, when the second drive signal is switched from a high level to a low level, the charge of the gate of the second power transistor is stored in the energy storage capacitor group through the switch combination; When the first drive signal is switched from a low level to a high level, the charge in the energy storage capacitor group is transferred to the gate of the first power transistor through the switch combination, and / or, when the second drive signal is switched from a low level to a high level, the charge in the energy storage capacitor group is transferred to the gate of the second power transistor through the switch combination.
2. The DC-DC converter according to claim 1, characterized in that: The first power transistor includes a first PMOS transistor, the second power transistor includes a first NMOS transistor, When the first driving signal is at a low level, the first power transistor connects the input voltage and the switch node; when the first driving signal is at a high level, the first power transistor disconnects the input voltage and the switch node; When the second driving signal is at a high level, the second power transistor connects the ground terminal and the switch node; when the second driving signal is at a low level, the second power transistor disconnects the ground terminal and the switch node; When the first power transistor is turned on, the second power transistor is turned off; When the second power transistor is turned on, the first power transistor is turned off; The output circuit further includes: an inductor connected between the voltage output terminal and the switch node; An output capacitor is connected between the voltage output terminal and the ground terminal.
3. The DC-DC converter according to claim 1, characterized in that: The energy storage capacitor group includes a first energy storage capacitor and a second energy storage capacitor, wherein: When the first drive signal is switched from a high level to a low level, the charge of the gate of the first power transistor is stored in the first energy storage capacitor through the switch combination, and / or, when the second drive signal is switched from a high level to a low level, the charge of the gate of the second power transistor is stored in the second energy storage capacitor through the switch combination; When the first drive signal is switched from a low level to a high level, the charge in the first energy storage capacitor or the second energy storage capacitor is transferred to the gate of the first power transistor through the switch combination, and / or, when the second drive signal is switched from a low level to a high level, the charge in the first energy storage capacitor or the second energy storage capacitor is transferred to the gate of the second power transistor through the switch combination.
4. The DC-DC converter according to claim 3, characterized in that: The switch combination includes a first switch combination, a second switch combination, a third switch combination and a fourth switch combination, wherein: The first switch combination selectively connects the first connection end of the first energy storage capacitor to the power supply end or the ground end; The second switch combination selectively connects the second connection end of the first energy storage capacitor to the gate of the first power transistor or the gate of the second power transistor; The third switch combination selectively connects the first connection end of the second energy storage capacitor to the power supply end or the ground end; The fourth switch combination selectively connects the second connection end of the second energy storage capacitor to the gate of the first power transistor or the gate of the second power transistor.
5. The DC-DC converter according to claim 4, characterized in that: When the first drive signal is switched from a high level to a low level, the fourth switch combination connects the second connection end of the second energy storage capacitor to the gate of the first power transistor, and the third switch combination connects the first connection end of the second energy storage capacitor to the ground end, at which time the charge of the gate of the first power transistor is stored in the second energy storage capacitor, and / or, when the second drive signal is switched from a high level to a low level, the second switch combination connects the second connection end of the first energy storage capacitor to the gate of the second power transistor, and the first switch combination connects the first connection end of the first energy storage capacitor to the ground end, at which time the charge of the gate of the second power transistor is stored in the first energy storage capacitor; When the first drive signal is switched from a low level to a high level, the fourth switch combination connects the second connection end of the second energy storage capacitor to the gate of the second power transistor, and the third switch combination connects the first connection end of the second energy storage capacitor to the power supply end, at which time the charge of the second energy storage capacitor is delivered to the gate of the second power transistor, and / or, when the second drive signal is switched from a low level to a high level, the second switch combination connects the second connection end of the first energy storage capacitor to the gate of the first power transistor, and the first switch combination connects the first connection end of the first energy storage capacitor to the power supply end, at which time the charge in the first energy storage capacitor is delivered to the gate of the first power transistor.
6. The DC-DC converter according to claim 5, characterized in that: The first switch combination includes a second NMOS transistor and a second PMOS transistor; The second switch combination includes a third PMOS transistor and a fourth PMOS transistor; The third switch combination includes a fifth PMOS transistor and a third NMOS transistor; The fourth switch combination includes a sixth PMOS transistor and a seventh PMOS transistor.
7. The DC-DC converter according to claim 6, characterized in that: Also includes: A first inverter and a second inverter are connected in series between the signal input terminal and the gate of the first power transistor, and the output terminal of the second inverter outputs the first driving signal; A third inverter and a fourth inverter are connected in series between the signal input terminal and the gate of the second power transistor, and the output terminal of the fourth inverter outputs the second driving signal; The first inverter and the third inverter are input with control signals through signal input terminals.
8. The DC-DC converter according to claim 7, characterized in that: The control end of the second NMOS transistor is connected to the control end of the second PMOS transistor and the output end of the first inverter, the first end of the second PMOS transistor is connected to a power supply, and the second end of the second PMOS transistor is connected to the first end of the second NMOS transistor and the first connection end of the first energy storage capacitor; The second terminal of the second NMOS transistor is grounded; When the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the second NMOS transistor is turned on and the second PMOS transistor is turned off, connecting the first connection end of the first energy storage capacitor to the ground end; When the control signal switches from a low level to a high level, after the first drive signal switches from a low level to a high level, the second PMOS transistor is turned on and the second NMOS transistor is turned off, connecting the first connection end of the first energy storage capacitor to the power supply end.
9. The DC-DC converter according to claim 7, characterized in that: The control end of the third PMOS transistor is connected to the output end of the first inverter, the first end of the third PMOS transistor is connected to the second connection end of the first energy storage capacitor and the first end of the fourth PMOS transistor, and the second end of the third PMOS transistor is connected to the gate of the first power transistor; The control signal is input to the control terminal of the fourth PMOS transistor, and the second terminal of the fourth PMOS transistor is connected to the gate of the second power transistor; When the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the third PMOS transistor is turned on and the fourth PMOS transistor is turned off, connecting the second connection end of the first energy storage capacitor to the gate of the second power transistor; When the control signal switches from a low level to a high level, after the first drive signal switches from a low level to a high level, the third PMOS transistor is turned off and the fourth PMOS transistor is turned on, connecting the second connection end of the first energy storage capacitor to the gate of the first power transistor.
10. The DC-DC converter according to claim 7, characterized in that: The control end of the fifth PMOS transistor is connected to the control end of the third NMOS transistor and the output end of the third inverter, the first end of the fifth PMOS transistor is connected to a power supply, and the second end of the fifth PMOS transistor is connected to the first end of the third NMOS transistor and the first connection end of the second energy storage capacitor; The second terminal of the third NMOS transistor is grounded; When the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the third NMOS transistor is turned on and the fifth PMOS transistor is turned off, connecting the first connection end of the second energy storage capacitor to the ground end; When the control signal switches from a low level to a high level, after the first drive signal switches from a low level to a high level, the third NMOS transistor is turned off and the fifth PMOS transistor is turned on, connecting the first connection end of the second energy storage capacitor to the power supply end.
11. The DC-DC converter according to claim 7, characterized in that: The control signal is input to the control end of the sixth PMOS transistor, the first end of the sixth PMOS transistor is connected to the gate of the first power transistor, and the second end of the sixth PMOS transistor is connected to the first end of the seventh PMOS transistor and the second connection end of the second energy storage capacitor; The control end of the seventh PMOS transistor is connected to the output end of the third inverter, and the second end of the seventh PMOS transistor is connected to the gate of the second power transistor; When the control signal is switched from a high level to a low level, after the first drive signal is switched from a high level to a low level, the sixth PMOS transistor is turned off and the seventh PMOS transistor is turned on, connecting the second connection end of the second energy storage capacitor to the gate of the second power transistor; When the control signal switches from a low level to a high level, after the first drive signal switches from a low level to a high level, the sixth PMOS transistor is turned on and the seventh PMOS transistor is turned off, connecting the second connection end of the second energy storage capacitor to the gate of the first power transistor.