Boost cold start circuit

Abstract

The embodiment of the present invention discloses a boost cold start circuit. The circuit includes an oscillator, a self-biased charge pump, a monitoring module, an energy storage module and a switch module; the oscillator is used to generate a clock signal, the self-biased charge pump is used to boost the initial low voltage input to its signal input terminal according to the clock signal to generate a first bias voltage and a second bias voltage, the energy storage module is used to store the first bias voltage, the monitoring module is used to control the switch module to output the first bias voltage to the boost circuit when the first bias voltage is greater than or equal to a preset voltage threshold, and the second bias voltage is used to control the switch module to block the output of the first bias voltage to the boost circuit when the first bias voltage is less than the preset voltage threshold. This solution can realize the boost cold start circuit while improving the charge pump's ability to transmit charge, which is conducive to integration and simple in design.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of circuit technology, and in particular to a boost cold start circuit. Background Art

[0002] At present, boost circuits are often used for energy collection in micro-environments. However, if the voltage input from the DC energy source (such as thermoelectric energy) to the boost circuit is too low, the boost circuit cannot be started. Taking the thermoelectric power generation chip as an example, when the temperature difference is only 1-2°C, the thermoelectric voltage generated by the thermoelectric power generation chip is <200mV. Obviously, the thermoelectric voltage generated by the thermoelectric power generation chip cannot adjust the conduction state of the high-power switch in the boost to make the boost work. Therefore, without relying on an additional voltage source (for example, a battery), the boost circuit cannot be started.

[0003] In view of the above problems, a cold start scheme can be used to start the boost circuit without relying on an additional voltage source. Among them, the cold start scheme includes an inductive scheme and a capacitive scheme. In the inductive scheme, a large inductor other than the inductor included in the boost circuit is used to quickly accumulate energy, so that the boost circuit is started. For example, a transformer is used to achieve positive feedback, and an LC oscillator generates an oscillation signal for boosting. Although the inductive scheme reduces the difficulty of cold starting the boost circuit, the use of a large inductor is not conducive to integrating the cold start circuit on a chip. The capacitive scheme generally uses an improved Dickson charge pump that replaces the diode of the charge pump with a gate-controlled MOS tube to raise the input voltage through a gate boost circuit, thereby improving the charge transfer capacity of the charge pump. However, the improved Dickson charge pump requires a two-phase non-overlapping clock, and the two-phase non-overlapping clock does not overlap with the charge pump clock, which makes the cold start circuit complicated. Summary of the invention

[0004] The embodiment of the present invention provides a boost cold start circuit, so as to realize that the boost cold start circuit improves the charge transmission capability of a charge pump while being easy to integrate and having a simple design.

[0005] An embodiment of the present invention provides a boost cold start circuit, which includes an oscillator, a self-biased charge pump, a monitoring module, an energy storage module, and a switch module;

[0006] The oscillator is connected to the clock end of the self-bias charge pump, the first output end of the self-bias charge pump is connected to the energy storage module, the first end of the switch module and the monitoring module, the second output end of the self-bias charge pump is connected to the second end of the switch module, the monitoring module is connected to the third end of the switch module, and the fourth end of the switch module is connected to the boost circuit;

[0007] The oscillator is used to generate a clock signal, and the self-biased charge pump is used to input a signal to its signal input terminal according to the clock signal. Initial low voltage The boosting is performed to generate a first bias voltage and a second bias voltage, the energy storage module is used to store the first bias voltage, the monitoring module is used to control the switch module to output the first bias voltage to the boost circuit when the first bias voltage is greater than or equal to a preset voltage threshold, and the second bias voltage is used to control the switch module to block the output of the first bias voltage to the boost circuit when the first bias voltage is less than the preset voltage threshold.

[0008] Optionally, the self-biased charge pump includes a first branch charge pump group, a second branch charge pump group, a third branch charge pump group, a fourth branch charge pump group, a first branch rectifier unit, a second branch rectifier unit, a third branch rectifier unit and a fourth branch rectifier unit;

[0009] The first end of the first branch charge pump group and the first end of the second branch charge pump group are connected and serve as the signal input end of the self-bias charge pump;

[0010] The second end of the first branch charge pump group and the first end of the third branch charge pump group are both connected to the first end of the first branch rectifier unit, the second end of the second branch charge pump group and the first end of the fourth branch charge pump group are both connected to the first end of the second branch rectifier unit, the second end of the first branch rectifier unit and the second end of the second branch rectifier unit are connected and serve as the first output end of the self-biased charge pump;

[0011] The second end of the third branch charge pump group is connected to the first end of the third branch rectifier unit, the second end of the fourth branch charge pump group is connected to the first end of the fourth branch rectifier unit, the second end of the third branch rectifier unit is connected to the second end of the fourth branch rectifier unit, and serves as the second output end of the self-biased charge pump;

[0012] The clock end of the first branch charge pump group, the clock end of the second branch charge pump group, the clock end of the third branch charge pump group and the clock end of the fourth branch charge pump group all serve as the clock end of the self-bias charge pump.

[0013] Optionally, the oscillator comprises a first clock signal output terminal and a second clock signal output terminal; the potential of the first clock signal outputted from the first clock signal output terminal is opposite to the potential of the clock signal outputted from the second clock signal output terminal;

[0014] The first branch charge pump group includes the first charge pump unit of the first level-the first charge pump unit of the 16th level and the first voltage sampling point of the first level-the first voltage sampling point of the 16th level; the second branch charge pump group includes the second charge pump unit of the first level-the second charge pump unit of the 16th level and the second voltage sampling point of the first level-the second voltage sampling point of the 16th level; the third branch charge pump group includes the first charge pump unit of the 17th level-the first charge pump unit of the 19th level and the first voltage sampling point of the 17th level-the first voltage sampling point of the 19th level; the fourth branch charge pump group includes the second charge pump unit of the 17th level-the second charge pump unit of the 19th level and the second voltage sampling point of the 17th level-the second voltage sampling point of the 19th level;

[0015] The clock signal input end of the odd-numbered first charge pump unit of the first branch charge pump group, the clock signal input end of the even-numbered second charge pump unit of the second branch charge pump group, the clock signal input end of the odd-numbered first charge pump unit of the third branch charge pump group, and the clock signal input end of the even-numbered second charge pump unit of the fourth branch charge pump group are all connected to the first clock signal output end of the oscillator, and the clock signal input end of the even-numbered first charge pump unit of the first branch charge pump group, the clock signal input end of the odd-numbered second charge pump unit of the second branch charge pump group, the clock signal input end of the even-numbered first charge pump unit of the third branch charge pump group, and the clock signal input end of the odd-numbered second charge pump unit of the fourth branch charge pump group are all connected to the second clock signal output end of the oscillator;

[0016] The first end of the first charge pump unit of the first stage is connected to the first end of the second charge pump unit of the first stage and serves as the first end of the first branch charge pump group;

[0017] The control end of the first charge pump unit of the first stage is connected to the control end of the second charge pump unit of the second stage, and the second end of the first charge pump unit of the first stage is connected to the first voltage sampling point of the first stage; the control end of the second charge pump unit of the first stage is connected to the control end of the first charge pump unit of the second stage, and the second end of the second charge pump unit of the first stage is connected to the second voltage sampling point of the first stage;

[0018] The first end of the second-stage first charge pump unit is connected to the first-stage first voltage sampling point, the first comparison end of the second-stage first charge pump unit is connected to the first clock signal output end of the oscillator, the logic input end of the second-stage first charge pump unit is connected to the first-stage second voltage sampling point, the second comparison end of the second-stage first charge pump unit is connected to the second-stage second voltage sampling point, and the second end of the second-stage first charge pump unit is connected to the second-stage first voltage sampling point;

[0019] The first end of the first charge pump unit of the N1th level is connected to the first voltage sampling point of the N1-1th level, the first comparison end of the first charge pump unit of the N1th level is connected to the second voltage sampling point of the N1-2th level, the logic input end of the first charge pump unit of the N1th level is connected to the second voltage sampling point of the N1-1th level, the second comparison end of the first charge pump unit of the N1th level is connected to the second voltage sampling point of the N1th level, and the second end of the first charge pump unit of the N1th level is connected to the first voltage sampling point of the N1th level; 3≤N1≤19 and N is a positive integer;

[0020] The first end of the second charge pump unit of the second stage is connected to the second voltage sampling point of the first stage, the first comparison end of the second charge pump unit of the second stage is connected to the second clock signal output end of the oscillator, the logic input end of the second charge pump unit of the second stage is connected to the first voltage sampling point of the first stage, the second comparison end of the second charge pump unit of the second stage is connected to the first voltage sampling point of the second stage, and the second end of the second charge pump unit of the second stage is connected to the second voltage sampling point of the second stage;

[0021] The first end of the second charge pump unit of the N2th level is connected to the second voltage sampling point of the N2-1th level, the first comparison end of the second charge pump unit of the N2th level is connected to the first voltage sampling point of the N2-2th level, the logic input end of the second charge pump unit of the N2th level is connected to the first voltage sampling point of the N2-1th level, the second comparison end of the second charge pump unit of the N2th level is connected to the first voltage sampling point of the N2th level, and the second end of the second charge pump unit of the N2th level is connected to the second voltage sampling point of the N2th level; 3≤N2≤19 and N is a positive integer;

[0022] The second end of the 16th-level first charge pump unit serves as the second end of the first branch charge pump group, and the second end of the 16th-level second charge pump unit serves as the second end of the second branch charge pump group; the second end of the 19th-level first charge pump unit serves as the second end of the third branch charge pump group, and the second end of the 19th-level second charge pump unit serves as the second end of the fourth branch charge pump group.

[0023] Optionally, the first stage first charge pump unit comprises a first branch zero-threshold N-type transistor and a first branch capacitor;

[0024] The first electrode of the first zero-threshold N-type transistor in the branch serves as the first end of the first-stage first charge pump unit, the first end of the first capacitor in the branch serves as the clock signal input end of the first-stage first charge pump unit, the second electrode of the first zero-threshold N-type transistor in the branch is connected to the second end of the first capacitor in the branch and serves as the second end of the first-stage first charge pump unit, and the control end of the first zero-threshold N-type transistor in the branch serves as the control end of the first-stage first charge pump unit;

[0025] The M1-th stage first charge pump unit comprises a branch M1-th zero-threshold N-type transistor, a branch M1-th capacitor, a branch M1-th N-type transistor and a branch M1-th P-type transistor; 2≤M1≤16 and M1 is a positive integer;

[0026] The first electrode of the branch M1 zero-threshold N-type transistor serves as the first end of the M1 first charge pump unit, the first end of the branch M1 capacitor serves as the clock signal input end of the M1 first charge pump unit, the second electrode of the branch M1 zero-threshold N-type transistor is connected to the second end of the branch M1 capacitor and serves as the second end of the M1 first charge pump unit, the first electrode of the branch M1 N-type transistor serves as the first comparison end of the M1 first charge pump unit, and the first end of the branch M1 N-type transistor serves as the clock signal input end of the M1 first charge pump unit. The second electrode of the body tube and the first electrode of the M1th P-type transistor in the branch are both connected to the control end of the M1th zero-threshold N-type transistor in the branch. The control end of the M1th zero-threshold N-type transistor in the branch serves as the control end of the M1th first charge pump unit. The control end of the M1th N-type transistor in the branch is connected to the control end of the M1th P-type transistor in the branch and serves as the logic input end of the M1th first charge pump unit. The second electrode of the M1th P-type transistor in the branch serves as the second comparison end of the M1th first charge pump unit.

[0027] Optionally, the first-stage second charge pump unit includes a second-branch first zero-threshold N-type transistor and a second-branch first capacitor;

[0028] The first electrode of the second-branch first zero-threshold N-type transistor serves as the first end of the first-stage second charge pump unit, the first end of the second-branch first capacitor serves as the clock signal input end of the first-stage second charge pump unit, the second electrode of the second-branch first zero-threshold N-type transistor is connected to the second end of the second-branch first capacitor and serves as the second end of the first-stage second charge pump unit, and the control end of the second-branch first zero-threshold N-type transistor serves as the control end of the first-stage second charge pump unit;

[0029] The M2-stage second charge pump unit comprises a second-branch M2-th zero-threshold N-type transistor, a second-branch M2-th capacitor, a second-branch M2-th N-type transistor and a second-branch M2-th P-type transistor; 2≤M2≤16 and M2 is a positive integer;

[0030] The first electrode of the second branch M2 zero-threshold N-type transistor serves as the first end of the M2 second charge pump unit, the first end of the second branch M2 capacitor serves as the clock signal input end of the M2 second charge pump unit, the second electrode of the second branch M2 zero-threshold N-type transistor is connected to the second end of the second branch M2 capacitor and serves as the second end of the M2 second charge pump unit, the first electrode of the second branch M2 N-type transistor serves as the first comparison end of the M2 second charge pump unit, and the second electrode of the second branch M2 N-type transistor serves as the clock signal input end of the M2 second charge pump unit. The second electrode of the tube and the first electrode of the M2th P-type transistor in the second branch are both connected to the control end of the M2th zero-threshold N-type transistor in the second branch, the control end of the M2th zero-threshold N-type transistor in the second branch serves as the control end of the M2th level second charge pump unit, the control end of the M2th N-type transistor in the second branch is connected to the control end of the M2th P-type transistor in the second branch and serves as the logic input end of the M2th level second charge pump unit, and the second electrode of the M2th P-type transistor in the second branch serves as the second comparison end of the M2th level second charge pump unit.

[0031] Optionally, the M3-th level first charge pump unit includes three branches of M3-th zero-threshold N-type transistors, three branches of M3-th capacitors, three branches of M3-th N-type transistors, and three branches of M3-th P-type transistors; 17≤M3≤19 and M3 is a positive integer;

[0032] The first electrode of the M3th zero-threshold N-type transistor of the three branches serves as the first end of the M3th first charge pump unit, the first end of the M3th capacitor of the three branches serves as the clock signal input end of the M3th first charge pump unit, the second electrode of the M3th zero-threshold N-type transistor of the three branches is connected to the second end of the M3th capacitor of the three branches and serves as the second end of the M3th first charge pump unit, the first electrode of the M3th N-type transistor of the three branches serves as the first comparison end of the M3th first charge pump unit, and the M3th N-type transistor of the three branches serves as the clock signal input end of the M3th first charge pump unit. The second electrode of the body tube and the first electrode of the M3th P-type transistor of the three branches are both connected to the control end of the M3th zero-threshold N-type transistor of the three branches. The control end of the M3th zero-threshold N-type transistor of the three branches serves as the control end of the M3th first charge pump unit. The control end of the M3th N-type transistor of the three branches is connected to the control end of the M3th P-type transistor of the three branches and serves as the logic input end of the M3th first charge pump unit. The second electrode of the M3th P-type transistor of the three branches serves as the second comparison end of the M3th first charge pump unit.

[0033] Optionally, the M4-th level second charge pump unit includes four-branch M4-th zero-threshold N-type transistors, four-branch M4-th capacitors, four-branch M4-th N-type transistors and four-branch M4-th P-type transistors; 17≤M4≤19 and M4 is a positive integer;

[0034] The first electrode of the M4th zero-threshold N-type transistor of the four branches serves as the first end of the M4th second charge pump unit, the first end of the M4th capacitor of the four branches serves as the clock signal input end of the M4th second charge pump unit, the second electrode of the M4th zero-threshold N-type transistor of the four branches is connected to the second end of the M4th capacitor of the four branches and serves as the second end of the M4th second charge pump unit, the first electrode of the M4th N-type transistor of the four branches serves as the first comparison end of the M4th second charge pump unit, and the first end of the M4th N-type transistor of the four branches serves as the clock signal input end of the M4th second charge pump unit. The second electrode of the body tube and the first electrode of the M4th P-type transistor of the four branches are both connected to the control end of the M4th zero-threshold N-type transistor of the four branches. The control end of the M4th zero-threshold N-type transistor of the four branches serves as the control end of the M4th second charge pump unit. The control end of the M4th N-type transistor of the four branches is connected to the control end of the M4th P-type transistor of the four branches and serves as the logic input end of the M4th second charge pump unit. The second electrode of the M4th P-type transistor of the four branches serves as the second comparison end of the M4th second charge pump unit.

[0035] Optionally, the first branch rectifying unit includes a first diode, the second branch rectifying unit includes a second diode, the third branch rectifying unit includes a third diode, and the fourth branch rectifying unit includes a fourth diode;

[0036] The first electrode of the first diode serves as the first end of the first branch rectifying unit, and the second electrode of the first diode serves as the second end of the first branch rectifying unit;

[0037] The first electrode of the second diode serves as the first end of the second branch rectifying unit, and the second electrode of the second diode serves as the second end of the second branch rectifying unit;

[0038] The first electrode of the third diode serves as the first end of the third branch rectifying unit, and the second electrode of the third diode serves as the second end of the third branch rectifying unit;

[0039] The first electrode of the fourth diode serves as the first end of the fourth branch rectifying unit, and the second electrode of the fourth diode serves as the second end of the fourth branch rectifying unit.

[0040] Optionally, the monitoring module includes a hysteresis voltage comparator, and the energy storage module includes an energy storage capacitor;

[0041] The first output end of the self-biased charge pump is connected to the first end of the energy storage capacitor, the first end of the switch module and the input end of the hysteresis voltage comparator, the output end of the hysteresis voltage comparator is connected to the third end of the switch module, and the second end of the energy storage capacitor is grounded.

[0042] Optionally, the switch module includes a P-type transistor and an N-type transistor;

[0043] The first output end of the self-biased charge pump is connected to the first end of the energy storage capacitor, the first electrode of the P-type transistor and the input end of the hysteresis voltage comparator, the second output end of the self-biased charge pump is connected to the control end of the P-type transistor and the first electrode of the N-type transistor, the output end of the hysteresis voltage comparator is connected to the control end of the N-type transistor, the second electrode of the N-type transistor is grounded, and the second electrode of the P-type transistor is connected to the boost circuit.

[0044] In the embodiment of the present invention, a self-biased charge pump is used to input a clock signal to a signal input terminal according to a clock signal generated by an oscillator. Initial low voltage The voltage is boosted to generate a first bias voltage and a second bias voltage, and the charge transfer capacity of the charge pump is improved with a simple design. Compared with the prior art, the inductor is set to accumulate energy to raise the initial low voltage of the input, which is easier to integrate. By setting the second bias voltage output by the self-biased charge pump to control the switch module to cut off the connection between the first output end of the self-biased charge pump and the startup boost circuit, the first bias voltage can be prevented from leaking to the boost circuit to ensure that the first bias voltage can quickly accumulate energy and rise to a voltage value that meets the startup boost circuit. By setting the monitoring module, the switch module can be controlled to output the first bias voltage to the boost circuit when the first bias voltage is greater than or equal to the preset voltage threshold. During the period when the switch module outputs the first bias voltage to the boost circuit, the energy storage module can maintain a stable first bias voltage output to the boost circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic diagram of the structure of a boost cold start circuit provided by an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of the structure of a self-biased charge pump provided by an embodiment of the present invention;

[0048] Figure 3 A schematic structural diagram of another boost cold start circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] Figure 1 A schematic diagram of a boost cold start circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the boost cold start circuit includes an oscillator 110, a self-biased charge pump 120, a monitoring module 130, an energy storage module 140 and a switch module 150;

[0052] The oscillator 110 is connected to the clock end of the self-biased charge pump 120, the first output end of the self-biased charge pump 120 is connected to the energy storage module 140, the first end of the switch module 150 and the monitoring module 130, the second output end of the self-biased charge pump 120 is connected to the second end of the switch module 150, the monitoring module 130 is connected to the third end of the switch module 150, and the fourth end of the switch module 150 is connected to the boost circuit 210;

[0053] The oscillator 110 is used to generate a clock signal, the self-biased charge pump 120 is used to boost the initial low voltage input to its signal input terminal according to the clock signal to generate a first bias voltage and a second bias voltage, the energy storage module 140 is used to store the first bias voltage, the monitoring module 130 is used to control the switch module 150 to output the first bias voltage to the boost circuit 210 when the first bias voltage is greater than or equal to a preset voltage threshold, and the second bias voltage is used to control the switch module 150 to block the output of the first bias voltage to the boost circuit 210 when the first bias voltage is less than the preset voltage threshold.

[0054] Specifically, the oscillator 110 can generate a square wave with a continuously changing voltage to provide a clock signal to the self-biased charge pump. The self-biased charge pump 120 can raise the voltage of the input small voltage (initial low voltage) through the charge pump according to the clock signal to output a first bias voltage and a second bias voltage. Among them, the second bias voltage is greater than the first bias voltage. The initial low voltage is a low voltage source equivalent to an energy source, and the voltage value of the initial low voltage is much smaller than the starting voltage value of the boost circuit 210. The monitoring module 130 can monitor the raising of the first bias voltage output by the self-biased charge pump 120, and when the first bias voltage is raised to a voltage value that meets the starting boost circuit 210, the control switch module 150 outputs the first bias voltage to the boost circuit 210. The second bias voltage can prevent the first bias voltage from leaking to the boost circuit 210 by controlling the switch module 150 during the period when the first bias voltage is raised, so as to ensure that the first bias voltage can quickly accumulate energy and raise it to a voltage value that meets the starting boost circuit 210. The switch module 150 can switch on or off the connection between the first output terminal of the self-biased charge pump 120 and the startup boost circuit 210 .

[0055] According to the above connection relationship, the working principle of the boost cold start circuit is explained: the oscillator 110 generates a clock signal and provides it to the self-bias charge pump 120. When the initial low voltage is input to the signal input end of the self-bias charge pump 120, the self-bias charge pump 120 boosts the initial low voltage input to its signal input end according to the clock signal to generate a first bias voltage and a second bias voltage. When the first bias voltage is less than a preset voltage threshold, the second bias voltage controls the switch module 150 to block the first bias voltage from being output to the boost circuit 210. The energy storage module 140 can store the first bias voltage, and when the first bias voltage is greater than or equal to the preset voltage threshold, the monitoring module 130 controls the switch module 150 to output the first bias voltage stored in the energy storage module 140 to the boost circuit 210.

[0056] In the embodiment of the present invention, the self-biased charge pump 120 is used to boost the initial low voltage input to its signal input terminal according to the clock signal generated by the oscillator 110 to generate the first bias voltage and the second bias voltage, so as to improve the charge transfer capacity of the charge pump with a simple design, and is more convenient for integration compared with the prior art in which the inductor is set to accumulate energy to raise the voltage of the initial low voltage input. By setting the second bias voltage output by the self-biased charge pump 120 to control the switch module 150 to cut off the connection between the first output terminal of the self-biased charge pump 120 and the startup boost circuit 210, the first bias voltage can be prevented from leaking to the boost circuit 210, so as to ensure that the first bias voltage can quickly accumulate energy and be raised to a voltage value that meets the startup boost circuit 210. By setting the monitoring module 130, the switch module 150 can be controlled to output the first bias voltage to the boost circuit 210 when the first bias voltage is greater than or equal to the preset voltage threshold. During the period when the switch module 150 outputs the first bias voltage to the boost circuit 210 , the energy storage module 140 can maintain a stable first bias voltage to output to the boost circuit 210 .

[0057] Based on the above embodiment, optionally, Figure 2 FIG. 1 is a schematic diagram of a structure of a self-biased charge pump 120 provided in an embodiment of the present invention. Figure 2 As shown, the self-biased charge pump 120 includes a first branch charge pump group 121, a second branch charge pump group 122, a third branch charge pump group 123, a fourth branch charge pump group 124, a first branch rectifier unit 125, a second branch rectifier unit 126, a third branch rectifier unit 127 and a fourth branch rectifier unit 128;

[0058] A first end of the first branch charge pump group 121 is connected to a first end of the second branch charge pump group 122 and serves as a signal input end of the self-bias charge pump 120;

[0059] The second end of the first branch charge pump group 121 and the first end of the third branch charge pump group 123 are both connected to the first end of the first branch rectifier unit 125, the second end of the second branch charge pump group 122 and the first end of the fourth branch charge pump group 124 are both connected to the first end of the second branch rectifier unit 126, the second end of the first branch rectifier unit 125 and the second end of the second branch rectifier unit 126 are connected, and serve as the first output end of the self-biased charge pump 120;

[0060] The second end of the third branch charge pump group 123 is connected to the first end of the third branch rectifier unit 127, the second end of the fourth branch charge pump group 124 is connected to the first end of the fourth branch rectifier unit 128, the second end of the third branch rectifier unit 127 is connected to the second end of the fourth branch rectifier unit 128, and serves as the second output end of the self-biased charge pump 120;

[0061] The clock ends of the first branch charge pump group 121 , the second branch charge pump group 122 , the third branch charge pump group 123 and the fourth branch charge pump group 124 all serve as the clock ends of the self-bias charge pump 120 .

[0062] Among them, the loop formed by the first branch charge pump group 121, the second branch charge pump group 122, the first branch rectifier unit 125 and the second branch rectifier unit 126 is used to generate a first bias voltage, and the loop formed by the third branch charge pump group 123, the fourth branch charge pump group 124, the third branch rectifier unit 127 and the fourth branch rectifier unit 128 is used to generate a second bias voltage.

[0063] Specifically, the oscillator 110 includes a first clock signal output terminal CK and a second clock signal output terminal CKB; the potential of the first clock signal outputted from the first clock signal output terminal CK is opposite to the potential of the clock signal outputted from the second clock signal output terminal CKB;

[0064] The first branch charge pump group 121 includes the first charge pump unit of the first stage to the first charge pump unit of the 16th stage and the first voltage sampling point A1 of the first stage to the first voltage sampling point A16 of the 16th stage; the second branch charge pump group 122 includes the second charge pump unit of the first stage to the second charge pump unit of the 16th stage and the second voltage sampling point B1 of the first stage to the second voltage sampling point B16 of the 16th stage; the third branch charge pump group 123 includes the first charge pump unit of the 17th stage to the first charge pump unit of the 19th stage and the first voltage sampling point A17 of the 17th stage to the first voltage sampling point A19 of the 19th stage; the fourth branch charge pump group 124 includes the second charge pump unit of the 17th stage to the second charge pump unit of the 19th stage and the second voltage sampling point B17 of the 17th stage to the second voltage sampling point B19 of the 19th stage;

[0065] Among them, the clock signal input end of the odd-numbered first charge pump unit of the first branch charge pump group 121, the clock signal input end of the even-numbered second charge pump unit of the second branch charge pump group 122, the clock signal input end of the odd-numbered first charge pump unit of the third branch charge pump group 123, and the clock signal input end of the even-numbered second charge pump unit of the fourth branch charge pump group 124 are all connected to the first clock signal output end CK of the oscillator 110, and the clock signal input end of the even-numbered first charge pump unit of the first branch charge pump group 121, the clock signal input end of the odd-numbered second charge pump unit of the second branch charge pump group 122, the clock signal input end of the even-numbered first charge pump unit of the third branch charge pump group 123, and the clock signal input end of the odd-numbered second charge pump unit of the fourth branch charge pump group 124 are all connected to the second clock signal output end CKB of the oscillator 110;

[0066] The first end of the first charge pump unit of the first stage is connected to the first end of the second charge pump unit of the first stage and serves as the first end of the first branch charge pump group 121;

[0067] The control end of the first charge pump unit of the first stage is connected to the control end of the second charge pump unit of the second stage, and the second end of the first charge pump unit of the first stage is connected to the first voltage sampling point A1 of the first stage; the control end of the second charge pump unit of the first stage is connected to the control end of the first charge pump unit of the second stage, and the second end of the second charge pump unit of the first stage is connected to the second voltage sampling point B1 of the first stage;

[0068] The first end of the first charge pump unit of the second stage is connected to the first voltage sampling point A1 of the first stage, the first comparison end of the first charge pump unit of the second stage is connected to the first clock signal output end CK of the oscillator 110, the logic input end of the first charge pump unit of the second stage is connected to the second voltage sampling point B1 of the first stage, the second comparison end of the first charge pump unit of the second stage is connected to the second voltage sampling point B2 of the second stage, and the second end of the first charge pump unit of the second stage is connected to the first voltage sampling point A2 of the second stage;

[0069] The first end of the first charge pump unit of the N1th stage is connected to the first voltage sampling point A N1-1 of the N1-1th stage, the first comparison end of the first charge pump unit of the N1th stage is connected to the second voltage sampling point B N1-2 of the N1-2th stage, the logic input end of the first charge pump unit of the N1th stage is connected to the second voltage sampling point B N1-1 of the N1-1th stage, the second comparison end of the first charge pump unit of the N1th stage is connected to the second voltage sampling point B N1 of the N1th stage, and the second end of the first charge pump unit of the N1th stage is connected to the first voltage sampling point A N1 of the N1th stage; 3≤N1≤19 and N is a positive integer;

[0070] The first end of the second charge pump unit of the second stage is connected to the second voltage sampling point B1 of the first stage, the first comparison end of the second charge pump unit of the second stage is connected to the second clock signal output end CKB of the oscillator 110, the logic input end of the second charge pump unit of the second stage is connected to the first voltage sampling point A1 of the first stage, the second comparison end of the second charge pump unit of the second stage is connected to the first voltage sampling point A2 of the second stage, and the second end of the second charge pump unit of the second stage is connected to the second voltage sampling point B2 of the second stage;

[0071] The first end of the second charge pump unit of the N2th stage is connected to the second voltage sampling point B N2-1 of the N2-1th stage, the first comparison end of the second charge pump unit of the N2th stage is connected to the first voltage sampling point AN2-2 of the N2-2th stage, the logic input end of the second charge pump unit of the N2th stage is connected to the first voltage sampling point AN2-1 of the N2-1th stage, the second comparison end of the second charge pump unit of the N2th stage is connected to the first voltage sampling point AN2 of the N2th stage, and the second end of the second charge pump unit of the N2th stage is connected to the second voltage sampling point B N2 of the N2th stage; 3≤N2≤19 and N is a positive integer;

[0072] The second end of the 16th-stage first charge pump unit serves as the second end of the first branch charge pump group 121, and the second end of the 16th-stage second charge pump unit serves as the second end of the second branch charge pump group 122; the second end of the 19th-stage first charge pump unit serves as the second end of the third branch charge pump group 123, and the second end of the 19th-stage second charge pump unit serves as the second end of the fourth branch charge pump group 124.

[0073] Specifically, the first stage first charge pump unit includes a branch first zero threshold N-type transistor T11 and a branch first capacitor C11;

[0074] The first electrode of the first zero-threshold N-type transistor T11 of a branch serves as the first end of the first-stage first charge pump unit, the first end of the first capacitor C11 of a branch serves as the clock signal input end of the first-stage first charge pump unit, the second electrode of the first zero-threshold N-type transistor T11 of a branch is connected to the second end of the first capacitor C11 of a branch and serves as the second end of the first-stage first charge pump unit, and the control end of the first zero-threshold N-type transistor T11 of a branch serves as the control end of the first-stage first charge pump unit;

[0075] The M1-th stage first charge pump unit comprises a branch M1-th zero-threshold N-type transistor T1M1, a branch M1-th capacitor C1M1, a branch M1-th N-type transistor Q1M1, and a branch M1-th P-type transistor G1M1; 2≤M1≤16 and M1 is a positive integer;

[0076] The first electrode of the branch M1 zero-threshold N-type transistor T1M1 serves as the first end of the M1 first charge pump unit, the first end of the branch M1 capacitor C1M1 serves as the clock signal input end of the M1 first charge pump unit, the second electrode of the branch M1 zero-threshold N-type transistor T1M1 is connected to the second end of the branch M1 capacitor C1M1 and serves as the second end of the M1 first charge pump unit, the first electrode of the branch M1 N-type transistor Q1M1 serves as the first comparison end of the M1 first charge pump unit, and the branch M1 N-type transistor Q1M1 serves as the clock signal input end of the M1 first charge pump unit. The second electrode of the branch M1P-type transistor G1M1 and the first electrode of the branch M1P-type transistor are both connected to the control end of the branch M1Zero-threshold N-type transistor T1M1, the control end of the branch M1Zero-threshold N-type transistor T1M1 serves as the control end of the M1-stage first charge pump unit, the control end of the branch M1N-type transistor Q1M1 and the control end of the branch M1P-type transistor G1M1 are connected and serve as the logic input end of the M1-stage first charge pump unit, and the second electrode of the branch M1P-type transistor G1M1 serves as the second comparison end of the M1-stage first charge pump unit.

[0077] The first-stage second charge pump unit comprises a second-branch first zero-threshold N-type transistor T21 and a second-branch first capacitor C21;

[0078] The first electrode of the second branch first zero threshold N-type transistor T21 serves as the first end of the first stage second charge pump unit, the first end of the second branch first capacitor C21 serves as the clock signal input end of the first stage second charge pump unit, the second electrode of the second branch first zero threshold N-type transistor T21 is connected to the second end of the second branch first capacitor C21 and serves as the second end of the first stage second charge pump unit, and the control end of the second branch first zero threshold N-type transistor T21 serves as the control end of the first stage second charge pump unit;

[0079] The M2-stage second charge pump unit comprises a second-branch M2-th zero-threshold N-type transistor T2M2, a second-branch M2-th capacitor C2M2, a second-branch M2-th N-type transistor Q2M2, and a second-branch M2-th P-type transistor G2M2; 2≤M2≤16 and M2 is a positive integer;

[0080] The first electrode of the second branch M2 zero threshold N-type transistor T2M2 is used as the first end of the M2 second charge pump unit, the first end of the second branch M2 capacitor C2M2 is used as the clock signal input end of the M2 second charge pump unit, the second electrode of the second branch M2 zero threshold N-type transistor T2M2 is connected to the second end of the second branch M2 capacitor C2M2 and serves as the second end of the M2 second charge pump unit, the first electrode of the second branch M2 N-type transistor Q2M2 is used as the first comparison end of the M2 second charge pump unit, and the second branch M2 N-type transistor Q2M2 is used as the clock signal input end of the M2 second charge pump unit. The second electrode of the second branch M2P-type transistor G2M2 and the first electrode of the second branch M2P-type transistor G2M2 are both connected to the control end of the second branch M2P-type transistor T2M2, the control end of the second branch M2P-type transistor T2M2 serves as the control end of the M2P-type transistor second charge pump unit, the control end of the second branch M2N-type transistor Q2M2 and the control end of the second branch M2P-type transistor G2M2 are connected and serve as the logic input end of the M2P-type transistor G2M2, and the second electrode of the second branch M2P-type transistor G2M2 serves as the second comparison end of the M2P-type transistor second charge pump unit.

[0081] The M3-th level first charge pump unit comprises three-branch M3-th zero-threshold N-type transistors T3M3, three-branch M3-th capacitors C3M3, three-branch M3-th N-type transistors Q3M3, and three-branch M3-th P-type transistors G3M3; 17≤M3≤19 and M3 is a positive integer;

[0082] The first electrode of the M3th zero-threshold N-type transistor T3M3 of the three branches serves as the first end of the M3th first charge pump unit, the first end of the M3th capacitor C3M3 of the three branches serves as the clock signal input end of the M3th first charge pump unit, the second electrode of the M3th zero-threshold N-type transistor T3M3 of the three branches is connected to the second end of the M3th capacitor C3M3 of the three branches and serves as the second end of the M3th first charge pump unit, the first electrode of the M3th N-type transistor Q3M3 of the three branches serves as the first comparison end of the M3th first charge pump unit, and the M3th N-type transistor Q3M3 of the three branches serves as the clock signal input end of the M3th first charge pump unit. The second electrode of the M3P-type transistor G3M3 of the three branches is connected to the control end of the M3th zero-threshold N-type transistor T3M3 of the three branches. The control end of the M3th zero-threshold N-type transistor T3M3 of the three branches serves as the control end of the M3th first charge pump unit. The control end of the M3N-type transistor Q3M3 of the three branches is connected to the control end of the M3P-type transistor G3M3 of the three branches and serves as the logic input end of the M3th first charge pump unit. The second electrode of the M3P-type transistor G3M3 of the three branches serves as the second comparison end of the M3th first charge pump unit.

[0083] The M4-th level second charge pump unit includes four-branch M4-th zero-threshold N-type transistors T4M4, four-branch M4-th capacitors C4M4, four-branch M4-th N-type transistors Q4M4, and four-branch M4-th P-type transistors G4M4; 17≤M4≤19 and M4 is a positive integer;

[0084] The first electrode of the M4th zero-threshold N-type transistor T4M4 of the four-branch serves as the first end of the M4th-stage second charge pump unit, the first end of the M4th capacitor C4M4 of the four-branch serves as the clock signal input end of the M4th-stage second charge pump unit, the second electrode of the M4th zero-threshold N-type transistor T4M4 of the four-branch is connected to the second end of the M4th capacitor C4M4 of the four-branch and serves as the second end of the M4th-stage second charge pump unit, the first electrode of the M4th N-type transistor Q4M4 of the four-branch serves as the first comparison end of the M4th-stage second charge pump unit, and the M4th N-type transistor Q4M4 of the four-branch serves as the clock signal input end of the M4th-stage second charge pump unit. The second electrode of the M4th P-type transistor G4M4 of the four branches is connected to the control end of the M4th zero-threshold N-type transistor T4M4 of the four branches. The control end of the M4th zero-threshold N-type transistor T4M4 of the four branches serves as the control end of the M4th second charge pump unit. The control end of the M4th N-type transistor Q4M4 of the four branches is connected to the control end of the M4th P-type transistor G4M4 of the four branches and serves as the logic input end of the M4th second charge pump unit. The second electrode of the M4th P-type transistor G4M4 of the four branches serves as the second comparison end of the M4th second charge pump unit.

[0085] Among them, the voltages of the odd-numbered first voltage sampling points (A1, A3, ... A17, A19) and the voltages of the even-numbered second voltage sampling points (B2, B4, ... B16, B18) are the same as the potential of the first clock signal output from the first clock signal output terminal CK of the oscillator 110, and the voltages of the even-numbered first voltage sampling points (A2, A4, ... A16, A18) and the voltages of the odd-numbered second voltage sampling points (B1, B3, ... B17, B19) are the same as the potential of the second clock signal output from the second clock signal output terminal CKB of the oscillator 110.

[0086] Taking the third-stage first charge pump unit as an example, the voltage outputted by the second-stage second voltage sampling point B2 is used as the control end logic gate input of the third branch N-type transistor Q13 and the third branch P-type transistor G13, the voltage outputted by the first-stage second voltage sampling point B1 is used as the first electrode input of the third branch N-type transistor Q13, and the voltage outputted by the third-stage second voltage sampling point B3 is used as the first electrode input of the third branch P-type transistor G13. When the voltage outputted by the second-stage second voltage sampling point B2 is a high voltage, the voltage outputted by the first-stage second voltage sampling point B1 is used as the gate voltage of the third branch zero-threshold N-type transistor T13, which can control the first electrode and the second electrode of the third branch zero-threshold N-type transistor T13 to be non-conductive; when the voltage outputted by the second-stage second voltage sampling point B2 is a low voltage, the voltage outputted by the third-stage second voltage sampling point B3 is used as the gate voltage of the third branch zero-threshold N-type transistor T13, which can control the first electrode and the second electrode of the third branch zero-threshold N-type transistor T13 to be conductive.

[0087] It should be noted that, since there is a load at the output end of the self-biased charge pump 120 , the voltage at the rear-stage voltage sampling point is not completely greater than the voltage at the front-stage voltage sampling point.

[0088] In addition, taking the first-stage first charge pump unit, the second-stage first charge pump unit and the third-stage first charge pump unit of the first branch charge pump group 121 as examples, the working principle of the self-biased charge pump 120 is briefly described: when the first clock signal is at a low potential and the second clock signal is at a high potential, the first-stage first voltage sampling point A1 and the second-stage second voltage sampling point B2 are at a low potential, and the second-stage first voltage sampling point A2 and the first-stage second voltage sampling point B1 are at a high potential; thus, the control ends of the second-branch N-type transistor Q22 and the second-branch P-type transistor G22 are at a low voltage, the second-branch P-type transistor G22 is turned on, and the potential of the control end of the second-branch zero-threshold N-type transistor T22 is at a high potential. The control end of the first zero-threshold N-type transistor T11 in one branch is connected to the control end of the second zero-threshold N-type transistor T22 in the second branch. Obviously, the control end of the first zero-threshold N-type transistor T11 in one branch is at a high potential, so that the first zero-threshold N-type transistor T11 in one branch is turned on, so that the potential of the first voltage sampling point A1 of the first stage is raised to the voltage of the initial low voltage VIN.

[0089] When the first clock signal jumps to a high potential and the second clock signal jumps to a low potential, the first voltage sampling point A1 of the first level and the second voltage sampling point B2 of the second level are high potentials, and the first voltage sampling point A2 of the second level and the second voltage sampling point B1 of the first level are low potentials; therefore, the control end of the second N-type transistor Q22 of the second branch and the second P-type transistor G22 of the second branch are high voltages, the second N-type transistor Q22 of the second branch is turned on, and the potential of the control end of the second zero-threshold N-type transistor T22 of the second branch is low potential. The control end of the first zero-threshold N-type transistor T11 of the first branch is connected to the control end of the second zero-threshold N-type transistor T22 of the second branch. Obviously, the control end of the first zero-threshold N-type transistor T11 of the first branch is low potential, so that the first zero-threshold N-type transistor T11 of the first branch is turned off. Under the action of the self-coupling of the capacitor, the potential of the first voltage sampling point A1 of the first level is raised to the sum of the voltage of the initial low voltage VIN and the high voltage of the clock signal. The control terminals of the second N-type transistor Q12 of a branch and the second P-type transistor G12 of a branch are at a low voltage, and the second P-type transistor G12 of a branch is turned on, so that the control terminal of the second zero-threshold N-type transistor T12 of a branch is at a high voltage, and the second zero-threshold N-type transistor T12 of a branch is turned on, so that the potential of the second-level first voltage sampling point A2 is raised to the sum of the initial low voltage VIN voltage and the high voltage of the clock signal. The control terminals of the third N-type transistor Q13 of a branch and the third P-type transistor G13 of a branch are at a high voltage, and the third N-type transistor Q13 of a branch is turned on, so that the control terminal of the third zero-threshold N-type transistor T13 of a branch is at a low voltage, and the third zero-threshold N-type transistor T13 of a branch is turned off;

[0090] When the first clock signal jumps to a low potential and the second clock signal jumps to a high potential, the first voltage sampling point A1 of the first level and the second voltage sampling point B2 of the second level are low potentials, and the first voltage sampling point A2 of the second level and the second voltage sampling point B1 of the first level are high potentials; therefore, the control terminals of the second N-type transistor Q22 of the second branch and the second P-type transistor G22 of the second branch are low voltages, and the second P-type transistor G22 of the second branch makes the potential of the control terminal of the second zero-threshold N-type transistor T22 of the second branch high potential. The control terminal of the first zero-threshold N-type transistor T11 of the first branch is connected to the control terminal of the second zero-threshold N-type transistor T22 of the second branch. Obviously, the control terminal of the first zero-threshold N-type transistor T11 of the first branch is high potential, so that the first zero-threshold N-type transistor T11 of the first branch is turned on, and the potential of the first voltage sampling point A1 of the first level is the voltage of the initial low voltage VIN. The control terminals of the second N-type transistor Q12 of a branch and the second P-type transistor G12 of a branch are high voltages, the second N-type transistor Q12 of a branch is turned on, so that the control terminal of the second zero-threshold N-type transistor T12 of a branch is low voltage, the second zero-threshold N-type transistor T12 of a branch is turned off, and the potential of the second-level first voltage sampling point A2 is raised to the sum of the initial low voltage VIN voltage and the high voltage of the clock signal twice under the action of the self-coupling of the capacitor. The control terminals of the third N-type transistor Q13 of a branch and the third P-type transistor G13 of a branch are low voltages, the third P-type transistor G13 of a branch is turned on, so that the control terminal of the third zero-threshold N-type transistor T13 of a branch is high voltage, the third zero-threshold N-type transistor T13 of a branch is turned on, so that the potential of the second-level first voltage sampling point A2 is the sum of the initial low voltage VIN voltage and the high voltage of the clock signal twice.

[0091] Therefore, according to the above process, the self-biased charge pump 120 can boost the initial low voltage input to its signal input terminal according to the clock signal to generate the first bias voltage and the second bias voltage, so as to enhance the charge transfer capability of the charge pump.

[0092] Based on the above embodiment, optionally, continue to refer to Figure 2 , the first branch rectifier unit 125 includes a first diode D1, the second branch rectifier unit 126 includes a second diode D2, the third branch rectifier unit 127 includes a third diode D3, and the fourth branch rectifier unit 128 includes a fourth diode D4;

[0093] The first electrode of the first diode D1 serves as the first end of the first branch rectifying unit 125, and the second electrode of the first diode D1 serves as the second end of the first branch rectifying unit 125;

[0094] The first electrode of the second diode D2 serves as the first end of the second branch rectifying unit 126, and the second electrode of the second diode D2 serves as the second end of the second branch rectifying unit 126;

[0095] The first electrode of the third diode D3 serves as the first end of the third branch rectifying unit 127, and the second electrode of the third diode D3 serves as the second end of the third branch rectifying unit 127;

[0096] The first electrode of the fourth diode D4 serves as the first end of the fourth branch rectifying unit 128 , and the second electrode of the fourth diode D4 serves as the second end of the fourth branch rectifying unit 128 .

[0097] Among them, the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 can rectify the electric energy transmitted by the previous stage circuit; the first diode D1 is turned on to output the first bias voltage when the voltage transmitted by the previous stage circuit is higher than the threshold of the first diode D1, and the second diode D2 is turned on to output the first bias voltage when the voltage transmitted by the previous stage circuit is higher than the threshold of the second diode D2; the third diode D3 is turned on to output the second bias voltage when the voltage transmitted by the previous stage circuit is higher than the threshold of the third diode D3, and the fourth diode D4 is turned on to output the second bias voltage when the voltage transmitted by the previous stage circuit is higher than the threshold of the fourth diode D4.

[0098] Based on the above embodiment, optionally, Figure 3 A schematic diagram of another boost cold start circuit provided by an embodiment of the present invention. Figure 3 As shown, the monitoring module 130 includes a hysteresis voltage comparator 131, and the energy storage module 140 includes an energy storage capacitor C;

[0099] The first output end of the self-biased charge pump 120 is connected to the first end of the energy storage capacitor C, the first end of the switch module 150 and the input end of the hysteresis voltage comparator 131, the output end of the hysteresis voltage comparator 131 is connected to the third end of the switch module 150, and the second end of the energy storage capacitor C is grounded.

[0100] The energy storage module 140 can store a first bias voltage, and the hysteresis voltage comparator 131 controls the switch module 150 to output the first bias voltage stored in the energy storage capacitor C to the boost circuit 210 when the first bias voltage is greater than or equal to a preset voltage threshold.

[0101] Based on the above embodiment, optionally, continue to refer to Figure 3 , the switch module 150 includes a P-type transistor P1 and an N-type transistor Q1;

[0102] The first output end of the self-biased charge pump 120 is connected to the first end of the energy storage capacitor C, the first electrode of the P-type transistor P1 and the input end of the hysteresis voltage comparator 131, the second output end of the self-biased charge pump 120 is connected to the control end of the P-type transistor P1 and the first electrode of the N-type transistor Q1, the output end of the hysteresis voltage comparator 131 is connected to the control end of the N-type transistor Q1, the second electrode of the N-type transistor Q1 is grounded, and the second electrode of the P-type transistor P1 is connected to the boost circuit 210.

[0103] The second bias voltage is used to control the P-type transistor P1 to turn off when the first bias voltage is less than the preset voltage threshold, so as to block the first bias voltage from being output to the boost circuit 210. The hysteresis voltage comparator 131 can control the P-type transistor P1 to turn on by controlling the N-type transistor Q1 to turn on when the first bias voltage is greater than or equal to the preset voltage threshold, so that the first bias voltage stored in the energy storage capacitor C is output to the boost circuit 210.

[0104] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0105] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A boost cold start circuit, characterized in that: Including oscillator, self-biased charge pump, monitoring module, energy storage module and switch module; The oscillator is connected to the clock end of the self-bias charge pump, the first output end of the self-bias charge pump is connected to the energy storage module, the first end of the switch module and the monitoring module, the second output end of the self-bias charge pump is connected to the second end of the switch module, the monitoring module is connected to the third end of the switch module, and the fourth end of the switch module is connected to the boost circuit; The oscillator is used to generate a clock signal, the self-biased charge pump is used to boost the initial low voltage input to its signal input terminal according to the clock signal to generate a first bias voltage and a second bias voltage, the energy storage module is used to store the first bias voltage, the monitoring module is used to control the switch module to output the first bias voltage to the boost circuit when the first bias voltage is greater than or equal to a preset voltage threshold, and the second bias voltage is used to control the switch module to block the output of the first bias voltage to the boost circuit when the first bias voltage is less than the preset voltage threshold.

2. The boost cold start circuit according to claim 1, characterized in that: The self-biased charge pump comprises a first branch charge pump group, a second branch charge pump group, a third branch charge pump group, a fourth branch charge pump group, a first branch rectifier unit, a second branch rectifier unit, a third branch rectifier unit and a fourth branch rectifier unit; The first end of the first branch charge pump group and the first end of the second branch charge pump group are connected and serve as the signal input end of the self-bias charge pump; The second end of the first branch charge pump group and the first end of the third branch charge pump group are both connected to the first end of the first branch rectifier unit, the second end of the second branch charge pump group and the first end of the fourth branch charge pump group are both connected to the first end of the second branch rectifier unit, the second end of the first branch rectifier unit and the second end of the second branch rectifier unit are connected and serve as the first output end of the self-biased charge pump; The second end of the third branch charge pump group is connected to the first end of the third branch rectifier unit, the second end of the fourth branch charge pump group is connected to the first end of the fourth branch rectifier unit, the second end of the third branch rectifier unit is connected to the second end of the fourth branch rectifier unit, and serves as the second output end of the self-biased charge pump; The clock end of the first branch charge pump group, the clock end of the second branch charge pump group, the clock end of the third branch charge pump group and the clock end of the fourth branch charge pump group all serve as the clock end of the self-bias charge pump.

3. The boost cold start circuit according to claim 2, characterized in that: The oscillator comprises a first clock signal output terminal and a second clock signal output terminal; the potential of the first clock signal outputted from the first clock signal output terminal is opposite to the potential of the clock signal outputted from the second clock signal output terminal; The first branch charge pump group includes the first charge pump unit of the first level-the first charge pump unit of the 16th level and the first voltage sampling point of the first level-the first voltage sampling point of the 16th level; the second branch charge pump group includes the second charge pump unit of the first level-the second charge pump unit of the 16th level and the second voltage sampling point of the first level-the second voltage sampling point of the 16th level; the third branch charge pump group includes the first charge pump unit of the 17th level-the first charge pump unit of the 19th level and the first voltage sampling point of the 17th level-the first voltage sampling point of the 19th level; the fourth branch charge pump group includes the second charge pump unit of the 17th level-the second charge pump unit of the 19th level and the second voltage sampling point of the 17th level-the second voltage sampling point of the 19th level; The clock signal input end of the odd-numbered first charge pump unit of the first branch charge pump group, the clock signal input end of the even-numbered second charge pump unit of the second branch charge pump group, the clock signal input end of the odd-numbered first charge pump unit of the third branch charge pump group, and the clock signal input end of the even-numbered second charge pump unit of the fourth branch charge pump group are all connected to the first clock signal output end of the oscillator, and the clock signal input end of the even-numbered first charge pump unit of the first branch charge pump group, the clock signal input end of the odd-numbered second charge pump unit of the second branch charge pump group, the clock signal input end of the even-numbered first charge pump unit of the third branch charge pump group, and the clock signal input end of the odd-numbered second charge pump unit of the fourth branch charge pump group are all connected to the second clock signal output end of the oscillator; The first end of the first charge pump unit of the first stage is connected to the first end of the second charge pump unit of the first stage and serves as the first end of the first branch charge pump group; The control end of the first charge pump unit of the first stage is connected to the control end of the second charge pump unit of the second stage, and the second end of the first charge pump unit of the first stage is connected to the first voltage sampling point of the first stage; the control end of the second charge pump unit of the first stage is connected to the control end of the first charge pump unit of the second stage, and the second end of the second charge pump unit of the first stage is connected to the second voltage sampling point of the first stage; The first end of the second-stage first charge pump unit is connected to the first-stage first voltage sampling point, the first comparison end of the second-stage first charge pump unit is connected to the first clock signal output end of the oscillator, the logic input end of the second-stage first charge pump unit is connected to the first-stage second voltage sampling point, the second comparison end of the second-stage first charge pump unit is connected to the second-stage second voltage sampling point, and the second end of the second-stage first charge pump unit is connected to the second-stage first voltage sampling point; The first end of the first charge pump unit of the N1th level is connected to the first voltage sampling point of the N1-1th level, the first comparison end of the first charge pump unit of the N1th level is connected to the second voltage sampling point of the N1-2th level, the logic input end of the first charge pump unit of the N1th level is connected to the second voltage sampling point of the N1-1th level, the second comparison end of the first charge pump unit of the N1th level is connected to the second voltage sampling point of the N1th level, and the second end of the first charge pump unit of the N1th level is connected to the first voltage sampling point of the N1th level; 3≤N1≤19 and N is a positive integer; The first end of the second charge pump unit of the second stage is connected to the second voltage sampling point of the first stage, the first comparison end of the second charge pump unit of the second stage is connected to the second clock signal output end of the oscillator, the logic input end of the second charge pump unit of the second stage is connected to the first voltage sampling point of the first stage, the second comparison end of the second charge pump unit of the second stage is connected to the first voltage sampling point of the second stage, and the second end of the second charge pump unit of the second stage is connected to the second voltage sampling point of the second stage; The first end of the second charge pump unit of the N2th level is connected to the second voltage sampling point of the N2-1th level, the first comparison end of the second charge pump unit of the N2th level is connected to the first voltage sampling point of the N2-2th level, the logic input end of the second charge pump unit of the N2th level is connected to the first voltage sampling point of the N2-1th level, the second comparison end of the second charge pump unit of the N2th level is connected to the first voltage sampling point of the N2th level, and the second end of the second charge pump unit of the N2th level is connected to the second voltage sampling point of the N2th level; 3≤N2≤19 and N is a positive integer; The second end of the 16th-level first charge pump unit serves as the second end of the first branch charge pump group, and the second end of the 16th-level second charge pump unit serves as the second end of the second branch charge pump group; the second end of the 19th-level first charge pump unit serves as the second end of the third branch charge pump group, and the second end of the 19th-level second charge pump unit serves as the second end of the fourth branch charge pump group.

4. The boost cold start circuit according to claim 3, characterized in that: The first stage first charge pump unit comprises a first branch zero threshold N-type transistor and a first branch capacitor; The first electrode of the first zero-threshold N-type transistor in the branch serves as the first end of the first-stage first charge pump unit, the first end of the first capacitor in the branch serves as the clock signal input end of the first-stage first charge pump unit, the second electrode of the first zero-threshold N-type transistor in the branch is connected to the second end of the first capacitor in the branch and serves as the second end of the first-stage first charge pump unit, and the control end of the first zero-threshold N-type transistor in the branch serves as the control end of the first-stage first charge pump unit; The M1-th stage first charge pump unit comprises a branch M1-th zero-threshold N-type transistor, a branch M1-th capacitor, a branch M1-th N-type transistor and a branch M1-th P-type transistor; 2≤M1≤16 and M1 is a positive integer; The first electrode of the branch M1 zero-threshold N-type transistor serves as the first end of the M1 first charge pump unit, the first end of the branch M1 capacitor serves as the clock signal input end of the M1 first charge pump unit, the second electrode of the branch M1 zero-threshold N-type transistor is connected to the second end of the branch M1 capacitor and serves as the second end of the M1 first charge pump unit, the first electrode of the branch M1 N-type transistor serves as the first comparison end of the M1 first charge pump unit, and the first end of the branch M1 N-type transistor serves as the clock signal input end of the M1 first charge pump unit. The second electrode of the body tube and the first electrode of the M1th P-type transistor in the branch are both connected to the control end of the M1th zero-threshold N-type transistor in the branch. The control end of the M1th zero-threshold N-type transistor in the branch serves as the control end of the M1th first charge pump unit. The control end of the M1th N-type transistor in the branch is connected to the control end of the M1th P-type transistor in the branch and serves as the logic input end of the M1th first charge pump unit. The second electrode of the M1th P-type transistor in the branch serves as the second comparison end of the M1th first charge pump unit.

5. The boost cold start circuit according to claim 3, characterized in that: The first-stage second charge pump unit comprises a second-branch first zero-threshold N-type transistor and a second-branch first capacitor; The first electrode of the second-branch first zero-threshold N-type transistor serves as the first end of the first-stage second charge pump unit, the first end of the second-branch first capacitor serves as the clock signal input end of the first-stage second charge pump unit, the second electrode of the second-branch first zero-threshold N-type transistor is connected to the second end of the second-branch first capacitor and serves as the second end of the first-stage second charge pump unit, and the control end of the second-branch first zero-threshold N-type transistor serves as the control end of the first-stage second charge pump unit; The M2-stage second charge pump unit comprises a second-branch M2-th zero-threshold N-type transistor, a second-branch M2-th capacitor, a second-branch M2-th N-type transistor and a second-branch M2-th P-type transistor; 2≤M2≤16 and M2 is a positive integer; The first electrode of the second branch M2 zero-threshold N-type transistor serves as the first end of the M2 second charge pump unit, the first end of the second branch M2 capacitor serves as the clock signal input end of the M2 second charge pump unit, the second electrode of the second branch M2 zero-threshold N-type transistor is connected to the second end of the second branch M2 capacitor and serves as the second end of the M2 second charge pump unit, the first electrode of the second branch M2 N-type transistor serves as the first comparison end of the M2 second charge pump unit, and the second electrode of the second branch M2 N-type transistor serves as the clock signal input end of the M2 second charge pump unit. The second electrode of the tube and the first electrode of the M2th P-type transistor in the second branch are both connected to the control end of the M2th zero-threshold N-type transistor in the second branch, the control end of the M2th zero-threshold N-type transistor in the second branch serves as the control end of the M2th level second charge pump unit, the control end of the M2th N-type transistor in the second branch is connected to the control end of the M2th P-type transistor in the second branch and serves as the logic input end of the M2th level second charge pump unit, and the second electrode of the M2th P-type transistor in the second branch serves as the second comparison end of the M2th level second charge pump unit.

6. The boost cold start circuit according to claim 3, characterized in that: The M3-th level first charge pump unit comprises three branches of M3-th zero-threshold N-type transistors, three branches of M3-th capacitors, three branches of M3-th N-type transistors and three branches of M3-th P-type transistors; 17≤M3≤19 and M3 is a positive integer; The first electrode of the M3th zero-threshold N-type transistor of the three branches serves as the first end of the M3th first charge pump unit, the first end of the M3th capacitor of the three branches serves as the clock signal input end of the M3th first charge pump unit, the second electrode of the M3th zero-threshold N-type transistor of the three branches is connected to the second end of the M3th capacitor of the three branches and serves as the second end of the M3th first charge pump unit, the first electrode of the M3th N-type transistor of the three branches serves as the first comparison end of the M3th first charge pump unit, and the M3th N-type transistor of the three branches serves as the clock signal input end of the M3th first charge pump unit. The second electrode of the body tube and the first electrode of the M3th P-type transistor of the three branches are both connected to the control end of the M3th zero-threshold N-type transistor of the three branches. The control end of the M3th zero-threshold N-type transistor of the three branches serves as the control end of the M3th first charge pump unit. The control end of the M3th N-type transistor of the three branches is connected to the control end of the M3th P-type transistor of the three branches and serves as the logic input end of the M3th first charge pump unit. The second electrode of the M3th P-type transistor of the three branches serves as the second comparison end of the M3th first charge pump unit.

7. The boost cold start circuit according to claim 3, characterized in that: The M4-th level second charge pump unit includes four-branch M4-th zero-threshold N-type transistors, four-branch M4-th capacitors, four-branch M4-th N-type transistors and four-branch M4-th P-type transistors; 17≤M4≤19 and M4 is a positive integer; The first electrode of the M4th zero-threshold N-type transistor of the four branches serves as the first end of the M4th second charge pump unit, the first end of the M4th capacitor of the four branches serves as the clock signal input end of the M4th second charge pump unit, the second electrode of the M4th zero-threshold N-type transistor of the four branches is connected to the second end of the M4th capacitor of the four branches and serves as the second end of the M4th second charge pump unit, the first electrode of the M4th N-type transistor of the four branches serves as the first comparison end of the M4th second charge pump unit, and the first end of the M4th N-type transistor of the four branches serves as the clock signal input end of the M4th second charge pump unit. The second electrode of the body tube and the first electrode of the M4th P-type transistor of the four branches are both connected to the control end of the M4th zero-threshold N-type transistor of the four branches. The control end of the M4th zero-threshold N-type transistor of the four branches serves as the control end of the M4th second charge pump unit. The control end of the M4th N-type transistor of the four branches is connected to the control end of the M4th P-type transistor of the four branches and serves as the logic input end of the M4th second charge pump unit. The second electrode of the M4th P-type transistor of the four branches serves as the second comparison end of the M4th second charge pump unit.

8. The boost cold start circuit according to claim 2, characterized in that: The first branch rectifying unit includes a first diode, the second branch rectifying unit includes a second diode, the third branch rectifying unit includes a third diode, and the fourth branch rectifying unit includes a fourth diode; The first electrode of the first diode serves as the first end of the first branch rectifying unit, and the second electrode of the first diode serves as the second end of the first branch rectifying unit; The first electrode of the second diode serves as the first end of the second branch rectifying unit, and the second electrode of the second diode serves as the second end of the second branch rectifying unit; The first electrode of the third diode serves as the first end of the third branch rectifying unit, and the second electrode of the third diode serves as the second end of the third branch rectifying unit; The first electrode of the fourth diode serves as the first end of the fourth branch rectifying unit, and the second electrode of the fourth diode serves as the second end of the fourth branch rectifying unit.

9. The boost cold start circuit according to claim 1, characterized in that: The monitoring module includes a hysteresis voltage comparator, and the energy storage module includes an energy storage capacitor; The first output end of the self-biased charge pump is connected to the first end of the energy storage capacitor, the first end of the switch module and the input end of the hysteresis voltage comparator, the output end of the hysteresis voltage comparator is connected to the third end of the switch module, and the second end of the energy storage capacitor is grounded.

10. The boost cold start circuit according to claim 9, characterized in that: The switch module includes a P-type transistor and an N-type transistor; The first output end of the self-biased charge pump is connected to the first end of the energy storage capacitor, the first electrode of the P-type transistor and the input end of the hysteresis voltage comparator, the second output end of the self-biased charge pump is connected to the control end of the P-type transistor and the first electrode of the N-type transistor, the output end of the hysteresis voltage comparator is connected to the control end of the N-type transistor, the second electrode of the N-type transistor is grounded, and the second electrode of the P-type transistor is connected to the boost circuit.

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