On-time sampling circuit, driving signal generating circuit and flyback conversion circuit

Abstract

The invention relates to the technical field of switching power supplies, in particular to a turn-on time sampling circuit, a driving signal generation circuit and a flyback conversion circuit. The turn-on time sampling circuit comprises two voltage sampling circuits, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator. According to the principle of volt-second balance between a primary side and a secondary side of a transformer, two paths of charging currents are respectively controlled to charge capacitors according to sampled voltage values, when the voltages on the two capacitors are the same, a first marking signal is output, the first marking signal can represent blanking time of a synchronous rectification transistor in a current period, and the first marking signal can represent blanking time of the synchronous rectification transistor in the current period. The secondary controller controls the synchronous rectification transistor to be kept in an on state in the blanking time period according to the first marking signal, so that the condition that the synchronous rectification transistor is turned off by mistake due to the fact that the drain-source voltage of the synchronous rectification transistor is greater than zero when the two discharge branches carry out commutation is avoided; and the working stability of the multi-path output flyback conversion circuit is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a conduction time sampling circuit, a drive signal generating circuit and a flyback conversion circuit. Background Art

[0002] With the development of electronic technology, various types of electronic devices emerge in an endless stream. Different types of electronic devices may have different charging interface types. In order to meet the charging needs of electronic devices with different interface types, the power adapter can usually be implemented using a dual-path flyback conversion circuit. The dual-path flyback conversion circuit is provided with two different charging interfaces, and each charging interface corresponds to a discharge branch, so that electronic devices with different charging interfaces can be charged at the same time.

[0003] In the related art, in order to rectify the discharge voltage outputted from each charging branch, a synchronous rectifier transistor with a low conduction voltage drop is usually provided in the secondary winding loop to rectify the discharge voltage. Usually, the synchronous rectifier transistor can be implemented by a MOS tube with a low conduction voltage drop. Then, in the actual operation of the dual-path flyback conversion circuit, when the two discharge branches are switched on, that is, when the two discharge branches are commutated, the current of the synchronous rectifier transistor will drop. In severe cases, the drain-source voltage of the synchronous rectifier transistor will be greater than zero, so that the synchronous rectifier transistor is mistakenly turned off, thereby causing the dual-path flyback conversion circuit to have an operating error. Summary of the invention

[0004] The present application provides a conduction time sampling circuit, a drive signal generating circuit and a flyback conversion circuit, in order to solve the technical problem that in a dual-path flyback conversion circuit in the related art, a synchronous rectification transistor is prone to erroneous shutdown when commutating between two discharge branches.

[0005] In a first aspect, the present application provides a conduction time sampling circuit, which is used in a multi-channel output flyback conversion circuit, wherein the multi-channel output flyback conversion circuit includes a transformer, a synchronous rectification transistor, a secondary controller, and at least two discharge branches; a first end of the secondary winding of the transformer is connected to an input end of the discharge branch, a second end of the secondary winding is connected to a first electrode of the synchronous rectification transistor, a second electrode of the synchronous rectification transistor is grounded, and a control electrode of the synchronous rectification transistor is connected to the secondary controller;

[0006] The on-time sampling circuit comprises a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, wherein the capacitance values ​​of the first capacitor and the second capacitor are the same;

[0007] The first voltage sampling circuit is used to sample a first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current according to the first voltage value to charge the first capacitor; the second voltage sampling circuit is used to sample a second voltage value on the first electrode of the synchronous rectifier transistor, and the second current source is used to output a corresponding current according to the second voltage value to charge the second capacitor;

[0008] The non-inverting input terminal of the first comparator is used to sample the voltage value on the first capacitor, and the inverting input terminal of the first comparator is used to sample the voltage value on the second capacitor. The first comparator is used to output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; the first flag signal is used to indicate the blanking time of the synchronous rectification transistor in the current cycle;

[0009] The secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal.

[0010] In a possible design, a sampling end of the first voltage sampling circuit is connected to a first end of the secondary winding, an output end of the first voltage sampling circuit is connected to a control end of the first current source, an output end of the first current source is connected to a first end of the first capacitor, a second end of the first capacitor is grounded, and the first end of the first capacitor is also connected to a non-inverting input end of the first comparator;

[0011] The sampling end of the second voltage sampling circuit is connected to the second end of the secondary winding, the output end of the second voltage sampling circuit is connected to the control end of the second current source, the output end of the second current source is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, and the first end of the second capacitor is also connected to the inverting input end of the first comparator.

[0012] In a second aspect, the present application further provides a drive signal generating circuit, which is used in a multi-channel output flyback conversion circuit, wherein the multi-channel output flyback conversion circuit includes a transformer, a synchronous rectification transistor, a secondary controller, and at least two discharge branches; a first end of the secondary winding of the transformer is connected to an input end of the discharge branch, a second end of the secondary winding is connected to a first electrode of the synchronous rectification transistor, a second electrode of the synchronous rectification transistor is grounded, and a control electrode of the synchronous rectification transistor is connected to the secondary controller;

[0013] The drive signal generating circuit comprises an on-time sampling circuit; the on-time sampling circuit comprises a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, and the capacitance values ​​of the first capacitor and the second capacitor are the same;

[0014] The first voltage sampling circuit is used to sample a first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current according to the first voltage value to charge the first capacitor; the second voltage sampling circuit is used to sample a second voltage value on the first electrode of the synchronous rectifier transistor, and the second current source is used to output a corresponding current according to the second voltage value to charge the second capacitor;

[0015] The non-inverting input terminal of the first comparator is used to sample the voltage value on the first capacitor, and the inverting input terminal of the first comparator is used to sample the voltage value on the second capacitor. The first comparator is used to output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; the first flag signal is used to indicate the blanking time of the synchronous rectification transistor in the current cycle;

[0016] The secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal.

[0017] In a possible design, the drive signal generating circuit further includes a second comparator, an inverting input terminal of the second comparator is connected to the output terminal of the second voltage sampling circuit, and a non-inverting input terminal of the second comparator is used to receive a first threshold voltage; the second comparator is used to output a first drive signal when the second voltage value is less than the first threshold voltage;

[0018] The secondary controller is used to control the synchronous rectification transistor to turn on according to the first driving signal.

[0019] In a possible design, the drive signal generating circuit further includes a third comparator, a non-inverting input terminal of the third comparator is connected to the output terminal of the second voltage sampling circuit, and an inverting input terminal of the third comparator is used to receive a second threshold voltage; the third comparator is used to output a second drive signal when the second voltage value is equal to the second threshold voltage;

[0020] The secondary controller is further configured to pull down the voltage value on the control electrode of the synchronous rectification transistor according to the second driving signal, and to control the second voltage value to be equal to the second threshold voltage according to the second driving signal.

[0021] In a possible design, the drive signal generating circuit further includes a fourth comparator, a non-inverting input terminal of the fourth comparator is connected to the output terminal of the second voltage sampling circuit, and an inverting input terminal of the fourth comparator is used to receive a third threshold voltage; the fourth comparator is used to output a third drive signal when the second voltage value is greater than the third threshold voltage;

[0022] The secondary controller is further configured to control the synchronous rectification transistor to turn off according to the third driving signal.

[0023] In a possible design, the drive signal generating circuit further includes an SR latch, the output end of the second comparator and the output end of the fourth comparator are respectively connected to the set end and the reset end of the SR latch, and the output end of the SR latch is connected to the secondary controller;

[0024] The SR latch is used to latch the states of the first drive signal and the third drive signal, and output a second flag signal according to the states of the first drive signal and the third drive signal;

[0025] The secondary controller is further configured to control the synchronous rectification transistor to be turned on or off according to the logic state of the second flag signal.

[0026] In a possible design, the SR latch is used to output the logic state of the second flag signal as 1 when the logic state of the first drive signal is 1 and the logic state of the third drive signal is 0; and to output the logic state of the second flag signal as 0 when the logic state of the first drive signal is 0 and the logic state of the third drive signal is 1;

[0027] The secondary controller is further configured to control the synchronous rectification transistor to be turned on when the logic state of the second flag signal is 1, and to control the synchronous rectification transistor to be turned off when the logic state of the second flag signal is 0.

[0028] In a third aspect, the present application further provides a multi-channel output flyback conversion circuit, the multi-channel output flyback conversion circuit comprising: a transformer, a primary controller, a secondary controller, a primary transistor, a synchronous rectification transistor and at least two discharge branches;

[0029] The first end of the primary winding of the transformer is used to receive the power supply voltage, the second end of the primary winding is connected to the first electrode of the primary transistor, and the second electrode of the primary transistor is grounded; the control electrode of the primary transistor is connected to the primary controller; the first end of the secondary winding of the transformer is connected to the input end of the discharge branch, the output end of the discharge branch is used to connect the load, the second end of the secondary winding is connected to the first electrode of the synchronous rectification transistor, the second electrode of the synchronous rectification transistor is grounded, and the control electrode of the synchronous rectification transistor is connected to the secondary controller;

[0030] Wherein, at least one switch circuit is provided on the discharge branch, and the control end of the switch circuit is also connected to the secondary controller, and the secondary controller is used to control the conduction or shutoff of the switch circuit on the discharge branch, thereby controlling the conduction or shutoff of the discharge branch;

[0031] The secondary controller comprises a drive signal generating circuit, the drive signal generating circuit comprises a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, and the capacitance values ​​of the first capacitor and the second capacitor are the same;

[0032] The first voltage sampling circuit is used to sample a first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current according to the first voltage value to charge the first capacitor; the second voltage sampling circuit is used to sample a second voltage value on the first electrode of the synchronous rectifier transistor, and the second current source is used to output a corresponding current according to the second voltage value to charge the second capacitor;

[0033] The two input terminals of the first comparator are used to sample the voltage values ​​on the first capacitor and the second capacitor respectively, and output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; the first flag signal is used to indicate the blanking time of the synchronous rectification transistor in the current cycle;

[0034] The secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal.

[0035] In a possible design, a sampling end of the first voltage sampling circuit is connected to a first end of the secondary winding, an output end of the first voltage sampling circuit is connected to a control end of the first current source, an output end of the first current source is connected to a first end of the first capacitor, a second end of the first capacitor is grounded, and the first end of the first capacitor is also connected to an inverting input end of the first comparator;

[0036] The sampling end of the second voltage sampling circuit is connected to the second end of the secondary winding, the output end of the second voltage sampling circuit is connected to the control end of the second current source, the output end of the second current source is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, and the first end of the second capacitor is also connected to the non-inverting input end of the first comparator.

[0037] In a possible design, the secondary controller further includes a second comparator, an inverting input terminal of the second comparator is connected to the output terminal of the second voltage sampling circuit, and a non-inverting input terminal of the second comparator is used to receive a first threshold voltage; the second comparator is used to output a first drive signal when the second voltage value is less than the first threshold voltage;

[0038] The secondary controller is used to control the synchronous rectification transistor to turn on according to the first driving signal.

[0039] In a possible design, the drive signal generating circuit further includes a third comparator, a non-inverting input terminal of the third comparator is connected to the output terminal of the second voltage sampling circuit, and an inverting input terminal of the third comparator is used to receive a second threshold voltage; the third comparator is used to output a second drive signal when the second voltage value is equal to the second threshold voltage;

[0040] The secondary controller is further configured to pull down the voltage value on the control electrode of the synchronous rectification transistor according to the second driving signal, and to control the second voltage value to be equal to the second threshold voltage according to the second driving signal.

[0041] In a possible design, the drive signal generating circuit further includes a fourth comparator, a non-inverting input terminal of the fourth comparator is connected to the output terminal of the second voltage sampling circuit, and an inverting input terminal of the fourth comparator is used to receive a third threshold voltage; the fourth comparator is used to output a third drive signal when the second voltage value is greater than the third threshold voltage;

[0042] The secondary controller is further configured to control the synchronous rectification transistor to turn off according to the third driving signal.

[0043] In a possible design, the drive signal generating circuit further includes an SR latch, the output end of the second comparator and the output end of the fourth comparator are respectively connected to the set end and the reset end of the SR latch, and the output end of the SR latch is connected to the secondary controller;

[0044] The SR latch is used to latch the states of the first drive signal and the third drive signal, and output a second flag signal according to the states of the first drive signal and the third drive signal;

[0045] The secondary controller is further configured to control the synchronous rectification transistor to be turned on or off according to the logic state of the second flag signal.

[0046] In a possible design, the SR latch is used to output the logic state of the second flag signal as 1 when the logic state of the first drive signal is 1 and the logic state of the third drive signal is 0; and to output the logic state of the second flag signal as 0 when the logic state of the first drive signal is 0 and the logic state of the third drive signal is 1;

[0047] The secondary controller is further configured to control the synchronous rectification transistor to be turned on when the logic state of the second flag signal is 1, and to control the synchronous rectification transistor to be turned off when the logic state of the second flag signal is 0.

[0048] In a possible design, within a working cycle, the primary controller is used to control the opening of the primary transistor at a starting moment, and to close the primary transistor at a second moment after a first preset time has passed.

[0049] In a possible design, the secondary controller is used to control, at the second moment, to open a switch circuit on a target discharge branch among the at least two discharge branches, so that the target discharge branch is turned on;

[0050] After the second moment, when it is detected that the logic state of the second flag signal is 1, controlling the synchronous rectification transistor to be turned on;

[0051] After the synchronous rectification transistor is turned on, when the second driving signal is detected, controlling the voltage value on the control electrode of the synchronous rectification transistor to be pulled down, and controlling the second voltage value to be maintained at the second threshold voltage;

[0052] When the first flag signal is detected at a fourth moment, the duration from the second moment to the fourth moment is determined to be the blanking time of the synchronous rectifier transistor in the current working cycle, and the synchronous rectifier transistor is controlled to remain in an on state during the blanking time period, and when the current value on the synchronous rectifier transistor decreases to a first current threshold, the second voltage value is controlled to be released from being maintained at the second threshold voltage;

[0053] After the fourth time, when it is detected at a fifth time that the logic state of the second flag signal is 0, the synchronous rectification transistor is controlled to be turned off.

[0054] In a possible design, the secondary controller is further used to obtain the blanking time of the synchronous rectifier transistor in a current working cycle, and use the blanking time in the current working cycle as the blanking time of the synchronous rectifier transistor in a next working cycle;

[0055] Alternatively, the product of the blanking time in the current working cycle and the preset proportionality coefficient is used as the blanking time of the synchronous rectification transistor in the next working cycle, and the preset proportionality coefficient is 0.8-1.

[0056] In a possible design, the primary controller is further configured to, after the fifth moment, turn on the primary transistor again to start the next working cycle when it is detected that the primary transistor oscillates through zero and then passes a quarter of an oscillation cycle.

[0057] In a possible design, the secondary controller is further used to control the switch circuit on the target discharge branch to close and control the discharge switch on another discharge branch to open between the second moment and the fourth moment to achieve switching between the discharge branches.

[0058] In a possible design, the switch circuit includes a first transistor and a second transistor; a first electrode of the first transistor is connected to a first end of the secondary winding, a second electrode of the first transistor is connected to a second electrode of the second transistor, and a first electrode of the second transistor is connected to a first end of an energy storage capacitor; control electrodes of the first transistor and the second transistor are both connected to the secondary controller;

[0059] The secondary controller is used to control the on and off of the first transistor and the second transistor, thereby controlling the on and off of the switch circuit.

[0060] In a fourth aspect, the present application further provides a control method for a multi-channel output flyback conversion circuit, wherein the multi-channel output flyback conversion circuit is a multi-channel output flyback conversion circuit as described in any one of the above items;

[0061] The control method comprises:

[0062] In a working cycle, the primary transistor is controlled to be turned on at a starting moment, and after a first preset time has elapsed, the primary transistor is turned off at a second moment;

[0063] At the second moment, controlling to open a switch circuit on a target discharge branch among the at least two discharge branches, so that the target discharge branch is turned on;

[0064] After the second moment, when it is detected that the logic state of the second flag signal is 1, controlling the synchronous rectification transistor to be turned on;

[0065] When the first flag signal is detected at a fourth moment, determining the duration from the second moment to the fourth moment as the blanking time of the synchronous rectifier transistor in the current working cycle, and controlling the synchronous rectifier transistor to remain in an on state during the blanking time period;

[0066] After the fourth moment, when it is detected at a fifth moment that the logic state of the second flag signal is 0, controlling the synchronous rectification transistor to be turned off;

[0067] After the fifth moment, when it is detected that the primary transistor has oscillated through zero and then passed a quarter of the oscillation cycle, the primary transistor is turned on again to start the next working cycle.

[0068] In a possible design, the control method of the multi-channel output flyback conversion circuit further includes: after the synchronous rectification transistor is turned on, when the second driving signal is detected, controlling to lower the voltage value on the control electrode of the synchronous rectification transistor, and controlling the second voltage value to be maintained at the second threshold voltage;

[0069] And when the current value on the synchronous rectification transistor decreases to a first current threshold, control is performed to release the second voltage value from being maintained at the second threshold voltage.

[0070] In a possible design, the control method of the multi-output flyback conversion circuit further includes:

[0071] After the fifth moment, when it is detected that the primary transistor has oscillated through zero and then passed a quarter of the oscillation cycle, the primary transistor is turned on again to start the next working cycle.

[0072] In a fifth aspect, the present application also provides a chip, wherein the chip includes a conduction time sampling circuit as described in any one of the above items; or the chip includes a drive signal generating circuit as described in any one of the above items; or the chip includes a multi-channel output flyback conversion circuit as described in any one of the above items.

[0073] In a sixth aspect, the present application also provides an electronic device, comprising a conduction time sampling circuit as described in any one of the above items; or the electronic device comprises a drive signal generating circuit as described in any one of the above items; or the electronic device comprises a multi-channel output flyback conversion circuit as described in any one of the above items.

[0074] The conduction time sampling circuit provided by the first aspect above includes a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, wherein the capacitance values ​​of the first capacitor and the second capacitor are the same; the first voltage sampling circuit is used to sample the first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current to charge the first capacitor according to the first voltage value; the second voltage sampling circuit is used to sample the second voltage value on the first pole of the synchronous rectification transistor, and the second current source is used to output a corresponding current to charge the second capacitor according to the second voltage value; the inverting input terminal of the first comparator is used to sample the voltage value on the first capacitor, the non-inverting input terminal of the first comparator is used to sample the voltage value on the second capacitor, and the first comparator is used to output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; the first flag signal is used to characterize the blanking time of the synchronous rectification transistor in the current cycle; the secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal. It can be seen that according to the on-time sampling circuit provided in the present application, based on the principle of volt-second balance between the primary and secondary sides of the transformer, according to the sampled first voltage value and the second voltage value, the two charging currents are respectively controlled to charge the capacitor. When the voltages on the two capacitors are the same, it can be determined that the circuit has reached a volt-second balance, and a first flag signal is output. Therefore, the first flag signal can represent the blanking time of the synchronous rectifier transistor in the current cycle, and the secondary controller controls the synchronous rectifier transistor to remain in the on state during the blanking time period according to the first flag signal, thereby avoiding the situation in which the synchronous rectifier transistor is mistakenly shut down due to the drain-source voltage of the synchronous rectifier transistor being greater than zero when the two discharge branches are commutating, thereby ensuring the working stability of the multi-output flyback conversion circuit.

[0075] In addition, according to the drive signal generating circuit provided by the present application, during the operation of the multi-channel output flyback conversion circuit, after the synchronous rectifier transistor is turned on, when it is detected that the second voltage value on the first electrode of the synchronous rectifier transistor is equal to the second threshold voltage, a second drive signal is output; the secondary controller can control the voltage value on the control electrode of the synchronous rectifier transistor to be lowered according to the second drive signal, and control the second voltage value to be maintained at the second threshold voltage. In this way, since the voltage value on the control electrode of the synchronous rectifier transistor is lowered in advance, the voltage value on the control electrode of the synchronous rectifier transistor is close to the turn-off threshold of the synchronous rectifier transistor, so the turn-off delay time of the synchronous rectifier transistor can be reduced, and finally, when it is detected that the second voltage value on the first electrode of the synchronous rectifier transistor is greater than zero, the gate voltage of the synchronous rectifier transistor is further reduced to achieve rapid turn-off of the synchronous rectifier transistor, thereby further ensuring the working stability of the multi-channel output flyback conversion circuit.

[0076] The beneficial effects provided in the above-mentioned other aspects and various possible designs of the above-mentioned other aspects can be referred to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 A schematic diagram of the structure of a dual-path flyback conversion circuit provided for related technologies;

[0078] Figure 2 A schematic diagram of waveforms of a dual-path flyback conversion circuit in the related art when it is working;

[0079] Figure 3 One of the structural schematic diagrams of the dual-output flyback conversion circuit provided in the embodiment of the present application;

[0080] Figure 4 A schematic diagram of the structure of a conduction time sampling circuit provided in an embodiment of the present application;

[0081] Figure 5 A schematic diagram of the structure of a drive signal generating circuit provided in an embodiment of the present application;

[0082] Figure 6 The waveform diagram of each signal of the dual-output flyback conversion circuit in a single working cycle of the embodiment of the present application;

[0083] Figure 7 The waveform diagram of each signal of the dual-output flyback conversion circuit in multiple working cycles of the embodiment of the present application;

[0084] Figure 8 The second structural schematic diagram of the dual-output flyback conversion circuit provided in the embodiment of the present application;

[0085] Fig. 9 A flow chart of a control method for a multi-output flyback conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0086] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0087] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0088] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0089] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0090] With the development of electronic technology, the charging efficiency and charging safety of electronic devices are an issue that people are concerned about. In the related art, the switching power supply circuit for fast charging of electronic devices usually includes a transformer, a primary switch tube, a secondary switch tube, a primary control unit and a secondary control unit. Among them, the primary switch tube is arranged in the primary winding loop of the transformer, and the secondary switch tube is arranged in the secondary winding loop of the transformer. The transformer is used to convert the input power supply voltage, and then make the secondary winding output a charging voltage that is adapted to the electronic device. The primary control unit and the secondary control unit are respectively used to control the conduction or shutdown of the primary switch tube and the secondary switch tube, so as to control the switching power supply circuit to work in different charging modes to meet the charging needs of various scenarios.

[0091] At present, different types of electronic devices on the market may have different types of charging interfaces. In order to meet the charging needs of electronic devices with different interface types, the power adapter can usually be set with two or more different charging interfaces, and each charging interface corresponds to a discharge branch, so that electronic devices with different charging interfaces can be charged at the same time. For example, a fast charging adapter can realize two outputs at the same time, one output can power an electronic device with a USB Type-C interface, and the other output can charge an electronic device with a USB Type-A interface, and the two outputs can charge two electronic devices at the same time without affecting each other. Among them, different electronic devices include different loads, so when multiple electronic devices are charged at the same time, the charging voltages output by each discharge branch will generally be different.

[0092] In order to rectify the discharge voltage output on each charging branch, a rectifier diode is usually set in the secondary winding loop. Then, with the development of electronic technology, the demand for fast charging of electronic equipment is getting higher and higher, and accordingly, higher requirements are put forward for the efficiency of the switching power supply. In the low-voltage and high-current charging scenario, the conduction voltage drop of the rectifier diode is relatively high, which increases the circuit loss and thus reduces the efficiency of the switching power supply. In recent years, synchronous rectification technology is one of the important technologies. Synchronous rectification technology can use MOS tubes with lower conduction voltage drop to replace rectifier diodes, which can achieve the rectification function while reducing the rectification loss, thereby improving the system efficiency. Therefore, in the dual-path flyback conversion circuit, a synchronous rectification transistor with reduced conduction voltage drop can be set in the secondary winding loop to achieve the purpose of rectifying the discharge voltage. Usually, the synchronous rectification transistor can be implemented by a MOS tube with lower conduction voltage drop. Then, in the actual operation of the dual-path flyback conversion circuit, when the two discharge branches are switched on, that is, when the two discharge branches are commutating, the current of the synchronous rectifier transistor will drop. In severe cases, it will cause the drain-source voltage of the synchronous rectifier transistor to be greater than zero, thereby causing the synchronous rectifier transistor to be mistakenly shut down, thereby causing the dual-path flyback conversion circuit to have an operating error.

[0093] In addition, when the synchronous rectifier transistor is turned off, it takes a certain amount of time for the gate voltage to discharge from the maximum value to the turn-off threshold of the synchronous rectifier transistor. During this period, negative current will flow through the synchronous rectifier transistor, causing current backflow, which will also affect the stability of the dual-path flyback conversion circuit.

[0094] Figure 1 For the structural diagram of the dual-path flyback conversion circuit provided for the related technology, please refer to Figure 1 As shown, the dual-path flyback conversion circuit includes a first transformer T1, a primary transistor M1, a secondary transistor M2, a primary controller 11, a secondary controller 12, a first output branch Vc1 and a second output branch Vc2.

[0095] The opposite-name end of the primary winding of the first transformer T1 is used to receive the power supply voltage V0, the same-name end of the primary winding of the first transformer T1 is connected to the first electrode of the primary transistor M1, and the second electrode of the primary transistor M1 is grounded GND; the control electrode of the primary transistor M1 is connected to the primary controller 11, and the primary controller 11 is used to control the on or off of the primary transistor M1. The same-name end of the secondary winding of the first transformer T1 is respectively connected to the input end of the first output branch Vc1 and the second discharge branch Vc2, the output end of the first output branch Vc1 is used to connect the first load, and the output end of the second output branch Vc2 is used to connect the second load. The opposite-name end of the secondary winding is connected to the first electrode of the secondary transistor M2, the second electrode of the secondary transistor M2 is grounded GND, and the control electrode of the secondary transistor M2 is connected to the secondary controller 12, and the secondary controller 12 is used to control the on and off of the secondary transistor M2. Among them, a first switch tube S11 is provided on the first output branch Vc1, and the control end of the first switch tube S11 is also connected to the secondary controller 12. The secondary controller 12 is used to control the conduction or shutdown of the first switch tube S11 on the first output branch Vc1, thereby controlling the conduction or shutdown of the first output branch Vc1. A second switch tube S12 is provided on the second output branch Vc2, and the control end of the second switch tube S12 is also connected to the secondary controller 12. The secondary controller 12 is used to control the conduction or shutdown of the second switch tube S12 on the second output branch Vc2, thereby controlling the conduction or shutdown of the second output branch Vc2.

[0096] Figure 1 The primary transistor M1 and the secondary transistor M2 in the embodiment may be NMOS (N-Metal-Oxide-Semiconductor) transistors. In other embodiments, the above Figure 1The primary transistor M1 and the secondary transistor M2 may also be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when the primary transistor M1 and the secondary transistor M2 are NMOS transistors, the first electrode is the drain, the second electrode is the source, and the control electrode is the gate.

[0097] Figure 2 This is a waveform diagram of the dual-path flyback conversion circuit in the related art. Figure 2 As shown, when the dual-path flyback conversion circuit is working, Figure 2 In, V GS_M2 Represents the gate-source voltage of the secondary transistor M2, V DS_M2 represents the drain-source voltage of the secondary transistor M2, i M2 represents the current value flowing through the secondary transistor M2, i S11 represents the current value flowing through the first switch tube S11, that is, the current value output by the first output branch Vc1, i S12 represents the current value flowing through the second switch tube S12, that is, the current value outputted from the second output branch Vc2. DS_M2 =i M2* R ds_on , R ds_on is the on-resistance of the secondary transistor M2.

[0098] Please continue to see Figure 2 As shown, at time t1, the primary controller 11 controls the primary transistor M1 to turn on, and at time t2, the secondary controller 12 controls the secondary transistor M2 to turn on, and at the same time turns on the second switch tube S12, so that the second output branch Vc2 discharges the second load; at time t3, the secondary controller 12 controls the second switch tube S12 to turn off, and at the same time turns on the first switch tube S11, so that the first output branch Vc1 discharges the first load, thereby realizing the first output branch Vc1 and the second output branch Vc2 to switch on, that is, to realize the first output branch Vc1 and the second output branch Vc2 to commutate. It can be seen that at time t3, when the first output branch Vc1 and the second output branch Vc2 are commutating, the current i on the secondary transistor M2 is M1 There will be a rapid drop, at this time, the drain-source voltage V DS_M2 There will be a rapid increase, that is, a voltage spike phenomenon will occur. In severe cases, it will cause the drain-source voltage V DS_M2 is greater than zero, which causes the secondary transistor M2 to be turned off by mistake, resulting in a working error in the dual-path flyback conversion circuit. At time t4, the drain-source voltage V DS_M2is greater than 0V, and then the secondary controller 12 controls to turn off the secondary transistor M2. After a short time, when the secondary transistor M2 is turned off, the gate-source voltage V GS_M2 Equal to 0V.

[0099] Also, please see Figure 2 As shown, at time t4, the drain-source voltage V DS_M2 is greater than 0V, so the secondary transistor M2 needs to be turned off. Before the secondary transistor M2 is turned off, the gate-source voltage V GS_M2 Always maintain at the maximum value state, because when the secondary transistor M2 is turned off, the gate-source voltage V GS_M2 It takes a certain amount of time to discharge from the maximum value to the turn-off threshold of the secondary transistor M2, during which a negative current will flow through the secondary transistor M2. That is, at time t4, the current i M1 Reverse current occurs, causing current backflow, which will also affect the stability of the dual-path flyback conversion circuit.

[0100] In order to overcome the defects in the above-mentioned related technologies, the present application provides a conduction time sampling circuit, which includes a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, wherein the capacitance values ​​of the first capacitor and the second capacitor are the same; the first voltage sampling circuit is used to sample the first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current to charge the first capacitor according to the first voltage value; the second voltage sampling circuit is used to sample the second voltage value on the first pole of the synchronous rectification transistor, and the second current source is used to output a corresponding current to charge the second capacitor according to the second voltage value; the inverting input terminal of the first comparator is used to sample the voltage value on the first capacitor, and the non-inverting input terminal of the first comparator is used to sample the voltage value on the second capacitor, and the first comparator is used to output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; the first flag signal is used to characterize the blanking time of the synchronous rectification transistor in the current cycle; the secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal. It can be seen that according to the on-time sampling circuit provided in the present application, based on the principle of volt-second balance between the primary and secondary sides of the transformer, according to the sampled first voltage value and the second voltage value, the two charging currents are respectively controlled to charge the capacitor. When the voltages on the two capacitors are the same, it can be determined that the circuit has reached a volt-second balance, and a first flag signal is output. Therefore, the first flag signal can represent the blanking time of the synchronous rectifier transistor in the current cycle, and the secondary controller controls the synchronous rectifier transistor to remain in the on state during the blanking time period according to the first flag signal, thereby avoiding the situation in which the synchronous rectifier transistor is mistakenly shut down due to the drain-source voltage of the synchronous rectifier transistor being greater than zero when the two discharge branches are commutating, thereby ensuring the working stability of the multi-output flyback conversion circuit.

[0101] Furthermore, during the operation of the multi-channel output flyback conversion circuit, after the synchronous rectifier transistor is turned on, when it is detected that the second voltage value on the first electrode of the synchronous rectifier transistor is equal to the second threshold voltage, the voltage value on the control electrode of the synchronous rectifier transistor is controlled to be lowered, and the second voltage value is controlled to be maintained at the second threshold voltage. In this way, since the voltage value on the control electrode of the synchronous rectifier transistor is lowered in advance, the voltage value on the control electrode of the synchronous rectifier transistor is close to the turn-off threshold of the synchronous rectifier transistor, so the turn-off delay time of the synchronous rectifier transistor can be reduced. Finally, when it is detected that the second voltage value on the first electrode of the synchronous rectifier transistor is greater than zero, the gate voltage of the synchronous rectifier transistor is further reduced to achieve rapid turn-off of the synchronous rectifier transistor, thereby further ensuring the working stability of the multi-channel output flyback conversion circuit.

[0102] The on-time sampling circuit and the drive signal generating circuit provided by the present application are mainly applied to a multi-channel output flyback conversion circuit, which includes a transformer, a primary transistor, a synchronous rectifier transistor, a primary controller, a secondary controller, and at least two discharge branches; the first end of the primary winding of the transformer is used to receive the power supply voltage, the second end of the primary winding is connected to the first pole of the primary transistor, and the second pole of the primary transistor is grounded; the control pole of the primary transistor is connected to the primary controller, and the primary controller is used to control the on or off of the primary transistor. The first end of the secondary winding of the transformer is connected to the input end of each discharge branch, and the output end of each discharge branch is used to connect the load. The second end of the secondary winding is connected to the first pole of the synchronous rectifier transistor, the second pole of the synchronous rectifier transistor is grounded, the control pole of the synchronous rectifier transistor is connected to the secondary controller, and the secondary controller is used to control the on and off of the synchronous rectifier transistor. Among them, at least one switch circuit is provided on the discharge branch, and the control end of the switch circuit is also connected to the secondary controller. The secondary controller is used to control the on or off of the switch circuit on the discharge branch, thereby controlling the on or off of the discharge branch.

[0103] The following further describes the on-time sampling circuit provided by the present application by taking a dual-channel output flyback conversion circuit as an example. It should be noted that the following embodiments only take a dual-channel output flyback conversion circuit as an example, which does not mean that the on-time sampling circuit and the drive signal generating circuit provided by the present application can only be applied to the dual-channel output flyback conversion circuit. In fact, when the dual-channel output flyback conversion circuit is expanded to a multi-channel output flyback conversion circuit, the on-time sampling circuit and the drive signal generating circuit provided by the present application can also be applied to the multi-channel output flyback conversion circuit.

[0104] Figure 3 One of the structural diagrams of the dual-output flyback conversion circuit provided in the embodiment of the present application is shown in FIG. Figure 3As shown, the dual-output flyback conversion circuit includes a second transformer T2, a primary transistor Q1, a synchronous rectifier transistor SR, a primary controller 21, a secondary controller 22, a first discharge branch Vo1 and a second discharge branch Vo2; the first end of the primary winding of the second transformer T2 is used to receive the power supply voltage V1, the second end of the primary winding is connected to the first electrode of the primary transistor Q1, and the second electrode of the primary transistor Q1 is grounded GND; the control electrode of the primary transistor Q1 is connected to the primary controller 21, and the primary controller 21 is used to control the on or off of the primary transistor Q1. The first end of the secondary winding of the second transformer T2 is respectively connected to the input end of the first discharge branch Vo1 and the second discharge branch Vo2, the output end of the first discharge branch Vo1 is used to connect the first load, and the output end of the second discharge branch Vo2 is used to connect the second load. The second end of the secondary winding is connected to the first electrode of the synchronous rectifier transistor SR, the second electrode of the synchronous rectifier transistor SR is grounded GND, and the control electrode of the synchronous rectifier transistor SR is connected to the secondary controller 22, which is used to control the on and off of the synchronous rectifier transistor SR.

[0105] Among them, a first switch circuit S21 is provided on the first discharge branch Vo1, and the control end of the first switch circuit S21 is also connected to the secondary controller 22. The secondary controller 22 is used to control the conduction or shutoff of the first switch circuit S21 on the first discharge branch Vo1, thereby controlling the conduction or shutoff of the first discharge branch Vo1. A second switch circuit S22 is provided on the second discharge branch Vo2, and the control end of the first switch circuit S21 is also connected to the secondary controller 22. The secondary controller 22 is used to control the conduction or shutoff of the second switch circuit S22 on the second discharge branch Vo2, thereby controlling the conduction or shutoff of the second discharge branch Vo2.

[0106] Wherein, a third capacitor C21 is arranged on the first discharge branch Vo1, a first end of the third capacitor C21 is connected to the output end of the first switch circuit S21, a second end of the third capacitor C21 is grounded GND, a first end of the third capacitor C21 is the output end of the first discharge branch Vo1, two ends of the third capacitor C21 are connected to the first load, the third capacitor C21 is used to store energy when the first switch circuit S21 is turned on, and discharges to the first load after the first switch circuit S21 is turned off. A fourth capacitor C22 is arranged on the second discharge branch Vo2, a first end of the fourth capacitor C22 is connected to the output end of the second switch circuit S22, a second end of the fourth capacitor C22 is grounded GND, a first end of the fourth capacitor C22 is the output end of the second discharge branch Vo2, two ends of the fourth capacitor C22 are connected to the second load, the fourth capacitor C22 is used to store energy when the second switch circuit S22 is turned on, and discharges to the second load after the second switch circuit S22 is turned off.

[0107] Figure 4 The schematic diagram of the structure of the conduction time sampling circuit provided in the embodiment of the present application is as follows: Figure 3 In the dual output flyback converter circuit shown in Figure 4 As shown, the on-time sampling circuit includes a first voltage sampling circuit 23, a second voltage sampling circuit 24, a first current source IA1, a second current source IA2, a first capacitor C23, a second capacitor C24 and a first comparator CMP1, and the capacitance values ​​of the first capacitor C23 and the second capacitor C24 are the same.

[0108] The sampling end of the first voltage sampling circuit 23 is connected to the first end of the secondary winding of the second transformer T2, the output end of the first voltage sampling circuit 23 is connected to the control end of the first current source IA1, the output end of the first current source IA1 is connected to the first end of the first capacitor C23, the second end of the first capacitor C23 is grounded GND, and the first end of the first capacitor C23 is also connected to the non-inverting input end of the first comparator CMP1. The sampling end of the second voltage sampling circuit 24 is connected to the second end of the secondary winding of the second transformer T2, the sampling end of the second voltage sampling circuit 24 is specifically connected to the drain of the synchronous rectifier transistor SR, the output end of the second voltage sampling circuit 24 is connected to the control end of the second current source IA2, the output end of the second current source IA2 is connected to the first end of the second capacitor C24, the second end of the second capacitor C24 is grounded GND, and the first end of the second capacitor C24 is also connected to the inverting input end of the first comparator CMP1.

[0109] In this embodiment, the first current source IA1 and the second current source IA2 are both voltage-controlled current sources, which can adjust the current in the output circuit according to an external input voltage signal.

[0110] The first voltage sampling circuit 23 is used to sample the first voltage value V at the first end of the secondary winding of the second transformer T2. IN The first current source IA1 is used to generate a first voltage value V IN The output corresponding current charges the first capacitor C23; the second voltage sampling circuit 24 is used to sample the second voltage value V on the first electrode of the synchronous rectifier transistor SR DS_SR The second current source IA2 is used to generate a second current according to the second voltage value V DS_SR The corresponding current is output to charge the second capacitor C24.

[0111] The first voltage sampling circuit 23 and the second voltage sampling circuit 24 of this embodiment may adopt voltage sampling commonly used in the circuit field, which will not be described in detail here.

[0112] It should be noted that, in this embodiment, the primary transistor Q1 and the synchronous rectifier transistor SR may be NMOS (N-Metal-Oxide-Semiconductor) tubes, and in other embodiments, the primary transistor Q1 and the synchronous rectifier transistor SR may also be PMOS (P-Metal-Oxide-Semiconductor) tubes. For example, when the primary transistor Q1 and the synchronous rectifier transistor SR are NMOS tubes, their first pole is the drain, their second pole is the source, and their control pole is the gate.

[0113] In one embodiment, when the primary transistor Q1 is an NMOS transistor, the drain of the primary transistor Q1 is connected to the same-name end of the primary winding of the second transformer T2, the source of the primary transistor Q1 is grounded GND, and the gate of the primary transistor Q1 is connected to the primary controller 21. When the synchronous rectifier transistor SR is an NMOS transistor, the drain of the synchronous rectifier transistor SR is connected to the opposite-name end of the secondary winding of the second transformer T2, the source of the synchronous rectifier transistor SR is grounded GND, and the gate of the synchronous rectifier transistor SR is connected to the secondary controller 22.

[0114] The non-inverting input terminal of the first comparator CMP1 is used to sample the voltage value on the first capacitor C23, and the inverting input terminal of the first comparator CMP1 is used to sample the voltage value on the second capacitor C24. The first comparator CMP1 is used to output a first flag signal T when the voltage value on the first capacitor C23 is equal to the voltage value on the second capacitor C24. BLANK ; The first flag signal T BLANK , used to characterize the blanking time of the synchronous rectifier transistor SR in the current cycle. Specifically, the first flag signal T BLANK It indicates that the blanking time of the synchronous rectifier transistor SR in the current cycle ends, that is, when the first flag signal T is not detected BLANK When the secondary controller 22 is in operation, the synchronous rectifier transistor SR needs to be controlled to maintain the current state and not to operate.

[0115] Specifically, the secondary controller 22 is used to BLANK , control the synchronous rectifier transistor SR to remain in the on state during the blanking period, thus avoiding the drain-source voltage V of the synchronous rectifier transistor SR to increase when the first discharge branch Vo1 and the second discharge branch Vo2 are commutating. DS_SR When the value is greater than zero, the synchronous rectifier transistor SR is mistakenly turned off, thereby ensuring the working stability of the multi-channel output flyback conversion circuit.

[0116] Among them, the sampled source-drain voltage V of the synchronous rectifier transistor SR DS_SRIt can reflect the volt-second relationship in the primary circuit of the second transformer T2, and sample the first voltage value V at the first end of the second transformer T2. IN It can reflect the volt-second relationship in the secondary circuit of the second transformer T2. According to the volt-second balance relationship between the primary and secondary sides of the second transformer T2, in one working cycle, when the primary transistor Q1 in the primary circuit is turned on, according to the first voltage value V IN The first current source IA1 is controlled to output a corresponding current to charge the first capacitor C23, and at the same time, according to the second voltage value V DS_SR The second current source IA2 is controlled to output a corresponding current to charge the second capacitor C24. Since the capacitance values ​​of the first capacitor C23 and the second capacitor C24 are the same, when the voltage values ​​on the first capacitor C23 and the second capacitor C24 are the same, it means that the primary and secondary sides of the second transformer T2 have reached volt-second balance, and the first comparator CMP1 outputs the first flag signal T BLANK .

[0117] Among them, it should be noted that, in the present embodiment, the first end of the primary winding of the second transformer T2 is an opposite-name end, the second end of the primary winding is a like-name end, the first end of the secondary winding is a like-name end, and the second end of the secondary winding is an opposite-name end; in other embodiments, the first end of the primary winding of the second transformer T2 can be a like-name end, and the second end thereof can be an opposite-name end, and correspondingly, the first end of the secondary winding can be an opposite-name end, and the second end thereof can be a like-name end.

[0118] It should be noted that Figure 4 The dual-channel output flyback conversion circuit shown can be expanded to multiple channels, for example, the dual-channel output flyback conversion circuit can be expanded to a three-channel output flyback conversion circuit. Since the structure of each discharge branch is the same and the input end of each discharge branch is connected to the first end of the secondary winding, it is easy for those skilled in the art to expand the dual-channel output flyback conversion circuit to multiple channels, which will not be described in detail here. At the same time, the conduction time sampling circuit provided in this embodiment is also applicable to the multi-channel output flyback conversion circuit to ensure that when any two of the multiple discharge branches are commutated, the drain-source voltage V DS_SR When the value is greater than zero, the synchronous rectifier transistor SR is mistakenly turned off, thereby ensuring the working stability of the multi-channel output flyback conversion circuit.

[0119] Figure 5The present invention provides a schematic diagram of the structure of a drive signal generation circuit in an embodiment of the present invention. The drive signal generation circuit is used in a multi-channel output flyback conversion circuit. The multi-channel output flyback conversion circuit includes a transformer, a synchronous rectifier transistor, a secondary controller, and at least two discharge branches. The first end of the transformer secondary winding is connected to the input end of the discharge branch, the second end of the secondary winding is connected to the first electrode of the synchronous rectifier transistor, the second electrode of the synchronous rectifier transistor is grounded, and the control electrode of the synchronous rectifier transistor is connected to the secondary controller. In order to more clearly introduce the structure and working principle of the drive signal generation circuit provided in the present invention, the present embodiment uses Figure 3 The dual-output flyback conversion circuit shown in FIG. 1 is used as an example to further illustrate the drive signal generation circuit provided by the present application. Figure 3 The dual-channel output flyback conversion circuit shown is taken as an example, which does not mean that the drive signal generating circuit provided by the present application can only be applied to the dual-channel output flyback conversion circuit. In fact, when the dual-channel output flyback conversion circuit is expanded to a multi-channel output flyback conversion circuit, the drive signal generating circuit provided by the present application can also be applied to the multi-channel output flyback conversion circuit.

[0120] See also Figure 5 As shown, the driving signal generating circuit provided in this embodiment includes a conduction time sampling circuit 25, and the conduction time sampling circuit 25 includes a first voltage sampling circuit 23, a second voltage sampling circuit 24, a first current source IA1, a second current source IA2, a first capacitor C23, a second capacitor C24 and a first comparator CMP1, and the capacitance values ​​of the first capacitor C23 and the second capacitor C24 are the same. Among them, the sampling end of the first voltage sampling circuit 23 is connected to the first end of the secondary winding of the second transformer T2, the output end of the first voltage sampling circuit 23 is connected to the control end of the first current source IA1, the output end of the first current source IA1 is connected to the first end of the first capacitor C23, the second end of the first capacitor C23 is grounded GND, and the first end of the first capacitor C23 is also connected to the non-inverting input end of the first comparator CMP1. Among them, the sampling end of the second voltage sampling circuit 24 is connected to the second end of the secondary winding of the second transformer T2, the output end of the second voltage sampling circuit 24 is connected to the control end of the second current source IA2, the output end of the second current source IA2 is connected to the first end of the second capacitor C24, the second end of the second capacitor C24 is grounded GND, and the first end of the second capacitor C24 is also connected to the inverting input end of the first comparator CMP1.

[0121] In this embodiment, the first current source IA1 and the second current source IA2 are both voltage-controlled current sources, which can adjust the current in the output circuit according to an external input voltage signal.

[0122] The first voltage sampling circuit 23 is used to sample the first voltage value V at the first end of the secondary winding of the second transformer T2. IN The first current source IA1 is used to generate a first voltage value V IN The output corresponding current charges the first capacitor C23; the second voltage sampling circuit 24 is used to sample the second voltage value V on the first electrode of the synchronous rectifier transistor SR DS_SR The second current source IA2 is used to generate a second current according to the second voltage value V DS_SR The corresponding current is output to charge the second capacitor C24.

[0123] The non-inverting input terminal of the first comparator CMP1 is used to sample the voltage value on the first capacitor C23, and the inverting input terminal of the first comparator CMP1 is used to sample the voltage value on the second capacitor C24. The first comparator CMP1 is used to output a first flag signal T when the voltage value on the first capacitor C23 is equal to the voltage value on the second capacitor C24. BLANK ; The first flag signal T BLANK , used to characterize the blanking time of the synchronous rectifier transistor SR in the current cycle. Specifically, the first flag signal T BLANK It indicates that the blanking time of the synchronous rectifier transistor SR in the current cycle ends, that is, when the first flag signal T is not detected BLANK When the secondary controller 22 is in operation, the synchronous rectifier transistor SR needs to be controlled to maintain the current state and not to operate.

[0124] Specifically, the secondary controller 22 is used to BLANK , control the synchronous rectifier transistor SR to remain in the on state during the blanking period, thus avoiding the drain-source voltage V of the synchronous rectifier transistor SR to increase when the first discharge branch Vo1 and the second discharge branch Vo2 are commutating. DS_SR When the value is greater than zero, the synchronous rectifier transistor SR is mistakenly turned off, thereby ensuring the working stability of the multi-channel output flyback conversion circuit.

[0125] It should be noted that the circuit structure and working principle of the conduction time sampling circuit 25 in this embodiment can refer to the above embodiments, and will not be repeated here.

[0126] Please continue to see Figure 5 As shown, the driving signal generating circuit of this embodiment further includes a second comparator CMP2, the inverting input terminal of the second comparator CMP2 is connected to the output terminal of the second voltage sampling circuit 24, and the non-inverting input terminal of the second comparator CMP2 is used to receive the first threshold voltage V th_on The second comparator CMP2 is used to DS_SR is less than the first threshold voltage V th_onWhen the first driving signal is output, the first driving signal is output; the secondary controller 22 is used to control the synchronous rectification transistor SR to turn on according to the first driving signal.

[0127] It can be understood that in a working cycle, when the primary controller 21 controls the primary transistor Q1 to turn off, and then turns on a discharge branch to supply power to the load, at this time, the drain-gate voltage V DS_SR Will decrease rapidly when the drain-gate voltage V DS_SR drops below the first threshold voltage V th_on When , the second comparator CMP2 outputs a first driving signal, and the secondary controller 22 is used to control the synchronous rectification transistor SR to turn on according to the first driving signal, so as to turn on the secondary loop.

[0128] Figure 6 : is a waveform diagram of each signal of the dual-output flyback conversion circuit in a single working cycle of the embodiment of the present application, Figure 7 : is a waveform diagram of each signal of the dual-output flyback conversion circuit in multiple working cycles of the embodiment of the present application, Figure 6 and Figure 7 In, V GS _ Q1 、V GS _ S21 、V GS _ S22 The driving signals input to the control terminals of the primary transistor Q1, the first switch circuit S21 and the second switch circuit S22 are respectively. It can be understood that, at V GS _ Q1 When it is high, it means that the primary transistor Q1 is turned on. GS _ Q1 When it is low, it means that the primary transistor Q1 is turned off; GS _ S21 When it is high level, it means that the first switch circuit S21 is turned on. GS _ S21 When it is low level, it means that the first switch circuit S21 is turned off; GS _ S22 When it is high level, it means that the second switch circuit S22 is turned on. GS _ S22 When it is at a low level, it indicates that the second switch circuit S22 is turned off. Figure 6 Medium V IN is the voltage signal on the same-name end of the secondary winding, i SR represents the current value flowing through the synchronous rectifier transistor SR, where i S22 represents the current value flowing through the second switch circuit S22 when the second switch circuit S22 is turned on, i S21V represents the current value flowing through the first switch circuit S21 when the first switch circuit S21 is turned on. GS_SR represents the gate-source voltage on the synchronous rectifier transistor SR, V DS_SR Represents the drain-source voltage on the synchronous rectifier transistor SR, V DS_SR =i SR* R ds_on , R ds_on Represents the on-resistance of the synchronous rectifier transistor SR. Figure 6 and Figure 7 In the figure, the dotted line indicates that the first current source IA1 is proportional to the first voltage value V IN The first ramp voltage signal V sec_Ramp The solid line indicates that the second current source IA2 is proportional to the second voltage value V DS_SR The converted second ramp voltage signal V pri_Ramp Wherein, T2 represents the blanking time of the synchronous rectifier transistor SR in the current working cycle. Figure 7 In, T (N-1) Indicates the blanking time of the synchronous rectifier transistor SR in the previous working cycle, T (N) Indicates the blanking time of the synchronous rectifier transistor SR in the current working cycle, T (N+1) Indicates the blanking duration of the synchronous rectifier transistor SR in the next working cycle.

[0129] See also Figure 6 As shown, at time t1, the primary controller 21 controls to open the primary transistor Q1, and at time t2, the secondary controller 22 controls to open the second switch circuit S22 on the second discharge branch Vo2, so that the drain-source voltage V DS_SR is less than the first threshold voltage V th_on , the second comparator CMP2 outputs the first drive signal as a high level, that is, the logic state of the first drive signal is 1.

[0130] Please continue to see Figure 5 As shown, in one embodiment, the drive signal generating circuit further includes a third comparator CMP3, the non-inverting input terminal of the third comparator CMP3 is connected to the output terminal of the second voltage sampling circuit 24, and the inverting input terminal of the third comparator CMP3 is used to receive the second threshold voltage V th The third comparator CMP3 is used to determine the second voltage value V DS_SR Equal to the second threshold voltage V th The secondary controller 22 is also used to pull down the voltage value on the control electrode (specifically the gate) of the synchronous rectifier transistor SR according to the second drive signal, and control the second voltage value to be equal to the second threshold voltage according to the second drive signal.

[0131] Please continue to see Figure 6 As shown, at time t31, the drain-source voltage V DS_SR Equal to the second threshold voltage V th When the third comparator CMP3 outputs the second drive signal as a high level, that is, the logic state of the second drive signal is 1, the secondary controller 22 pulls down the voltage value on the control electrode of the synchronous rectifier transistor SR according to the second drive signal, and controls the second voltage value to be equal to the second threshold voltage V according to the second drive signal. th .

[0132] According to the driving signal generating circuit provided in this embodiment, during the operation of the multi-channel output flyback conversion circuit, after the synchronous rectifier transistor SR is turned on, when the second voltage value V DS_SR Equal to the second threshold voltage V th When the secondary controller 22 controls the voltage value on the control electrode of the synchronous rectifier transistor SR to be pulled down, and controls the second voltage value V DS_SR Maintain at the second threshold voltage V th Specifically, the voltage value on the control electrode of the synchronous rectifier transistor SR can be controlled to be lowered to a preset value, which can be close to 0V. Since the turn-off threshold of the synchronous rectifier transistor SR is 0V, the voltage value on the control electrode (specifically the gate) of the synchronous rectifier transistor SR is pulled down to the turn-off threshold in advance, so that the voltage value on the control electrode of the synchronous rectifier transistor SR is close to the turn-off threshold of the synchronous rectifier transistor SR, thereby reducing the turn-off delay time of the synchronous rectifier transistor SR. Finally, when the drain-source voltage V DS_SR When it is greater than 0V, the gate voltage of the synchronous rectifier transistor SR is further reduced to 0V, so that the synchronous rectifier transistor SR is quickly turned off, further ensuring the working stability of the dual-output flyback conversion circuit.

[0133] Please continue to see Figure 6 As shown, at time t2, the secondary controller 22 controls the second switch circuit S22 on the second discharge branch Vo2 to turn on. In one embodiment, the secondary controller 22 is also used to control the switch circuit on the target discharge branch to turn off and control the discharge switch on another discharge branch to turn on between the second time and the fourth time, so as to achieve switching between the discharge branches. For example, at time t3, when the secondary controller 22 controls the second switch circuit S22 on the second discharge branch Vo2 to turn off and switches to control the first switch circuit S21 on the first discharge branch Vo1 to turn on, that is, when the first discharge branch Vo1 and the second discharge branch Vo2 are controlled to commutate, the current i on the synchronous rectifier transistor SR is SR There will be a rapid drop, at this time, the drain-source voltage VDS_SR There will be a rapid increase, that is, a voltage spike phenomenon will occur. In severe cases, it will cause the drain-source voltage V DS_SR is greater than zero, which causes the synchronous rectifier transistor SR to be turned off incorrectly, resulting in an operating error in the dual-path flyback conversion circuit.

[0134] Please continue to see Figure 6 As shown, Figure 6 In the embodiment, the first voltage value V on the first end of the secondary winding of the second transformer T2 sampled by the first voltage sampling circuit 23 is IN It can represent the output voltage of the dual-output flyback conversion circuit, that is, the first voltage value V IN It can reflect the volt-second relationship in the secondary circuit of the second transformer T2, and the second voltage value V on the drain of the synchronous rectifier transistor SR sampled by the second voltage sampling circuit 24 is DS_SR It can represent the output voltage of the primary circuit of the second transformer T2. Then, starting from time t1, the first current source IA1 converts the first voltage value V IN Converted into a first ramp voltage signal V sec_Ramp The second current source IA2 converts the second voltage value V DS_SR Converted into a second ramp voltage signal V pri_Ramp , then the second ramp voltage signal V pri_Ramp It can reflect the volt-second relationship when the primary transistor Q1 is turned on. The first ramp voltage signal V sec_Ramp It can reflect the volt-second relationship when the synchronous rectifier transistor SR is turned on. At time t1, when the primary transistor Q1 of the primary side is turned on, the first ramp voltage signal V sec_Ramp and the second ramp voltage signal V pri_Ramp Both start to rise. At time t4, when the first ramp voltage signal V sec_Ramp Equal to the second ramp voltage signal V pri_Ramp When , it indicates that the circuit reaches volt-second balance, at this time, the first comparator CMP1 outputs the first flag signal T BLANK , the logic state is 1, and the first flag signal T BLANK , can represent the blanking time T2. Specifically, in this embodiment, the time period from the moment when the synchronous rectifier transistor SR is turned on at time t2 to the moment when t4 (when the volt-second balance is reached) is taken as the blanking time T2. The secondary controller 22 needs to control the synchronous rectifier transistor SR to maintain the current state and not to act during the blanking time T2, that is, the secondary controller 22 needs to control the synchronous rectifier transistor SR to continue to be turned on during the blanking time T2. In this way, the drain-source voltage V of the synchronous rectifier transistor SR is avoided when the first discharge branch Vo1 and the second discharge branch Vo2 are commutated. DS_SRWhen the value is greater than zero, the synchronous rectifier transistor SR is mistakenly turned off, thereby ensuring the working stability of the multi-channel output flyback conversion circuit.

[0135] In one embodiment, the secondary controller 22 is also used to obtain the blanking time of the synchronous rectifier transistor SR in the current working cycle, and use the blanking time in the current working cycle as the blanking time of the synchronous rectifier transistor SR in the next working cycle; or the secondary controller 22 uses the product of the blanking time in the current working cycle and the preset proportional coefficient as the blanking time of the synchronous rectifier transistor SR in the next working cycle, and the preset proportional coefficient is 0.8-1, that is, (0.8-1) times the blanking duration in the current working cycle is used as the blanking time in the next working cycle.

[0136] See also Figure 7 As shown, in one embodiment, during the operation of the dual-output flyback converter circuit, the secondary controller 22 is also used to collect the blanking time T of the synchronous rectifier transistor SR in the previous working cycle. (N-1) , in the current working cycle, the blanking time T in the previous working cycle is (N-1) 90% of the current duty cycle is taken as the blanking time of the synchronous rectifier transistor SR, that is, T (N) =90%T (N-1) Similarly, the secondary controller 22 collects the blanking time T of the synchronous rectifier transistor SR in the current working cycle (N) In the next working cycle, 90% of the blanking time T(N) in the current working cycle is used as the blanking time of the synchronous rectifier transistor SR in the next working cycle, that is, T (N+1) =90%T (N) .

[0137] Please continue to see Figure 5 As shown, in one embodiment, the drive signal generating circuit further includes a fourth comparator CMP4, the non-inverting input terminal of the fourth comparator CMP4 is connected to the output terminal of the second voltage sampling circuit 24, and the inverting input terminal of the fourth comparator CMP4 is used to receive the third threshold voltage; the fourth comparator CMP4 is used to DS_SR When it is greater than the third threshold voltage, a third driving signal is output; the secondary controller 22 is also used to control the synchronous rectification transistor SR to turn off according to the third driving signal output by the fourth comparator CMP4.

[0138] The third threshold voltage can be set to 0V, that is, the inverting input terminal of the fourth comparator CMP4 can be grounded GND. When the fourth comparator CMP4 detects the drain-source voltage V DS_SRWhen it is greater than 0V, the third drive signal is output, so that the secondary controller 22 controls the synchronous rectifier transistor SR to turn off according to the third drive signal output by the fourth comparator CMP4. After the synchronous rectifier transistor SR is turned off, the dual-output flyback conversion circuit will enter the capacitor discharge stage.

[0139] Please continue to see Figure 6 As shown, at time t5, the drain-source voltage V DS_SR is greater than 0V. At this time, the third drive signal output by the fourth comparator CMP4 is at a high level, that is, the logic state value of the third drive signal is 1. The secondary controller 22 controls the synchronous rectifier transistor SR to turn off when the logic state value of the third drive signal is detected to be 1. After the synchronous rectifier transistor SR is turned off, the dual-channel output flyback conversion circuit will enter the capacitor discharge stage. For details, please refer to FIG. Figure 6 At time t5-t6, when the third capacitor C21 in the dual-output flyback conversion circuit is discharged, the drain-source voltage V DS_SR There will be shocks.

[0140] In one embodiment, after time t5, when the primary controller 21 detects that the primary transistor Q1 oscillates through zero and then passes through a quarter of an oscillation cycle, the primary transistor Q1 is turned on again to start the next working cycle.

[0141] For further information, please see Figure 5 As shown, in one embodiment, the drive signal generating circuit further includes an SR latch 26, the output end of the second comparator CMP2 is connected to the set end (i.e., the S end) of the SR latch 26, the output end of the fourth comparator CMP4 is connected to the reset end (i.e., the R end) of the SR latch 26, and the output end of the SR latch 26 is connected to the secondary controller 22. The SR latch 26 is used to latch the state of the first drive signal and the third drive signal, and output a second flag signal according to the state of the first drive signal and the third drive signal; the secondary controller 22 is also used to control the synchronous rectifier transistor SR to be turned on or off according to the logic state of the second flag signal.

[0142] Among them, the SR latch 26 is used to output the logic state of the second flag signal as 1 when the logic state of the first drive signal is 1 and the logic state of the third drive signal is 0; and to output the logic state of the second flag signal as 0 when the logic state of the first drive signal is 0 and the logic state of the third drive signal is 1; the secondary controller 22 is also used to control the synchronous rectifier transistor SR to turn on when the logic state of the second flag signal is 1, and to control the synchronous rectifier transistor SR to turn off when the logic state of the second flag signal is 0.

[0143] According to the above description, when the logic state of the first drive signal output by the second comparator CMP2 is 1 at time t2, that is, S=1, the SR latch 26 latches the logic state of the first drive signal, until reaching time t5, the logic state of the second flag signal output by the SR latch 26 is also 1, until reaching time t5, the logic state value of the third drive signal output by the fourth comparator CMP4 is 1, that is, R=1, then at this time, the logic state of the second flag signal output by the SR latch 26 is 0. In other words, when the logic state of the second flag signal output by the SR latch 26 is 1, the secondary controller 22 controls the synchronous rectifier transistor SR to turn on, and when the logic state of the second flag signal output by the SR latch 26 is 0, the secondary controller 22 controls the synchronous rectifier transistor SR to turn off.

[0144] Generally, the secondary controller 22 includes a driving circuit 26. The output end of the SR latch 26, the output end of the first comparator CMP1, and the output end of the third comparator CMP3 are all connected to the driving circuit 26. The driving circuit 26 outputs corresponding level driving signals according to the logic states of the above-mentioned signals to drive the synchronous rectifier transistor SR to operate.

[0145] Figure 8 The second structural diagram of the dual-output flyback conversion circuit provided in the embodiment of the present application is shown in FIG. Figure 8 As shown, in one embodiment, the first switch circuit S21 on the first discharge branch Vo1 includes a first transistor Q11 and a second transistor Q12; the first electrode of the first transistor Q11 is connected to the first end of the secondary winding of the second transformer T2, the second electrode of the first transistor Q11 is connected to the second electrode of the second transistor Q12, and the first electrode of the second transistor Q12 is connected to the first end of the third capacitor C21; the control electrodes of the first transistor Q11 and the second transistor Q12 are both connected to the secondary controller 22; the secondary controller 22 is used to control the conduction and disconnection of the first transistor Q11 and the second transistor Q12. Among them, the second switch circuit S22 on the second discharge branch Vo2 includes a third transistor Q13 and a fourth transistor Q14; the first electrode of the third transistor Q13 is connected to the first end of the secondary winding of the second transformer T2, the second electrode of the third transistor Q13 is connected to the second electrode of the fourth transistor Q14, and the first electrode of the fourth transistor Q14 is connected to the first end of the fourth capacitor C22; the control electrodes of the third transistor Q13 and the fourth transistor Q14 are both connected to the secondary controller 22; the secondary controller 22 is used to control the conduction and shutdown of the third transistor Q13 and the fourth transistor Q14.

[0146] Among them, the first transistor Q11, the second transistor Q12, the third transistor Q13 and the fourth transistor Q14 of this embodiment can adopt NMOS (N-Metal-Oxide-Semiconductor) tubes, specifically MOSFET tubes, GaN tubes, and SiC tubes; in other embodiments, the first transistor Q11, the second transistor Q12, the third transistor Q13 and the fourth transistor Q14 can also adopt PMOS (P-Metal-Oxide-Semiconductor) tubes. For example, when the first transistor Q11, the second transistor Q12, the third transistor Q13 and the fourth transistor Q14 of this embodiment adopt NMOS tubes, their first pole is the drain, their second pole is the source, and their control pole is the gate.

[0147] The present application also provides a multi-channel output flyback conversion circuit, which includes: a transformer, a primary controller, a secondary controller, a primary transistor, a synchronous rectification transistor and multiple discharge branches; the first end of the primary winding of the transformer is used to receive the power supply voltage, the second end of the primary winding is connected to the first pole of the primary transistor, and the second pole of the primary transistor is grounded; the control pole of the primary transistor is connected to the primary controller; the first end of the secondary winding of the transformer is connected to the input end of the discharge branch, the output end of the discharge branch is used to connect the load, the second end of the secondary winding is connected to the first pole of the synchronous rectification transistor, the second pole of the synchronous rectification transistor is grounded, and the control pole of the synchronous rectification transistor is connected to the secondary controller; wherein, at least one switching circuit and an energy storage capacitor are arranged on the discharge branch, the control end of the switching circuit is also connected to the secondary controller, and the secondary controller is used to control the conduction or disconnection of the switching circuit on the discharge branch, thereby controlling the conduction or disconnection of the discharge branch.

[0148] The secondary controller in the multi-channel output flyback conversion circuit includes the drive signal generating circuit and the drive circuit 26 provided in the above embodiments. The circuit structure of the multi-channel output flyback conversion circuit can be based on Figure 3 and Figure 8 The dual-output flyback converter circuit shown in FIG. 1 is expanded, and the waveform diagram of the multi-output flyback converter circuit when working can be seen in FIG. Figure 6 As shown in the working waveform diagram of the dual-output flyback conversion circuit, the circuit structure and working principle of the drive signal generating circuit and the drive circuit 26 in this embodiment can refer to the above embodiments, which will not be repeated here.

[0149] In a working cycle, the primary controller 21 in the multi-output flyback conversion circuit is used to control the opening of the primary transistor Q1 at the start time, and to close the primary transistor Q1 at the second time after a first preset time has passed.

[0150] In one working cycle, the secondary controller 22 in the multi-channel output flyback conversion circuit is mainly used for:

[0151] At the second moment, the switch circuit on the target discharge branch in at least two discharge branches is controlled to be turned on so that the target discharge branch is turned on; after the second moment, when the logic state of the second flag signal is detected to be 1, the synchronous rectification transistor is controlled to be turned on; after the synchronous rectification transistor is turned on, when the second drive signal is detected, the voltage value on the control electrode of the synchronous rectification transistor is controlled to be lowered, and the second voltage value is controlled to be maintained at the second threshold voltage; when the first flag signal is detected at the fourth moment, the duration from the second moment to the fourth moment is determined to be the blanking time of the synchronous rectification transistor in the current working cycle, and the synchronous rectification transistor is controlled to remain in the on state during the blanking time period, and when the current value on the synchronous rectification transistor is reduced to the first current threshold, the second voltage value is controlled to be released to be maintained at the second threshold voltage; after the fourth moment, when the logic state of the second flag signal is detected to be 0 at the fifth moment, the synchronous rectification transistor is controlled to be turned off; after the fifth moment, when it is detected that the primary transistor Q1 oscillates through the zero point and then passes through a quarter of the oscillation cycle, the primary transistor Q1 is turned on again to start the next working cycle.

[0152] The secondary controller 22 is further used to control the switch circuit on the target discharge branch to be closed and control the discharge switch on another discharge branch to be opened between the second moment and the fourth moment, so as to realize the switching between the discharge branches.

[0153] In one embodiment, the switching circuit on each discharge branch includes a first transistor and a second transistor; the first electrode of the first transistor is connected to the first end of the secondary winding, the second electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the first end of the energy storage capacitor, and the second end of the energy storage capacitor is grounded; the control electrodes of the first transistor and the second transistor are both connected to the secondary controller; the secondary controller 22 is used to control the conduction and shutdown of the first transistor and the second transistor, thereby controlling the conduction and shutdown of the corresponding switching circuit.

[0154] In this embodiment, the switch circuit is provided with a group of two transistors arranged back to back, and the transistors arranged back to back can prevent the output energy from being injected into each other. In the PD (Power Delivery) application scenario, since the voltage output by each discharge branch needs to be adjustable, the relative size of the voltage output by each discharge branch will change, so the switch circuit needs to be able to withstand bidirectional withstand voltage. Therefore, when the switch circuit of this embodiment is implemented using a MOS tube, due to the body diode, the switch circuit requires two back-to-back MOS tubes, and the MOS tube can specifically use other types of power devices such as MOSFET tubes, GaN tubes, and SiC tubes.

[0155] The first transistor and the second transistor of this embodiment adopt NMOS (N-Metal-Oxide-Semiconductor) tubes, which can be MOSFET tubes, GaN tubes, and SiC tubes; in other embodiments, the first transistor and the second transistor can also adopt PMOS (P-Metal-Oxide-Semiconductor) tubes. For example, when the first transistor and the second transistor of this embodiment adopt NMOS tubes, the first electrode is the drain, the second electrode is the source, and the control electrode is the gate.

[0156] In other embodiments, the two back-to-back transistors in the above switch circuit may also adopt a bidirectional switch, which can also prevent the output energy from being injected into each other.

[0157] In one embodiment, the multi-output flyback conversion circuit further includes an isolated communication circuit, and the primary controller 21 is electrically connected to the secondary controller 22 via the isolated communication circuit. It can be understood that during the operation of the circuit, the isolated communication circuit mainly plays the role of safety, stability and noise isolation to ensure stable operation of the circuit, which will not be described in detail here.

[0158] In one embodiment, the secondary controller 22 is used to control the on-time ratio of the switch circuit on each discharge branch according to the energy ratio required by the load on the output end of each discharge branch, so as to adjust the discharge power of each discharge branch output end. Specifically, the on-time of the corresponding switch circuit is longer when the energy required by the load on the discharge branch is larger, so that multiple outputs can be realized to charge the electronic device at the same time.

[0159] Fig. 9 Flow chart of the control method of the multi-channel output flyback conversion circuit provided in the embodiment of the present application. The control method is mainly used in the multi-channel output flyback conversion circuit provided in the above embodiments. Fig. 9 As shown, the control method of the multi-output flyback conversion circuit provided in this embodiment includes:

[0160] S901 . In a working cycle, at a starting moment, the primary transistor is controlled to be turned on, and after a first preset time has elapsed, the primary transistor is turned off at a second moment.

[0161] Among them, within each working cycle, the first preset duration of the conduction of the primary transistor in this embodiment can be specifically set according to different application scenarios; in one embodiment, the primary controller is also used to detect the current value on the second transformer, and when the current value on the second transformer increases to a preset value, the primary transistor is controlled to be turned off.

[0162] S902. At a second moment, control to open a switch circuit on a target discharge branch among at least two discharge branches, so that the target discharge branch is turned on.

[0163] Specifically, at the second moment, according to the energy required by the load connected to the output end of each discharge branch, it is determined to control a certain discharge branch to be turned on, so as to charge the load.

[0164] S903 . After the second moment, when it is detected that the logic state of the second flag signal is 1, control the synchronous rectification transistor to be turned on.

[0165] S904: When the first flag signal is detected at the fourth moment, determine the duration from the second moment to the fourth moment as the blanking time of the synchronous rectification transistor in the current working cycle, and control the synchronous rectification transistor to remain in an on state during the blanking time period.

[0166] Specifically, when the first flag signal is detected at the fourth moment, it indicates that the primary and secondary sides of the circuit have reached a volt-second balance, and the time from the synchronous rectifier transistor being turned on to the current moment is used as the blanking time in the current working cycle. The secondary controller controls the synchronous rectifier transistor to remain on during the blanking time period according to the first flag signal, thereby avoiding the situation in which the synchronous rectifier transistor is mistakenly shut down due to the drain-source voltage of the synchronous rectifier transistor being greater than zero when the two discharge branches are commutating, thereby ensuring the working stability of the multi-output flyback conversion circuit.

[0167] S905 . After the fourth moment, when it is detected at a fifth moment that the logic state of the second flag signal is 0, control the synchronous rectification transistor to be turned off.

[0168] S906 , after the fifth moment, when it is detected that the primary transistor oscillates through zero and then passes through a quarter of an oscillation cycle, the primary transistor is turned on again to start the next working cycle.

[0169] In one embodiment, the control method of the multi-output flyback conversion circuit also includes: after the synchronous rectification transistor is turned on, when a second drive signal is detected, controlling the voltage value on the control electrode of the synchronous rectification transistor to be pulled down, and controlling the second voltage value to be maintained at a second threshold voltage; and when the current value on the synchronous rectification transistor is reduced to a first current threshold, controlling the second voltage value to be released from being maintained at the second threshold voltage.

[0170] Specifically, when the second driving signal is detected, the secondary controller 22 controls the voltage value on the control electrode of the synchronous rectifier transistor to be pulled down, and controls the second voltage value to be maintained at the second threshold voltage. In this way, since the voltage value on the control electrode of the synchronous rectifier transistor is pulled down in advance, the voltage value on the control electrode of the synchronous rectifier transistor is close to the turn-off threshold of the synchronous rectifier transistor, so the turn-off delay time of the synchronous rectifier transistor can be reduced. Finally, when it is detected that the second voltage value on the first electrode of the synchronous rectifier transistor is greater than zero, the gate voltage of the synchronous rectifier transistor is further reduced to achieve rapid turn-off of the synchronous rectifier transistor, thereby further ensuring the working stability of the multi-channel output flyback conversion circuit.

[0171] In one embodiment, the control method of the multi-channel output flyback conversion circuit further includes: after the fifth moment, when it is detected that the primary transistor Q1 oscillates through zero and then passes through a quarter of the oscillation cycle, turning on the primary transistor Q1 again to start the next working cycle.

[0172] This embodiment also provides a chip, which includes the on-time sampling circuit provided in any one of the above embodiments; or the chip includes the drive signal generating circuit provided in any one of the above embodiments; or the chip includes the multi-channel output flyback conversion circuit provided in any one of the above embodiments.

[0173] This embodiment also provides an electronic device, which includes the on-time sampling circuit provided in any one of the above embodiments; or the electronic device includes the drive signal generating circuit provided in any one of the above embodiments; or the electronic device includes the multi-channel output flyback conversion circuit provided in any one of the above embodiments.

[0174] The electronic device of this embodiment may be a power adapter or a portable charger or other devices.

[0175] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A conduction time sampling circuit, used in a multi-channel output flyback conversion circuit, the multi-channel output flyback conversion circuit comprising a transformer, a synchronous rectification transistor, a secondary controller and at least two discharge branches; a first end of the secondary winding of the transformer is connected to an input end of the discharge branch, a second end of the secondary winding is connected to a first electrode of the synchronous rectification transistor, a second electrode of the synchronous rectification transistor is grounded, and a control electrode of the synchronous rectification transistor is connected to the secondary controller; It is characterized in that The on-time sampling circuit comprises a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, wherein the capacitance values ​​of the first capacitor and the second capacitor are the same; The first voltage sampling circuit is used to sample a first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current according to the first voltage value to charge the first capacitor; the second voltage sampling circuit is used to sample a second voltage value on the first electrode of the synchronous rectifier transistor, and the second current source is used to output a corresponding current according to the second voltage value to charge the second capacitor; The non-inverting input terminal of the first comparator is used to sample the voltage value on the first capacitor, the inverting input terminal of the first comparator is used to sample the voltage value on the second capacitor, and the first comparator is used to output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; The first flag signal is used to indicate the blanking time of the synchronous rectification transistor in the current cycle; The secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal.

2. The on-time sampling circuit according to claim 1, characterized in that: The sampling end of the first voltage sampling circuit is connected to the first end of the secondary winding, the output end of the first voltage sampling circuit is connected to the control end of the first current source, the output end of the first current source is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, and the first end of the first capacitor is also connected to the non-inverting input end of the first comparator; The sampling end of the second voltage sampling circuit is connected to the second end of the secondary winding, the output end of the second voltage sampling circuit is connected to the control end of the second current source, the output end of the second current source is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, and the first end of the second capacitor is also connected to the inverting input end of the first comparator.

3. A drive signal generating circuit, used in a multi-channel output flyback conversion circuit, wherein the multi-channel output flyback conversion circuit comprises a transformer, a synchronous rectifier transistor, a secondary controller and at least two discharge branches; the first end of the secondary winding of the transformer is connected to the input end of the discharge branch, the second end of the secondary winding is connected to the first electrode of the synchronous rectifier transistor, the second electrode of the synchronous rectifier transistor is grounded, and the control electrode of the synchronous rectifier transistor is connected to the secondary controller; characterized in that, The drive signal generating circuit comprises the on-time sampling circuit as claimed in claim 1 or 2; The drive signal generating circuit further includes a second comparator, an inverting input terminal of the second comparator is connected to the output terminal of the second voltage sampling circuit, and a non-inverting input terminal of the second comparator is used to receive a first threshold voltage; the second comparator is used to output a first drive signal when the second voltage value is less than the first threshold voltage; The secondary controller is used to control the synchronous rectification transistor to turn on according to the first driving signal.

4. The driving signal generating circuit according to claim 3, characterized in that: The drive signal generating circuit further includes a third comparator, wherein a non-inverting input terminal of the third comparator is connected to an output terminal of the second voltage sampling circuit, and an inverting input terminal of the third comparator is used to receive a second threshold voltage; the third comparator is used to output a second drive signal when the second voltage value is equal to the second threshold voltage; The secondary controller is further configured to pull down the voltage value on the control electrode of the synchronous rectification transistor according to the second driving signal, and to control the second voltage value to be equal to the second threshold voltage according to the second driving signal.

5. The driving signal generating circuit according to claim 4, characterized in that: The drive signal generating circuit further includes a fourth comparator, wherein a non-inverting input terminal of the fourth comparator is connected to an output terminal of the second voltage sampling circuit, and an inverting input terminal of the fourth comparator is used to receive a third threshold voltage; the fourth comparator is used to output a third drive signal when the second voltage value is greater than the third threshold voltage; The secondary controller is further configured to control the synchronous rectification transistor to turn off according to the third driving signal.

6. The driving signal generating circuit according to claim 5, characterized in that: The drive signal generating circuit further includes an SR latch, the output end of the second comparator and the output end of the fourth comparator are respectively connected to the set end and the reset end of the SR latch, and the output end of the SR latch is connected to the secondary controller; The SR latch is used to latch the states of the first drive signal and the third drive signal, and output a second flag signal according to the states of the first drive signal and the third drive signal; The secondary controller is further configured to control the synchronous rectification transistor to be turned on or off according to the logic state of the second flag signal.

7. The driving signal generating circuit according to claim 6, characterized in that: The SR latch is used to output the logic state of the second flag signal as 1 when the logic state of the first drive signal is 1 and the logic state of the third drive signal is 0; and to output the logic state of the second flag signal as 0 when the logic state of the first drive signal is 0 and the logic state of the third drive signal is 1; The secondary controller is further configured to control the synchronous rectification transistor to be turned on when the logic state of the second flag signal is 1, and to control the synchronous rectification transistor to be turned off when the logic state of the second flag signal is 0.

8. A multi-output flyback conversion circuit, characterized in that: The multi-output flyback conversion circuit comprises: a transformer, a primary controller, a secondary controller, a primary transistor, a synchronous rectification transistor and at least two discharge branches; The first end of the primary winding of the transformer is used to receive the power supply voltage, the second end of the primary winding is connected to the first electrode of the primary transistor, and the second electrode of the primary transistor is grounded; the control electrode of the primary transistor is connected to the primary controller; the first end of the secondary winding of the transformer is connected to the input end of the discharge branch, the output end of the discharge branch is used to connect the load, the second end of the secondary winding is connected to the first electrode of the synchronous rectification transistor, the second electrode of the synchronous rectification transistor is grounded, and the control electrode of the synchronous rectification transistor is connected to the secondary controller; Wherein, at least one switch circuit is provided on the discharge branch, and the control end of the switch circuit is also connected to the secondary controller, and the secondary controller is used to control the conduction or shutoff of the switch circuit on the discharge branch, thereby controlling the conduction or shutoff of the discharge branch; The secondary controller comprises a drive signal generating circuit, the drive signal generating circuit comprises a first voltage sampling circuit, a second voltage sampling circuit, a first current source, a second current source, a first capacitor, a second capacitor and a first comparator, and the capacitance values ​​of the first capacitor and the second capacitor are the same; The first voltage sampling circuit is used to sample a first voltage value on the first end of the secondary winding, and the first current source is used to output a corresponding current according to the first voltage value to charge the first capacitor; the second voltage sampling circuit is used to sample a second voltage value on the first electrode of the synchronous rectifier transistor, and the second current source is used to output a corresponding current according to the second voltage value to charge the second capacitor; The two input terminals of the first comparator are used to sample the voltage values ​​on the first capacitor and the second capacitor respectively, and output a first flag signal when the voltage value on the first capacitor is equal to the voltage value on the second capacitor; the first flag signal is used to indicate the blanking time of the synchronous rectification transistor in the current cycle; The secondary controller is used to control the synchronous rectification transistor to remain in an on state during the blanking time period according to the first flag signal.

9. The multi-output flyback converter circuit according to claim 8, characterized in that: The sampling end of the first voltage sampling circuit is connected to the first end of the secondary winding, the output end of the first voltage sampling circuit is connected to the control end of the first current source, the output end of the first current source is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, and the first end of the first capacitor is also connected to the inverting input end of the first comparator; The sampling end of the second voltage sampling circuit is connected to the second end of the secondary winding, the output end of the second voltage sampling circuit is connected to the control end of the second current source, the output end of the second current source is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, and the first end of the second capacitor is also connected to the non-inverting input end of the first comparator.

10. The multi-output flyback converter circuit according to claim 8, characterized in that: The secondary controller further includes a second comparator, an inverting input terminal of the second comparator is connected to the output terminal of the second voltage sampling circuit, and a non-inverting input terminal of the second comparator is used to receive a first threshold voltage; the second comparator is used to output a first drive signal when the second voltage value is less than the first threshold voltage; The secondary controller is used to control the synchronous rectification transistor to turn on according to the first driving signal.

11. The multi-output flyback converter circuit according to claim 10, characterized in that: The drive signal generating circuit further includes a third comparator, wherein a non-inverting input terminal of the third comparator is connected to an output terminal of the second voltage sampling circuit, and an inverting input terminal of the third comparator is used to receive a second threshold voltage; the third comparator is used to output a second drive signal when the second voltage value is equal to the second threshold voltage; The secondary controller is further configured to pull down the voltage value on the control electrode of the synchronous rectification transistor according to the second driving signal, and to control the second voltage value to be equal to the second threshold voltage according to the second driving signal.

12. The multi-output flyback converter circuit according to claim 11, characterized in that: The drive signal generating circuit further includes a fourth comparator, wherein a non-inverting input terminal of the fourth comparator is connected to an output terminal of the second voltage sampling circuit, and an inverting input terminal of the fourth comparator is used to receive a third threshold voltage; the fourth comparator is used to output a third drive signal when the second voltage value is greater than the third threshold voltage; The secondary controller is further configured to control the synchronous rectification transistor to turn off according to the third driving signal.

13. The multi-output flyback converter circuit according to claim 12, characterized in that: The drive signal generating circuit further includes an SR latch, the output end of the second comparator and the output end of the fourth comparator are respectively connected to the set end and the reset end of the SR latch, and the output end of the SR latch is connected to the secondary controller; The SR latch is used to latch the states of the first drive signal and the third drive signal, and output a second flag signal according to the states of the first drive signal and the third drive signal; The secondary controller is further configured to control the synchronous rectification transistor to be turned on or off according to the logic state of the second flag signal.

14. The multi-output flyback converter circuit according to claim 13, characterized in that: The SR latch is used to output the logic state of the second flag signal as 1 when the logic state of the first drive signal is 1 and the logic state of the third drive signal is 0; and to output the logic state of the second flag signal as 0 when the logic state of the first drive signal is 0 and the logic state of the third drive signal is 1; The secondary controller is further configured to control the synchronous rectification transistor to be turned on when the logic state of the second flag signal is 1, and to control the synchronous rectification transistor to be turned off when the logic state of the second flag signal is 0.

15. The multi-output flyback converter circuit according to any one of claims 8 to 14, characterized in that: In a working cycle, the primary controller is used to control the opening of the primary transistor at a starting moment, and to close the primary transistor at a second moment after a first preset time has passed.

16. The multi-output flyback converter circuit according to claim 15, characterized in that: The secondary controller is used for controlling, at the second moment, opening a switch circuit on a target discharge branch among the at least two discharge branches, so that the target discharge branch is turned on; After the second moment, when it is detected that the logic state of the second flag signal is 1, controlling the synchronous rectification transistor to be turned on; After the synchronous rectification transistor is turned on, when the second driving signal is detected, controlling the voltage value on the control electrode of the synchronous rectification transistor to be pulled down, and controlling the second voltage value to be maintained at the second threshold voltage; When the first flag signal is detected at a fourth moment, the duration from the second moment to the fourth moment is determined to be the blanking time of the synchronous rectifier transistor in the current working cycle, and the synchronous rectifier transistor is controlled to remain in an on state during the blanking time period, and when the current value on the synchronous rectifier transistor decreases to a first current threshold, the second voltage value is controlled to be released from being maintained at the second threshold voltage; After the fourth time, when it is detected at a fifth time that the logic state of the second flag signal is 0, the synchronous rectification transistor is controlled to be turned off.

17. The multi-output flyback converter circuit according to claim 16, characterized in that: The secondary controller is further used to obtain the blanking time of the synchronous rectifier transistor in the current working cycle, and use the blanking time in the current working cycle as the blanking time of the synchronous rectifier transistor in the next working cycle; Alternatively, the product of the blanking time in the current working cycle and the preset proportionality coefficient is used as the blanking time of the synchronous rectification transistor in the next working cycle, and the preset proportionality coefficient is 0.8-1.

18. The multi-output flyback converter circuit according to claim 16, characterized in that: The primary controller is further configured to, after the fifth moment, turn on the primary transistor again to start the next working cycle when it is detected that the primary transistor has oscillated through zero and then passed a quarter of the oscillation cycle.

19. The multi-output flyback converter circuit according to claim 15, characterized in that: The secondary controller is further used to control the switch circuit on the target discharge branch to be closed and control the discharge switch on another discharge branch to be opened between the second moment and the fourth moment, so as to realize switching between the discharge branches.

20. The multi-output flyback converter circuit according to any one of claims 8 to 14, characterized in that: The switch circuit includes a first transistor and a second transistor; a first electrode of the first transistor is connected to a first end of the secondary winding, a second electrode of the first transistor is connected to a second electrode of the second transistor, and a first electrode of the second transistor is connected to a first end of an energy storage capacitor; control electrodes of the first transistor and the second transistor are both connected to the secondary controller; The secondary controller is used to control the on and off of the first transistor and the second transistor, thereby controlling the on and off of the switch circuit.

21. A control method for a multi-output flyback conversion circuit, characterized in that: The multi-channel output flyback conversion circuit is a multi-channel output flyback conversion circuit as claimed in any one of claims 8 to 14; The control method comprises: In a working cycle, the primary transistor is controlled to be turned on at a starting moment, and after a first preset time has elapsed, the primary transistor is turned off at a second moment; At the second moment, controlling to open a switch circuit on a target discharge branch among the at least two discharge branches, so that the target discharge branch is turned on; After the second moment, when it is detected that the logic state of the second flag signal is 1, controlling the synchronous rectification transistor to be turned on; When the first flag signal is detected at a fourth moment, determining the duration from the second moment to the fourth moment as the blanking time of the synchronous rectifier transistor in the current working cycle, and controlling the synchronous rectifier transistor to remain in an on state during the blanking time period; After the fourth moment, when it is detected at a fifth moment that the logic state of the second flag signal is 0, controlling the synchronous rectification transistor to be turned off; After the fifth moment, when it is detected that the primary transistor has oscillated through zero and then passed a quarter of the oscillation cycle, the primary transistor is turned on again to start the next working cycle.

22. The control method of the multi-output flyback converter circuit according to claim 21, characterized in that: The control method further comprises: after the synchronous rectification transistor is turned on, when the second driving signal is detected, controlling to lower the voltage value on the control electrode of the synchronous rectification transistor, and controlling the second voltage value to be maintained at the second threshold voltage; And when the current value on the synchronous rectification transistor decreases to a first current threshold, control is performed to release the second voltage value from being maintained at the second threshold voltage.

23. The control method of the multi-output flyback converter circuit according to claim 21 or 22, characterized in that: The control method further comprises: After the fifth moment, when it is detected that the primary transistor has oscillated through zero and then passed a quarter of the oscillation cycle, the primary transistor is turned on again to start the next working cycle.

24. A chip, characterized in that: The chip includes the on-time sampling circuit as described in claim 1 or 2; or the chip includes the drive signal generating circuit as described in any one of 3-7; or the chip includes the multi-output flyback conversion circuit as described in any one of 8-20.

25. An electronic device, characterized in that: The electronic device includes the on-time sampling circuit as described in claim 1 or 2; or the electronic device includes the drive signal generating circuit as described in any one of 3-7; or the electronic device includes the multi-output flyback conversion circuit as described in any one of 8-20.

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