CCDD rectifier, radio frequency energy acquisition circuit, chip and communication equipment

Abstract

The invention discloses a CCDD rectifier, a radio frequency energy acquisition circuit, a chip and communication equipment. The CCDD rectifier comprises a first signal line, a second signal line, a first rectifier module and a second rectifier module. The first signal line is configured to access a first AC voltage signal. The second signal line is configured to access a second AC voltage signal, and the polarity of the second AC voltage signal is opposite to the polarity of the first AC voltage signal. The first rectifier module comprises multiple stages of first capacitors and multiple stages of first switch modules. The second rectifier module comprises a plurality of stages of second capacitors and a plurality of second switch modules. The first rectifier module and the second rectifier module are used in combination. Compared with a CCDD rectifier structure in the prior art, the CCDD rectifier provided by the embodiment of the invention has the advantages that the circuit series of the CCDD rectifier is doubled on the premise of not increasing the circuit area and parasitic capacitance, and the conversion efficiency of the CCDD rectifier is improved.

Description

Technical Field

[0001] The present application relates to the technical field of rectifiers, and more specifically, to a CCDD rectifier, a radio frequency energy harvesting circuit, a chip and a communication device. Background Art

[0002] A multi-stage cross-coupled differential-drive (CCDD) rectifier forms a current path switching based on the alternating conduction and cutoff of complementary switching devices, thereby achieving the purpose of rectification. The complementary switching devices ensure the continuity of the current, avoid direct short circuit, and improve the conversion efficiency of the CCDD rectifier.

[0003] On the one hand, the voltage amplification factor of the CCDD rectifier is related to the circuit level of the CCDD rectifier. The larger the circuit level, the greater the current amplification factor. On the other hand, the output voltage of the CCDD rectifier is affected by the parasitic capacitance of each level. The increase in the circuit level will limit the output voltage or even reduce the output voltage. Since the parasitic capacitance of each level will limit the output voltage, the circuit level of the CCDD rectifier is set at 5 or 6 levels, and the voltage amplification factor of the CCDD rectifier is limited. Summary of the invention

[0004] Embodiments of the present application provide a CCDD rectifier, a radio frequency energy harvesting circuit, a chip, and a communication device.

[0005] The CCDD rectifier provided in the embodiment of the present application may include a first signal line, a second signal line, a first rectifier module and a second rectifier module. The first signal line is configured to access a first AC voltage signal. The second signal line is configured to access a second AC voltage signal, and the polarity of the second AC voltage signal is opposite to the polarity of the first AC voltage signal. The first rectifier module may include multiple first capacitors and multiple first switch modules. The second rectifier module may include multiple second capacitors and multiple second switch modules. Among them, the first end of each first capacitor is connected to the first signal line, the first switch module of each level is connected to the second end of the corresponding first capacitor of the first level, and the first switch module of each level is also connected to the first switch module of the next level, and the first switch module of each level is configured to be periodically turned on and off so that the first capacitor of each level is periodically charged and discharged. The first end of each level of the second capacitor is connected to the second signal line, the second switch module of each level is connected to the second end of the corresponding first-level second capacitor, the first-level second switch module is connected to the last-level first switch module, and each level of the second switch module is also connected to the next-level second switch module. Each level of the second switch module is configured to be periodically turned on and off so that the second capacitor of each level is periodically charged and discharged.

[0006] It is understandable that the first rectifier module and the second rectifier module can be used in combination, so that the voltage amplification factor of the CCDD rectifier is determined according to the sum of the number of stages of the first switch module and the number of stages of the second switch module. Compared with the CCDD rectifier structure in the related art, the CCDD rectifier provided in the embodiment of the present application doubles the number of circuit stages of the CCDD rectifier without increasing the circuit area and parasitic capacitance, thereby improving the conversion efficiency of the CCDD rectifier.

[0007] In some embodiments, each stage of the first switch module is configured to be periodically turned on and off according to the second AC voltage signal, and each stage of the second switch module is configured to be periodically turned on and off according to the first AC voltage signal.

[0008] In this way, by multiplexing the first AC voltage signal provided by the first signal line and the second AC voltage signal provided by the second signal line, the CCDD rectifier does not need to be additionally provided with a control signal line, thereby saving circuit resources.

[0009] In some embodiments, each first switch module includes a first transistor and a second transistor. The first electrode of the first transistor is connected to the first electrode of the second transistor, and is connected to the second end of the corresponding first capacitor of the first stage. The second electrode of the first transistor is connected to the corresponding first switch module of the previous stage, and the second electrode of the second transistor is connected to the corresponding first switch module of the next stage. The second electrode of the second transistor of the last first switch module is connected to the first second switch module.

[0010] In this way, a cascade relationship of multiple first switch modules can be achieved based on the connection relationship between the first transistor and the second transistor.

[0011] In some embodiments, the second electrode of the first transistor of the first switching module of the first stage is grounded.

[0012] In this way, in the first working cycle of the CCDD rectifier, the first signal line can charge the first capacitor of the first stage.

[0013] In some embodiments, each first switch module includes a third capacitor, a first end of the third capacitor is connected to the second signal line, and a second end of the third capacitor is connected to the control electrode of the first transistor and the control electrode of the second transistor.

[0014] In this way, the third capacitor can quickly release or absorb charges, helping the transistor to respond to signal changes more quickly.

[0015] In some embodiments, when the first transistor is turned on, the second transistor is turned off; when the second transistor is turned on, the first transistor is turned off.

[0016] In this way, the first transistor and the second transistor can be alternately turned on and off to switch the current path, thereby achieving the purpose of rectification. The first transistor and the second transistor can be used as complementary switching devices to ensure the continuity of the current, avoid direct short circuit, and improve the conversion efficiency of the rectifier.

[0017] In some embodiments, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor, or the first transistor is a PMOS transistor and the second transistor is an NMOS transistor; the body terminal of the first transistor is connected to the gate terminal, and the body terminal of the second transistor is connected to the gate terminal.

[0018] In this way, the body terminal of the first transistor is connected to the gate terminal, and the body terminal of the second transistor is connected to the gate terminal, which can reduce the threshold voltage of the transistors and further reduce the output voltage loss of the first rectifier module.

[0019] In some embodiments, each level of the second switch module includes a third transistor and a fourth transistor. The first electrode of the third transistor is connected to the first electrode of the fourth transistor and to the second end of the second capacitor of the corresponding level, the second electrode of the third transistor is connected to the corresponding second switch module of the previous level, and the second electrode of the fourth transistor is connected to the corresponding second switch module of the next level. The second electrode of the third transistor of the first level of the second switch module is connected to the first switch module of the last level.

[0020] In this way, a cascade relationship of multiple second switch modules can be achieved based on the connection relationship between the third transistor and the fourth transistor.

[0021] In some embodiments, the second electrode of the fourth transistor of the second switch module of the last stage is configured to provide the output voltage of the rectifier.

[0022] In this way, the second electrode of the fourth transistor of the second switch module of the last stage can be set as the output end of the CCDD rectifier.

[0023] In some embodiments, each level of the second switch module includes a fourth capacitor, a first end of each of the fourth capacitors is connected to the signal line, and a second end of the fourth capacitor is connected to the control electrode of the third transistor and the control electrode of the fourth transistor.

[0024] In this way, the fourth capacitor can quickly release or absorb charges, helping the transistor to respond to signal changes more quickly.

[0025] In some embodiments, when the third transistor is turned on, the fourth transistor is turned off; when the fourth transistor is turned on, the third transistor is turned off.

[0026] In this way, the third transistor and the fourth transistor can be alternately turned on and off to form a current path switch, thereby achieving the purpose of rectification. The third transistor and the fourth transistor can be used as complementary switching devices to ensure the continuity of the current, avoid direct short circuit phenomenon, and improve the conversion efficiency of the rectifier.

[0027] In some embodiments, the third transistor is an NMOS transistor, the fourth transistor is a PMOS transistor, or the third transistor is a PMOS transistor, the fourth transistor is an NMOS transistor; the body terminal of the third transistor is connected to the gate terminal, and the body terminal of the fourth transistor is connected to the gate terminal.

[0028] In this way, the body terminal of the third transistor is connected to the gate terminal, and the body terminal of the fourth transistor is connected to the gate terminal, which can reduce the threshold voltage of the transistor, thereby reducing the output voltage loss of the second rectifier module.

[0029] In some embodiments, the rectifier further includes a plurality of bias modules. Each bias module is connected between the second end of the corresponding first-level first capacitor and the control end of the corresponding first-level first switch module, and each bias module is configured to provide a bias voltage to the second end of the first capacitor and the control end of the corresponding first-level first switch module; or each bias module is connected between the second end of the corresponding first-level second capacitor and the control end of the corresponding first-level second switch module, and each bias module is configured to provide a bias voltage to the second end of the second capacitor and the control end of the corresponding first-level second switch module.

[0030] In this way, the bias module can provide a bias voltage to the transistors of the first switch module and the second switch module. The bias voltage can increase the on-resistance of the transistor, reduce the reverse leakage of the transistor to the input end, and reduce the loss of the output voltage.

[0031] In some embodiments, each bias module includes a bias transistor. A first electrode of the bias transistor is connected to a control electrode and connected to a second end of a corresponding first-level first capacitor, and a second electrode of the bias transistor is connected to a control end of a corresponding first-level first switch module; or a first electrode of the bias transistor is connected to a control electrode and connected to a second end of a corresponding first-level second capacitor, and a second electrode of the bias transistor is connected to a control end of a corresponding first-level second switch module.

[0032] In this way, the bias transistor can provide a bias voltage to the transistors of the first switch module and the second switch module.

[0033] In some embodiments, each bias module includes a bias diode. The anode of the bias diode is connected to the second end of the corresponding first-level first capacitor, and the cathode of the bias diode is connected to the control end of the corresponding first-level first switch module; or the anode of the bias diode is connected to the second end of the corresponding first-level second capacitor, and the cathode of the bias diode is connected to the control end of the corresponding first-level second switch module.

[0034] In this way, the bias diode can provide a bias voltage for the transistors of the first switch module and the second switch module.

[0035] In some embodiments, the bias transistor is an NMOS transistor, and a body terminal of the bias transistor is connected to a gate terminal.

[0036] In this way, the gate terminal and the body terminal of the bias transistor are connected, which can reduce the threshold voltage of the bias transistor, and further reduce the output voltage loss of the first rectifier module and the output voltage loss of the second rectifier module.

[0037] The radio frequency energy collection circuit provided in the embodiment of the present application. The radio frequency energy collection circuit includes a collection and conversion circuit, a storage capacitor and the CCDD rectifier of the above embodiment. The collection and conversion circuit is configured to collect radio frequency signals and convert the radio frequency signals into corresponding AC voltage signals for output. The CCDD rectifier is configured to convert the AC voltage signal output by the conversion circuit into a DC voltage signal for output. The storage capacitor is configured to store the DC voltage signal output by the CCDD rectifier.

[0038] In some embodiments, the acquisition and conversion circuit may include an antenna, a first matching network, and a second matching network. The antenna is configured to acquire a radio frequency signal and convert the radio frequency signal into a corresponding single-ended voltage signal. The first matching network is configured to adjust the input impedance of the antenna so that the antenna matches the impedance of the CCDD rectifier. The second matching network is configured to convert the single-ended voltage signal into a corresponding double-ended differential voltage signal and provide it to the CCDD rectifier.

[0039] In some embodiments, the first matching network includes a first matching capacitor, a second matching capacitor and a matching inductor, wherein the first end of the first matching capacitor is connected to the first end of the matching inductor and is connected to the antenna. The second end of the first matching capacitor is grounded, the second end of the matching inductor is connected to the first end of the second matching capacitor and is connected to the second matching network, and the second end of the second matching capacitor is grounded.

[0040] An embodiment of the present application further provides a chip, which may include the radio frequency energy harvesting circuit of the above embodiment.

[0041] An embodiment of the present application further provides a communication device, which may include the chip or radio frequency energy harvesting circuit of the above embodiment.

[0042] The embodiments of the present application provide a CCDD rectifier, a radio frequency energy collection circuit, a chip and a communication device. The CCDD rectifier may include a first signal line, a second signal line, a first rectifier module and a second rectifier module. The first signal line is configured to access a first AC voltage signal. The second signal line is configured to access a second AC voltage signal, and the polarity of the second AC voltage signal is opposite to the polarity of the first AC voltage signal. The first rectifier module may include multiple first capacitors and multiple first switch modules. The second rectifier module may include multiple second capacitors and multiple second switch modules. Among them, the first end of each first capacitor is connected to the first signal line, the first switch module of each level is connected to the second end of the corresponding first capacitor of the first level, and the first switch module of each level is also connected to the first switch module of the next level, and the first switch module of each level is configured to be periodically turned on and off so that the first capacitor of each level is periodically charged and discharged. The first end of each level of the second capacitor is connected to the second signal line, the second switch module of each level is connected to the second end of the corresponding first-level second capacitor, the first-level second switch module is connected to the last-level first switch module, and each level of the second switch module is also connected to the next-level second switch module. Each level of the second switch module is configured to be periodically turned on and off so that the second capacitor of each level is periodically charged and discharged.

[0043] In the CCDD rectifier of the embodiment of the present application, the first rectifier module and the second rectifier module can be used in combination, so that the voltage amplification factor of the CCDD rectifier is determined according to the sum of the number of stages of the first switch module and the number of stages of the second switch module. Compared with the CCDD rectifier structure in the related art, the CCDD rectifier provided in the embodiment of the present application doubles the number of circuit stages of the CCDD rectifier without increasing the circuit area and parasitic capacitance, thereby improving the conversion efficiency of the CCDD rectifier.

[0044] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0046] Figure 1 is a schematic diagram of a CCDD rectifier of a series-parallel structure according to an embodiment of the present application;

[0047] Figure 2is a circuit diagram of a CCDD rectifier of a series-parallel structure in certain embodiments of the present application;

[0048] Figure 3 is a circuit diagram of a CCDD rectifier in the related art;

[0049] Figure 4 is a circuit diagram of a first-stage circuit of a series-parallel structure in an embodiment of the present application;

[0050] Figure 5 is a circuit diagram of the last stage circuit of the series-parallel structure of the implementation mode of the present application;

[0051] Figure 6 is a schematic diagram of a series-parallel CCDD rectifier with dynamic lead bias according to an embodiment of the present application;

[0052] Figure 7 is a circuit diagram of a series-parallel CCDD rectifier with dynamic lead bias according to certain embodiments of the present application;

[0053] Figure 8 It is a circuit diagram of a first-stage circuit of a series-parallel structure of a dynamic lead bias according to an embodiment of the present application;

[0054] Fig. 9 It is a circuit diagram of the last stage circuit of the series-parallel structure of the dynamic lead bias in the implementation mode of the present application;

[0055] Fig.10 is a schematic diagram of a radio frequency energy harvesting circuit according to an embodiment of the present application;

[0056] Fig.11 is a schematic diagram of a chip and a communication device according to an embodiment of the present application;

[0057] Fig.12 is a schematic diagram of an output voltage of a CCDD rectifier in the related art;

[0058] Fig.13 Schematic diagram of output voltage of CCDD rectifier with series-parallel structure in the embodiment of the present application;

[0059] Fig.14 Schematic diagram of the output voltage of a series-parallel CCDD rectifier with dynamic lead bias according to an embodiment of the present application.

[0060] Reference numerals:

[0061] Rectifier 100, first signal line 10, second signal line 20, first rectifier module 30, first capacitor 31, first switch module 32, first transistor 321, second transistor 322, third capacitor 323, second rectifier module 40, second capacitor 41, second switch module 42, third transistor 421, fourth transistor 422, fourth capacitor 423, bias module 50, bias transistor 51, RF energy collection circuit 1000, collection and conversion circuit 200, antenna 210, first matching network 220, first matching capacitor 221, second matching capacitor 222, matching inductor 223, second matching network 230, storage capacitor 300, chip 2000, communication device 3000. DETAILED DESCRIPTION

[0062] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0063] A multi-stage cross-coupled differential-drive (CCDD) rectifier forms a current path switching based on the alternating conduction and cutoff of complementary switching devices, thereby achieving the purpose of rectification. The complementary switching devices ensure the continuity of the current, avoid direct short circuit, and improve the conversion efficiency of the CCDD rectifier.

[0064] On the one hand, the voltage amplification factor of the CCDD rectifier is related to the circuit level of the CCDD rectifier. The larger the circuit level, the greater the current amplification factor. On the other hand, the output voltage of the CCDD rectifier is affected by the parasitic capacitance of each level. The increase in the circuit level will limit the output voltage or even reduce the output voltage. Since the parasitic capacitance of each level will limit the output voltage, the circuit level of the CCDD rectifier is set at 5 or 6 levels, and the voltage amplification factor of the CCDD rectifier is limited.

[0065] The present application embodiment provides a CCDD rectifier (such as Figure 1 , Figure 2 , Figures 4 to 9 As shown, the CCDD rectifier has a series-parallel structure. The CCDD rectifier provided in the embodiment of the present application can increase the number of circuit levels to twice that of the prior art without increasing the circuit area and parasitic capacitance, and the output voltage is also increased by two times, thereby improving the power conversion efficiency of the CCDD rectifier.

[0066] Reference Figure 1The CCDD rectifier 100 provided in the embodiment of the present application may include a first signal line 10, a second signal line 20, a first rectifier module 30, and a second rectifier module 40. The first signal line 10 is configured to access a first AC voltage signal. The second signal line 20 is configured to access a second AC voltage signal, and the polarity of the second AC voltage signal is opposite to that of the first AC voltage signal. The first rectifier module 30 may include a multi-stage first capacitor 31 and a multi-stage first switch module 32. The second rectifier module 40 may include a multi-stage second capacitor 41 and a plurality of second switch modules 42. Among them, the first end of each stage of the first capacitor 31 is connected to the first signal line 10, and the first switch module 32 of each stage is connected to the second end of the corresponding first capacitor 31 of the first stage. Each first switch module 32 of each stage is also connected to the first switch module 32 of the next stage, and each first switch module 32 of each stage is configured to be periodically turned on and off so that each stage of the first capacitor 31 is periodically charged and discharged. The first end of each level of the second capacitor 41 is connected to the second signal line 20, the second switch module 42 of each level is connected to the second end of the corresponding first-level second capacitor 41, the first-level second switch module 42 is connected to the last-level first switch module 32, and each level of the second switch module 42 is also connected to the next-level second switch module 42. Each level of the second switch module 42 is configured to be periodically turned on and off so that each level of the second capacitor 41 is periodically charged and discharged.

[0067] Specifically, the first signal line 10 and the second signal line 20 can be set as differential input signal lines of the CCDD rectifier 100. The CCDD rectifier 100 can perform rectification according to the differential signal of the first AC voltage signal and the second AC voltage signal, thereby eliminating the influence of common mode noise and improving the accuracy of the CCDD rectifier 100.

[0068] Each stage of the first switch module 32 and each stage of the second switch module 42 are periodically turned on and off, so that the first signal line 10 sequentially charges each stage of the first capacitor 31, and the second signal line 20 sequentially charges each stage of the second capacitor 41. The rectifier 100 forms a current path switching based on the complementary switching devices alternately turned on and off, thereby achieving the purpose of rectification. The complementary switching devices ensure the continuity of the current, avoid direct short circuit phenomenon, and improve the conversion efficiency of the rectifier 100.

[0069] Since the first-stage second switch module 42 can be cascaded with the last-stage first switch module, the first-stage second switch module 42 can serve as the next cascade unit of the last-stage switch module, so that the voltage amplification factor of the CCDD rectifier 100 is determined according to the sum of the number of stages of the first switch module 32 and the number of stages of the second switch module 42.

[0070] The first rectifier module 30 may include a plurality of cascaded first switch modules 32, and the first rectifier module 30 may provide an amplified output voltage at the N1 node, and provide the output voltage to the second rectifier module 40. The second rectifier module 40 may include a plurality of cascaded second switch modules 42, and the second rectifier module 40 may amplify the voltage connected to the N1 node and output it at the N2 node. The amplification factor of the first rectifier module 30 may be set to m, the amplification factor of the second rectifier module 40 may be set to n, and the amplification factor of the CCDD rectifier 100 may be set to m+n.

[0071] by Figure 2 For example, the first signal line 10 can be set as the signal line VP, and the second signal line 20 can be set as the signal line VN. Capacitor elements C1, C4, C7 and C10 can be set as four cascaded first capacitors 31. Capacitor elements C13, C16, C19 and C22 can be set as four cascaded second capacitors 41.

[0072] In the first working cycle of the CCDD rectifier 100, the signal line VP can charge the capacitor element C1. In the second working cycle of the CCDD rectifier 100, the capacitor element C1 can be discharged through the first-stage first switch module 32. In the third working cycle of the CCDD rectifier 100, the signal line VP can charge the capacitor element C4, and in the fourth working cycle of the CCDD rectifier 100, the capacitor element C4 can be discharged through the second-stage first switch module 32. In the fifth working cycle of the CCDD rectifier 100, the signal line VP can charge the capacitor element C7. In the sixth working cycle of the CCDD rectifier 100, the capacitor element C7 can be discharged through the third-stage first switch module 32. In the seventh working cycle of the CCDD rectifier 100, the signal line VP can charge the capacitor element C10. In the eighth working cycle of the CCDD rectifier 100, the capacitor element C10 can be discharged through the fourth-stage first switch module 32.

[0073] The charging and discharging processes of capacitor element C13, capacitor element C16, capacitor element C19 and capacitor element C22 may refer to the charging and discharging processes of capacitor element C1, capacitor element C4, capacitor element C7 and capacitor element C10, and are not described in detail here.

[0074] The voltage at which the capacitor element discharges each time can be set to V0, the circuit level of the first rectifier module 30 is 4, and the voltage output by the first rectifier module 30 at the node N1 can be set to 4V0. The circuit level of the second rectifier module 40 is 4, and the voltage output by the second rectifier module 40 at the node N2 can be set to 8V0, and the circuit level of the CCDD rectifier 100 can be set to 8 levels.

[0075] Reference Figure 3 In the related art, the rectifier modules of the CCDD rectifier 100 are arranged in parallel, and the output voltage is proportional to the number of circuit stages of the switch module. Affected by the parasitic capacitance of each stage, the increase in the number of stages will limit the output voltage or even reduce the output voltage. Generally, the CCDD rectifier 100 of this structure has 5 to 6 stages.

[0076] It is understandable that the first rectifier module 30 and the second rectifier module 40 can be used in combination, so that the voltage amplification factor of the CCDD rectifier 100 is determined according to the sum of the number of stages of the first switch module 32 and the number of stages of the second switch module 42 .

[0077] Thus, compared with the CCDD rectifier 100 structure in the related art, the CCDD rectifier 100 provided in the embodiment of the present application doubles the number of circuit levels of the CCDD rectifier 100 without increasing the circuit area and parasitic capacitance, thereby improving the conversion efficiency of the CCDD rectifier 100.

[0078] In some embodiments, each stage of the first switch module 32 is configured to be periodically turned on and off according to the second AC voltage signal, and each stage of the second switch module 42 is configured to be periodically turned on and off according to the first AC voltage signal.

[0079] Specifically, the second AC voltage signal provided by the second signal line 20 can control the periodic on and off of each first switch module 32. The second signal line 20 can be used as a control signal line for each first switch module 32, and the CCDD rectifier 100 does not need to set an additional control signal line for the first switch module 32, saving circuit resources.

[0080] by Figure 2 For example, the first switch module 32 may include transistor MN1, transistor MP1, transistor MN2, transistor MP2, transistor MN3, transistor MP3, transistor MN4 and transistor MP4, and the signal line VN may be connected to the control electrodes of transistor MN1, transistor MP1, transistor MN2, transistor MP2, transistor MN3, transistor MP3, transistor MN4 and transistor MP4.

[0081] The first AC voltage signal provided by the first signal line 10 can control the periodic on and off of each second switch module 42. The first signal line 10 can be used as a control signal line for each second switch module 42. The CCDD rectifier 100 does not need to set up an additional control signal line for the second switch module 42, saving circuit resources.

[0082] by Figure 2For example, the second switch module 42 may include transistor MN5, transistor MP5, transistor MN6, transistor MP6, transistor MN7, transistor MP7, transistor MN8 and transistor MP8, and the signal line VP may be connected to the control electrodes of transistor MN5, transistor MP5, transistor MN6, transistor MP6, transistor MN7, transistor MP7, transistor MN8 and transistor MP8.

[0083] The second AC voltage signal provided by the second signal line 20 can control the periodic on and off of each first switch module 32. The second signal line 20 can be used as a control signal line for each first switch module 32. The CCDD rectifier 100 does not need to set an additional control signal line for the first switch module 32, saving circuit resources.

[0084] In this way, by multiplexing the first AC voltage signal provided by the first signal line 10 and the second AC voltage signal provided by the second signal line 20 , the CCDD rectifier 100 does not need to set up an additional control signal line, thereby saving circuit resources.

[0085] In some embodiments, each first switch module 32 includes a first transistor 321 and a second transistor 322. The first electrode of the first transistor 321 is connected to the first electrode of the second transistor 322, and is connected to the second end of the corresponding first capacitor 31. The second electrode of the first transistor 321 is connected to the corresponding first switch module 32 of the previous stage, and the second electrode of the second transistor 322 is connected to the corresponding first switch module 32 of the next stage. The second electrode of the second transistor 322 of the last first switch module 32 is connected to the first second switch module 42.

[0086] Specifically, Figure 2 For example, in the first-stage first switch module 32, the first transistor 321 can be set to transistor MN1, and the second transistor 322 can be set to transistor MP1. In the second-stage first switch module 32, the first transistor 321 can be set to MN2, and the second transistor 322 can be set to MP2. In the third-stage first switch module 32, the first transistor 321 can be set to MN3, and the second transistor 322 can be set to MP3. In the fourth-stage first switch module 32, the first transistor 321 can be set to MN4, and the second transistor 322 can be set to MP4.

[0087] The first electrode of transistor MN1 is connected to the first electrode of transistor MP1 and to capacitor C1. The first electrode of transistor MN2 is connected to the first electrode of transistor MP2 and to capacitor C4. The first electrode of transistor MN3 is connected to the first electrode of transistor MP3 and to capacitor C7. The first electrode of transistor MN4 is connected to the first electrode of transistor MP4 and to capacitor C10. The second electrode of transistor MP1 is connected to the second electrode of transistor MN2, the second electrode of transistor MP2 is connected to the second electrode of transistor MN3, the second electrode of transistor MP3 is connected to the second electrode of transistor MN4, and the second electrode of transistor MN4 is connected to node N1.

[0088] In this way, a cascade connection relationship of a plurality of first switch modules 32 can be achieved based on the connection relationship between the first transistor 321 and the second transistor 322 .

[0089] In some embodiments, the second electrode of the first transistor 321 of the first-stage first switch module 32 is grounded.

[0090] Specifically, Figure 4 For example, in the first-stage first switch module 32, the first transistor 321 can be set as the transistor MN1, and the second transistor 322 can be set as the transistor MP1. The first electrode of the transistor MN1 can be grounded.

[0091] In the first working cycle of the CCDD rectifier 100, the signal line VN can control the transistor MN1 to be turned on, so that the voltage connected to the first electrode of the transistor MN1 can be written into the first end of the capacitor C1, and the first end of the capacitor C1 can be connected to a low level. The second end of the capacitor C1 is connected to the signal line VP, and the AC voltage signal provided by the signal line VP can charge the capacitor C1.

[0092] Thus, in the first working cycle of the CCDD rectifier 100 , the first signal line 10 can charge the first capacitor 31 of the first stage.

[0093] In some embodiments, each first switch module 32 includes a third capacitor 323 , a first end of the third capacitor 323 is connected to the second signal line 20 , and a second end of the third capacitor 323 is connected to the control electrode of the first transistor 321 and the control electrode of the second transistor 322 .

[0094] Specifically, Figure 2For example, in the first-stage first switch module 32, the third capacitor 323 may include a capacitor C2 and a capacitor C3. The first end of the capacitor C2 may be connected to the signal line VN, and the second end of the capacitor C2 may be connected to the control electrode of the transistor MN1. The first end of the capacitor C3 may be connected to the signal line VN, and the second end of the capacitor C3 may be connected to the control electrode of the transistor MP1.

[0095] In the second-stage first switch module 32, the third capacitor 323 can be set as a capacitor element C5 and a capacitor element C6. The first end of the capacitor element C5 can be connected to the signal line VN, and the second end of the capacitor element C5 can be connected to the control electrode of the transistor MN2. The first end of the capacitor element C6 can be connected to the signal line VN, and the second end of the capacitor element C6 can be connected to the control electrode of the transistor MP2.

[0096] In the third-stage first switch module 32, the third capacitor 323 can be set as a capacitor element C8 and a capacitor element C9. The first end of the capacitor element C8 can be connected to the signal line VN, and the second end of the capacitor element C8 can be connected to the control electrode of the transistor MN3. The first end of the capacitor element C9 can be connected to the signal line VN, and the second end of the capacitor element C9 can be connected to the control electrode of the transistor MP3.

[0097] In the fourth-stage first switch module 32, the third capacitor 323 can be set as a capacitor element C11 and a capacitor element C12. The first end of the capacitor element C11 can be connected to the signal line VN, and the second end of the capacitor element C11 can be connected to the control electrode of the transistor MN4. The first end of the capacitor element C12 can be connected to the signal line VN, and the second end of the capacitor element C12 can be connected to the control electrode of the transistor MP4.

[0098] The capacitor connected to the control electrode of the transistor can be used as a buffer to help drive the transistor, reduce the current required to drive the transistor, thereby reducing power consumption and increasing the switching speed of the circuit. The third capacitor 323 can store charge. When the control signal changes, the third capacitor 323 can quickly release or absorb charge to help the transistor respond to the signal change faster.

[0099] In this way, the third capacitor 323 can quickly release or absorb charges, helping the transistor to respond to signal changes more quickly.

[0100] In some embodiments, when the first transistor 321 is turned on, the second transistor 322 is turned off. When the second transistor 322 is turned on, the first transistor 321 is turned off.

[0101] Specifically, in the first-stage first switch module 32, when the transistor MN1 is turned on, the transistor MP1 is turned off, and the capacitor C1 can be charged. When the transistor MN1 is turned off, the transistor MP1 is turned on, and the capacitor C1 can be discharged through the transistor MP1. In the second-stage first switch module 32, when the transistor MN2 is turned on, the transistor MP2 is turned off, and the capacitor C4 can be charged. When the transistor MN2 is turned off, the transistor MP2 is turned on, and the capacitor C4 can be discharged through the transistor MP2. In the third-stage first switch module 32, when the transistor MN3 is turned on, the transistor MP3 is turned off, and the capacitor C7 can be charged. When the transistor MN3 is turned off, the transistor MP3 is turned on, and the capacitor C7 can be discharged through the transistor MP3. In the fourth-stage first switch module 32, when the transistor MN4 is turned on, the transistor MP4 is turned off, and the capacitor C10 can be charged. When the transistor MN4 is turned off, the transistor MP4 is turned on, and the capacitor C10 can be discharged through the transistor MP4.

[0102] In this way, the first transistor 321 and the second transistor 322 can be alternately turned on and off to form a current path switch, thereby achieving the purpose of rectification. The first transistor 321 and the second transistor 322 can be used as complementary switching devices to ensure the continuity of the current, avoid direct short circuit phenomenon, and improve the conversion efficiency of the rectifier 100.

[0103] In some embodiments, the first transistor 321 is an NMOS transistor and the second transistor 322 is a PMOS transistor, or the first transistor 321 is a PMOS transistor and the second transistor 322 is an NMOS transistor. The body terminal of the first transistor 321 is connected to the gate terminal, and the body terminal of the second transistor 322 is connected to the gate terminal.

[0104] Specifically, the first transistor 321 and the second transistor 322 can both be set as MOS tubes. The gate terminal and the body terminal of the first transistor 321 are connected, which can reduce the threshold voltage of the first transistor 321. The gate terminal and the body terminal of the second transistor 322 are connected, which can reduce the threshold voltage of the second transistor 322, thereby reducing the output voltage loss of the first rectifier module 30.

[0105] by Figure 2 For example, the voltage at which the capacitor element discharges each time can be set to V0, the circuit level of the first rectifier module 30 is 4, and the voltage output by the first rectifier module 30 at the node N1 can be set to 4V0.

[0106] The voltage amplitude provided by the first signal line 10 can be set to VRF, the threshold voltage of the first transistor 321 and the threshold voltage of the second transistor 322 can both be set to VTH, V0=VRF-VTH, and the voltage output by the first rectifier module 30 at the node N1 can be set to 4 (VRF-VTH).

[0107] In this way, the body terminal of the first transistor 321 is connected to the gate terminal, and the body terminal of the second transistor 322 is connected to the gate terminal, which can reduce the threshold voltage of the transistors and further reduce the output voltage loss of the first rectifier module 30.

[0108] In some embodiments, each level of the second switch module 42 includes a third transistor 421 and a fourth transistor 422. The first electrode of the third transistor 421 is connected to the first electrode of the fourth transistor 422 and to the second end of the corresponding first-level second capacitor 41, the second electrode of the third transistor 421 is connected to the corresponding previous-level second switch module 42, and the second electrode of the fourth transistor 422 is connected to the corresponding next-level second switch module 42. The second electrode of the third transistor 421 of the first-level second switch module 42 is connected to the last-level first switch module 32.

[0109] Specifically, Figure 2 For example, in the first-stage second switch module 42, the third transistor 421 can be set to transistor MN5, and the fourth transistor 422 can be set to transistor MP5. In the second-stage second switch module 42, the third transistor 421 can be set to MN6, and the fourth transistor 422 can be set to MP6. In the third-stage second switch module 42, the third transistor 421 can be set to MN7, and the fourth transistor 422 can be set to MP7. In the fourth-stage second switch module 42, the third transistor 421 can be set to MN8, and the fourth transistor 422 can be set to MP8.

[0110] The first electrode of transistor MN5 is connected to the first electrode of transistor MP5 and to capacitor C13. The first electrode of transistor MN6 is connected to the first electrode of transistor MP6 and to capacitor C16. The first electrode of transistor MN7 is connected to the first electrode of transistor MP7 and to capacitor C19. The first electrode of transistor MN8 is connected to the first electrode of transistor MP8 and to capacitor C22. The first electrode of transistor MP5 can be connected to node N1. The second electrode of transistor MP5 is connected to the second electrode of transistor MN6, the second electrode of transistor MP6 is connected to the second electrode of transistor MN7, and the second electrode of transistor MP7 is connected to the second electrode of transistor MN8.

[0111] In this way, a cascade connection relationship of a plurality of second switch modules 42 can be realized based on the connection relationship between the third transistor 421 and the fourth transistor 422 .

[0112] In some embodiments, the second electrode of the fourth transistor 422 of the last-stage second switch module 42 is configured to provide the output voltage of the rectifier 100 .

[0113] Specifically, Figure 5 For example, in the last-stage second switch module 42, the third transistor 421 can be set as the transistor MN8, the fourth transistor 422 can be set as the transistor MP8, and the second electrode of the transistor MP8 can be connected to the node VOUT.

[0114] Each time the capacitor is discharged, the voltage can be set to V0. The second electrode of the transistor MP8 can provide an output voltage of 8V0 as the output voltage of the CCDD rectifier 100.

[0115] In some embodiments, each level of the second switch module 42 includes a fourth capacitor 423 , a first end of each fourth capacitor 423 is connected to a signal line, and a second end of the fourth capacitor 423 is connected to a control electrode of the third transistor 421 and a control electrode of the fourth transistor 422 .

[0116] Specifically, Figure 2 For example, in the first-stage second switch module 42, the fourth capacitor 423 may include a capacitor C14 and a capacitor C15. The first end of the capacitor C14 may be connected to the signal line VP, and the second end of the capacitor C14 may be connected to the control electrode of the transistor MN5. The first end of the capacitor C15 may be connected to the signal line VP, and the second end of the capacitor C15 may be connected to the control electrode of the transistor MP5.

[0117] In the second-stage second switch module 42, the fourth capacitor 423 can be set to a capacitor element C17 and a capacitor element C18. The first end of the capacitor element C17 can be connected to the signal line VP, and the second end of the capacitor element C17 can be connected to the control electrode of the transistor MN6. The first end of the capacitor element C18 can be connected to the signal line VP, and the second end of the capacitor element C18 can be connected to the control electrode of the transistor MP6.

[0118] In the third-stage second switch module 42, the fourth capacitor 423 can be set as a capacitor element C20 and a capacitor element C21. The first end of the capacitor element C20 can be connected to the signal line VP, and the second end of the capacitor element C20 can be connected to the control electrode of the transistor MN7. The first end of the capacitor element C21 can be connected to the signal line VP, and the second end of the capacitor element C21 can be connected to the control electrode of the transistor MP7.

[0119] In the fourth-stage second switch module 42, the fourth capacitor 423 can be set as a capacitor element C23 and a capacitor element C24. The first end of the capacitor element C23 can be connected to the signal line VP, and the second end of the capacitor element C23 can be connected to the control electrode of the transistor MN8. The first end of the capacitor element C24 can be connected to the signal line VP, and the second end of the capacitor element C24 can be connected to the control electrode of the transistor MP8.

[0120] The capacitor connected to the control electrode of the transistor can be used as a buffer to help drive the transistor, reduce the current required to drive the transistor, thereby reducing power consumption and increasing the switching speed of the circuit. The fourth capacitor 423 can store charge. When the control signal changes, the fourth capacitor 423 can quickly release or absorb charge to help the transistor respond to the signal change faster.

[0121] In this way, the fourth capacitor 423 can quickly release or absorb charges, helping the transistor to respond to signal changes more quickly.

[0122] In some embodiments, when the third transistor 421 is turned on, the fourth transistor 422 is turned off. When the fourth transistor 422 is turned on, the third transistor 421 is turned off.

[0123] Specifically, in the first-stage second switch module 42, when the transistor MN5 is turned on, the transistor MP5 is turned off, and the capacitor C13 can be charged. When the transistor MN5 is turned off, the transistor MP5 is turned on, and the capacitor C13 can be discharged through the transistor MP5. In the second-stage second switch module 42, when the transistor MN6 is turned on, the transistor MP6 is turned off, and the capacitor C16 can be charged. When the transistor MN6 is turned off, the transistor MP6 is turned on, and the capacitor C16 can be discharged through the transistor MP6. In the third-stage second switch module 42, when the transistor MN7 is turned on, the transistor MP7 is turned off, and the capacitor C19 can be charged. When the transistor MN7 is turned off, the transistor MP7 is turned on, and the capacitor C19 can be discharged through the transistor MP7. In the fourth-stage second switch module 42, when the transistor MN8 is turned on, the transistor MP8 is turned off, and the capacitor C22 can be charged. When the transistor MN8 is turned off, the transistor MP8 is turned on, and the capacitor C22 can be discharged through the transistor MP8.

[0124] In this way, the third transistor 421 and the fourth transistor 422 can be alternately turned on and off to form a current path switch, thereby achieving the purpose of rectification. The third transistor 421 and the fourth transistor 422 can be used as complementary switching devices to ensure the continuity of the current, avoid direct short circuit phenomenon, and improve the conversion efficiency of the rectifier 100.

[0125] In some embodiments, the third transistor 421 is an NMOS transistor, the fourth transistor 422 is a PMOS transistor, or the third transistor 421 is a PMOS transistor. The fourth transistor 422 is an NMOS transistor, the body terminal of the third transistor 421 is connected to the gate terminal, and the body terminal of the fourth transistor is connected to the gate terminal.

[0126] Specifically, the third transistor 421 and the fourth transistor 422 can both be set as MOS transistors. The gate terminal and the body terminal of the third transistor 421 are connected, which can reduce the threshold voltage of the third transistor 421. The gate terminal and the body terminal of the fourth transistor 422 are connected, which can reduce the threshold voltage of the fourth transistor 422, thereby reducing the output voltage loss of the first rectifier module 30.

[0127] by Figure 2 For example, the voltage at which the capacitor element discharges each time can be set to V0, the circuit level of the second rectifier module 40 is 4, and the voltage output by the second rectifier module 40 at the node N2 can be set to 8V0.

[0128] The voltage amplitude provided by the first signal line 10 can be set to VRF, and the voltage amplitude provided by the second signal line 20 can be set to VRF. The threshold voltage of the third transistor 421 and the threshold voltage of the fourth transistor 422 can both be set to VTH, V0=VRF-VTH, and the voltage output by the second rectifier module 40 at the node N2 can be set to 8 (VRF-VTH).

[0129] In this way, the body terminal of the third transistor 421 is connected to the gate terminal, and the body terminal of the fourth transistor 422 is connected to the gate terminal, which can reduce the threshold voltage of the transistors and further reduce the output voltage loss of the second rectifier module 40.

[0130] Reference Figure 6 The rectifier 100 provided in the embodiment of the present application further includes a plurality of bias modules 50. Each bias module 50 is connected between the second end of the corresponding first-level capacitor 31 and the control end of the corresponding first-level switch module 32, and each bias module 50 is configured to provide a bias voltage to the second end of the first capacitor 31 and the control end of the corresponding first-level switch module 32; or each bias module 50 is connected between the second end of the corresponding second-level capacitor 41 and the control end of the corresponding second-level switch module 42, and each bias module 50 is configured to provide a bias voltage to the second end of the second capacitor 41 and the control end of the corresponding second-level switch module 42.

[0131] Specifically, the bias module 50 can be connected between the control electrode of the first transistor 321 and the first capacitor 31, and the bias module 50 can also be connected between the second transistor 322 and the first capacitor 31. The bias module 50 can be connected between the control electrode of the third transistor 421 and the second capacitor 41, and the bias module 50 can also be connected between the fourth transistor 422 and the second capacitor 41. The bias voltage provided by the bias module 50 can increase the on-resistance of the transistor.

[0132] It is understandable that the output voltage may leak back to the input terminal through the transistor during the process of alternating conduction of the transistors in the CCDD rectifier 100. The bias voltage provided by the bias module 50 can increase the on-resistance of the transistor, reduce the reverse leakage of the transistor to the input terminal, and reduce the loss of the output voltage.

[0133] In this way, the bias module 50 can provide a bias voltage to the transistors of the first switch module 32 and the second switch module 42. The bias voltage can increase the on-resistance of the transistor, reduce the reverse leakage of the transistor to the input terminal, and reduce the loss of the output voltage.

[0134] In some embodiments, each bias module 50 includes a bias transistor 51. A first electrode of the bias transistor 51 is connected to a control electrode and to a second end of a corresponding first-level capacitor 31, and a second electrode of the bias transistor 51 is connected to a control end of a corresponding first-level switch module 32; or a first electrode of the bias transistor 51 is connected to a control electrode and to a second end of a corresponding first-level second capacitor 41, and a second electrode of the bias transistor 51 is connected to a control end of a corresponding first-level second switch module 42.

[0135] Specifically, Figure 7For example, the bias transistor 51 may include transistors M1 to M16. The first electrode and control electrode of transistor M1 may be connected to the capacitor element C1, and the second electrode of transistor M1 may be connected to the control electrode of transistor MN1. The first electrode and control electrode of transistor M2 may be connected to the capacitor element C1, and the second electrode of transistor M2 may be connected to the control electrode of transistor MP1. The first electrode and control electrode of transistor M3 may be connected to the capacitor element C2, and the second electrode of transistor M3 may be connected to the control electrode of transistor MN2. The first electrode and control electrode of transistor M4 may be connected to the capacitor element C2, and the second electrode of transistor M4 may be connected to the control electrode of transistor MP2. The first electrode and control electrode of transistor M5 may be connected to the capacitor element C3, and the second electrode of transistor M5 may be connected to the control electrode of transistor MN3. The first electrode and control electrode of transistor M6 may be connected to the capacitor element C7, and the second electrode of transistor M6 may be connected to the control electrode of transistor MP3. The first electrode and control electrode of transistor M7 may be connected to the capacitor element C10, and the second electrode of transistor M7 may be connected to the control electrode of transistor MN4. The first pole and control pole of transistor M8 can be connected to capacitor C10, and the second pole of transistor M8 can be connected to the control pole of transistor MP4. The first pole and control pole of transistor M9 can be connected to capacitor C13, and the second pole of transistor M9 can be connected to the control pole of transistor MN5. The first pole and control pole of transistor M10 can be connected to capacitor C13, and the second pole of transistor M10 can be connected to the control pole of transistor MP5. The first pole and control pole of transistor M11 can be connected to capacitor C16, and the second pole of transistor M11 can be connected to the control pole of transistor MN6. The first pole and control pole of transistor M12 can be connected to capacitor C16, and the second pole of transistor M12 can be connected to the control pole of transistor MP6. The first pole and control pole of transistor M13 can be connected to capacitor C19, and the second pole of transistor M13 can be connected to the control pole of transistor MN7. The first pole and control pole of transistor M14 can be connected to capacitor C19, and the second pole of transistor M14 can be connected to the control pole of transistor MP7. The first electrode and control electrode of transistor M15 can be connected to capacitor C22, and the second electrode of transistor M15 can be connected to the control electrode of transistor MN8. The first electrode and control electrode of transistor M16 can be connected to capacitor C22, and the second electrode of transistor M16 can be connected to the control electrode of transistor MP8.

[0136] The first electrode of the bias transistor 51 is short-circuited with the control electrode. The bias transistor 51 can be used as an equivalent diode. The anode of the equivalent diode is connected to the corresponding capacitor element, and the cathode of the equivalent diode is connected to the control electrode of the transistor of the first switch module 32 and the second switch module 42. The equivalent diode can provide a corresponding bias voltage.

[0137] In this way, the bias transistor 51 can provide a bias voltage for the transistors of the first switch module 32 and the second switch module 42 .

[0138] In some embodiments, each bias module 50 includes a bias diode. The anode of the bias diode is connected to the second end of the corresponding first-level capacitor 31, and the cathode of the bias diode is connected to the control end of the corresponding first-level switch module 32; or the anode of the bias diode is connected to the second end of the corresponding first-level second capacitor 41, and the cathode of the bias diode is connected to the control end of the corresponding first-level second switch module 42.

[0139] Specifically, the connection relationship of the bias diode can refer to the connection relationship of the equivalent diode of the bias transistor 51, which will not be described in detail here.

[0140] In this way, the bias diode can provide a bias voltage for the transistors of the first switch module 32 and the second switch module 42 .

[0141] In some embodiments, the bias transistor 51 is an NMOS transistor, and the body terminal of the bias transistor 51 is connected to the gate terminal.

[0142] Specifically, the bias transistors 51 can be set as NMOS transistors, the first electrode of the bias transistor 51 can be set as the drain of the NMOS transistor, and the second electrode of the bias transistor 51 can be set as the source of the NMOS transistor. The gate terminal and the body terminal of the bias transistor 51 are connected, which can reduce the threshold voltage of the bias transistor 51, and further reduce the output voltage loss of the first rectifier module 30 and the output voltage loss of the second rectifier module 40.

[0143] by Figure 8 For example, in the first stage circuit of the CCDD rectifier 100 circuit, the voltage of each discharge of the capacitor C1 can be set to (V0-VTH-Vth). Among them, VTH can be set to the threshold voltage of the first transistor 321 and the threshold voltage of the second transistor 322, and Vth can be set to the threshold voltage of the bias transistor 51.

[0144] by Fig. 9For example, in the last stage circuit of the CCDD rectifier 100 circuit, the voltage of each discharge of the capacitor C22 can be set to (V0-VTH-Vth). Among them, VTH can be set to the threshold voltage of the first transistor 321 and the threshold voltage of the second transistor 322, and Vth can be set to the threshold voltage of the bias transistor 51.

[0145] In this way, the gate terminal and the body terminal of the bias transistor 51 are connected, which can reduce the threshold voltage of the bias transistor 51 and further reduce the output voltage loss of the first rectifier module 30 and the output voltage loss of the second rectifier module 40 .

[0146] Reference Fig.10 The embodiment of the present application provides a radio frequency energy harvesting circuit 1000. The radio frequency energy harvesting circuit 1000 includes a harvesting and conversion circuit 200, a storage capacitor 300 and the CCDD rectifier 100 of the above embodiment.

[0147] Specifically, the acquisition and conversion circuit 200 is configured to acquire radio frequency signals and convert the radio frequency signals into corresponding AC voltage signals for output. The CCDD rectifier 100 is configured to convert the AC voltage signals output by the conversion circuit into DC voltage signals for output. The storage capacitor 300 is configured to store the DC voltage signals output by the CCDD rectifier 100.

[0148] In some embodiments, the acquisition and conversion circuit 200 may include an antenna 210 , a first matching network 220 , and a second matching network 230 .

[0149] Specifically, the antenna 210 is configured to collect RF signals and convert the RF signals into corresponding single-ended voltage signals. The first matching network 220 is configured to adjust the input impedance of the antenna 210 so that the antenna 210 matches the impedance of the CCDD rectifier 100. The second matching network 230 is configured to convert the single-ended voltage signal into a corresponding double-ended differential voltage signal and provide it to the CCDD rectifier 100.

[0150] The second matching network 230 can be configured as a balanced and unbalanced converter, which can convert a balanced signal into an unbalanced differential signal and provide the corresponding differential signal to the CCDD rectifier 100. The CCDD rectifier 100 can access the differential signal provided by the second matching network 230 based on the signal line VP and the signal line VN.

[0151] Balanced and unbalanced converters may contain inductive and capacitive elements that adjust the input impedance of the circuit to match that of an external unbalanced system, thereby improving signal transmission efficiency and reducing energy loss.

[0152] In some embodiments, the first matching network 220 includes a first matching capacitor 221, a second matching capacitor 222, and a matching inductor 223, wherein a first end of the first matching capacitor 221 is connected to a first end of the matching inductor 223 and is connected to the antenna 210. A second end of the first matching capacitor 221 is grounded, a second end of the matching inductor 223 is connected to a first end of the second matching capacitor 222 and is connected to the second matching network 230, and a second end of the second matching capacitor 222 is grounded.

[0153] Specifically, the first matching capacitor 221, the second matching capacitor 222 and the matching inductor 223 can form a corresponding capacitor-inductor resonant circuit. The capacitance value and the inductance value corresponding to the first matching capacitor 221, the second matching capacitor 222 and the matching inductor 223 can be adjusted based on the input impedance of the antenna 210 and the impedance of the rectifier 100.

[0154] Maximum power transfer is achieved when the input impedance of a capacitor-inductor resonant circuit matches the external load impedance. Ideally, when these two impedances are equal, the circuit is perfectly matched, transferring all input power to the load with none reflected back to the source.

[0155] Reference Fig.11 The present application also provides a chip 2000 and a communication device 3000. The chip 2000 may include the RF energy harvesting circuit 1000 of the above embodiment. The communication device 3000 may include the chip 2000 or the RF energy harvesting circuit 1000 of the above embodiment.

[0156] The CCDD rectifier 100 in the related art (such as Figure 3 ) can refer to the output voltage simulation diagram Fig.12 When the power of the input RF signal is -34 dBm and the frequency is 915 MHz, the output voltage of the CCDD rectifier 100 is 337 mV.

[0157] The CCDD rectifier 100 (eg, Figure 1 , Figure 2 , Figure 4 , Figure 5 The output voltage simulation diagram shown in Fig.13 When the input RF signal has a power of -34 dBm and a frequency of 915 MHz, the output voltage of the CCDD rectifier 100 is 673 mV. Compared with the CCDD rectifier 100 in the related art, the output voltage provided by the CCDD rectifier 100 in the series-parallel structure is doubled.

[0158] Dynamically leading biased series-parallel CCDD rectifier 100 (eg Figure 6 to Figure 9 The output voltage simulation diagram shown in Fig.14 When the power of the input RF signal is -34dBm and the frequency is 915MHz, the output voltage of the CCDD rectifier 100 is 683mV. Compared with the CCDD rectifier 100 of the series-parallel structure, the output voltage provided by the CCDD rectifier 100 of the series-parallel structure is further increased by 10mV.

[0159] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" means that the specific features, deconstructions, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0160] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0161] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0162] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0163] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A CCDD rectifier, characterized in that: include: A first signal line is configured to receive a first AC voltage signal; a second signal line configured to receive a second AC voltage signal, wherein the polarity of the second AC voltage signal is opposite to that of the first AC voltage signal; A first rectifier module, comprising a plurality of first capacitors and a plurality of first switch modules, wherein a first end of each first capacitor is connected to the first signal line, and each first switch module is connected to a second end of a corresponding first capacitor of a first stage, and each first switch module is also connected to the first switch module of a next stage, and each first switch module is configured to be periodically turned on and off, so that each first capacitor is periodically charged and discharged; The second rectifier module includes multiple stages of second capacitors and multiple second switch modules, wherein the first end of each stage of the second capacitor is connected to the second signal line, the second switch module of each stage is connected to the second end of the second capacitor of the corresponding stage, the second switch module of the first stage is connected to the first switch module of the last stage, and the second switch module of each stage is also connected to the second switch module of the next stage, and the second switch module of each stage is configured to be periodically turned on and off so that the second capacitor of each stage is periodically charged and discharged.

2. The CCDD rectifier according to claim 1, characterized in that: The first switch module at each stage is configured to be periodically turned on and off according to the second AC voltage signal, and the second switch module at each stage is configured to be periodically turned on and off according to the first AC voltage signal.

3. The CCDD rectifier according to claim 2, characterized in that: The first switch module at each level includes a first transistor and a second transistor, the first electrode of the first transistor is connected to the first electrode of the second transistor, and is connected to the second end of the first capacitor of the corresponding level, the second electrode of the first transistor is connected to the corresponding first switch module of the previous level, the second electrode of the second transistor is connected to the corresponding first switch module of the next level, and the second electrode of the second transistor of the first switch module of the last level is connected to the second switch module of the first level.

4. The CCDD rectifier according to claim 3, characterized in that: The second electrode of the first transistor of the first switch module of the first stage is grounded.

5. The CCDD rectifier according to claim 3, characterized in that: The first switch module of each stage includes a third capacitor, a first end of the third capacitor is connected to the second signal line, and a second end of the third capacitor is connected to the control electrode of the first transistor and the control electrode of the second transistor.

6. The CCDD rectifier according to claim 3, characterized in that: When the first transistor is turned on, the second transistor is turned off; when the second transistor is turned on, the first transistor is turned off.

7. The CCDD rectifier according to claim 6, characterized in that: The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, or the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor; the body terminal of the first transistor is connected to the gate terminal, and the body terminal of the second transistor is connected to the gate terminal.

8. The CCDD rectifier according to claim 2, characterized in that: The second switch module at each level includes a third transistor and a fourth transistor, the first electrode of the third transistor is connected to the first electrode of the fourth transistor, and is connected to the second end of the second capacitor of the corresponding level, the second electrode of the third transistor is connected to the corresponding second switch module of the previous level, the second electrode of the fourth transistor is connected to the corresponding second switch module of the next level, and the second electrode of the third transistor of the first level second switch module is connected to the first switch module of the last level.

9. The CCDD rectifier according to claim 8, characterized in that: The second electrode of the fourth transistor of the second switch module of the last stage is configured to provide the output voltage of the rectifier.

10. The CCDD rectifier according to claim 8, characterized in that: Each level of the second switch module includes a fourth capacitor, a first end of each of the fourth capacitors is connected to the signal line, and a second end of the fourth capacitor is connected to the control electrode of the third transistor and the control electrode of the fourth transistor.

11. The CCDD rectifier according to claim 8, characterized in that: When the third transistor is turned on, the fourth transistor is turned off; when the fourth transistor is turned on, the third transistor is turned off.

12. The CCDD rectifier according to claim 11, characterized in that: The third transistor is an NMOS transistor, and the fourth transistor is a PMOS transistor, or the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor; the body terminal of the third transistor is connected to the gate terminal, and the body terminal of the fourth transistor is connected to the gate terminal.

13. The CCDD rectifier according to any one of claims 1 to 12, characterized in that: The rectifier further includes a plurality of bias modules, each bias module is connected between the second end of the corresponding first capacitor of the first level and the control end of the corresponding first switch module of the first level, and each bias module is configured to provide a bias voltage to the second end of the first capacitor and the control end of the corresponding first switch module of the first level; or Each bias module is connected between the second end of the corresponding first-level second capacitor and the control end of the corresponding first-level second switch module, and each bias module is configured to provide a bias voltage to the second end of the second capacitor and the control end of the corresponding first-level second switch module.

14. The CCDD rectifier according to claim 13, characterized in that: Each of the bias modules comprises a bias transistor, wherein a first electrode of the bias transistor is connected to a control electrode and is connected to a second end of a corresponding first-level first capacitor, and a second electrode of the bias transistor is connected to a control end of a corresponding first-level first switch module; or The first electrode of the bias transistor is connected to the control electrode and to the second end of the corresponding first-level second capacitor, and the second electrode of the bias transistor is connected to the control end of the corresponding first-level second switch module.

15. The CCDD rectifier according to claim 14, characterized in that: The bias transistor is an NMOS transistor, and a body terminal of the bias transistor is connected to a gate terminal.

16. The CCDD rectifier according to claim 13, characterized in that: Each of the bias modules comprises a bias diode, wherein an anode of the bias diode is connected to the second end of the corresponding first capacitor of the first level, and a cathode of the bias diode is connected to the control end of the corresponding first switch module of the first level; or The anode of the bias diode is connected to the second end of the corresponding first-level second capacitor, and the cathode of the bias diode is connected to the control end of the corresponding first-level second switch module.

17. A radio frequency energy harvesting circuit, characterized in that: The radio frequency energy collection circuit comprises: The acquisition and conversion circuit is configured to acquire radio frequency signals and convert the radio frequency signals into corresponding alternating current voltage signals for output; The CCDD rectifier according to any one of claims 1 to 16, configured to convert the AC voltage signal output by the conversion circuit into a DC voltage signal for output; The storage capacitor is configured to store the DC voltage signal output by the CCDD rectifier.

18. The radio frequency energy harvesting circuit according to claim 17, characterized in that: The acquisition and conversion circuit comprises: The antenna is configured to collect radio frequency signals and convert the radio frequency signals into corresponding single-ended voltage signals; a first matching network configured to adjust an input impedance of the antenna to match an impedance of the antenna to that of the CCDD rectifier; The second matching network is configured to convert the single-ended voltage signal into a corresponding double-ended differential voltage signal and provide the signal to the CCDD rectifier.

19. The radio frequency energy harvesting circuit according to claim 18, characterized in that: The first matching network includes a first matching capacitor, a second matching capacitor and a matching inductor, the first end of the first matching capacitor is connected to the first end of the matching inductor and to the antenna, the second end of the first matching capacitor is grounded, the second end of the matching inductor is connected to the first end of the second matching capacitor and to the second matching network, and the second end of the second matching capacitor is grounded.

20. A chip, characterized in that: The chip includes the CCDD rectifier described in any one of claims 1-16, or the radio frequency energy harvesting circuit described in any one of claims 17-19.

21. A communication device, characterized in that: The communication device includes the radio frequency energy harvesting circuit described in any one of claims 17-19, or the chip described in claim 20.

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