An attenuator chip

Abstract

The application discloses an attenuator chip, which comprises a first thin-film resistor, a second thin-film resistor, an input pad, an output pad, a third thin-film resistor and a fourth thin-film resistor; the first thin-film resistor, the second thin-film resistor, the input pad and the output pad are connected in series to form a main circuit; the third thin-film resistor and the fourth thin-film resistor are connected in parallel to ground; and the four thin-film resistors jointly form a pure T-shaped resistor attenuation structure. In the structure of a traditional T-shaped attenuator, the traditional single-ground thin-film resistor is divided into two parallel-ground thin-film resistors, and the symmetry is better. The pure resistor attenuator structure has a flat frequency response, can keep consistent attenuation effects in a wide frequency range, has low cost, simple structure and wide application. In addition, the ground sheet and the ground surface are conductive through a ground through hole, the structure enhances the symmetry of a signal, and thus the stability of the signal is improved. Furthermore, a serpentine detour design is adopted on a transmission line connected with the thin-film resistors, and the performance is better. The attenuator chip provided by the application is more flexible in use, smaller in size and better in performance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of attenuators, and particularly relates to an attenuator chip. BACKGROUND

[0002] In modern communication systems and radio frequency circuits, power control of signals is crucial. As a key passive component, attenuators are widely used in various electronic devices for adjusting signal power, matching impedance, and protecting other circuit components. With the development of wireless communication technology, especially in high frequency and millimeter wave frequency bands, signal stability and precise control become particularly important. Traditional attenuator structures face many challenges in modern high-integration circuits due to their large size and limited attenuation precision. Therefore, developing an attenuator chip with high integration, high precision, and small area has become the focus of current technology development.

[0003] Existing attenuator designs are mostly based on the combination of discrete components, which are large in size and not suitable for application in highly integrated systems. In addition, these designs often face problems such as uneven signal attenuation, parasitic effects, and impedance mismatch caused by transmission line effects at high frequencies. These shortcomings not only limit the application scenarios of attenuators, but also affect their performance in high-frequency and wideband communication systems. Therefore, developing an attenuator chip that can maintain stable performance at high frequencies while having precise control capabilities and high integration has become an urgent need in the industry. SUMMARY

[0004] To solve the problems of the prior art, the purpose of the present application is to provide an attenuator chip to solve the problems of inflexible use range, poor performance, and large size of existing attenuators.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the embodiments of the present application is as follows: an attenuator chip is designed, characterized in that the chip comprises a dielectric substrate and an attenuation unit arranged on the upper surface of the dielectric substrate, the back surface of the dielectric substrate is provided with a ground plane, and the attenuation unit comprises an input pad, an output pad, a first ground pad, a second ground pad, a third ground pad, a fourth ground pad, a first thin film resistor, a second thin film resistor, a third thin film resistor, a fourth thin film resistor, a first ground sheet, a second ground sheet, a third ground sheet, a fourth ground sheet, a fifth ground sheet, a sixth ground sheet, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, a fifth transmission line, a sixth transmission line, a seventh transmission line, an eighth transmission line, a ninth transmission line, a tenth transmission line, and an eleventh transmission line.

[0006] The input pad, the first thin film resistor, the second thin film resistor and the output pad are arranged in a horizontal state from left to right in the middle position of the upper surface of the dielectric substrate in sequence, wherein the input pad is opposite to the output pad, the first thin film resistor is arranged in the middle position close to the right side of the input pad, the second thin film resistor is arranged in the middle position close to the left side of the output pad, and the first thin film resistor is opposite to the second thin film resistor; the seventh transmission line is arranged in the middle position between the first thin film resistor and the second thin film resistor; the input pad and the first thin film resistor are conducted through the first transmission line, and the first thin film resistor and the seventh transmission line are conducted through the third transmission line; the output pad and the second thin film resistor are conducted through the second transmission line, and the second thin film resistor and the seventh transmission line are conducted through the fourth transmission line;

[0007] The structure formed by the input pad, the first transmission line, the first thin film resistor and the third transmission line is rotated by 180° right around the midpoint of the seventh transmission line, and coincides with the structure formed by the fourth transmission line, the second thin film resistor, the second transmission line and the output pad;

[0008] The fifth grounding sheet, the third thin film resistor, the seventh transmission line, the fourth thin film resistor and the second grounding sheet are arranged in a vertical state from top to bottom in the middle position of the upper surface of the dielectric substrate in sequence, wherein the fifth grounding sheet and one end of the third thin film resistor are conducted through the fifth transmission line, and the other end of the third thin film resistor is conducted with the seventh transmission line; one end of the fourth thin film resistor and the second grounding sheet are conducted through the sixth transmission line, and the other end of the fourth thin film resistor is conducted with the seventh transmission line;

[0009] The structure formed by the fifth grounding sheet, the fifth transmission line and the third thin film resistor is rotated by 180° right around the midpoint of the seventh transmission line, and coincides with the structure formed by the second grounding sheet, the sixth transmission line and the fourth thin film resistor;

[0010] The fourth grounding pad and the first grounding pad are arranged on the upper surface of the dielectric substrate on the upper and lower sides of the input pad at equal intervals, respectively, and the third grounding pad and the second grounding pad are arranged on the upper surface of the dielectric substrate on the upper and lower sides of the output pad at equal intervals, respectively;

[0011] A sixth grounding plate is provided at a central position on the upper surface of the dielectric substrate above the fourth grounding pad, a fourth grounding plate is provided at a central position on the upper surface of the dielectric substrate above the third grounding pad, a first grounding plate is provided at a central position on the upper surface of the dielectric substrate below the first grounding pad, and a third grounding plate is provided at a central position on the upper surface of the dielectric substrate below the second grounding pad. The lower side of the sixth grounding plate is electrically connected to the upper side of the fourth grounding pad via an eighth transmission line, the lower side of the fourth grounding plate is electrically connected to the upper side of the third grounding pad via a ninth transmission line, the upper side of the first grounding plate is electrically connected to the lower side of the first grounding pad via a tenth transmission line, and the upper side of the third grounding plate is electrically connected to the lower side of the second grounding pad via an eleventh transmission line.

[0012] A grounding through-hole is provided in the middle of each of the first, second, third, fourth, fifth, and sixth grounding plates, and extends through the back surface of the dielectric substrate. A conductive cylinder is provided in each grounding through-hole, so that each grounding plate is electrically connected to the ground plane on the back surface of the dielectric substrate.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: the attenuator chip designed by the present invention is composed of a first thin film resistor, a second thin film resistor, an input pad, and an output pad connected in series to form a main circuit, and the third thin film resistor and the fourth thin film resistor are connected to the ground in parallel, and the four thin film resistors together constitute a pure T-type resistance attenuation structure. The pure resistance attenuator structure has a flat frequency response and can maintain a consistent attenuation effect within a wide frequency range. At the same time, it is low-cost, simple in structure, and widely used. In the structure of the traditional T-type attenuator, the traditional single grounded thin film resistor is divided into two parallel-connected grounded thin film resistors, which has better symmetry. In addition, the grounding plate and the grounding surface are connected through a grounding through-hole. This structure enhances the symmetry of the signal, thereby improving the stability of the signal. In addition, a serpentine design is adopted on the transmission line connecting the thin film resistors to better guarantee performance. The attenuator chip provided by the present invention has a more flexible scope of use, a smaller size, and better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a schematic diagram of the front structure of an attenuator chip according to an embodiment of the present invention.

[0016] Figure 2This is a simulation curve of the attenuation value of an attenuator chip according to an embodiment of the present invention when the attenuation is 1dB, 2dB, 3dB, 4dB, 5dB, 6dB, 7dB, and 10dB.

[0017] Figure 3 This is a simulation curve of the input return loss of an attenuator chip of an embodiment of the present invention when the attenuation is 1dB, 2dB, 3dB, 4dB, 5dB, 6dB, 7dB, and 10dB.

[0018] Figure 4 This is a simulation curve of the output return loss of an attenuator chip of an embodiment of the present invention when the attenuation is 1dB, 2dB, 3dB, 4dB, 5dB, 6dB, 7dB, and 10dB. DETAILED DESCRIPTION

[0019] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] It should be noted that, in this application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0021] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate directions or positional relationships based on the accompanying drawings. Figure 1 The orientations or positional relationships shown are intended solely to facilitate and simplify the description of the present invention. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limitations on the present invention. The term "conductivity" refers to electrical connection between two devices. This can be achieved through direct contact between conductive devices or through other technical means, such as conductive adhesive or conductive wire.

[0022] like Figure 1 As shown, Figure 1 This is a schematic diagram of the front structure of the attenuator chip provided in an embodiment of the present invention. The attenuator chip refers to a chip circuit design that can realize the function, and does not include a packaging structure and an external pin part. The packaging structure and external pins are only for the convenience of chip application, and do not affect its function or hinder its normal use.

[0023] This embodiment provides an attenuator chip, which includes a dielectric substrate and an attenuation unit disposed on the upper surface of the dielectric substrate. A ground plane is disposed on the back surface of the dielectric substrate. The attenuation unit includes an input pad IN, an output pad OUT, a first ground pad P1, a second ground pad P2, a third ground pad P3, a fourth ground pad P4, a first thin-film resistor R1, a second thin-film resistor R2, a third thin-film resistor R3, a fourth thin-film resistor R4, a first ground plate B1, a second ground plate B2, a third ground plate B3, a fourth ground plate B4, a fifth ground plate B5, a sixth ground plate B6, a first transmission line L1, a second transmission line L2, a third transmission line L3, a fourth transmission line L4, a fifth transmission line L5, a sixth transmission line L6, a seventh transmission line L7, an eighth transmission line L8, a ninth transmission line L9, a tenth transmission line L10, and an eleventh transmission line L11.

[0024] The input pad IN, the first thin-film resistor R1, the second thin-film resistor R2, and the output pad OUT are arranged horizontally in sequence from left to right in the middle position of the upper surface of the dielectric substrate, wherein the input pad IN and the output pad OUT are directly opposite each other, the first thin-film resistor R1 is arranged in the middle position close to the right side of the input pad IN, and the second thin-film resistor R2 is arranged in the middle position close to the left side of the output pad OUT, and the first thin-film resistor R1 and the second thin-film resistor R2 are directly opposite each other; the seventh transmission line L7 is arranged in the middle position between the first thin-film resistor R1 and the second thin-film resistor R2; the input pad IN and the first thin-film resistor R1 are electrically connected via the first transmission line L1, and the first thin-film resistor R1 and the seventh transmission line L7 are electrically connected via the third transmission line L3; the output pad OUT and the second thin-film resistor R2 are electrically connected via the second transmission line L2, and the second thin-film resistor R2 and the seventh transmission line L7 are electrically connected via the fourth transmission line L4;

[0025] The structure formed by the input pad IN, the first transmission line L1, the first thin-film resistor R1, and the third transmission line L3 is rotated 180° clockwise around the midpoint of the seventh transmission line L7 and overlaps with the structure formed by the fourth transmission line L4, the second thin-film resistor R2, the second transmission line L2, and the output pad OUT.

[0026] The fifth grounding plate B5, the third thin-film resistor R3, the seventh transmission line L7, the fourth thin-film resistor R4, and the second grounding plate B2 are arranged vertically in sequence from top to bottom in the middle position of the upper surface of the dielectric substrate. The fifth grounding plate B5 is electrically connected to one end of the third thin-film resistor R3 via the fifth transmission line L5, and the other end of the third thin-film resistor R3 is electrically connected to the seventh transmission line L7. One end of the fourth thin-film resistor R4 is electrically connected to the second grounding plate B2 via the sixth transmission line L6, and the other end of the fourth thin-film resistor R4 is electrically connected to the seventh transmission line L7.

[0027] The structure formed by the fifth ground sheet B5, the fifth transmission line L5 and the third thin film resistor R3 is rotated 180° clockwise around the midpoint of the seventh transmission line L7 and coincides with the structure formed by the second ground sheet B2, the sixth transmission line L6 and the fourth thin film resistor R4.

[0028] The fourth ground pad P4 and the first ground pad P1 are arranged equidistantly on the upper surface of the medium substrate on the upper and lower sides of the input pad IN, and the third ground pad P3 and the second ground pad P2 are arranged equidistantly on the upper surface of the medium substrate on the upper and lower sides of the output pad OUT;

[0029] The sixth ground sheet B6 is arranged at the middle position of the upper surface of the medium substrate on the upper side of the fourth ground pad P4, the fourth ground sheet B4 is arranged at the middle position of the upper surface of the medium substrate on the upper side of the third ground pad P3, the first ground sheet B1 is arranged at the middle position of the upper surface of the medium substrate on the lower side of the first ground pad P1, and the third ground sheet B3 is arranged at the middle position of the upper surface of the medium substrate on the lower side of the second ground pad P2; the lower side of the sixth ground sheet B6 is connected to the upper side of the fourth ground pad P4 through the eighth transmission line L8, the lower side of the fourth ground sheet B4 is connected to the upper side of the third ground pad P3 through the ninth transmission line L9, the upper side of the first ground sheet B1 is connected to the lower side of the first ground pad P1 through the tenth transmission line L10, and the upper side of the third ground sheet B3 is connected to the lower side of the second ground pad P2 through the eleventh transmission line L11;

[0030] The middle positions of the first ground sheet B1, the second ground sheet B2, the third ground sheet B3, the fourth ground sheet B4, the fifth ground sheet B5 and the sixth ground sheet B6 are provided with ground through holes which penetrate through to the back surface of the medium substrate; a conductive cylinder is arranged in each ground through hole so that each ground sheet is electrically connected to the ground surface on the back surface of the medium substrate;

[0031] The ground sheet and the ground surface are connected through the ground through hole, which enhances the symmetry of the signal and improves the stability of the signal.

[0032] The first thin film resistor R1 and the second thin film resistor R2 are made of the same material and have the same size, and the third thin film resistor R3 and the fourth thin film resistor R4 are made of the same material and have the same size;

[0033] The third transmission line L3 and the fourth transmission line L4 are identical in structure and size, and are in a serpentine structure. As an embodiment, the third transmission line L3 includes a first horizontal rectangular strip, a first right-angled triangular piece, a second vertical rectangular strip, a second right-angled triangular piece, a second horizontal rectangular strip, a third right-angled triangular piece, a third vertical rectangular strip, a fourth right-angled triangular piece, and a third horizontal rectangular strip, totaling nine parts. The nine parts are sequentially connected from left to right, wherein the left end of the first horizontal rectangular strip is connected to the middle of the left side of the first thin-film resistor R1, the right end of the first horizontal rectangular strip and the bottom end of the second vertical rectangular strip are respectively connected to two right-angled edges of the first right-angled triangular piece, and the hypotenuse of the first right-angled triangular piece is below the bottom end of the second vertical rectangular strip; the top end of the second vertical rectangular strip and the left end of the second horizontal rectangular strip are respectively connected to two right-angled edges of the second right-angled triangular piece, and the hypotenuse of the second right-angled triangular piece is above the top end of the second vertical rectangular strip; the right end of the second horizontal rectangular strip and the top end of the third vertical rectangular strip are respectively connected to two right-angled edges of the third right-angled triangular piece, and the hypotenuse of the third right-angled triangular piece is above the top end of the third vertical rectangular strip; the bottom end of the third vertical rectangular strip and the left end of the third horizontal rectangular strip are respectively connected to two right-angled edges of the fourth right-angled triangular piece, and the hypotenuse of the fourth right-angled triangular piece is below the bottom end of the third vertical rectangular strip; and the right end of the third horizontal rectangular strip is connected to the middle of the left side of the seventh transmission line L7. The serpentine structure can guarantee the best performance in a limited chip area by calculating and simulating the characteristic impedance and the tangent value of the electrical length of the transmission line. The vertical edges of the first, second, and third horizontal rectangular strips are equal in length to the horizontal edges of the second and third vertical rectangular strips, and the vertical edges of the second and third vertical rectangular strips are equal in length; the first, second, third, and fourth right-angled triangular pieces are isosceles right-angled triangles, and the right-angled edges of the four pieces are equal in length to the vertical edge of the first horizontal rectangular strip.

[0034] The first thin-film resistor R1, the second thin-film resistor R2, the input pad IN, and the output pad OUT are connected in series to form a main circuit, the third thin-film resistor R3 and the fourth thin-film resistor R4 are connected in parallel to ground, and the four thin-film resistors R1-R4 together form a pure T-type resistor attenuation structure. The pure resistor attenuator structure has a flat frequency response, can maintain consistent attenuation effects in a wide frequency range, and is low in cost, simple in structure, and widely applicable.

[0035] In this embodiment, the chip is based on an integrated circuit process, and a gallium arsenide (GaAs) material with a dielectric constant of 12.9 is used as a dielectric substrate. The thickness of the dielectric substrate is 75 μm, and the back surface of the GaAs substrate serves as the ground surface of the chip.

[0036] The fixed attenuator chip belongs to a passive device, and mainly realizes signal attenuation through a built-in resistance network, so that no external power supply is needed during operation. The ground plane of the chip is connected to the four GND pins of the external package through the first ground pad P1, the second ground pad P2, the third ground pad P3, and the fourth ground pad P4 through gold-plated bonding wires. The input pad IN and the output pad OUT are respectively connected to the IN pin and the OUT pin of the external package through gold-plated bonding wires. The IN pin of the external package is connected to a 50-ohm radio frequency source input, and the OUT pin of the external package is connected to a 50-ohm radio frequency source output. The output is the output signal after the input signal is attenuated by the internal resistance network of the attenuator chip.

[0037] When the attenuation is 1dB, 5dB, 6dB, or 7dB, the third thin film resistor R3 and the fourth thin film resistor R4 use epitaxial resistors. When the attenuation is 2dB, 3dB, 4dB, or 10dB, the third thin film resistor R3 and the fourth thin film resistor R4 use tantalum nitride resistors. Due to the limitation of chip size, two types of resistors are selected for use under different attenuation values. The first thin film resistor and the second thin film resistor under all attenuation values use tantalum nitride resistors; tantalum nitride resistors can maintain accurate resistance values, but at large resistance values, the length is too long to exceed the chip area, so it is necessary to use epitaxial resistors with slightly lower precision instead. Epitaxial resistors can still maintain a small length at large resistance values, ensuring consistent chip size under different attenuation values.

[0038] The thin film resistor R1 and the thin film resistor R2 have the same size, and the thin film resistor R3 and the thin film resistor R4 have the same size. The length and width of the thin film resistors are changed according to different attenuation values to change the resistance values of the resistors, thereby achieving the change of attenuation. That is, different attenuation values are achieved by thin film resistors with different lengths and widths, and the performance of the attenuator is improved by adjusting the length and width of the first transmission line and the second transmission line.

[0039] The input pad, the output pad, and the ground pad are all square structures, and the ground through hole is a circular structure. The purpose is to realize reliable packaging of the chip in the process.

[0040] In this embodiment, the input pad IN, the output pad OUT, the first thin film resistor R1, and the second thin film resistor R2 are arranged in parallel along the horizontal direction to ensure the shortest path and the smallest loss during signal transmission. The third thin film resistor R3, the fourth thin film resistor R4, the second ground sheet B2, and the fifth ground sheet B5 are arranged in parallel along the vertical direction to serve as T-shaped ground resistors.

[0041] In this embodiment, the length of the medium substrate in the horizontal direction is 660μm, and the length in the vertical direction is 760μm, which effectively limits the area of the chip and has the characteristics of small area and wide application scenarios.

[0042] In this embodiment, the first ground pad and the second ground pad of the attenuator chip are symmetrically distributed in the vertical direction, and the first ground pad and the fourth ground pad are symmetrical in the horizontal direction, and the distances from the surrounding pads and ground through holes to the seventh transmission line are the same.

[0043] In this embodiment, the center distance between the input pad and the output pad is 342.9 μm, the center distance between the first ground pad and the second ground pad, and the center distance between the third ground pad and the fourth ground pad is 342.9 μm, and the size of each pad is 100 μm × 100 μm, and the center distance between the first ground pad and the fourth ground pad, and the center distance between the second ground pad and the third ground pad is 300 μm.

[0044] The third transmission line and the fourth transmission line have the same length and a length range of 70 μm to 180 μm, and a width range of 3.5 μm to 13 μm. The length here refers to the total length of the outer curve on the upper side or the lower side of the third transmission line, which includes the lengths of the horizontal sides of the first horizontal rectangular strip, the second horizontal rectangular strip, and the third horizontal rectangular strip, as well as the lengths of the vertical sides of the second vertical rectangular strip and the third vertical rectangular strip, and the lengths of the hypotenuses of the second right-angled triangle piece and the third right-angled triangle piece; the width refers to the length of the vertical side of the first horizontal rectangular strip.

[0045] The first transmission line and the second transmission line have the same size and are 25μm×40.2μm at 1dB attenuation, and 25μm×30.2μm at other attenuations. The lengths of the fifth and sixth transmission lines range from 30μm to 100μm. The horizontal width of the seventh transmission line is consistent with the horizontal width of the third thin-film resistor, and its vertical length varies with the vertical length of the first thin-film resistor at different attenuations (i.e., the length remains consistent). Its vertical length ranges from 35.4μm to 50.4μm.

[0046] Furthermore, the size of all ground plates is 50 μm × 50 μm.

[0047] In this embodiment, the simulation results show that Figure 2 It can be seen that the attenuation error of the attenuator chip can be maintained at ±0.3dB at a frequency of DC ~ 30GHz, especially the attenuation accuracy is maintained at ±0.15dB at 1 dB, 2 dB, 3 dB, and 4 dB. The higher the attenuation accuracy, the better the performance of the attenuator, and the more stable the attenuation can be at high frequencies.

[0048] Figure 3 、 Figure 4The input and output return losses of the attenuator are shown separately. Higher return losses indicate less signal reflection, meaning the attenuator effectively matches the system's impedance, thereby reducing power loss and signal distortion caused by reflections. This is crucial for maintaining the system's signal integrity and improving transmission efficiency. Simulations show that both input and output return losses are less than -15dB, with a particular range of less than -20dB from 0 to 20GHz. The input and output return loss curves are consistent, demonstrating the attenuator's excellent symmetry.

[0049] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

[0050] Any matters not described in the present invention are applicable to the prior art.

Claims

1. An attenuator chip, characterized in that: The chip includes a dielectric substrate and an attenuation unit arranged on the upper surface of the dielectric substrate. The back surface of the dielectric substrate is provided with a ground plane. The attenuation unit includes an input pad, an output pad, a first ground pad, a second ground pad, a third ground pad, a fourth ground pad, a first thin-film resistor, a second thin-film resistor, a third thin-film resistor, a fourth thin-film resistor, a first ground plate, a second ground plate, a third ground plate, a fourth ground plate, a fifth ground plate, a sixth ground plate, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, a fifth transmission line, a sixth transmission line, a seventh transmission line, an eighth transmission line, a ninth transmission line, a tenth transmission line, and an eleventh transmission line. The input pad, the first thin-film resistor, the second thin-film resistor, and the output pad are arranged horizontally in sequence from left to right in the middle position of the upper surface of the dielectric substrate, wherein the input pad and the output pad are directly opposite each other, the first thin-film resistor is arranged in the middle position near the right side of the input pad, the second thin-film resistor is arranged in the middle position near the left side of the output pad, and the first thin-film resistor and the second thin-film resistor are directly opposite each other; the seventh transmission line is arranged in the middle position between the first thin-film resistor and the second thin-film resistor; the input pad and the first thin-film resistor are electrically connected via the first transmission line, and the first thin-film resistor and the seventh transmission line are electrically connected via the third transmission line; the output pad and the second thin-film resistor are electrically connected via the second transmission line, and the second thin-film resistor and the seventh transmission line are electrically connected via the fourth transmission line; The structure formed by the input pad, the first transmission line, the first thin-film resistor, and the third transmission line is rotated 180° clockwise around the midpoint of the seventh transmission line and overlaps with the structure formed by the fourth transmission line, the second thin-film resistor, the second transmission line, and the output pad; A fifth grounding plate, a third thin-film resistor, a seventh transmission line, a fourth thin-film resistor, and a second grounding plate are arranged vertically in sequence from top to bottom at a center position on the upper surface of the dielectric substrate. The fifth grounding plate is electrically connected to one end of the third thin-film resistor via the fifth transmission line, and the other end of the third thin-film resistor is electrically connected to the seventh transmission line. One end of the fourth thin-film resistor is electrically connected to the second grounding plate via the sixth transmission line, and the other end of the fourth thin-film resistor is electrically connected to the seventh transmission line. The structure formed by the fifth grounding plate, the fifth transmission line, and the third thin-film resistor is rotated 180° clockwise around the midpoint of the seventh transmission line and overlaps with the structure formed by the second grounding plate, the sixth transmission line, and the fourth thin-film resistor; A fourth ground pad and a first ground pad are disposed on the upper surface of the dielectric substrate on both sides above and below the input pad at equal intervals, and a third ground pad and a second ground pad are disposed on the upper surface of the dielectric substrate on both sides above and below the output pad at equal intervals. A sixth grounding plate is provided at a central position on the upper surface of the dielectric substrate above the fourth grounding pad, a fourth grounding plate is provided at a central position on the upper surface of the dielectric substrate above the third grounding pad, a first grounding plate is provided at a central position on the upper surface of the dielectric substrate below the first grounding pad, and a third grounding plate is provided at a central position on the upper surface of the dielectric substrate below the second grounding pad. The lower side of the sixth grounding plate is electrically connected to the upper side of the fourth grounding pad via an eighth transmission line, the lower side of the fourth grounding plate is electrically connected to the upper side of the third grounding pad via a ninth transmission line, the upper side of the first grounding plate is electrically connected to the lower side of the first grounding pad via a tenth transmission line, and the upper side of the third grounding plate is electrically connected to the lower side of the second grounding pad via an eleventh transmission line. A grounding through-hole is provided in the middle of each of the first, second, third, fourth, fifth, and sixth grounding plates, and extends through the back surface of the dielectric substrate. A conductive cylinder is provided in each grounding through-hole, so that each grounding plate is electrically connected to the ground plane on the back surface of the dielectric substrate.

2. The attenuator chip according to claim 1, characterized in that: The first thin film resistor and the second thin film resistor are made of the same material and have the same size. The third thin film resistor and the fourth thin film resistor are made of the same material and have the same size.

3. The attenuator chip according to claim 1, characterized in that: The third transmission line and the fourth transmission line have the same structure and size. The third transmission line L3 includes a first horizontal rectangular strip, a first right-angled triangle piece, a second vertical rectangular strip, a second right-angled triangle piece, a second horizontal rectangular strip, a third right-angled triangle piece, a third vertical rectangular strip, a fourth right-angled triangle piece, and a third horizontal rectangular strip, a total of nine parts. The above nine parts are connected in sequence from left to right, wherein the left end of the first horizontal rectangular strip is connected to the middle of the left side of the first thin-film resistor R1, the right end of the first horizontal rectangular strip and the bottom end of the second vertical rectangular strip are respectively connected to the two right-angled sides of the first right-angled triangle piece, and the hypotenuse of the first right-angled triangle piece is located below the bottom end of the second vertical rectangular strip; The top of the second vertical rectangular strip and the left end of the second horizontal rectangular strip are respectively connected to the two right-angled sides of the second right-angled triangle piece, and the hypotenuse of the second right-angled triangle piece is located above the top of the second vertical rectangular strip; the right end of the second horizontal rectangular strip and the top of the third vertical rectangular strip are respectively connected to the two right-angled sides of the third right-angled triangle piece, and the hypotenuse of the third right-angled triangle piece is located above the top of the third vertical rectangular strip; the bottom end of the third vertical rectangular strip and the left end of the third horizontal rectangular strip are respectively connected to the two right-angled sides of the fourth right-angled triangle piece, and the hypotenuse of the fourth right-angled triangle piece is located below the bottom end of the third vertical rectangular strip; the right end of the third horizontal rectangular strip is connected to the middle of the left side of the seventh transmission line L7.

4. The attenuator chip according to claim 1, characterized in that: The dielectric substrate is a gallium arsenide material with a dielectric constant of 12.

9.

5. The attenuator chip according to claim 1, characterized in that: The dielectric substrate has a thickness of 75 μm, a horizontal length of 660 μm, and a vertical length of 760 μm.

6. The attenuator chip according to claim 1, characterized in that: When the attenuation is 1dB, 5dB, 6dB, and 7dB, the third and fourth thin film resistors are epitaxial resistors. When the attenuation is 2dB, 3dB, 4dB, and 10dB, the third and fourth thin film resistors are tantalum nitride resistors.

7. The attenuator chip according to claim 1, characterized in that: The first thin film resistor and the second thin film resistor are both nitride resistors.

8. The attenuator chip according to claim 1, characterized in that: The input pad, output pad, and ground pad are all square structures. The center distance between the input pad and the output pad is 342.9 μm, the center distance between the first ground pad and the second ground pad, and the center distance between the third ground pad and the fourth ground pad is 342.9 μm, and the size of each pad is 100 μm × 100 μm. The center distance between the first ground pad and the fourth ground pad, and the center distance between the second ground pad and the third ground pad is 300 μm; the size of all ground plates is 50 μm × 50 μm.

9. The attenuator chip according to claim 1, characterized in that: The third transmission line and the fourth transmission line are equal in length and have a length range of 70 μm ~ 180 μm and a width range of 3.5 μm ~ 13 μm; the first transmission line and the second transmission line are equal in size and are 25 μm × 40.2 μm at 1 dB attenuation and 25 μm × 30.2 μm at other attenuations; the fifth transmission line and the sixth transmission line have a length range of 30 μm ~ 100 μm, the width of the seventh transmission line in the horizontal direction is consistent with the width of the third thin-film resistor in the horizontal direction, and its length in the vertical direction varies with the length of the first thin-film resistor in the vertical direction at different attenuations, and its length in the vertical direction ranges from 35.4 μm to 50.4 μm.

10. The attenuator chip according to claim 3, characterized in that: The vertical sides of the first horizontal rectangular strip, the second horizontal rectangular strip, and the third horizontal rectangular strip are all equal in length, and are equal to the lengths of the horizontal sides of the second vertical rectangular strip and the third vertical rectangular strip. The vertical sides of the second vertical rectangular strip and the third vertical rectangular strip are equal in length; the first right-angled triangle piece, the second right-angled triangle piece, the third right-angled triangle piece, and the fourth right-angled triangle piece are all isosceles right triangles, and the right-angled sides of the four are all equal and equal in length to the vertical side of the first horizontal rectangular strip.

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