Pin input multiplexing multifunctional phase-locked loop

Abstract

The invention discloses a pin input multiplexing multifunctional phase-locked loop, relates to a phase-locked loop chip technology, and provides a scheme for solving the problems that pins are limited and the like in the prior art. Comprising a multifunctional input module, wherein a multifunctional input pin is respectively connected with an input end of a buffer, a first connecting end of a first switch and a first connecting end of a second switch; the second connecting end of the first switch is in gating connection with VDD or VSS; the second connecting end of the second switch is connected to the input end of the loop filter; and the output end of the buffer is respectively connected with the input end of the loop filter, the output end of the loop filter through a third switch and the output end of the voltage-controlled oscillator through a fourth switch after passing through the one-by-two frequency divider. The multi-functional input pin has the advantages that a plurality of functions can be realized by utilizing the multi-functional input pin, and the effect of one-pin multiplexing is achieved, so that the complexity of the phase-locked loop chip is reduced, and the design efficiency of the phase-locked loop chip is improved.

Description

Technical Field

[0001] The invention relates to a phase-locked loop chip technology, in particular to a multifunctional phase-locked loop with pin input multiplexing. Background Art

[0002] The phase-locked loop (PLL) is the most important module in the transceiver system. It provides the local oscillator signal (LO) for the receiver system and the transmitter system. The LO signal determines the operating frequency band of the RF transceiver. The LO's phase noise, frequency spurious, frequency switching speed and other indicators directly affect the performance of the RF transceiver system. It can be seen that the design of the phase-locked loop is crucial to the RF transceiver system.

[0003] Common RF charge pump phase-locked loops such as Figure 1 As shown, it usually includes a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator which are electrically connected in sequence; it also includes a lock detection circuit and a digital control circuit which control the charge pump and the loop filter according to a reference signal and a frequency division signal; at the output end of the voltage controlled oscillator, the frequency division signal is fed back to the phase frequency detector through a feedback frequency divider. It can be seen that the phase-locked loop system is very large and extremely complex, so the phase-locked loop system usually has more pins; in addition, due to the complexity of the phase-locked loop system, the system must have good testability during the design process to facilitate problem finding and solving in the system.

[0004] In the prior art, the design of phase-locked loop chips often encounters the following problems:

[0005] 1: The chip pins are limited. Since the phase-locked loop system is relatively complex, which contains many system-level control algorithms, the number of bits of the digital control register under each algorithm is large, so the number of pins of the phase-locked loop chip is large.

[0006] 2: The testability requirement of the phase-locked loop chip is that the external input can provide the local oscillator. Due to the yield rate of chip production, when some chips fail to function, it is necessary to perform chip function testing through the testable channels reserved during design. When the internal local oscillator signal of the phase-locked loop chip fails, the chip needs to reserve pins to allow external input to provide the local oscillator.

[0007] 3: The PLL chip is very complex and has low design efficiency. Each function must be completed with the corresponding pins, which reduces the design efficiency. Summary of the invention

[0008] The present invention aims to provide a multifunctional phase-locked loop with pin input multiplexing to solve the problems existing in the above-mentioned prior art.

[0009] The multifunctional phase-locked loop with pin input multiplexing described in the present invention comprises a phase frequency detector, a charge pump, a loop filter and a voltage-controlled oscillator which are electrically connected in sequence; further comprises a lock detection circuit and a digital control circuit for controlling the charge pump and the loop filter according to a reference signal and a frequency division signal; at the output end of the voltage-controlled oscillator, the frequency division signal is fed back to the phase frequency detector through a feedback frequency divider;

[0010] It also includes a multifunctional input module: the multifunctional input pins are respectively connected to the buffer input end, the first connection end of the first switch and the first connection end of the second switch; the second connection end of the first switch is selected and connected to VDD or VSS; the second connection end of the second switch is connected to the loop filter input end; the buffer output end is respectively connected to the loop filter input end after passing through a one-to-two frequency divider, connected to the loop filter output end through the third switch, and connected to the voltage-controlled oscillator output end through the fourth switch.

[0011] The advantage of the multifunctional phase-locked loop with pin input multiplexing described in the present invention is that several functions can be realized by utilizing the multifunctional input pin, achieving the effect of one pin multiplexing, thereby reducing the complexity of the phase-locked loop chip and improving the design efficiency of the phase-locked loop chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of a phase-locked loop in the prior art.

[0013] Figure 2 It is a schematic diagram of the structure of the multifunctional phase-locked loop described in the present invention.

[0014] Figure 3 It is a simulation diagram of the change of VTUNE in the multifunctional phase-locked loop PATH2 of the present invention when the input signal is pulled up / down.

[0015] Figure 4 It is an output simulation diagram of the multifunctional phase-locked loop PATH3 described in the present invention.

[0016] Reference numerals:

[0017] SW1 to SW4: first switch to fourth switch;

[0018] BUF: buffer;

[0019] DIV2: Divide by two frequency divider. DETAILED DESCRIPTION

[0020] like Figure 2As shown, the multifunctional phase-locked loop with pin input multiplexing described in the present invention includes a phase frequency detector, a charge pump, a loop filter and a voltage-controlled oscillator which are electrically connected in sequence. It also includes a lock detection circuit and a digital control circuit for controlling the charge pump and the loop filter according to a reference signal and a frequency division signal. The frequency division signal is fed back to the phase frequency detector through a feedback frequency divider at the output end of the voltage-controlled oscillator.

[0021] The invention also includes a multifunctional input module: the multifunctional input pins are respectively connected to the buffer input terminal, the first connection terminal of the first switch and the first connection terminal of the second switch. The second connection terminal of the first switch is connected to VDD or VSS. The second connection terminal of the second switch is connected to the input terminal of the loop filter. The output terminal of the buffer is respectively connected to the input terminal of the loop filter after passing through a one-to-two frequency divider, connected to the output terminal of the loop filter through a third switch, and connected to the output terminal of the voltage-controlled oscillator through a fourth switch.

[0022] relatively Figure 1 The prior art solution, in addition to the traditional phase-locked loop path PATH1 inherent in the original technology, also adds three common input functional paths PATH2, PATH3 and PATH4, thereby realizing the following multiple functions.

[0023] The basic function of the path PATH1 is that it is the path in which the phase-locked loop works normally. The charge pump generates a frequency adjustment signal VTUNE after filtering the input signal of the loop filter through a third-order filter to adjust the output frequency of the phase-locked loop.

[0024] Function of path PATH2: The first switch SW1 selects VDD or VSS, and the second switch SW2 and the third switch SW3 are closed to pull the output voltage VTUNE of the loop filter to the power supply or ground, such as Figure 3 As shown in FIG. 1 , the working path for fast frequency fine adjustment can accelerate the loop locking time. Then the path PATH1 is used to work to accelerate the frequency fine adjustment process of the phase-locked loop.

[0025] The function of path PATH3 is to generate a local oscillation signal by passing the external input oscillation signal through a buffer and a divider by two, disconnect the first to third switches and close the fourth switch SW4, and BYPASS the original voltage-controlled oscillator. Figure 4 shown.

[0026] Function of path PATH4: disconnect the first switch SW1 and the fourth switch SW4, close the second switch SW2 and the third switch SW3. The VTUNE voltage output by the loop filter can be detected outside the chip through this pin to monitor the circuit status, thereby enhancing the testability of the chip.

[0027] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A multifunctional phase-locked loop with pin input multiplexing, comprising a phase frequency detector, a charge pump, a loop filter and a voltage-controlled oscillator electrically connected in sequence; further comprising a lock detection circuit and a digital control circuit for controlling the charge pump and the loop filter according to a reference signal and a frequency division signal; and feeding back the frequency division signal to the phase frequency detector through a feedback frequency divider at the output end of the voltage-controlled oscillator; It is characterized in that It also includes a multifunctional input module: the multifunctional input pins are respectively connected to the buffer input end, the first connection end of the first switch and the first connection end of the second switch; the second connection end of the first switch is selected and connected to VDD or VSS; the second connection end of the second switch is connected to the loop filter input end; the buffer output end is respectively connected to the loop filter input end after passing through a one-to-two frequency divider, connected to the loop filter output end through the third switch, and connected to the voltage-controlled oscillator output end through the fourth switch.

2. A multifunctional phase-locked loop with pin input multiplexing according to claim 1, characterized in that: The first switch is closed to select VDD, the second switch and the third switch are closed, and the fourth switch is open; and the output voltage of the loop filter is pulled to the power supply to accelerate the loop locking time.

3. A multifunctional phase-locked loop with pin input multiplexing according to claim 1, characterized in that: The first switch is closed to select VSS, the second switch and the third switch are closed, and the fourth switch is open; and the output voltage of the loop filter is pulled to ground to accelerate the loop locking time.

4. A multifunctional phase-locked loop with pin input multiplexing according to claim 1, characterized in that: The first switch, the second switch and the third switch are all opened, and the fourth switch is closed, so as to localize the external input oscillation signal after passing through the buffer and the divide-by-two frequency divider to generate a local oscillation signal.

5. A multifunctional phase-locked loop with pin input multiplexing according to claim 1, characterized in that: The first switch and the fourth switch are both opened, and the second switch and the third switch are closed, so as to detect the output voltage of the loop filter externally through the multi-function input pin.

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