Multi-event time-to-digital converter with scalable range

Abstract

The present application relates to a multi-event time-to-digital converter with an extendable range, comprising: a T flip-flop array for encoding an end signal according to the timing of an acquisition event to generate an edge change signal from the end signal; a TDC delay chain for generating a time stamp of the edge change signal in each delay unit from the edge change signal; an XOR gate module for performing a logical judgment based on the time stamp of the edge change signal to determine the event distribution of the acquisition event; a D flip-flop array for latching the event distribution of the acquisition event within each coarse counting clock cycle and storing it in a corresponding storage unit; and a histogram statistics module for distributing the time difference between the end signal and the start signal of the acquisition event to various time intervals to generate a statistical histogram of the event distribution of the acquisition event over M coarse counting clock cycles. The present application can significantly improve the range of the multi-event time-to-digital converter while maintaining high time measurement accuracy.

Description

Technical Field

[0001] The present application relates to the field of signal acquisition circuits, and in particular to a multi-event time-to-digital converter with an expandable range. Background Art

[0002] A time-to-digital converter (TDC) is an electronic device used to measure the time interval between two signals and convert it into a digital output. It has a wide range of applications in photon time-of-flight measurement, medical imaging, particle detection, and industrial automation control. TDCs are often combined with single-photon detectors for time-correlated single photon counting (TCSPC) measurements. TDCs can be categorized as single-event or multi-event based on the number of events received at the TDC's stop (STOP) terminal within the same signal cycle during TCSPC measurements. A single-event TDC only measures the arrival time of the first event encountered at the STOP terminal after the start (START) signal, ignoring all subsequent events. This acquisition method can cause the time domain distribution of the measured signal to deviate significantly from the true signal at high photon fluxes (often referred to as pile-up distortion), and its event sampling rate is limited to one event per signal cycle. The multi-event time-to-digital converter can measure the time interval (i.e., arrival time) of multiple events arriving at the STOP end within the same signal cycle relative to the START signal, which can effectively overcome the limitations of the single-event time-to-digital converter.

[0003] The implementation of a multi-event time-to-digital converter (MEDC) requires more hardware resources than a single-event time-to-digital converter (SEDC). This, to a certain extent, limits the design range (i.e., the range of measurable time intervals) of the MDC. Currently, the maximum range of high-sampling-rate MDCs is mostly limited to less than 100 nanoseconds, which is insufficient for applications requiring a wide range, such as mid- and long-range lidar and analysis of long-life fluorescent species. To expand the applicability of MDCs, their range needs to be further increased.

[0004] Existing multi-event time-to-digital converters primarily have two structures: flash delay chains and cyclic delay chains. Expanding the range of flash delay chain multi-event time-to-digital converters can be achieved by increasing the number of delay chain stages. However, this approach consumes a significant amount of on-chip resources (such as CARRY4 resources in FPGAs or inverter resources in ASICs), making it difficult to significantly increase the range given limited hardware resources. Furthermore, excessively long delay chains can lead to performance degradation at the end of the delay chain due to the continuous accumulation of integral nonlinearity. Increasing the range of cyclic delay chain multi-event time-to-digital converters can be achieved by increasing the number of delay chain cycles. However, since these multi-event time-to-digital converters require a certain amount of time to read each event (i.e., readout dead time), further increases in the sampling rate of these multi-event time-to-digital converters are severely restricted.

[0005] Traditional histogram statistical functions are often implemented using a time-addressed approach. This involves presetting a memory array, where each memory cell address represents a time value. When a TDC measures a time value, the time value is used as the memory cell address to store the measurement result. This approach, when used in a multi-event time-to-digital converter (MECTC), requires multiple addressing and storage operations for each piece of time information. This increases the MECTC's dead time and thus limits its event sampling rate.

[0006] To sum up, the multi-event time-to-digital converter in the existing technology has a short range, and the traditional histogram statistical function is often implemented using a time addressing method. This method is used for the multi-event time-to-digital converter, which requires multiple addressing and storage operations for multiple time information respectively, which will increase the dead time of the multi-event time-to-digital converter, thereby limiting the event sampling rate of the multi-event time-to-digital converter and other problems. The applicant has made corresponding explorations to solve this problem. Summary of the Invention

[0007] The purpose of the present application is to solve the above-mentioned problem and provide a multi-event time-to-digital converter with an expandable range.

[0008] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0009] A multi-event time-to-digital converter with an extendable range is proposed to meet one of the purposes of this application, comprising:

[0010] A synchronization signal generation module, configured to generate a start signal and a synchronization signal, wherein the start signal is used to trigger the TDC delay chain to generate a coarse counting clock signal, and the synchronization signal is used to trigger an external application to generate end signals corresponding to multiple acquisition events;

[0011] a T flip-flop array, configured to encode the end signal according to a timing of the acquisition event to generate an edge-changing signal from the end signal, wherein both a rising edge and a falling edge of the edge-changing signal represent an arrival time of the acquisition event;

[0012] A TDC delay chain, configured to generate a time stamp corresponding to the edge-changing signal in each delay unit, wherein the time stamp represents an arrival time of the acquisition event;

[0013] an XOR gate module, configured to perform a logical judgment based on a time stamp corresponding to the edge change signal to determine an event distribution corresponding to the acquisition event;

[0014] a D flip-flop array, configured to latch an event distribution corresponding to the acquisition event and store it in a corresponding storage unit in each coarse counting clock cycle until the measurement of M coarse counting clock cycles is completed, wherein the event distribution represents a time difference between an end signal and a start signal corresponding to the acquisition event in each coarse counting clock cycle;

[0015] A histogram statistics module is used to distribute the time difference between the end signal and the start signal corresponding to the acquisition event to each time interval range to generate a statistical histogram of event distribution corresponding to the acquisition event of M coarse counting clock cycles.

[0016] Optionally, the multi-event time-to-digital converter includes M coarse counting clock cycles; the TDC delay chain includes N delay units; the histogram statistics module is constructed by a storage module array, wherein the storage module array includes N storage modules, wherein each storage module includes M storage units, the delay units in the TDC delay chain correspond to the storage modules in the histogram statistics module, and each storage unit in the histogram statistics module corresponds to each coarse counting clock cycle.

[0017] Optionally, when entering the second coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the first coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address 0 corresponding to the first coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back in the storage unit with the storage unit address 0 in the third coarse counting clock cycle;

[0018] When entering the third coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the second coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 1 corresponding to the second coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 1 in the fourth coarse counting clock cycle;

[0019] By analogy, in the M+1th coarse counting clock cycle, the D flip-flop and the XOR gate module capture the event distribution within the Mth coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address M-1 corresponding to the Mth coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and then store it back to the storage unit with the storage unit address M-1 in the M+2th coarse counting clock cycle, until the event distribution storage of M coarse counting clock cycles is completed, so as to complete one measurement of the range of the multi-event time-to-digital converter.

[0020] Optionally, the event distribution of the first storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the first coarse counting clock cycle, the event distribution of the second storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the second coarse counting clock cycle, and the reading is carried out in sequence until the event distribution of the Mth storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the Mth coarse counting clock cycle, so as to complete the histogram statistical data output of a measurement in the statistical histogram module.

[0021] Optionally, the range of the multi-event time-to-digital converter is expressed as:

[0022] K=M×T=M×N×Δt,

[0023] Wherein, K represents the range of the multi-event time-to-digital converter, M represents the number of coarse counting clock cycles, T represents the duration of the coarse counting clock cycle, N represents the number of delay units, and Δt is the width of the delay unit, which represents the delay time length of the delay unit.

[0024] Optionally, the multi-event time-to-digital converter is implemented based on a field programmable gate array or an application-specific integrated circuit.

[0025] Optionally, the synchronization signal generation module is implemented by an MMCM clock management unit in a field programmable gate array.

[0026] Optionally, the storage module array is implemented by BLOCK RAM storage resources in a field programmable gate array.

[0027] Optionally, the external application includes a single photon detector or a medium- and long-range lidar.

[0028] Compared with the prior art, the present application addresses the problem that traditional histogram statistical functions in the prior art are often implemented using a time addressing method. This method, when used in a multi-event time-to-digital converter, requires multiple addressing and storage operations for multiple time information, which increases the dead time of the multi-event time-to-digital converter and thus limits the event sampling rate of the multi-event time-to-digital converter. The present application includes but is not limited to the following beneficial effects:

[0029] First, the multi-event time-to-digital converter with scalable range of the present application, each delay unit is paired with a storage module to work synchronously to store the arrival time of multiple events. This design allows continuous time sampling of multiple events in a delay chain without the need to provide a separate time tracking unit for each event. By multiplexing the delay units in the delay chain, the range of the TDC can be effectively extended, allowing multiple events to be processed simultaneously. Each multiplexing increases the measurement time range of a delay chain (which is also equal to the coarse counting clock period), and more events can be tracked at the same time, improving the sampling capability of the system.

[0030] Secondly, the time accuracy of the scalable multi-event time-to-digital converter of this application is determined by the delay chain. This means that the system's time resolution is directly dependent on the accuracy of the delay chain, which is composed of multiple delay units. The accuracy of each delay unit determines the system's time sampling accuracy. By adopting a "first-in, first-out" (FIFO) storage mode, the storage module introduces almost no additional dead time. FIFO storage mode allows for the immediate storage of events upon their arrival, reducing the time delay or "dead time" in traditional storage systems, thereby maintaining high sampling rates and time accuracy in multi-event TDC designs.

[0031] Third, the scalable range multi-event time-to-digital converter of this application can control the increase in the range of the multi-event time-to-digital converter by the number of delay chain reuses. Each delay chain reuse increases the delay chain measurement time range, thereby expanding the range of the multi-event time-to-digital converter. This method neither sacrifices time accuracy nor affects the event sampling rate. By controlling the number of delay chain reuses, the range of the TDC can be precisely adjusted.

[0032] Fourth, each storage module is designed with sufficient depth to store statistical information for multiple events. This depth enables the system to perform long-term, continuous on-chip histogram statistics. Histogram statistics is a data processing process that generates a histogram of time distribution by collecting the arrival time of each event and classifying it into corresponding time intervals. This statistical method is very useful for analyzing the arrival time of events and the operating status of the system. Compared with traditional external memory, on-chip storage can provide faster read and write operations and reduce data transmission latency. This enables this method to continuously perform statistics on event data without relying on external storage, making it suitable for application scenarios that require high speed and high precision.

[0033] Furthermore, the scalable multi-event time-to-digital converter of this application, by optimizing the storage structure (FIFO mode) and delay chain multiplexing, can not only significantly increase the range of the multi-event time-to-digital converter, but also maintain high time resolution without sacrificing the event sampling rate. Through the design of on-chip histogram statistics, the system can collect data over a long period of time and quickly generate the distribution of event arrival times, which is of great significance for scenarios such as high-performance timing applications, experimental data acquisition, and high-frequency transient event monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0035] Figure 1 This is an exemplary architecture of a multi-event time-to-digital converter with scalable range in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of a T flip-flop and its typical input and output waveforms in an embodiment of the present application;

[0037] Figure 3 Schematic diagram of a delay chain and D flip-flop-XOR gate readout circuit architecture in an embodiment of the present application;

[0038] Figure 4 Schematic diagram of the state transition process of the histogram statistics module in an embodiment of the present application.

[0039] Figure 5 This is a schematic diagram of a structural diagram corresponding to a storage module array and a delay unit in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the time series of histogram statistics in an embodiment of the present application;

[0041] Figure 7 Schematic diagram of the timing of reading out histogram data in an embodiment of the present application.

[0042] Figure 8 Schematic diagram of the time domain line shape of two LED emission pulses measured by the multi-event time-to-digital converter with expandable range implemented based on FPGA in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limiting the present application.

[0044] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0045] Unless expressly stated to be mutually exclusive, the various embodiments disclosed in this application may be cross-combined with the relevant technical features of the various embodiments to flexibly construct new embodiments, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or resolve certain deficiencies in the prior art. Those skilled in the art should be aware of such flexibility.

[0046] In one embodiment of the multi-event time-to-digital converter with an expandable range of the present application, the multi-event time-to-digital converter with an expandable range includes: a synchronization signal generation module, a T trigger array, a TDC delay chain, an XOR gate module, a D trigger array, and a histogram statistics module, etc.

[0047] A synchronization signal generation module, configured to generate a start signal and a synchronization signal, wherein the start signal is used to trigger the TDC delay chain to generate a coarse counting clock signal, and the synchronization signal is used to trigger an external application to generate end signals corresponding to multiple acquisition events;

[0048] a T flip-flop array, configured to encode the end signal according to a timing of the acquisition event to generate an edge-changing signal from the end signal, wherein both a rising edge and a falling edge of the edge-changing signal represent an arrival time of the acquisition event;

[0049] A TDC delay chain, configured to generate a time stamp corresponding to the edge-changing signal in each delay unit, wherein the time stamp represents an arrival time of the acquisition event;

[0050] an XOR gate module, configured to perform a logical judgment based on a time stamp corresponding to the edge change signal to determine an event distribution corresponding to the acquisition event;

[0051] a D flip-flop array, configured to latch an event distribution corresponding to the acquisition event and store it in a corresponding storage unit in each coarse counting clock cycle until the measurement of M coarse counting clock cycles is completed, wherein the event distribution represents a time difference between an end signal and a start signal corresponding to the acquisition event in each coarse counting clock cycle;

[0052] A histogram statistics module is configured to distribute the time difference between the end signal and the start signal corresponding to the acquisition event to various time intervals to generate a statistical histogram of the event distribution corresponding to the acquisition event over M coarse count clock cycles. The multi-event time-to-digital converter includes M coarse count clock cycles, and controlling the size of M can control the range of the multi-event time-to-digital converter. The TDC delay chain includes N delay cells. The histogram statistics module is constructed from a storage module array, wherein the storage module array includes N storage modules, each storage module includes M storage cells, the delay cells in the TDC delay chain correspond to the storage modules in the histogram statistics module, and each storage cell in the histogram statistics module corresponds to each coarse count clock cycle. The exclusive-OR gate module can be an XOR array.

[0053] The coarse count clock cycle is the basic unit used to capture event timing in a TDC. Each coarse count clock cycle captures the distribution of events occurring within that cycle. This distribution is stored in a storage module within the histogram statistics module. During each coarse count clock cycle, the output of the XOR gate (i.e., the result of combining multiple delay cells) is fed into the storage module. The storage module accumulates the stored value with the current XOR gate output, effectively combining the event data for the current clock cycle with the previously accumulated data, thereby achieving data accumulation. The address of each storage cell is dynamically adjusted. That is, as the coarse count clock advances, the read and write addresses of the storage module are updated sequentially. This ensures that data is accumulated and stored in the chronological order of event occurrence. Each storage module has multiple storage cells, each storing a time distribution data item (e.g., the time locations of multiple events within a time period).

[0054] In each coarse counting clock cycle, the first storage module and the second storage module will respectively process the data output by an XOR gate. These data are stored in different storage units by gradual accumulation. Each storage unit corresponds to the event information within a time period.

[0055] The main function of the XOR gate is to combine the outputs of multiple delay units to generate new timing information. By feeding the outputs of every two delay units into an XOR gate, these signals can be synthesized. The output of each XOR gate reflects the synthesis result of certain timing information. For example, if the time difference between two delay units is critical data, the XOR gate can synthesize these time differences through its logical operation (usually). For example, the output of 423 XOR gates corresponds to the synthesis result of 424 delay units after pairing them together. These output results reflect the timing information captured from the input event data.

[0056] In each coarse counting clock cycle, the output of the XOR gate is added to the previously accumulated data in the storage module. This approach ensures that data over multiple clock cycles can be accumulated and ultimately generate complete timing data in the storage module.

[0057] During the first coarse counting clock cycle, the first storage unit of the storage module receives and accumulates the event data of the first clock cycle. Similarly, with the arrival of each new coarse counting clock cycle, the storage module gradually reads and accumulates the event data.

[0058] Ultimately, all event time series data are gradually stored in different storage units, and finally these data can be used for statistics and analysis, such as generating statistical histograms.

[0059] In some embodiments, a delay chain is used to generate fine counts for a multi-event time-to-digital converter. The delay time length of each delay unit (referred to as a bin) in the delay chain serves as the minimum resolution time unit of the multi-event time-to-digital converter. Assume that the delay chain includes N bins, and the width of each delay unit (bin) is Δt. The measurement range of the multi-event time-to-digital converter includes M coarse count clock cycles, and the coarse count clock cycle length is T. The expression for the measurement range of the multi-event time-to-digital converter is:

[0060] K=M×T=M×N×Δt,

[0061] Wherein, K represents the range of the multi-event time-to-digital converter, M represents the number of coarse counting clock cycles, T represents the duration of the coarse counting clock cycle, N represents the number of delay units, and Δt is the width of the delay unit, which represents the delay time length of the delay unit.

[0062] In some embodiments, the input signal is encoded by a T flip-flop with its T port set to "1", such as Figure 2 As shown, the rising edges of multiple events arriving at different times are converted into edge-changing signals. The rising and falling edges of the edge-changing signals both represent the arrival time of the events. The signal encoded by the T flip-flop (i.e., the edge-changing signal) enters the TDC delay chain for time measurement.

[0063] The XOR gate output data "0" and "1" represent "no event" and "presence event" of this delay chain unit.

[0064] The clock signal is used as the coarse counting clock of the multi-event TDC, and the rising edge of the clock signal is used as the starting point of the multi-event TDC measurement range.

[0065] In some embodiments, the multi-event time-to-digital converter is implemented based on a field programmable gate array or a dedicated integrated circuit; the synchronization signal generation module is implemented by the MMCM clock management unit in the field programmable gate array; the storage module array is implemented by the BLOCK RAM storage resource in the field programmable gate array; the external applications include but are not limited to single photon detectors and medium and long-range lidars.

[0066] Specifically, the multi-event time-to-digital converter with an expandable range of the present application can be implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The present application uses the multi-event time-to-digital converter with an expandable range based on a field programmable gate array as an example, which does not constitute a limitation to the present application.

[0067] See also Figure 1 The basic structure of the multi-event time-to-digital converter with scalable range in this application is as follows: Figure 1 As shown, the synchronization signal generation module is implemented by the MMCM clock management unit in the field programmable gate array (FPGA), wherein the MMCM clock management unit generates a clock signal with a coarse counting clock period of 5.0ns as the coarse counting clock signal of the multi-event time-to-digital converter (TDC); the CARRY4 module in the field programmable gate array is used as the basic delay unit, and the TDC delay chain of the multi-event time-to-digital converter is constructed by cascading CARRY4. The entire TDC delay chain has a total of 424 delay units, and the output interface of each delay unit is the CO port of CARRY4. The delay time (i.e., bin width) of each delay unit determines the accuracy of the multi-event time-to-digital converter (TDC) time measurement. The use of advanced process FPGA chips can realize a delay unit with an average delay time of 12.0ps, thereby realizing a multi-event time-to-digital converter (TDC) with a time measurement accuracy of 12.0ps.

[0068] See also Figure 2 , a T flip-flop is constructed using the D flip-flop module in the field programmable gate array, and the end signal (STOP signal) corresponding to the acquisition event is input into the clock port of the T flip-flop to convert it into an edge change signal; Figure 3 As shown, the output port of the T flip-flop is connected to the D flip-flop, and the output state of the T flip-flop is latched at the rising edge of the coarse counting clock; the LUT resource is used to build a two-input XOR gate module, and the output ends of the adjacent D flip-flops are connected to the XOR gate. The output state of the XOR gate represents the moment when the event arrives, that is, the event distribution corresponding to the acquisition event.

[0069] The synchronous pulse signal generated by the coarse counting clock serves as the start signal (START signal) for the multi-event time-to-digital converter (TDC). This start signal has a pulse width of 5.0 ns, indicating that each triggering of the start signal lasts 5.0 ns. It is used to determine the time window within which the multi-event time-to-digital converter begins timing. The start signal period is the number of coarse counting cycles (M) of the multi-event time-to-digital converter multiplied by the coarse counting clock cycle length, where the coarse counting clock cycle length is 5.0 ns. An external input signal serves as the end signal (STOP signal) for the multi-event time-to-digital converter (TDC); this external input signal can be a signal from a single-photon detector or a control signal from a controller.

[0070] The BLOCKRAM resources inside the field programmable gate array are used to build a storage module array (i.e., histogram statistics module). Since the TDC delay chain has a total of 424 delay units, and the outputs of two adjacent delay units are connected to an XOR gate module, it can be seen that there are a total of 423 storage modules in the storage module array. Each storage module reserves space for 8192 (or more) storage units for adjusting the storage depth and the range of the multi-event time-to-digital converter. Each storage unit is set to 32 bits, and can store a maximum of 2 32 -1 event.

[0071] More specifically, each delay cell does not directly correspond to a single memory module. Since the outputs of two adjacent delay cells are fed into the same XOR gate, this design means that within each coarse count clock cycle, the outputs of two adjacent delay cells are combined and processed. Therefore, the outputs of the 424 delay cells are effectively mapped one-to-one to the 423 memory modules.

[0072] In a further embodiment, the range of the multi-event time-to-digital converter can be set according to the requirements of external applications such as single-photon detectors, and the value of the coarse counting cycle number M of the multi-event time-to-digital converter can be set. For example, assuming that the single-photon detector requires a measurement range of 1000.0ns, the value of the coarse counting cycle number M of the multi-event time-to-digital converter is set to 200, that is, each storage module initializes 200 storage cells for storing measurement results. At the same time, this also means that the TDC delay chain is reused 200 times, so that the maximum range of the multi-event time-to-digital converter reaches 5.0ns×200=1000.0ns. The number of measurements P is input to the measurement number register of the multi-event time-to-digital converter, which means that the histogram statistics are repeated P times to obtain statistically significant results, where the P value is usually set at 10 3 above.

[0073] In some embodiments, when entering the second coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the first coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address 0 corresponding to the first coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address 0 in the third coarse counting clock cycle;

[0074] When entering the third coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the second coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 1 corresponding to the second coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 1 in the fourth coarse counting clock cycle;

[0075] By analogy, in the M+1th coarse counting clock cycle, the D flip-flop and the XOR gate module capture the event distribution within the Mth coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address M-1 corresponding to the Mth coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and then store it back to the storage unit with the storage unit address M-1 in the M+2th coarse counting clock cycle, until the event distribution storage of M coarse counting clock cycles is completed, so as to complete one measurement of the range of the multi-event time-to-digital converter.

[0076] Specifically, in the first coarse counting clock cycle of the multi-event time-to-digital converter, its rising edge serves as the starting point of the multi-event time-to-digital converter's range. This signal can also be used as a synchronization signal for external instruments, such as being output to the outside as a trigger signal for an external light source to cause it to emit a light pulse; the light pulse emitted by the light source acts on the sample, and the light signal reflected or re-emitted is detected by the single-photon detector; the multiple events detected by the single-photon detector within the same signal cycle are sent to the end terminal (STOP terminal) of the multi-event time-to-digital converter to achieve time-correlated single photon counting (TCSPC) measurement.

[0077] See also Figures 4 to 6 After the measurement is turned on, in the second coarse counting clock cycle of the multi-event time-to-digital converter, the coarse counting clock captures the event distribution within the first coarse counting clock cycle. At this time, the read address of the first storage module is set to 0, that is, the address of the first storage unit. The data in this unit is read out and accumulated with the output data of the first XOR gate. The data is input to the address unit in the third coarse counting clock cycle. The read address of the second storage module is also set to 0, accumulated with the output data of the second XOR gate, and re-input to the address unit.

[0078] During the third coarse count clock cycle of the multi-event time-to-digital converter, the coarse count clock captures the event distribution within the second clock cycle. At this point, the first storage module readout address is set to 1, which corresponds to the second storage cell address. The data within this cell is read out and added to the output data of the first XOR gate. The data is then input to this address cell during the fourth coarse count clock cycle. The second storage module readout address is also set to 1, added to the output data of the second XOR gate, and re-input to this address cell. This process is repeated M times, completing a statistical analysis of the distribution of all events within the range of the multi-event time-to-digital converter. This process continues until all 423 XOR gate data are stored, completing a measurement of the range of the multi-event time-to-digital converter.

[0079] After completing a multi-event time-to-digital converter range measurement, the measurement times counter of the multi-event time-to-digital converter range is increased by one, and the above steps are repeated until the measurement times counter value of the multi-event time-to-digital converter is equal to the setting value P of the measurement times register of the multi-event time-to-digital converter, thereby completing the histogram statistical measurement of the time domain distribution of the incident signal.

[0080] The output of each XOR gate represents the result of synthesizing a timing information set. The data from each XOR gate is fed into a storage module and accumulated with previously stored event data. The storage process is performed in the order of the coarse-count clock cycles: the first and second storage modules store the output data of each XOR gate, respectively, and gradually accumulate them within each coarse-count clock cycle. The 423 XOR gate data are obtained by pairing each of the 424 delay units with an XOR gate. Ultimately, the timing information of the event is captured and stored through the output of the XOR gate. In this way, the timing data of each event in the multi-event time-to-digital converter can be effectively merged and stored, providing a data foundation for further statistics and analysis.

[0081] In a further embodiment, the event distribution of the first storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the first coarse counting clock cycle, the event distribution of the second storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the second coarse counting clock cycle, and the reading is sequentially performed until the event distribution of the Mth storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the Mth coarse counting clock cycle, so as to complete the histogram statistical data output of a measurement in the statistical histogram module.

[0082] Specifically, see Figure 7 After completing the required P histogram statistics, the histogram statistical data is output, the histogram data is output, and the event distribution of the first storage unit of the 423 storage modules in the statistical histogram module is reconstructed in chronological order. The event distribution of the second storage unit of the 423 storage modules in the statistical histogram module is read to determine the event distribution within the first coarse counting clock cycle. The event distribution of the second storage unit of the 423 storage modules in the statistical histogram module is read to determine the event distribution within the second coarse counting clock cycle. The event distribution is read in sequence until the event distribution of the Mth storage unit of the 423 storage modules in the statistical histogram module is read to determine the event distribution within the Mth coarse counting clock cycle. This is repeated by analogy. The data in the 423 storage modules in all the statistical histogram modules are output to complete the statistical histogram data output.

[0083] In some embodiments, see Figure 8 , the single photon detector includes a single photon avalanche diode detector, Figure 8The time domain line shape of two light emitting diodes (LEDs) emitting light pulses under pulse drive was measured by combining a multi-event time-to-digital converter with an scalable range implemented based on FPGA and a single-photon avalanche diode detector, verifying that the range of the multi-event time-to-digital converter of the present application can reach 1000.0ns.

[0084] As can be seen from the above embodiments, compared to the prior art, the present application addresses the problems of the short range of the multi-event time-to-digital converter in the prior art and the fact that the traditional histogram statistical function is often implemented using a time addressing method. This method, when used in a multi-event time-to-digital converter, requires multiple addressing and storage operations for multiple time information, which increases the dead time of the multi-event time-to-digital converter and thus limits the event sampling rate of the multi-event time-to-digital converter. The present application includes but is not limited to the following beneficial effects:

[0085] First, in the multi-event time-to-digital converter of the present application with scalable range, each delay unit is paired with a storage module to synchronously store the arrival times of multiple events. This design allows continuous time sampling of multiple events in a delay chain without the need to provide a separate time tracking unit for each event. By multiplexing the delay units in the delay chain, the range of the TDC can be effectively extended, allowing multiple events to be processed simultaneously. Each multiplexing increases the measurement time range of a delay chain, and more events can be tracked at the same time, improving the sampling capability of the system.

[0086] Secondly, the time accuracy of the scalable multi-event time-to-digital converter of this application is determined by the delay chain. This means that the system's time resolution directly depends on the accuracy of the delay chain, which is composed of multiple delay units. The accuracy of each delay unit determines the system's time sampling accuracy. By adopting a "first-in, first-out" (FIFO) storage mode, the storage module introduces almost no additional dead time. FIFO storage mode allows for the instantaneous storage of event arrival times, reducing the time delay or "dead time" in traditional storage systems, thereby maintaining high sampling rates and time accuracy in multi-event TDC designs.

[0087] Third, the scalable range multi-event time-to-digital converter of this application can control the increase in the range of the multi-event time-to-digital converter by the number of delay chain reuses. Each delay chain reuse increases the delay chain measurement time range, thereby expanding the range of the multi-event time-to-digital converter. This method neither sacrifices time accuracy nor affects the event sampling rate. By controlling the number of delay chain reuses, the range of the TDC can be precisely adjusted.

[0088] Fourth, each storage module is designed with sufficient depth to store statistical information for a sufficient number of events. This storage depth enables the system to perform long-term, continuous on-chip histogram statistics. Histogram statistics is a data processing process that generates a histogram of time distribution by collecting the arrival time of each event and classifying it into corresponding time intervals. This statistical method is very useful for analyzing the arrival time of events and the operating status of the system. Compared with traditional external memory, on-chip storage can provide faster read and write operations and reduce data transmission latency. This enables this method to continuously perform statistics on event data without relying on external storage, making it suitable for application scenarios that require high speed and high precision.

[0089] Furthermore, the scalable multi-event time-to-digital converter of this application, by optimizing the storage structure (FIFO mode) and delay chain multiplexing, can not only significantly increase the range of the multi-event time-to-digital converter, but also maintain high time resolution without sacrificing the event sampling rate. Through the design of on-chip histogram statistics, the system can collect data over a long period of time and quickly generate the distribution of event arrival times, which is of great significance for scenarios such as high-performance timing applications, experimental data acquisition, and high-frequency transient event monitoring.

[0090] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A multi-event time-to-digital converter with an expandable range, characterized in that: include: A synchronization signal generation module, configured to generate a start signal and a synchronization signal, wherein the start signal is used to trigger the TDC delay chain to generate a coarse counting clock signal, and the synchronization signal is used to trigger an external application to generate end signals corresponding to multiple acquisition events; a T flip-flop array, configured to encode the end signal according to a timing of the acquisition event to generate an edge-changing signal from the end signal, wherein both a rising edge and a falling edge of the edge-changing signal represent an arrival time of the acquisition event; A TDC delay chain, configured to generate a time stamp corresponding to the edge-changing signal in each delay unit, wherein the time stamp represents an arrival time of the acquisition event; an XOR gate module, configured to perform a logical judgment based on a time stamp corresponding to the edge change signal to determine an event distribution corresponding to the acquisition event; a D flip-flop array, configured to latch an event distribution corresponding to the acquisition event and store it in a corresponding storage unit in each coarse counting clock cycle until the measurement of M coarse counting clock cycles is completed, wherein the event distribution represents a time difference between an end signal and a start signal corresponding to the acquisition event in each coarse counting clock cycle; A histogram statistics module is used to distribute the time difference between the end signal and the start signal corresponding to the acquisition event to each time interval range to generate a statistical histogram of event distribution corresponding to the acquisition event of M coarse counting clock cycles.

2. The multi-event time-to-digital converter with scalable range according to claim 1, characterized in that: The multi-event time-to-digital converter includes M coarse counting clock cycles; the TDC delay chain includes N delay units; The histogram statistics module is constructed by a storage module array, wherein the storage module array includes N storage modules, wherein each storage module includes M storage units, the delay units in the TDC delay chain correspond to the storage modules in the histogram statistics module, and each storage unit in the histogram statistics module corresponds to each coarse count clock cycle.

3. The multi-event time-to-digital converter with scalable range according to claim 2, wherein: When entering the second coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the first coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address 0 corresponding to the first coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store the result back to the storage unit with the storage unit address 0 in the third coarse counting clock cycle; When entering the third coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the second coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 1 corresponding to the second coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 1 in the fourth coarse counting clock cycle; By analogy, in the M+1th coarse counting clock cycle, the D flip-flop and the XOR gate module capture the event distribution within the Mth coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address M-1 corresponding to the Mth coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and then store it back to the storage unit with the storage unit address M-1 in the M+2th coarse counting clock cycle, until the event distribution storage of M coarse counting clock cycles is completed, so as to complete one measurement of the range of the multi-event time-to-digital converter.

4. The multi-event time-to-digital converter with scalable range according to claim 3, characterized in that: The event distribution of the first storage unit of each storage module in the histogram statistics module is read to determine the event distribution within the first coarse counting clock cycle, and the event distribution of the second storage unit of each storage module in the histogram statistics module is read to determine the event distribution within the second coarse counting clock cycle. The event distribution is read in sequence until the event distribution of the Mth storage unit of each storage module in the histogram statistics module is read to determine the event distribution within the Mth coarse counting clock cycle, so as to complete the histogram statistical data output of one measurement in the histogram statistics module.

5. The multi-event time-to-digital converter with scalable range according to claim 2, characterized in that: The range of the multi-event time-to-digital converter is expressed as: ； in, K Indicates the range of the multi-event time-to-digital converter, M Indicates the number of coarse counting clock cycles, T Indicates the length of the coarse counting clock cycle, N Indicates the number of delay units, Δ t is the width of the delay unit, which represents the delay time length of the delay unit.

6. The multi-event time-to-digital converter with scalable range according to claim 1, wherein: The multi-event time-to-digital converter is implemented based on a field programmable gate array or a dedicated integrated circuit.

7. The multi-event time-to-digital converter with scalable range according to claim 1, characterized in that: The synchronization signal generation module is implemented by the MMCM clock management unit in the field programmable gate array.

8. The multi-event time-to-digital converter with scalable range according to claim 2, wherein: The storage module array is implemented by BLOCK RAM storage resources in a field programmable gate array.

9. The multi-event time-to-digital converter with scalable range according to claim 1, characterized in that: The external applications include single photon detectors or medium and long-range lidars.

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