Soft bit data processing method, device and storage medium

Abstract

The present invention discloses a soft bit data processing method, device and storage medium, which relates to the field of wireless communications, in order to reduce the consumption of resources during data deinterleaving and rate matching. The present invention receives soft bit data, determines the write address of the soft bit data into a storage unit; writes the soft bit data into the storage unit according to the write address to obtain first data; and reads the first data from the storage unit for rate matching. The present invention designs the read and write addresses, only needs to use a single storage unit, and combined with the designed rate matching operation, no additional cache is needed, which effectively reduces the power consumption and area, and reduces the consumption of resources.

Description

Technical Field

[0001] The present invention relates to the field of wireless communications, and in particular to a soft bit data processing method, a soft bit data processing device, and a computer-readable storage medium. Background Art

[0002] In wireless communications, especially in 5G NR systems, interleaving is the exchange of coded data to combat channel fading. Rate matching aligns the number of coded bits with the actual number of available transmission resources. Corresponding deinterleaving and derate matching operations exist in the downlink PDSCH channel. HARQ is a key technology to improve system throughput. In 5G LDPC, the code generates the corresponding check bits, and rate matching is required to support HARQ and different transmission code rates. In addition, the discrete shift factor size of QC-LDPC also has some limitations on the support of information block size and code length, and rate matching needs to be achieved through additional padding and puncturing.

[0003] In 5G NR, a circular buffer is usually used to implement HARQ and rate matching, that is, the coded bits are stored in the circular buffer, and each time they are read sequentially from the circular buffer according to the redundant version, so as to achieve rate matching. In the prior art, the received data packets are stored in a circular buffer, and the number of storage areas in the circular buffer is the same as the modulation order, so as to achieve parallel deinterleaving and rate matching of 5G NR LDPC codes. However, in 5G NR LDPC decoding, the deinterleaving process is implemented by row-column transformation operations, and the rate matching is implemented by superimposing or filling the soft bits of the circular buffer. Usually, multiple cache spaces are required to achieve deinterleaving and rate matching, and the required resources are large. Summary of the invention

[0004] The object of the present invention is to provide a soft bit data processing method, device and storage medium to reduce the consumption of resources during data deinterleaving and rate matching in order to solve all or part of the above problems.

[0005] The technical solution adopted by the present invention is as follows:

[0006] The present invention provides a soft bit data processing method, the method comprising:

[0007] receiving soft bit data, and determining a write address at which the soft bit data is written into a storage unit;

[0008] Writing the soft bit data into a storage unit according to the write address to obtain first data;

[0009] The first data is read out from the storage unit for rate dematching.

[0010] The present invention also provides a computer-readable storage medium storing a computer program, and running the computer program can execute the above-mentioned soft bit data processing method.

[0011] The present invention also provides a soft bit data processing device, including a processor and a storage medium, wherein the storage medium stores a computer program, and the processor is configured to execute the computer program in the storage medium to execute the above-mentioned soft bit data processing method.

[0012] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0013] 1. The present invention uses a single storage unit to achieve deinterleaving and rate matching of soft bit data by calculating and allocating read and write addresses of soft bit data, which effectively reduces power consumption and resource consumption.

[0014] 2. In the process of rate matching, the present invention designs a zero-value filling process, which can flexibly fill the punctured bits, invalid bits and insufficient tail length that need to be filled during rate matching, and the entire process from input to output of soft bit data does not require additional cache.

[0015] 3. The present invention supports different redundant versions in the process of rate matching, and can adaptively calculate the read address according to different starting bits of the circular buffer. The strategy supports a variety of zero-value filling situations such as invalid bit filling and puncturing, without the need to handle them separately for each situation, and has strong versatility.

[0016] 4. The present invention starts to fill the punctured bits during the deinterleaving process, and automatically starts to fill invalid bits or zero values ​​after reading the corresponding bits of the soft bit data. The execution is smooth and the deinterleaving rate matching efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0018] Figure 1 is a diagram of a circular buffer model.

[0019] Figure 2 FIG. 4 is a data flow diagram of a soft bit data processing method in one embodiment.

[0020] Figure 3 FIG. 4 is a flow chart of a soft bit data processing method in one embodiment.

[0021] Figure 4 is a structural diagram of a soft bit data processing device in one embodiment.

[0022] Figure 5It is a structural diagram of a soft bit data processing device in another embodiment. DETAILED DESCRIPTION

[0023] All features disclosed in this specification, or steps in all methods or processes disclosed, except mutually exclusive features and / or steps, can be combined in any manner.

[0024] Any feature disclosed in this specification (including any additional claims and abstract), unless otherwise stated, may be replaced by other equivalent or alternative features having similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

[0025] According to the basic idea of ​​the present application, in some embodiments, the processing of soft bit data is implemented by a single storage unit (hereinafter described as RAM as an example), and for the received soft bit data, by calculating the write address of the storage unit, the deinterleaving operation is completed when the received soft bit data is written into the RAM, and the first data is obtained after the deinterleaving operation is completed on the received soft bit data, that is, the first data obtained after the soft bit data is deinterleaved is stored in the RAM. Then the deinterleaved first data is read out from the RAM for rate matching, for example, by calculating the read address, the first data is read out from the RAM for rate matching.

[0026] According to the basic idea of ​​the present application, in some embodiments, the row-column transformation matrix used in deinterleaving can be used to determine the write address when writing to the RAM based on the characteristic that the coordinates determine the output order. Specifically, the received soft bit data is stored in the row-column transformation matrix, and the write address of the soft bit data written to the RAM is determined based on the order in which the soft bit data is read out from the row-column transformation matrix. For example, in terms of the read-out order, the soft bit data can be stored in the row-column transformation matrix in columns, and then the soft bit data can be read out from the row-column transformation matrix in rows. At the computational level, the order in which the soft bit data is read out from the row-column transformation matrix can be determined based on the position in the row-column transformation matrix, and then the write address of the soft bit data can be calculated. The so-called position in the row-column transformation matrix, that is, the row and column in the row-column transformation matrix, can determine the row and column where the element is read each time according to the rule of reading elements from the row-column transformation matrix, and then determine the order in which each element is read.

[0027] In some specific embodiments, row and column counters are used to record the position of the soft bit data in the row-column transformation matrix, for example, counter row_cnt and counter col_cnt are set to indicate the position of the current soft bit data in the row-column transformation matrix, wherein counter row_cnt records the row (starting from 0) where the soft bit data is located in the row-column transformation matrix, and counter col_cnt records the column (also starting from 0) where the soft bit data is located in the row-column transformation matrix. Assume that the number of rows of the row-column transformation matrix is ​​represented by R, and the number of columns is represented by C, wherein R is determined by the modulation order Q of the current data demodulation. m Determine, and C is E represents the length before rate matching. Then the write address allocated to the soft bit data according to the records of the counter row_cnt and the counter col_cnt is:

[0028] dint_waddr=col_cnt+C*row_cnt;

[0029] Among them, dint_waddr represents the write address.

[0030] When each soft bit data is read out from the row-column transformation matrix, a corresponding record is generated on the counter row_cnt and the counter col_cnt respectively. According to the record, the write address in the RAM can be configured for the read soft bit data, and the read soft bit data can be written to the RAM according to the write address. This cycle can complete the deinterleaving process and deinterleave the soft bit data to obtain the first data.

[0031] In the rate matching process, the Figure 1 The circular buffer shown is used to store data, and the circular buffer length of the circular buffer is N cb , the information bit puncturing bit length is 2Z c , where Z c is the expansion factor. Figure 2 In, S i Indicates the starting position of the circular buffer, i∈[0,3]. During encoding, except for the punctured bits, the remaining bits (assuming the length is N) in the coded block are sequentially stored in the circular buffer. The starting position is determined according to the given redundancy version (RV), and the coded bits are transmitted sequentially. When the bit length in the circular buffer reaches N cb Stop filling when N>N cb In rate matching, the output length after rate matching is the length before rate matching, denoted as E, which includes padding bits (length is f, and padding bits do not participate in rate matching). If Ef>N cb , then after sending N cbThe length information is repeated until the transmission length reaches E bits; otherwise, the last bit is discarded after filling the E length information.

[0032] It can be seen that in the rate matching process, the coded data that is not transmitted includes at least the punctured bits and may also include N>N cb The bits of information discarded when Ef <N cb The last bits that are discarded when Ef is equal to N are used. These data need to be completed when solving rate matching (if they exist). In addition, during the rate matching process, when Ef>N cb Since bits are sent repeatedly, these data need to be combined when solving rate matching.

[0033] Therefore, according to the basic idea of ​​the present application, in some embodiments, the rate matching performed on the first data read from the RAM at least includes a padding process, and further, may include a merging process. Specifically, when the length after rate matching (i.e., the length before rate matching) E is greater than the circular buffer length N cb When the first data read from the RAM needs to be merged, the length E before the rate matching is within the circular buffer length N. cb Therefore, the merging operation in the rate matching solution is not used in some embodiments.

[0034] like Figure 2 As shown, according to the above-mentioned rate matching design, in some embodiments, in the rate matching link, after the first data is read out from the RAM according to the read address generated by calculation, the rate matching operation is completed by using the accumulation register and the filling data generation module. The accumulation register is used to make the length E greater than the circular buffer length N before the rate matching. cb The filling data generating module is responsible for the filling processing of the first data.

[0035] In some embodiments, the merging operation performed by the above-mentioned accumulation register is an accumulation operation on the first data. The filling processing performed by the filling data generation module includes zero value filling and invalid bit filling. Because two filling processing methods of zero value filling and invalid bit filling are designed, in the process of rate matching, the corresponding value can be adaptively filled in the position to be filled, and the corresponding filling processing is automatically performed when the corresponding position is read, without the need to perform filling processing separately for each case such as puncturing information, invalid bits, and end completion, which greatly improves the efficiency of rate matching.

[0036] For the data discarded in the rate matching process, in some embodiments, the de-rate matching (zero value filling part) operation performed on the read first data includes:

[0037] 1) Zero-filling to complete the puncturing information.

[0038] The zero-filling of this part is a process that must be included in the process of rate matching, which is to complete the position of the punctured data. Specifically, in a specific embodiment, the zero-filling of this part is a zero-filling operation on the punctured information before the rate matching is started, and the zero-filling length is the length of the punctured data, that is, 2Z c .

[0039] In addition, since the puncturing information is not stored in the circular buffer, the first data read from the RAM does not need to be considered during rate matching. Therefore, in some embodiments, there is no need to wait for the first data to be read from the RAM before completing the puncturing information. Zero value filling of the puncturing information can be performed before rate matching, for example, zero value filling of the completed puncturing information is performed during deinterleaving. By filling the puncturing bits in advance, the rate matching efficiency can be improved.

[0040] 2) Zero value padding is performed to make up for the insufficient amount of the first data read from the RAM.

[0041] As mentioned above, during the rate matching process, in Ef <N cb When the E length information is filled, the last bit will be discarded. If this situation exists, when de-rate matching, after reading all the first data in the RAM (that is, the number of first data currently read = E), the subsequent bits (that is, the other bits in the circular buffer except the invalid bits) are filled with zeros.

[0042] 3) Zero padding to make up for the shortfall in the circular buffer length compared to the rate matching output length.

[0043] This situation is for the rate matching process N>N cb In the case that the length of the remaining bits except the puncturing information exceeds the length of the circular buffer, the excess part will be discarded. Therefore, in the rate matching solution, the discarded part is padded with zeros, that is, when the rate matching solution outputs, the output end is padded with zeros, and the length is NN cb , that is, zero-filling is performed where the circular buffer length is less than the rate matching output length.

[0044] By designing the above-mentioned zero-value filling processing operation in the process of rate dematching, it is possible to flexibly fill the punctured bits, invalid bits and insufficient tail length that need to be filled during rate dematching, and the entire process from input to output of soft bit data does not require additional cache.

[0045] In addition, during rate matching, the padding bits with a length of f are also removed. Therefore, during rate matching, the position of these padding bits needs to be restored.

[0046] In some embodiments, the invalid bit filling performed when the read first data is rate-matched includes the invalid bit filling performed to complete the filling bits removed during rate matching for each soft bit data. In the specific operation, it is considered to restore the encoding of each first data in a timely manner, so the invalid bit filling is performed after reading the last information bit of each first data. Due to the use of this timely filling method, compared with the method of uniformly filling the invalid bits after reading all the first data, it is possible to avoid recalculating the position of each invalid bit, thereby reducing unnecessary calculations, improving the efficiency of rate matching, and eliminating the risk of errors in the completion position of each first data.

[0047] In order to facilitate the rate matching of the first data read from the RAM, in some embodiments, the first data stored in the RAM is segmented, and then the first data at the same position in each segment is read, and the rate matching is performed on each segment in a centralized manner. Specifically, the first data in the RAM is segmented into circular buffers according to the circular buffer length, and the read address of the first data to be read in each circular buffer segment is determined based on the position of the first data to be read in the circular buffer segment, so that the first data at the same position in each circular buffer segment can be read in sequence. The data in the RAM is segmented according to the circular buffer length, and the number of segments is the number of first data N involved in the merger each time. comb ,have When Ef>N cb When N comb >1, that is, the number of circular buffer segments reaches two or more segments, indicating that the first data needs to be accumulated and merged, and when Ef≤N cb When N comb =1, at this time, there is no need to merge the first data in the RAM.

[0048] Regarding the merging process, when reading out the first data from the RAM, all the circular buffer segments are read each time, and the first data at the same position in all the circular buffer segments are merged. Obviously, if there is only one segment, then the merging process is not required.

[0049] In some embodiments, in order to conveniently locate the position of each first data, the first counter para_cnt is used to record the order of the currently read circular buffer segment, that is, when reading the first data, the number of the current circular buffer segment is recorded; the second counter ncb_cnt is used to record the order of the currently read first data in the circular buffer segment, that is, the first data at which position in all circular buffer segments is to be read simultaneously. The above-mentioned invalid bit filling is after all information bits are read, that is, ncb_cnt = k d -1 hour (k d is the starting position of the filling bit), pause reading data from the RAM, and fill f invalid bits (usually +∞ or -∞, if it is in FPGA, take the saturation value according to the bit width). When calculating the read address of the first data, according to the record of the second counter ncb_cnt, the position of the first data to be read in the circular buffer segment is calculated based on the circular buffer starting bit k0; then the read address of the first data to be read is calculated in combination with the record of the first counter para_cnt and the effective bit length in each circular buffer segment, and the first counter para_cnt is used to traverse all the circular buffer segments to obtain the read address in all the circular buffer segments each time the first data is read. Specifically, there are:

[0050]

[0051] Among them, drm_rd_addr0 represents the position of the first data to be read out currently in the circular buffer segment, and the circular buffer start position k0 is given by the redundant version.

[0052] Then calculate the read address of the first data in each circular buffer segment (each time para_cnt is read, all circular buffer segments need to be traversed from the first circular buffer segment):

[0053] drm_rd_addr=drm_rd_addr0+(N cb -f)*para_cnt,

[0054] Among them, drm_rd_addr is the read address of the first data.

[0055] In addition, usually the first data in RAM is segmented and the length of the last segment is less than N. cb , the calculated read address may exceed the range of the write address. In this case, the read address exceeding the write address range is determined to be invalid, the first data of the read address is not read, and the part of the first data is ignored to avoid error in rate matching.

[0056] According to the embodiments of the present application, Figure 3FIG. 1 shows an embodiment of a soft bit data processing method implemented on an FPGA. In this embodiment, the execution process includes:

[0057] 1) Configure the deinterleaving and derate matching related parameters, and start receiving soft bit data packets. Initialize the counters row_cnt and col_cnt. At the same time, the derate matching output port starts to output 0 values, with a length of 2Z c , to fill the punctured bits.

[0058] 2) Calculate the soft bit data write address dint_raddr according to the records of the current counters row_cnt and col_cnt, and write the currently read soft bit data into the corresponding write address in the RAM.

[0059] 3) If all soft bit data have been written, the deinterleaving is completed. Otherwise, read the next soft bit data for writing into RAM, update the values ​​of counters row_cnt and col_cnt, and return to step 2). Specifically, the row-column transformation matrix is ​​R*C, where R represents the number of rows and C represents the number of columns. Each time a soft bit data is received, the records of counters row_cnt and col_cnt are updated as follows: if col_cnt=C-1, then col_cnt=0, and row_cnt=row_cnt+1; otherwise col_cnt=col_cnt+1, and row_cnt remains unchanged.

[0060] 4) After deinterleaving is completed, the first data in the RAM is read out, and the first data in the RAM is segmented according to the length of the circular buffer, and the number of segments N of the circular buffer is calculated. comb , the starting position of the circular buffer is k0, and the counters para_cnt and ncb_cnt are initialized at the same time.

[0061] 5) The counter ncb_cnt is used to determine the position of the first data in the circular buffer segment, and the counter para_cnt is used to select the current circular buffer segment. The current read address is calculated based on the records of the two counters, and the first data at the same position of each circular buffer segment is read each time. Figure 1 Specifically, each time a first data is read out, if para_cnt=N comb -1, then para_cnt = 0, and ncb_cnt = ncb_cnt + 1; otherwise para_cnt = para_cnt + 1, ncb_cnt remains unchanged.

[0062] 6) In the process of reading the first data from RAM, if the current bit is the last bit of the information bit, that is, ncb_cnt = k d-1, start filling invalid bits with a filling length of f; otherwise, return to step 5) and continue reading the first data at the next position in each circular buffer segment for merging.

[0063] 7) After reading all the first data in RAM, if Ef <N cb , then the subsequent bits are filled with zeros, and the zero-filling length is N cb +fE; otherwise continue.

[0064] 8) Output all N cb After N>N cb , then the subsequent bits are filled with zeros, and the zero-filling length is NN cb Otherwise, no processing is performed. The rate matching is now complete.

[0065] It can be found from the embodiments of the present application that since the deinterleaving and derate matching processes only involve data reordering and soft merging, by designing a counter to calculate the read and write addresses, only a single block of RAM is needed. Combined with flexible filling of data, there is no need to use additional cache, which effectively reduces power consumption and area, and reduces resource consumption.

[0066] According to the above embodiments of the present application, deinterleaving and derate matching can be applied in 5G NR LDPC decoding to obtain a deinterleaving and derate matching method for 5G NR LDPC decoding.

[0067] Based on the basic concept of the present application, in some embodiments, a computer-readable storage medium may be designed, in which a computer program is stored. Running the computer program may execute the soft bit data processing method of any of the above embodiments.

[0068] In addition, the soft bit data processing method can be executed by means of a processor. Specifically, based on the basic concept of the present application, a soft bit data processing device can be designed, such as Figure 4 As shown, the device includes a processor and a storage medium, in which a computer program is stored. Running the program can execute the soft bit data processing method in any of the above-mentioned embodiments. The processor is connected to the storage medium to execute the computer program in the storage medium to execute the soft bit data processing method in any of the above-mentioned embodiments.

[0069] In addition, based on the basic concept of the present application, in some embodiments, a soft bit data processing device is also designed, such as Figure 5 As shown, the device comprises:

[0070] The deinterleaving module is configured to: receive soft bit data, determine a write address for writing the soft bit data into a storage unit; write the soft bit data into the RAM according to the write address to obtain first data, and complete deinterleaving during the writing process;

[0071] The rate dematching module is configured to read the first data from the RAM to perform rate dematching.

[0072] The specific deinterleaving strategy and derate matching strategy configured in the deinterleaving module and the derate matching module can refer to the implementation method configured in any embodiment of the above-mentioned soft bit data processing method, that is, the features configured in any embodiment of the above-mentioned soft bit data processing method can be directly used in the deinterleaving module and the derate matching module here.

[0073] Specifically, in some embodiments, the deinterleaving module determines the write address of the soft bit data into the RAM according to the order in which the soft bit data is read out from the row-column transformation matrix, and the soft bit data is stored in the row-column transformation matrix after being received, and the deinterleaving is completed when the soft bit data is read out from the row-column transformation matrix and written into the RAM. For example, the storage and reading rules of the row-column transformation matrix are: the soft bit data is stored in the row-column transformation matrix in sequence by column, and then the soft bit data is read out from the row-column transformation matrix in sequence by row.

[0074] In some embodiments, the deinterleaving module determines the order in which the soft bit data is read out from the row-column transformation matrix according to the position in the row-column transformation matrix. In some embodiments, the position in the row-column transformation matrix can be recorded using row and column counters, where the counter row_cnt records the row starting from 0, and the counter col_cnt records the column starting from 0. The number of rows R of the row-column transformation matrix is ​​the modulation order Q of the current data demodulation m , the number of columns C is

[0075] Next, in an embodiment of using counters row_cnt and col_cnt to record the position of soft bit data, the deinterleaving module allocates the write address for the soft bit data according to the records of counter row_cnt and counter col_cnt as follows:

[0076] dint_waddr=col_cnt+C*row_cnt;

[0077] Among them, dint_waddr represents the write address.

[0078] Each time the deinterleaving module reads out soft bit data from the row-column transformation matrix, a corresponding record is generated on the counter row_cnt and the counter col_cnt respectively. Based on the record, the read soft bit data can be configured with a write address in the RAM, and the read soft bit data can be written to the RAM based on the write address. This cycle can complete the deinterleaving process.

[0079] For the rate dematching module, in some embodiments, the rate dematching is performed by calculating a read address for reading the first data from the RAM and reading the first data from the storage unit according to the read address.

[0080] In some embodiments, the rate de-matching module performs circular buffer segmentation on the first data in the RAM according to the circular buffer length, and determines the read address of the first data currently to be read in each circular buffer segment according to the position of the first data currently to be read in the circular buffer segment.

[0081] The position of the first data in the circular buffer segment is determined according to its order in the circular buffer segment and the start position of the circular buffer. In some embodiments, the rate matching module uses the first counter para_cnt to record the order of the currently read circular buffer segment, that is, when reading the first data, it records the number of the current circular buffer segment; and uses the second counter ncb_cnt to record the order of the currently read first data in the circular buffer segment, that is, the first data at which position in all the circular buffer segments is to be read simultaneously.

[0082] On this basis, when calculating the read address of the first data, the rate matching module calculates the position of the first data to be read in the circular buffer segment based on the record of the second counter ncb_cnt and the circular buffer start bit k0; and then calculates the read address of the first data to be read in combination with the record of the first counter para_cnt and the effective bit length in each circular buffer segment. By traversing all the circular buffer segments using the first counter para_cnt, the read address in all the circular buffer segments can be obtained each time the first data is read. Specifically, there are:

[0083]

[0084] Among them, drm_rd_addr0 represents the position of the first data to be read out currently in the circular buffer segment, and the circular buffer start position k0 is given by the redundant version.

[0085] Then calculate the read address of the first data in each circular buffer segment (each time para_cnt is read, all circular buffer segments need to be traversed from the first circular buffer segment):

[0086] drm_rd_addr=drm_rd_addr0+(N cb -f)*para_cnt,

[0087] Among them, drm_rd_addr is the read address of the first data.

[0088] In addition, usually the first data in RAM is segmented and the length of the last segment is less than N. cb , the calculated read address may exceed the range of the write address. In this case, the rate matching module determines that the read address exceeding the write address range is invalid, does not read the first data of the read address, and ignores the first data to avoid rate matching errors.

[0089] The de-rate matching operation configured in the de-rate matching module, in some embodiments, includes at least a padding process, and in some cases, also includes a merging process.

[0090] As mentioned above, the rate-decompression module segments the first data in the RAM. If the number of segments reaches two, the rate-decompression includes a merge process, which is: each time the first data at the same position in all the circular cache segments is read out and merged. Mathematically, the merge process configured by the rate-decompression module is an accumulation operation of the first data at the same position.

[0091] With respect to the puncturing information and discarding of data bits that occur during the rate matching process mentioned above, in some embodiments, the filling process configured by the rate de-matching module includes zero-value filling and invalid bit filling.

[0092] The zero padding configured in the derate matching module includes:

[0093] 1) Zero-filling to complete the puncturing information.

[0094] The zero-filling of this part belongs to the configuration determined in the rate matching module, which is to complete the position where the coded data is punctured. In a specific embodiment, the rate matching module fills the punctured information with zeros before the rate matching is started, and the zero-filling length is the punctured length.

[0095] In some embodiments, the derate matching module performs zero-value padding on the punctured information synchronously with the deinterleaving module, that is, the punctured information is padded with zeros synchronously when the deinterleaving module starts running (or at other time points before the derate matching starts), and the zero-padding length is the punctured length.

[0096] 2) Zero value padding is performed to make up for the insufficient amount of the first data read from the RAM.

[0097] If Ef <N cb , after reading all the first data in the RAM (ie, the number of first data currently read = E), the rate matching module fills the subsequent bits (ie, the other bits in the circular buffer except the invalid bits) with zeros.

[0098] 3) Zero padding to make up for the shortfall in the circular buffer length compared to the rate matching output length.

[0099] If N>N cb , then the rate matching module pads the output end with zeros when the rate matching output is output, and the length is NN cb , that is, zero-filling is performed where the circular buffer length is less than the rate matching output length.

[0100] In addition, during rate matching, the padding bits with a length of f are also removed. Therefore, the rate matching module needs to restore the position of this part of the padding bits.

[0101] In some embodiments, the invalid bit filling performed by the rate matching module when performing rate matching on the read first data includes the invalid bit filling performed to complete the padding bits removed during rate matching for each soft bit data. In specific operations, the rate matching module performs invalid bit filling after reading the last information bit of each first data.

[0102] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. A soft bit data processing method, characterized in that: The method comprises: receiving soft bit data, and determining a write address at which the soft bit data is written into a storage unit; Writing the soft bit data into a storage unit according to the write address to obtain first data; The first data is read out from the storage unit for rate dematching.

2. The soft bit data processing method according to claim 1, characterized in that: The soft bit data is stored in a row-column transformation matrix, and a write address for writing the soft bit data into the storage unit is determined according to the order in which the soft bit data is read out from the row-column transformation matrix.

3. The soft bit data processing method according to claim 2, characterized in that: The order in which the soft bit data are read out from the row-column transformation matrix is ​​determined according to the position in the row-column transformation matrix.

4. The soft bit data processing method according to any one of claims 1 to 3, characterized in that: The first data is read out from the storage unit according to a read address.

5. The soft bit data processing method according to claim 4, characterized in that: The first data in the storage unit is circularly buffered and segmented according to the circular buffer length, and a read address of the first data to be currently read out in each circular buffer segment is determined according to the position of the first data to be currently read out in the circular buffer segment.

6. The soft bit data processing method according to claim 5, characterized in that: The first counter is used to record the order of the currently read circular buffer segment, and the second counter is used to record the order of the currently read first data in the circular buffer segment.

7. The soft bit data processing method according to claim 6, characterized in that: According to the records of the second counter, the position of the first data to be read out in the circular buffer segment is calculated based on the starting bit of the circular buffer; then the read address of the first data to be read out is calculated in combination with the records of the first counter and the effective bit length in each circular buffer segment.

8. The soft bit data processing method according to claim 7, characterized in that: In the process of reading the first data from the storage unit, the first data of the read address beyond the write address range is ignored.

9. The soft bit data processing method according to claim 5, characterized in that: The solution rate matching comprises: When the number of the circular buffer segments is two or more, the first data at the same position in all the circular buffer segments are read out each time and merged.

10. The soft bit data processing method according to claim 5 or 9, characterized in that: The solution rate matching comprises: Zero padding to complete the puncturing information, and zero-filling to make up for the insufficient amount of the first data read from the storage unit, and Zero padding is performed to make up for the shortfall in the circular buffer length compared to the rate matching output length.

11. The soft bit data processing method according to claim 10, characterized in that: When writing the soft bit data into the storage unit, zero value filling is performed to complete the puncturing information.

12. The soft bit data processing method according to claim 10, characterized in that: The rate dematching further comprises: after reading all the first data in the storage unit, filling the other bits in the circular buffer with zero values ​​except the invalid bits.

13. The soft bit data processing method according to claim 10, characterized in that: The de-rate matching further comprises: when obtaining the de-rate matching output, zero-filling where the length of the circular buffer is less than the length of the de-rate matching output.

14. The soft bit data processing method according to claim 5, characterized in that: The solution rate matching comprises: Invalid bit filling is performed to fill in the filling bits removed during rate matching for each of the soft bit data.

15. The soft bit data processing method according to claim 14, characterized in that: Invalid bit filling is performed after reading the last information bit of each first data.

16. A computer-readable storage medium storing a computer program, characterized in that: Running the computer program can execute the soft bit data processing method as described in any one of claims 1-15.

17. A soft bit data processing device, comprising a processor and a storage medium, characterized in that: The storage medium stores a computer program, and the processor is configured to run the computer program in the storage medium to execute the soft bit data processing method according to any one of claims 1 to 15.

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