Decoding method and device, electronic equipment, storage medium and program product

Abstract

The embodiment of the invention provides a decoding method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: receiving a decoding request, wherein the decoding request comprises a symbol sequence and a check matrix; determining the number of check nodes corresponding to the check matrix according to the decoding request, and performing hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; determining a target parallelism degree according to the check matrix and the plurality of symbol groups; and sequentially carrying out iterative decoding processing on the plurality of symbol groups according to the target parallelism through the check matrix to obtain original data. According to the scheme, by determining the target parallelism degree, partial parallel decoding processing can be flexibly controlled, full parallel decoding processing on the whole symbol sequence is avoided, and the calculation complexity can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a decoding method, device, electronic device, storage medium and program product. Background Art

[0002] In the field of communication technology, channel coding and channel decoding are of great significance for improving the reliability of data transmission. At the data transmitting end, the original data to be sent is converted into a symbol sequence. The symbol sequence is converted into a signal form suitable for transmission on the channel by a modulator and transmitted through the channel. The symbol sequence can introduce redundant information through coding and modulation technology to enhance the signal's anti-interference ability. At the data receiving end, the received signal is converted back into a symbol sequence by a demodulator, and the symbol sequence is decoded to obtain the original data.

[0003] At the data receiving end, the symbol sequence is decoded step by step through message transmission between the variable node and the check node, and the estimated value of each symbol in the symbol sequence is continuously updated and optimized to obtain the original data.

[0004] However, when the number of symbols in the symbol sequence is large, this decoding process has the problem of high computational complexity. Summary of the invention

[0005] The embodiments of the present application provide a decoding method, an apparatus, an electronic device, a storage medium and a program product to reduce the computational complexity of decoding processing.

[0006] In a first aspect, an embodiment of the present application provides a decoding method, comprising: receiving a decoding request, the decoding request comprising a symbol sequence and a check matrix; determining, according to the decoding request, the number of check nodes corresponding to the check matrix, and performing layered processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; determining a target parallelism according to the check matrix and the plurality of symbol groups; and according to the target parallelism, performing iterative decoding processing on the plurality of symbol groups in sequence through the check matrix to obtain original data.

[0007] In one possible implementation, a target degree of parallelism is determined based on the check matrix and the multiple symbol groups, including: determining an amount of idle resources, the number of groups corresponding to the multiple symbol groups, and a row weight corresponding to the check matrix, the row weight being the number of variable nodes connected to each check node; determining the target degree of parallelism based on the amount of idle resources, the number of groups, and the row weight.

[0008] In a possible implementation, the multiple symbol groups are iteratively decoded in sequence according to the target parallelism through the check matrix to obtain original data, including: determining multiple computing tasks from the multiple symbol groups according to the target parallelism, each computing task including multiple sub-symbol groups; iteratively decoding the multiple sub-symbol groups corresponding to each computing task through the variable node to check node V2C message vector and the check node to variable node C2V message vector to obtain multiple target data corresponding to each computing task; and determining the original data according to the multiple target data corresponding to each computing task.

[0009] In a possible implementation, for any sub-symbol group under any computing task; the sub-symbol group is iteratively decoded through a variable node to check node V2C message vector and a check node to variable node C2V message vector to obtain multiple target data corresponding to the sub-symbol group, including: determining a channel noise characteristic value, a check node corresponding to the sub-symbol group, and a variable node corresponding to the sub-symbol group; calculating an initial log-likelihood ratio according to the channel noise characteristic value and the sub-symbol group, and determining the initial log-likelihood ratio as an initial V2C message vector of the variable node; determining the number of symbol values ​​of the sub-symbol group, and determining an initial C2V message vector of the check node according to a principle of equal posterior probability and the number of symbol values; iteratively processing according to the initial V2C message vector and the initial C2V message vector to obtain the multiple target data.

[0010] In a possible implementation, iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain the multiple target data, including: performing a preset operation until the number of times the preset operation is performed is greater than a preset number or a preset condition is satisfied, and determining the target data according to a judgment result; wherein the preset operation includes: determining a target element from the check matrix according to the variable node and the check node, performing finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, performing inverse permutation processing on the updated V2C message vector to obtain an inverse permutation vector, updating the check node by using the inverse permutation vector to obtain an updated C2V message vector, and performing judgment processing on the updated V2C message vector and the updated C2V message vector to obtain the judgment result, wherein the judgment result is a check pass or a check fail; wherein the preset condition is that the judgment result is a check pass.

[0011] In a possible implementation, the target data is determined according to the judgment result, including: determining, according to the judgment result, a plurality of candidate posterior probabilities when the variable node takes different symbol values; and determining the symbol value corresponding to the candidate posterior probability with the largest candidate posterior probability among the plurality of candidate posterior probabilities as the target data.

[0012] In a possible implementation, the decision processing includes: determining an index value corresponding to each symbol group; storing the updated V2C message vector and the updated C2V message vector obtained in each iteration into a cache, and updating a count value according to the index value corresponding to each symbol group; and performing the decision processing until the count value is equal to a preset value.

[0013] In a second aspect, an embodiment of the present application provides a decoding device, comprising: a receiving module, used to receive a decoding request, the decoding request comprising a symbol sequence and a check matrix; a message initialization module, used to determine, according to the decoding request, the number of check nodes corresponding to the check matrix, and perform layered processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups; a determination module, used to determine a target parallelism according to the check matrix and the multiple symbol groups; a partial parallel control module, used to perform iterative decoding processing on the multiple symbol groups in sequence through the check matrix according to the target parallelism to obtain original data.

[0014] In one possible implementation, the determination module is specifically used to determine the amount of idle resources, the number of groups corresponding to the multiple symbol groups, and the row weight corresponding to the check matrix, where the row weight is the number of variable nodes connected to each check node; the determination module is also specifically used to determine the target parallelism based on the amount of idle resources, the number of groups, and the row weight.

[0015] In a possible implementation, the device further includes: a processing module, used to determine multiple computing tasks from the multiple symbol groups according to the target parallelism, each computing task including multiple sub-symbol groups; the processing module is also used to perform iterative decoding processing on the multiple sub-symbol groups corresponding to each computing task through the variable node to check node V2C message vector and the check node to variable node C2V message vector to obtain multiple target data corresponding to each computing task; the processing module is also used to determine the original data according to the multiple target data corresponding to each computing task.

[0016] In a possible implementation, for any sub-symbol group under any computing task; the processing module is specifically used to determine a channel noise characteristic value, a check node corresponding to the sub-symbol group, and a variable node corresponding to the sub-symbol group; the processing module is also specifically used to calculate an initial log-likelihood ratio based on the channel noise characteristic value and the sub-symbol group, and determine the initial log-likelihood ratio as an initial V2C message vector of the variable node; the processing module is also specifically used to determine the number of symbol values ​​of the sub-symbol group, and determine the initial C2V message vector of the check node based on the principle of equal posterior probability and the number of symbol values; the processing module is also specifically used to perform iterative processing based on the initial V2C message vector and the initial C2V message vector to obtain the multiple target data.

[0017] In a possible implementation manner, the processing module is further configured to execute a preset operation until the number of times the preset operation is executed is greater than a preset number or a preset condition is satisfied, and then determine the target data according to a judgment result; wherein the preset operation includes: determining a target element from the check matrix according to the variable node and the check node, performing finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, performing inverse permutation processing on the updated V2C message vector to obtain an inverse permutation vector, updating the check node by using the inverse permutation vector to obtain an updated C2V message vector, performing judgment processing on the updated V2C message vector and the updated C2V message vector to obtain the judgment result, wherein the judgment result is a check pass or a check fail; wherein the preset condition is that the judgment result is a check pass.

[0018] In a possible implementation, the processing module is specifically used to determine, based on the judgment result, multiple candidate posterior probabilities when the variable node takes different symbol values; the processing module is also specifically used to determine the symbol value corresponding to the candidate posterior probability with the largest candidate posterior probability among the multiple candidate posterior probabilities as the target data.

[0019] In a possible implementation, the device includes: a cache module, used to determine the index value corresponding to each symbol group; the cache module is also used to store the updated V2C message vector and the updated C2V message vector obtained in each iteration into the cache, and update the count value according to the index value corresponding to each symbol group; the cache module is also used to perform a decision process until the count value is equal to a preset value.

[0020] In a third aspect, an embodiment of the present application provides a decoding device, including: a memory, a processor;

[0021] The memory stores computer-executable instructions;

[0022] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0023] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.

[0024] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementation methods of the first aspect.

[0025] The decoding method, device, electronic device, storage medium and program product provided by the embodiments of the present application include: receiving a decoding request, the decoding request includes a symbol sequence and a check matrix; according to the decoding request, determining the number of check nodes corresponding to the check matrix, and performing layered processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups; according to the check matrix and the multiple symbol groups, determining the target parallelism; through the check matrix, performing iterative decoding processing on the multiple symbol groups in turn according to the target parallelism to obtain the original data. The above scheme can flexibly control partial parallel decoding processing by determining the target parallelism, avoid full parallel decoding processing on the entire symbol sequence, and effectively reduce the computational complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0027] Figure 1 A schematic diagram of an application scenario of a decoding method provided in an embodiment of the present application;

[0028] Figure 2 A flowchart of a decoding method provided in an embodiment of the present application;

[0029] Figure 3 A flowchart of a decoding method provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of a Tanner graph of a check matrix provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of an adder provided in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a decoder provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of the structure of a decoding device provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of the structure of a decoding device provided in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0036] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] It should be noted that the decoding method, device, electronic device, storage medium and program product of the present application can be used in the field of communication technology, and can also be used in any field other than communication technology. The application field of the decoding method, device, electronic device, storage medium and program product of the present application is not limited.

[0039] Figure 1 A schematic diagram of an application scenario of a decoding method provided in an embodiment of the present application is given by way of example in combination with the illustrated scenario: a transmitting end 1 sends a symbol sequence to a receiving end 2, and the receiving end 2 decodes the symbol sequence to obtain original data.

[0040] Exemplarily, a symbol sequence refers to a series of symbols for transmission that are converted from the original data after encoding and modulation. Each symbol represents a certain number of information bits and is suitable for transmission on a channel. Specifically, the transmitter first groups and encodes the original data (such as LDPC encoding), and then maps the encoded bits into symbols through a modulator. These symbols can be in different types of signal forms, and each symbol carries a certain amount of bit information, so that multiple bits can be transmitted in each symbol period, thereby improving data transmission efficiency.

[0041] In practical applications, the receiving end decodes the conforming sequence through a decoder to obtain the original data. The decoding process involves a lot of calculations, and the operation of the decoder will occupy the computing resources of the receiving end.

[0042] In the related art, the decoder performs full parallel decoding processing on multiple symbols in the matching sequence. When the number of symbols in the symbol sequence is large, or the number of bits representing the symbol sequence is large, the computational complexity of the full parallel decoding processing is high. This results in a large amount of computing resources occupied by the decoder, affecting the operating efficiency of the receiving end.

[0043] The decoding method provided in this application is intended to solve the above technical problems.

[0044] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0045] Figure 2 A flowchart of a decoding method provided in an embodiment of the present application, the method comprising the following steps:

[0046] S201. Receive a decoding request, where the decoding request includes a symbol sequence and a check matrix.

[0047] Optionally, the conforming sequence may be encoded by a low-density parity-check code (LDPC for short).

[0048] Optionally, the LDPC check matrix is ​​sparse, including zero elements and non-zero elements. The sparse matrix greatly reduces the amount of calculation in the encoding and decoding process, thereby improving the efficiency of the algorithm. The sparse structure facilitates hardware implementation and reduces complexity.

[0049] Exemplarily, the executor of the present application is a receiving end, and the present application does not limit the specific device type of the receiving end.

[0050] S202: Determine the number of check nodes corresponding to the check matrix according to the decoding request, and perform layered processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups.

[0051] Optionally, the check matrix is ​​an m×n matrix, where m represents the number of check nodes (i.e., check equations) and n represents the number of variable nodes (i.e., symbols in the codeword). The number of rows m is read from the check matrix to obtain the number of check nodes. At the receiving end, the check matrix is ​​used to verify whether the symbol sequence contains errors. If errors are contained, the check matrix is ​​used to correct the errors.

[0052] Optionally, the symbol sequence is processed in layers based on the number of check nodes. Here, "layering" refers to dividing the symbol sequence into multiple symbol groups according to certain rules or strategies to facilitate parallel processing or reduce computational complexity.

[0053] For example, the symbol sequence is 400×6×8 bit data, the number of check nodes is 100, and the symbol sequence is layered according to the number of check nodes to obtain 100 layers×4×6×8 bit decoded data, where 400 represents the number of symbols in the symbol sequence, 6 represents a 64-bit finite field, and 8 represents the quantization bit width.

[0054] S203: Determine a target parallelism according to a check matrix and a plurality of symbol groups.

[0055] Optionally, the amount of computation required for decoding processing is determined based on the check matrix and multiple symbol groups, and a target parallelism matching the amount of computation is determined based on the amount of computation.

[0056] Combined with the scenario example, the higher the target parallelism, the higher the efficiency of the decoding process, and the higher the computational complexity of the decoding process. The appropriate target parallelism is determined based on the comprehensive efficiency and complexity to minimize the computational complexity while ensuring that the efficiency of the decoding process meets the requirements.

[0057] S204. According to the target parallelism, multiple symbol groups are iteratively decoded in sequence through a check matrix to obtain original data.

[0058] Exemplarily, partial parallel decoding processing is performed according to the target parallelism.

[0059] Combined with the scenario example, according to the target parallelism, the number of symbol groups to be decoded at the same time, and partial parallel decoding processing is performed according to the number of symbol groups to be processed at the same time. For example, if 100 symbol groups are obtained by layered processing, if the target parallelism is 10, the number of symbol groups to be decoded at the same time is 10, and during partial parallel decoding processing, the other symbol groups in the 100 symbol groups are not decoded. It can be understood that compared with full parallel decoding processing, the resource consumption of partial parallel decoding processing is reduced to 1 / 10 of the original.

[0060] Optionally, the iterative process may include variable node updates and check node updates. For each variable node, the messages it sends to all adjacent check nodes are calculated. These messages are based on all messages received by the variable node from other check nodes and the received initial values. Each variable node collects messages from all other adjacent check nodes and updates the message it sends to the current check node based on these messages. The updated message reflects the variable node's suggestion to the check node after considering the opinions of all other check nodes.

[0061] Specifically, for each check node, the message sent to all adjacent variable nodes is calculated. Each check node collects messages from all adjacent variable nodes and updates the message sent to the current variable node based on these messages. The updated message reflects the check node's suggestion to the variable node after considering the opinions of all other variable nodes. These messages are based on all messages received by the check node from other variable nodes. By exchanging information between variable nodes and check nodes, errors in symbol sequence transmission are gradually corrected, thereby improving the accuracy of decoding.

[0062] The decoding method provided in the embodiment of the present application receives a decoding request, the decoding request includes a symbol sequence and a check matrix; according to the decoding request, the number of check nodes corresponding to the check matrix is ​​determined, and the symbol sequence is layered according to the number of check nodes to obtain multiple symbol groups; according to the check matrix and the multiple symbol groups, the target parallelism is determined; through the check matrix, the multiple symbol groups are sequentially iteratively decoded according to the target parallelism to obtain the original data. The above scheme can flexibly control the partial parallel decoding processing by determining the target parallelism, avoid the full parallel decoding processing of the entire symbol sequence, and can effectively reduce the computational complexity.

[0063] Based on any of the above embodiments, Figure 3 , the detailed process of decoding is explained.

[0064] Figure 3 A flowchart of a decoding method provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the method includes:

[0065] S301. Receive a decoding request, where the decoding request includes a symbol sequence and a check matrix.

[0066] It should be noted that the execution process of S301 refers to S201 and will not be repeated here.

[0067] S302: Determine the number of check nodes corresponding to the check matrix according to the decoding request, and perform layered processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups.

[0068] It should be noted that the execution process of S302 refers to S202 and will not be repeated here.

[0069] S303: Determine the amount of idle resources, the number of groups corresponding to the multiple symbol groups, and the row weight corresponding to the check matrix, where the row weight is the number of variable nodes connected to each check node.

[0070] Optionally, the check matrix can be converted into a Tanner graph.

[0071] Next, combine Figure 4 The Tanner graph of the check matrix is ​​described.

[0072] Figure 4 A schematic diagram of the Tanner graph of the check matrix provided in the embodiment of the present application. Figure 4 As shown, the variable nodes correspond to the columns in the check matrix, the check nodes correspond to the rows in the check matrix, and the edges connecting the check nodes and the variable nodes identify the positions of the non-zero elements in the check matrix. The number of variable nodes connected to each check node corresponds to the row weight of the check matrix, and the number of check nodes connected to each variable node corresponds to the column weight of the check matrix. If a position in the check matrix is ​​1, there is an edge between the corresponding check node and the variable node. Figure 4 , it can be seen that the row weight of the check matrix is ​​4 and the column weight is 2.

[0073] Optionally, the idle resource amount refers to the unused computing resources in the current receiving end that can be used to perform decoding. This includes but is not limited to the number of processor cores, memory capacity, etc. For example, in a multi-core processor environment, if there are a total of 8 cores, and 4 of them are already occupied by other tasks, the idle resource amount is 4 cores. These idle cores can be used to perform decoding processing in parallel.

[0074] Exemplarily, the number of groups corresponding to the plurality of symbol groups reflects the total computational complexity of the decoding process.

[0075] Exemplarily, the row weight reflects the amount of computation for each symbol group, and a higher row weight means that more variable nodes participate in a certain check node, thus requiring more computational resources.

[0076] S304: Determine the target parallelism according to the amount of free resources, the number of groups, and the row weight.

[0077] Combined with the scenario example, the available computing resources are determined based on the amount of idle resources, and the required computing resources are determined based on the number of groups and row weight. The target parallelism is determined based on the available computing resources and the required computing resources to improve the efficiency of decoding processing while avoiding excessive use of computing resources that may cause performance degradation at the receiving end.

[0078] S305 . Determine a plurality of computing tasks from a plurality of symbol groups according to a target parallelism, wherein each computing task includes a plurality of sub-symbol groups.

[0079] In combination with a scenario example, for example, the number of multiple symbol groups is 100 and the target parallelism is 10, then 10 computing tasks are determined, and each computing task includes 10 sub-symbol groups.

[0080] S306, performing iterative decoding processing on multiple sub-symbol groups corresponding to each computing task respectively through the variable node to check node V2C message vector and the check node to variable node C2V message vector to obtain multiple target data corresponding to each computing task.

[0081] Exemplarily, a V2C message vector refers to a message vector sent from a variable node to a check node. Each variable node represents a bit or symbol and updates its state based on external information received (e.g., messages from other check nodes or initial message vectors). V2C messages usually contain probability estimation information about the bit corresponding to the variable node, such as the log-likelihood ratio (LLR). The LLR value indicates whether the received bit is more likely to be 0 or 1. The V2C message vector helps the check node determine whether the current bit meets the requirements of the check equation. By collecting message vectors from all associated variable nodes, the check node can calculate a new information vector and feed it back to the variable node.

[0082] Exemplarily, a C2V message vector is a message vector sent from a check node to a variable node. The check node is responsible for checking whether a set of variable nodes meet specific check constraints. The C2V message vector contains the message vector derived by the check node based on all V2C message vectors received from other connected variable nodes. This is usually the result of some nonlinear combination, which is used to indicate how a variable node adjusts its probability estimate to better meet the check equation. The C2V message vector is used to update the state of the variable node, that is, to adjust the variable node's confidence estimate of the bit it represents. This process helps to correct errors and gradually approach the correct decoding result.

[0083] A feasible implementation method is for any sub-symbol group under any computing task; iterative decoding processing can be performed by the following method: determining a channel noise characteristic value, a check node corresponding to the sub-symbol group, and a variable node corresponding to the sub-symbol group; calculating an initial log-likelihood ratio according to the channel noise characteristic value and the sub-symbol group, and determining the initial log-likelihood ratio as an initial V2C message vector of the variable node; determining the number of symbol values ​​of the sub-symbol group, and determining an initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values; iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain multiple target data.

[0084] Exemplarily, the formula for calculating the initial V2C message vector may be:

[0085]

[0086] in, represents the message vector from variable node n to check node m, α is the possible symbol value, It represents the log-likelihood ratio of variable node n to the value α, reflecting the confidence of variable node n to the value α in the current iteration.

[0087] Exemplarily, the formula for calculating the initial C2V message vector may be:

[0088]

[0089] in, represents the message vector sent from check node m to variable node n, is the conditional probability, which means the probability that the check node m satisfies the check equation under the condition that the value of the variable node n is α. q represents the number of symbol values.

[0090] Optionally, the C2V message vector is initialized, that is, before the check node receives the V2C vector of the variable node for updating, the posterior probabilities of the values ​​of each symbol are set to be equal.

[0091] Optionally, the message vector output by the variable node is permuted according to the non-zero elements at the corresponding positions in the check matrix. The message vector output by the variable node and the finite field element corresponding to the edge need to be finite field multiplied. This step is called message permutation. The product with the variable node symbol participates in the finite field addition in the check equation.

[0092] Optionally, the addition operation is performed by an adder.

[0093] Next, combine Figure 5 The adder will be described.

[0094] Figure 5 Schematic diagram of an adder provided in an embodiment of the present application. Figure 5 As shown in the figure, taking 6 bits as an example, when the result of the addition operation exceeds the 6-bit range, the result will be automatically truncated to ensure that the output value does not exceed the maximum value that can be represented by 6 bits (i.e. 63). This design prevents erroneous results caused by numerical overflow and maintains the closed nature of the finite field.

[0095] Based on the above implementation, since the initial probability of each symbol value is set to be the same, this setting ensures that all possible symbol values ​​are treated equally in the absence of additional information, thereby improving the accuracy of decoding.

[0096] A feasible implementation method can perform iterative processing through the following method: execute preset operations until the number of times the preset operations are executed is greater than the preset number or the preset conditions are met, and an updated V2C message vector is obtained; the updated V2C message vector is subjected to inverse permutation processing to obtain an inverse permutation vector; the check nodes are updated through the inverse permutation vector to obtain an updated C2V message vector; the updated V2C message vector and the updated C2V message vector are subjected to decision processing to obtain multiple target data; wherein the preset operations include: determining a target element from a check matrix according to variable nodes and check nodes, performing finite field multiplication calculation on an initial V2C message vector and a target element to obtain an updated V2C message vector, and the updated V2C message vector is input into a first check equation to obtain a first check result, wherein the first check result is a check pass or a check fail; wherein the preset condition is that the first check result is a check pass.

[0097] Combined with the scenario example, the finite field multiplication operation helps to adjust the message vector value to reflect the current state of the verification equation.

[0098] First verification equation: Input the updated V2C message into the first verification equation to check whether it satisfies the equation. If it does, it is called "verification passed"; otherwise, it is "verification failed".

[0099] Exemplarily, the check node is updated by the following formula:

[0100]

[0101] in, It represents the probability that the check equation is satisfied when the message vector of the variable node n is α. Express satisfaction for all The variable sequence V is summed. V represents the set of all symbol sequences that satisfy the mth check relation. It represents the probability that the check equation is satisfied given the variable sequence V. is the output of the calibration equation, is an element in the check matrix, is the value of the variable node. Indicates that in a given The probability of the variable sequence V under the condition of . For all neighbor nodes except n Multiply the probabilities of . Represents other variable nodes The updated V2C message vector.

[0102] Exemplarily, after obtaining the updated V2C message vector, an inverse permutation process is performed on it. The inverse permutation process refers to the process of restoring the original arrangement order, and this step is to correspond the message vector output by the check node with the original symbol value.

[0103] Exemplarily, the formula for the inverse permutation process may be:

[0104]

[0105] in, Represents the value of the C2V message vector after inverse permutation. Represents the value of the original C2V message vector output by the check node.

[0106] Exemplarily, the formula for updating the check node by using the inverse permutation vector may be:

[0107]

[0108] in, represents the posterior probability that the variable node n takes the value α, Represents the message vector of all check nodes associated with variable node n except the current check node m. The signal received by the receiving end. represents the prior probability based on the received signal. Indicates receiving signal The joint probability distribution of all nodes except the message vector of the current check node. Indicates that the variable node n takes the value α and receives the signal The joint probability distribution of all check nodes except the current check node m under the condition of . Represents the normalization factor, which determines whether the message vector of each variable node satisfies the normalization condition. represents the prior probability based on the received signal. represents the message vector from other check node k to variable node n.

[0109] Exemplarily, the posterior probability of the variable node is calculated based on the value of the variable node and the information of the check matrix, and the variable node can update its estimate of the check node value, thereby gradually correcting the error until all the check equations are satisfied.

[0110] Optionally, the posterior probability is a modified posterior probability after correlation is introduced into the check matrix, wherein the current check equation is eliminated to prevent the decoding from failing to converge due to recycling of information.

[0111] Exemplarily, the formula for decision processing may be:

[0112]

[0113] in, Indicates receiving signal In the case of check node message vectors associated with all variable nodes n, the posterior probability of variable node n taking the value α. Represents a normalization constant that ensures that the sum of the probabilities of all possible values ​​is 1.

[0114] In this feasible implementation, errors can be corrected step by step through iteration, thereby improving the accuracy of decoding.

[0115] A feasible implementation method can perform decision processing by the following method: determine the index value corresponding to each symbol group; store the updated V2C message vector and the updated C2V message vector obtained in each iteration into a cache, and update the count value according to the index value corresponding to each symbol group; until the count value is equal to the preset value, the decision processing is performed.

[0116] Optionally, a partial parallel control module is used to control the message vector to be stored in a cache and to control the counting process of the index value.

[0117] Optionally, each computing task corresponds to multiple sub-symbol groups, each sub-symbol group corresponds to a target data, and each target data corresponds to a unique index value.

[0118] Combined with the scenario example, take the number of symbol groups as 100 as an example, the index values ​​corresponding to the multiple symbol groups are determined from 0 to 99. The time when each symbol group iterates to obtain the target data is not fixed. By updating the count value, the number of target data currently generated can be determined. When the count value is equal to 100, it means that each symbol group has completed the iteration. At this time, the cache includes the iterative data corresponding to each symbol group, and the iterative data in the cache will be judged.

[0119] In this feasible implementation, the counter can accurately determine whether each symbol group has generated target data, thereby avoiding omissions and improving decoding accuracy.

[0120] A feasible implementation method determines the target data according to the judgment result, including: determining multiple candidate posterior probabilities when the variable node takes different optional data according to the judgment result; and determining the optional data corresponding to the candidate posterior probability with the largest candidate posterior probability as the target data.

[0121] Optionally, the constraints of the current verification equation are used to update the posterior probability, and the constraints of the current verification equation will be used in the final decision. According to the calculated posterior probabilities of the message vectors of each variable node, the decision is made, and the decision rules are as follows:

[0122]

[0123] in, It means that for each variable node n, the symbol value α that maximizes the posterior probability is selected as the estimated value of the node.

[0124] Exemplarily, multiple candidate posterior probabilities of variable nodes under different symbol values ​​are calculated according to the judgment result (i.e. ), select the symbol value corresponding to the maximum posterior probability and determine it as the target data corresponding to the variable node.

[0125] Exemplarily, after judging each element of the finite field GF(64) used by the current LDPC code, a judgment decoding sequence is obtained. If the checksum is an all-zero vector, it means that the decoding is successful, the iteration ends and the decoding sequence is returned; otherwise, the next round of variable node and check node information transmission is performed until the decoder reaches the maximum number of iterations or the decoding is successful. If the algorithm still has not converged when it iterates to the preset maximum number of iterations, the decoding fails, the algorithm stops iterating and outputs the current decoding sequence.

[0126] In this feasible implementation, it is ensured that, given the received signal and all relevant check node message vectors, the estimated value of each variable node is the most likely correct value, thereby improving the error correction capability and accuracy of the entire system.

[0127] S307: Determine original data according to multiple target data corresponding to each computing task.

[0128] Next, combine Figure 6 The decoder will be described.

[0129] Figure 6 Schematic diagram of a decoder provided in an embodiment of the present application. Figure 6As shown, the input data is initialized to initial messages, which are usually log-likelihood ratios extracted from the received signal. The initialized log-likelihood ratios are stored, and these values ​​will be updated and used in subsequent iterations. The partial parallel control module processes the initialized messages in layers to obtain the index value index of each layer, and permutes the initialized messages to meet the needs of checking node updates. The permutation operation ensures that information is correctly transmitted between different nodes. According to the permuted messages, the checking nodes perform update calculations. This step involves updating the messages of the checking nodes according to the constraints in the check matrix. The updated messages of the checking nodes are inversely permuted back to the original format so that the variable nodes can correctly process these messages. The variable nodes perform update calculations according to the inversely permuted messages. This step involves combining messages from multiple checking nodes to update the states of the variable nodes. The partial parallel control module controls the partial parallel operation of the entire decoding process to ensure that the decoder can run efficiently with limited hardware resources. The cache module stores the updated results of the variable nodes in the cache RES RAM, which will be used for subsequent decision decoding. Decision decoding is performed based on the results in the cache RES RAM to determine the final bit estimate. If the decoding is successful or the maximum number of iterations is reached, the result is output; otherwise, the iteration continues. If the decoding is successful or the maximum number of iterations is reached, the final decoding result is output. The maximum number of iterations is determined by the index value index.

[0130] Figure 7 A schematic diagram of the structure of a decoding device provided in an embodiment of the present application. Figure 7 As shown, the decoding device 70 may include: a receiving module 71, a message initialization module 72, a determination module 73, and a partial parallel control module 74, wherein:

[0131] The receiving module 71 is used to receive a decoding request, where the decoding request includes a symbol sequence and a check matrix.

[0132] The message initialization module 72 is used to determine the number of check nodes corresponding to the check matrix according to the decoding request, and perform layered processing on the symbol sequence according to the number of check nodes to obtain multiple symbol groups.

[0133] The determination module 73 is used to determine the target parallelism according to the check matrix and the multiple symbol groups.

[0134] The partial parallel control module 74 is used to perform iterative decoding processing on multiple symbol groups in sequence through the check matrix according to the target parallelism to obtain original data.

[0135] Optionally, the receiving module 71 may execute Figure 2 S201 in the embodiment.

[0136] Optionally, the message initialization module 72 may execute Figure 2 S202 in the embodiment.

[0137] Optionally, the determination module 73 may execute Figure 2 S203 in the embodiment.

[0138] Optionally, the partial parallel control module 74 may execute Figure 2 S204 in the embodiment.

[0139] It should be noted that the decoding device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0140] In a possible implementation manner, the determination module 73 is specifically configured to:

[0141] Determine the amount of idle resources, the number of groups corresponding to the plurality of symbol groups, and the row weight corresponding to the check matrix, where the row weight is the number of variable nodes connected to each check node;

[0142] Determine the target parallelism based on the amount of free resources, the number of groups, and the row weight.

[0143] Figure 8 A schematic diagram of the structure of a decoding device provided in an embodiment of the present application. Figure 7 Based on the embodiment shown, Figure 8 As shown, the decoding device 80 further includes: a processing module 75 and a cache module 76, wherein:

[0144] The processing module 75 is used to:

[0145] According to the target parallelism, a plurality of computing tasks are determined from the plurality of symbol groups, each computing task including a plurality of sub-symbol groups;

[0146] Iteratively decode multiple sub-symbol groups corresponding to each computing task through the variable node to check node V2C message vector and the check node to variable node C2V message vector to obtain multiple target data corresponding to each computing task;

[0147] The original data is determined according to a plurality of target data corresponding to each computing task.

[0148] In a possible implementation, for any sub-symbol group under any computing task, the processing module 75 is specifically configured to:

[0149] Determining a channel noise characteristic value, a check node corresponding to a sub-symbol group, and a variable node corresponding to the sub-symbol group;

[0150] An initial log-likelihood ratio is calculated based on the channel noise characteristic value and the sub-symbol group, and the initial log-likelihood ratio is determined as an initial V2C message vector of the variable node;

[0151] Determine the number of symbol values ​​of the sub-symbol group, and determine the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values;

[0152] Iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain multiple target data.

[0153] In a possible implementation manner, the processing module 75 is specifically configured to:

[0154] Execute the preset operation until the number of times the preset operation is executed exceeds the preset number or the preset condition is met, and determine the target data according to the judgment result;

[0155] The preset operation includes: determining a target element from a check matrix according to a variable node and a check node, performing finite field multiplication calculation on an initial V2C message vector and a target element to obtain an updated V2C message vector, performing inverse permutation processing on the updated V2C message vector to obtain an inverse permutation vector, performing update processing on the check node through the inverse permutation vector to obtain an updated C2V message vector, performing judgment processing on the updated V2C message vector and the updated C2V message vector to obtain a judgment result, wherein the judgment result is a check pass or a check fail;

[0156] Among them, the preset condition is that the judgment result is verification passed.

[0157] In a possible implementation manner, the processing module 75 is specifically configured to:

[0158] According to the judgment result, multiple candidate posterior probabilities when the variable node takes different symbol values ​​are determined;

[0159] The symbol value corresponding to the candidate posterior probability with the largest candidate posterior probabilities is determined as the target data.

[0160] The cache module 76 is used to:

[0161] Determine the index value corresponding to each symbol group;

[0162] The updated V2C message vector and the updated C2V message vector obtained in each iteration are stored in a cache, and the count value is updated according to the index value corresponding to each symbol group;

[0163] When the count value is equal to the preset value, the decision process is performed.

[0164] Fig. 9A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the electronic device includes:

[0165] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, the memory 292, and the communication interface 293 may communicate with each other through the bus 294. The communication interface 293 may be used for information transmission. The processor 291 may call the logic instructions in the memory 292 to execute the method of the above embodiment.

[0166] In addition, the logic instructions in the above-mentioned memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0167] The memory 292 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, that is, implementing the methods in the above method embodiments.

[0168] The memory 292 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 292 may include a high-speed random access memory and may also include a non-volatile memory.

[0169] An embodiment of the present application provides a non-temporary computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method as described in the above embodiment.

[0170] An embodiment of the present application provides a computer program product, including a computer program, which implements the method of the above embodiment when the computer program is executed by a processor.

[0171] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0172] It should be further noted that, although the various steps in the flowchart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0173] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present application can also be implemented in other ways. For example, the division of units / modules in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0174] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present application may be integrated into one unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0175] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. The processor may be any appropriate hardware processor, such as CPU, GPU, FPGA, DSP, and ASIC, etc. The storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0176] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0177] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0179] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A decoding method, characterized in that: include: receiving a decoding request, wherein the decoding request includes a symbol sequence and a check matrix; Determine, according to the decoding request, the number of check nodes corresponding to the check matrix, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; Determining a target parallelism according to the check matrix and the plurality of symbol groups; According to the target parallelism, the multiple symbol groups are iteratively decoded in sequence through the check matrix to obtain original data.

2. The method according to claim 1, characterized in that Determining a target parallelism according to the check matrix and the plurality of symbol groups includes: Determine the amount of idle resources, the number of groups corresponding to the multiple symbol groups, and the row weight corresponding to the check matrix, where the row weight is the number of variable nodes connected to each check node; The target parallelism is determined according to the amount of idle resources, the number of groups, and the row weight.

3. The method according to claim 1 or 2, characterized in that: By using the check matrix, the multiple symbol groups are iteratively decoded in sequence according to the target parallelism to obtain original data, including: Determining a plurality of computing tasks from the plurality of symbol groups according to the target parallelism, each computing task comprising a plurality of sub-symbol groups; Iteratively decode multiple sub-symbol groups corresponding to each computing task through the variable node to check node V2C message vector and the check node to variable node C2V message vector to obtain multiple target data corresponding to each computing task; The original data is determined according to a plurality of target data corresponding to each computing task.

4. The method according to claim 3, characterized in that For any sub-symbol group under any computing task; the sub-symbol group is iteratively decoded through a variable node to check node V2C message vector and a check node to variable node C2V message vector to obtain a plurality of target data corresponding to the sub-symbol group, including: Determining a channel noise characteristic value, a check node corresponding to the sub-symbol group, and a variable node corresponding to the sub-symbol group; Calculating an initial log-likelihood ratio according to the channel noise characteristic value and the sub-symbol group, and determining the initial log-likelihood ratio as an initial V2C message vector of the variable node; Determine the number of symbol values ​​of the sub-symbol group, and determine the initial C2V message vector of the check node according to the principle of equal posterior probability and the number of symbol values; Iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain the multiple target data.

5. The method according to claim 4, characterized in that Iterative processing is performed according to the initial V2C message vector and the initial C2V message vector to obtain the plurality of target data, including: Execute a preset operation until the number of times the preset operation is executed is greater than a preset number or a preset condition is met, and determine the target data according to the judgment result; The preset operation includes: determining a target element from the check matrix according to the variable node and the check node, performing finite field multiplication calculation on the initial V2C message vector and the target element to obtain an updated V2C message vector, performing inverse permutation processing on the updated V2C message vector to obtain an inverse permutation vector, performing update processing on the check node by using the inverse permutation vector to obtain an updated C2V message vector, performing decision processing on the updated V2C message vector and the updated C2V message vector to obtain the decision result, wherein the decision result is a check pass or a check fail; Among them, the preset condition is that the judgment result is verification passed.

6. The method according to claim 5, characterized in that Determine the target data based on the judgment result, including: According to the judgment result, determining a plurality of candidate posterior probabilities when the variable node takes different symbol values; The symbol value corresponding to the largest candidate posterior probability among the multiple candidate posterior probabilities is determined as the target data.

7. The method according to claim 5, characterized in that Conduct judgment processing, including: Determine the index value corresponding to each symbol group; The updated V2C message vector and the updated C2V message vector obtained in each iteration are stored in a cache, and the count value is updated according to the index value corresponding to each symbol group; When the count value is equal to the preset value, the decision process is performed.

8. A decoding device, characterized in that: include: A receiving module, configured to receive a decoding request, wherein the decoding request includes a symbol sequence and a check matrix; A message initialization module, configured to determine the number of check nodes corresponding to the check matrix according to the decoding request, and perform hierarchical processing on the symbol sequence according to the number of check nodes to obtain a plurality of symbol groups; A determination module, configured to determine a target parallelism according to the check matrix and the plurality of symbol groups; The partial parallel control module is used to perform iterative decoding processing on the multiple symbol groups in sequence through the check matrix according to the target parallelism to obtain original data.

9. The device according to claim 8, characterized in that The device also includes: A cache module, used for determining the index value corresponding to each symbol group; The cache module is further used to store the updated V2C message vector and the updated C2V message vector obtained in each iteration into the cache, and update the count value according to the index value corresponding to each symbol group; The cache module is also used to perform decision processing until the count value is equal to a preset value.

10. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

12. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 7 when being executed by a processor.

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