sending end, receiving end and communication device

Abstract

This application discloses a transmitter, a receiver, and a communication device. The transmitter includes an information sending module, which further includes a checksum generation unit and a sending unit. The checksum generation unit determines whether to generate a checksum for the received user data based on a checksum enable control word. If not, the user data is sent to the sending unit; if so, a checksum is generated based on a checksum mode control word, and the user data and checksum are sent to the sending unit. When checksum generation is enabled at the transmitter, the sending unit outputs the data of the data frame based on the bit width values ​​of the start bit, checksum, and data bits. When checksum generation is not enabled at the transmitter, the sending unit outputs the data of the data frame based on the bit width values ​​of the start bit and data bits. The transmitter of this application enables variable checksum mode and selectable bit width of the transmitted data frame, flexibly controlling the content transmitted by the information sending module.

Description

Technical Field

[0001] This invention relates to the field of communications, and more particularly to a transmitting end, a receiving end, and a communication device. Background Technology

[0002] Existing universal asynchronous receivers (UAR) typically have a fixed data frame format with 1 start bit, 5-8 data bits, 1 parity bit (supporting only odd or even parity), and 0.5 / 1 / 1.5 / 2 stop bits. This makes communication data inflexible and unable to meet current communication needs. Furthermore, existing UARs generally have a baud rate below 230400 bps; exceeding this rate can easily lead to communication errors, resulting in low speed and low reliability. Summary of the Invention

[0003] The purpose of this invention is to provide a transmitter, a receiver, and a communication device, which aims to solve the technical problem of inflexible communication data in existing general asynchronous receivers and transmitters.

[0004] To achieve the above objectives, the present invention provides a transmitting end for transmitting data frames, including an information transmitting module, wherein the information transmitting module includes a check code generation unit and a transmitting unit;

[0005] The verification code generation unit is used to determine whether to enable verification code generation based on the verification enable control word. If yes, it generates a verification code based on the verification method control word and the received user data, and sends the user data and the verification code to the sending unit. If no, it sends the user data to the sending unit.

[0006] The sending unit is used to generate and send a data frame based on the received user data and the check code or the user data. Depending on whether the check code exists, the data frame includes a start bit, a check bit, data bits and a stop bit in sequence, or includes a start bit, data bits and a stop bit in sequence.

[0007] When sending the data frame, the sending unit counts the number of bits in the currently sent data frame in real time to obtain an output count value;

[0008] When checksum generation is enabled, if the output count value reaches the bit width of the start bit, the sending unit outputs the data of the check bit starting from the next bit; when the output count value reaches the sum of the bit width of the start bit and the bit width of the check bit, the sending unit outputs the data of the data bit starting from the next bit; when the output count value reaches the sum of the bit width of the start bit, the bit width of the check bit, and the bit width of the data bit, the sending unit outputs the value of the stop bit starting from the next bit.

[0009] When checksum generation is not enabled, if the output count value reaches the bit width of the start bit, the sending unit outputs the data of the data bit starting from the next bit; when the output count value reaches the sum of the bit width of the start bit and the bit width of the data bit, the sending unit outputs the value of the stop bit starting from the next bit.

[0010] Compared with existing technologies, the sending end of this application can determine whether to enable checksum based on the checksum enable control word, select the corresponding checksum method based on the checksum method control word to generate checksum for the received data, and determine whether to send checksum after the information sending module sends start bit information based on the checksum enable control word. The sending end of this application can control whether checksum generation is enabled for the data frame, the checksum method of the data frame, and the sending length of the data frame based on the start bit width value, the checksum enable control word, the checksum method control word, and the data bit width value, thus achieving variable checksum method and selectable data frame width, flexibly controlling the content sent by the information sending module.

[0011] Optionally, when the transmitting end receives an output data valid signal, it sends the received user data to the output scheduling unit;

[0012] The output scheduling unit is used to query whether the information sending module is busy when it receives the user data. If it is busy, the user data is stored in the cache; otherwise, the user data is sent to the verification code generator.

[0013] Optionally, the transmitting unit includes a first baud rate generator and a first counter. The first baud rate generator is used to set a maximum transmit clock count value according to a baud rate control word. The maximum transmit clock count value is equal to the quotient of the clock frequency of the clock signal and the baud rate of the first baud rate generator. The first counter is used to count the clock pulses received by the first baud rate generator to obtain a transmit clock count value. When the transmit clock count value counts from zero to the maximum transmit clock count value minus one, the output count of one bit of the data frame is completed.

[0014] Optionally, the check code generation unit is configured with a plurality of check mode control words, and the check code generation unit generates check codes of different forms based on the plurality of check mode control words, wherein at least some forms of check codes correspond to check bits of different lengths.

[0015] To achieve the above objectives, this application also provides a receiving end for receiving data frames sent by the aforementioned sending end, including an information receiving module, wherein the information receiving module includes a check code verification unit and a receiving unit;

[0016] When the receiving port of the information receiving module receives the start receiving signal, the receiving unit begins to receive the data frame, and the receiving unit counts the number of bits of the currently received data frame in real time to obtain a receiving count value.

[0017] When checksum generation is enabled, if the received count value reaches the bit width of the start bit, the receiving unit starts receiving the data of the checksum bit of the data frame from the next bit; when the received count value reaches the bit width of the checksum bit, the receiving unit starts receiving the data of the data bits of the data frame from the next bit; when the received count value reaches the sum of the bit width of the start bit, the bit width of the checksum bit, and the bit width of the data bits of the data frame, the received checksum and the user data are sent to the checksum verification unit; the checksum verification unit generates a checksum based on the user data and the checksum mode control word, and compares the checksum with the checksum; if the checksum matches the checksum, the received user data is valid data.

[0018] When checksum generation is not enabled, if the receive count value reaches the bit width value of the start bit, the receiving unit starts receiving the data of the data bit from the next bit; when the receive count value reaches the sum of the bit width value of the start bit and the bit width value of the data bit, the reception of the data frame is completed.

[0019] Optionally, the receiving unit includes a second baud rate generator and a second counter. The second baud rate generator is used to set a maximum value of the receiving clock count according to the baud rate control word. The maximum value of the receiving clock count is equal to the quotient of the clock frequency of the clock signal and the baud rate of the second baud rate generator. The second counter is used to count the clock pulses received by the second baud rate generator to obtain a receiving clock count value. When the receiving clock count value counts from zero to the maximum value of the receiving clock count minus one, the receiving count of one bit of the data frame is completed.

[0020] Optionally, the start receiving signal is a falling edge signal;

[0021] When checksum generation is enabled, if the received clock count value reaches the difference between half of the maximum received clock count value and 1, and the received count value just exceeds the bit width value of the start bit of the data frame, then the receiving unit collects the value of the input port at this time as the next bit of data.

[0022] To achieve the above objectives, this application also provides a communication device, including the aforementioned transmitting end and the aforementioned receiving end.

[0023] To achieve the above objectives, this application also provides a communication device, including a retransmission control unit, the aforementioned transmitting end, and the aforementioned receiving end.

[0024] The sending end is used to send the data frame to another communication device, and the receiving end is used to receive the response frame corresponding to the data frame sent by the sending end of the other communication device.

[0025] When checksum generation is enabled, if the checksum of the response frame is inconsistent with the checksum generated by the receiving end, and the retransmission function is enabled, the retransmission control unit sends a retransmission data request to the output scheduling unit, so that the output scheduling unit retransmits the data frame to the information sending module.

[0026] When the checksum of the acknowledgment frame received by the receiving end of this application does not match the checksum generated by the receiving end, the communication device can choose to resend the data frame to another communication device, requesting the other communication device to resend the acknowledgment frame, thus making the communication between the two communication devices more reliable. Furthermore, the function of resending data frames can be optionally enabled or disabled, making the communication between the two communication devices more flexible.

[0027] Optionally, the retransmission control unit counts the number of times the data frame that needs to be retransmitted is sent to obtain a retransmission count, and the retransmission control unit does not send the retransmission data request to the output scheduling unit for the data frame whose retransmission count has reached a preset value of the retransmission count;

[0028] Optionally, if the response timeout retransmission function is enabled, the retransmission control unit also receives the output data valid signal, and when the output data valid signal is received, it counts the time when the receiving end receives the response frame to obtain a response time value; when the response time value is greater than the response time preset value, the retransmission control unit sends the retransmission data request to the output scheduling unit. Attached Figure Description

[0029] Figure 1 This is a schematic block diagram of the communication device according to an embodiment of this application.

[0030] Figure 2 This is a communication flowchart of the communication device in an embodiment of this application.

[0031] Figure 3 This is a schematic diagram of the transmitter and receiver according to an embodiment of this application. Detailed Implementation

[0032] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0033] The transmitter 1, receiver 2, and communication equipment involved in this application can be implemented using programmable devices such as FPGAs (Field Programmable Gate Arrays). For ease of understanding, the following description will focus on FPGAs. Of course, this application is not limited to FPGAs; it can also be implemented using actual circuit structures (such as PCBs or flexible circuit boards) or computers.

[0034] In some embodiments, users can control the transmitter 1, receiver 2, and communication device by setting relevant parameters (control words) of the FPGA's communication core (IP core).

[0035] Specifically, core communication parameters may include:

[0036] Baud rate P1: Used to set the baud rate of the baud rate generator.

[0037] The start bit width value P2: is used to set the start bit width.

[0038] Data bit width value P3: Used to set the bit width of the data bits.

[0039] Stop bit width value P4: Used to set the stop bit width.

[0040] Enable P5 verification: This setting determines whether to enable verification codes.

[0041] Verification method P6: Used to set the verification method for data bits, such as CRC8 / 16 / 32 check, ECC check, odd check and even check, etc. The length of the check code generated by each verification method is not necessarily the same.

[0042] Resend Enable P7: Whether the resend control unit 3 is allowed to start.

[0043] Retransmission count P8: The maximum number of times the retransmission control unit 3 can retransmit a data frame.

[0044] Response timeout control word P9: If the receiver 2 does not receive the response frame from the target device after the sender 1 sends a data frame to the target device within time P9, the retransmission control unit 3 sends a retransmission data request to the output scheduling unit for the data frame.

[0045] It should be understood that not every transmitter 1, receiver 2, or communication device has the above-mentioned parameters. Some parameters (such as whether to enable retransmission P7, the number of retransmissions P8, and the response timeout control word P9) may be omitted in other embodiments.

[0046] Accordingly, the data frame format is as follows:

[0047]

[0048] Please see Figure 1 This application discloses a transmitter 1 for transmitting data frames according to the above-described data frame format, including an information transmission module 11, which includes a checksum generation unit 111 and a transmission unit 112.

[0049] The check code generation unit 111 is used to determine whether to enable check code generation based on the check enable control word P5. If yes, it generates a check code based on the check mode control word P6 and the received user data, and sends the user data and check code to the sending unit 112. If no, it sends the user data to the sending unit 112.

[0050] The sending unit 112 is used to generate and send data frames based on the received user data and checksum, or user data. Depending on whether a checksum is present, the data frame sequentially includes a start bit, a checksum bit, data bits, and a stop bit, or sequentially includes a start bit, data bits, and a stop bit. That is, if the sending end 1 has enabled the checksum generation function, the data frame includes a checksum bit; if the sending end 1 has not enabled the checksum generation function, the data frame does not include a checksum bit. Whether the data frame includes or excludes a checksum bit, and the width of the checksum bit, are jointly determined by the checksum enable control word P5 and the checksum mode control word P6.

[0051] When sending a data frame, the sending unit 112 counts the number of bits in the currently sent data frame in real time to obtain an output count value.

[0052] When checksum generation is enabled, if the output count value reaches the bit width value P2 of the start bit, the transmitting unit 112 will start outputting the data of the check bit from the next bit; when the output count value reaches the sum of the bit width value P2 of the start bit and the bit width value of the check bit, the transmitting unit 112 will start outputting the data of the data bit from the next bit; when the output count value reaches the sum of the bit width value P2 of the start bit, the bit width value of the check bit, and the bit width value P3 of the data bit, the transmitting unit 112 will start outputting the value of the stop bit from the next bit.

[0053] When checksum generation is not enabled, if the output count value reaches the bit width of the start bit, the transmitting unit 112 will start from the next bit and output the data of the data bit; when the output count value reaches the sum of the bit width P2 of the start bit and the bit width P3 of the data bit, the transmitting unit 112 will start from the next bit and output the value of the stop bit.

[0054] Compared with the prior art, the transmitting end 1 of this application can determine whether to enable the checksum based on the checksum enable control word P5, select the corresponding checksum method according to the checksum method control word P6 to generate a checksum for the received data, and determine whether to send the checksum after the information sending module sends the start bit information based on the checksum enable control word P5. The transmitting end 1 of this application can control whether to enable checksum generation, the checksum method of the data frame, and the sending length of the data frame according to the start bit width value P1, the checksum enable control word P5, the checksum method control word P6, and the data bit width value P3, so as to realize the variable checksum method and the selectable bit width of the sent data frame, and flexibly control the sending content of the information sending module 11.

[0055] Please see Figure 1 In some embodiments, when the output count value reaches the sum of the bit width value P2 of the start bit, the bit width value of the parity bit, the bit width value P3 of the data bit, and the bit width value P4 of the stop bit, the serial output completion control position is set to the parameter corresponding to the completed state (for example, incomplete is set to "0", completed is set to "1"), and the output count value is set to "0" in the next clock cycle to prevent errors from occurring when recounting.

[0056] Please see Figure 1 In some embodiments, the transmitting end 1 further includes an output scheduling unit 12. When the transmitting end 1 receives an output data valid signal, it sends the received user data to the output scheduling unit 12. The output scheduling unit 12 is used to query whether the information sending module 11 is busy when it receives user data. If it is busy, it stores the user data in a buffer; otherwise, it sends the user data to the checksum generation unit 111.

[0057] Specifically, whether the information sending module 11 is in a busy state can be determined by querying the serial output busy control bit. Taking "1" to indicate busy and "0" to indicate idle as an example, when the information sending module 11 is in a busy state, the serial output busy control bit of the information sending module 11 is set to "1", and when the information sending module 11 is in a busy state, the serial output busy control bit of the information sending module 11 is set to "0". The output scheduling unit 12 can determine whether the information sending module 11 is in a busy state by querying whether the serial output busy control bit is "1" or "0".

[0058] Specifically, when the information sending module 11 is found to be busy, the output scheduling unit 12 stores the user data in the FIFO buffer (First Input First Output buffer).

[0059] Specifically, the output scheduling unit 12 receives user data in parallel and sends the user data to the checksum generation unit 111 in parallel. The checksum generation unit 111 determines, based on the checksum enable control word P5, whether to send the user data and checksum to the sending unit 112 in parallel, or to send only the user data. After receiving the data sent by the checksum generation unit 111, the sending unit 112 sends data frames serially.

[0060] Please see Figure 1 In some embodiments, the transmitting unit 112 includes a first baud rate generator 1121 and a first counter 1122. The first baud rate generator 1121 is used to set the maximum value of the transmitting clock count according to the baud rate control word P1. The maximum value of the transmitting clock count is equal to the quotient of the clock frequency of the clock signal and the baud rate of the first baud rate generator 1121. The first counter 1122 is used to count the clock pulses received by the first baud rate generator 1121 to obtain the transmitting clock count value. When the transmitting clock count value counts from zero to the maximum value of the transmitting clock count minus one, the output count of one bit of the data frame is completed.

[0061] Specifically, the transmitting unit 112 outputs the start bit according to the bit width value P2 of the start bit, the shift register 1123 of the transmitting unit 112 processes the user data according to the bit width value P3 of the data bits, and the transmitting unit 112 outputs the stop bit according to the bit width value P4 of the stop bit.

[0062] In some embodiments, the check code generation unit 111 is configured with multiple check mode control words P6. The check code generation unit 111 generates different forms of check codes (such as CRC8 / 16 / 32 check, ECC check, odd check and even check, etc.) based on the multiple check mode control words P6. At least some forms of check codes correspond to check bits of different lengths.

[0063] Please see Figure 1 In some embodiments, the information sending module 11 further includes an output counter (not shown), which counts the number of bits of the data frame currently sent by the sending unit 112 to obtain an output count value.

[0064] Please see Figure 1 This application also discloses a receiver 2 for receiving data frames sent by the sender 1, including an information receiving module 21, which includes a check code verification unit 211 and a receiving unit 212.

[0065] When the receiving port of the information receiving module 21 receives the start receiving signal, the receiving unit 212 starts receiving data frames, and the receiving unit 212 counts the number of bits of the currently received data frame in real time to obtain the receiving count value.

[0066] When checksum generation is enabled, if the received count value reaches the bit width value P2 of the start bit, the receiving unit 212 starts receiving the data of the check bit of the data frame from the next bit; when the received count value reaches the sum of the bit width value P2 of the start bit and the bit width value of the check bit, the receiving unit 212 starts receiving the data of the data bit of the data frame from the next bit; when the received count value reaches the sum of the bit width value P2 of the start bit, the bit width value of the check bit, and the bit width value P3 of the data frame, the received checksum and user data are sent to the checksum verification unit 211; the checksum verification unit 211 generates a checksum based on the user data and the checksum mode control word P6, and compares the checksum with the checksum. If the checksum and checksum match, the received user data is valid data.

[0067] When checksum generation is not enabled, if the receive count value reaches the bit width value of the start bit, the receiving unit 212 will start receiving the data of the data bit from the next bit; when the receive count value reaches the sum of the bit width value P2 of the start bit and the bit width value P3 of the data bit, the reception of the data frame is completed.

[0068] Please see Figure 1 In some embodiments, the receiving unit 212 includes a second baud rate generator 2121 and a second counter 2122. The second baud rate generator 2121 is used to set the maximum value of the receiving clock count according to the baud rate control word P1. The maximum value of the receiving clock count is equal to the quotient of the clock frequency of the clock signal and the baud rate of the second baud rate generator 2121. The second counter 2122 is used to count the clock pulses received by the second baud rate generator 2121 to obtain the receiving clock count value. When the receiving clock count value counts from zero to the maximum value of the receiving clock count minus one, the receiving count of one bit of the data frame is completed.

[0069] Specifically, the receiving unit 212 detects the start bit according to the bit width value P2 of the start bit, the shift register 2123 of the receiving unit 212 processes the user data according to the bit width value P3 of the data bits, and the receiving unit 212 detects the stop bit according to the bit width value P4 of the stop bit.

[0070] Please see Figure 1 In some embodiments, the signal to begin receiving is a falling edge signal;

[0071] When checksum generation is enabled, if the received clock count value reaches the difference between half of the maximum received clock count value and 1, and the received count value just exceeds the bit width of the start bit of the data frame, then the receiving unit 212 collects the value of the input port at this time as the next bit of data.

[0072] It is understandable that if the sending end 1 sends the data frame from the least significant bit to the most significant bit, then the receiving end 2 will also receive the data from the least significant bit to the most significant bit; if the sending end 1 sends the data frame from the most significant bit to the least significant bit, then the receiving end 2 will also receive the data from the most significant bit to the least significant bit.

[0073] In some embodiments, the receiving unit 212 receives data frames serially and sends user data to the check code verification unit 211 in parallel. The check code verification unit 211 determines whether to verify the check code based on the check enable control word P5 and the check mode control word P6. If not, the user data is sent to the user in parallel; if so, the check code is verified based on the check mode control word P6 and the user data, and the user data is sent to the user in parallel when the verification passes.

[0074] Please see Figure 1 This application also discloses a communication device, including the transmitting end 1 and the receiving end 2 as described above.

[0075] Please see Figure 1 This application also discloses a communication device, including a retransmission control unit 3, the aforementioned transmitting end 1, and the aforementioned receiving end 2.

[0076] Sending end 1 is used to send data frames to receiving end 2 of another communication device, and receiving end 2 is used to receive the response frame corresponding to the data frame sent by sending end 1 of the other communication device.

[0077] When checksum generation is enabled, if the checksum of the response frame is inconsistent with the checksum generated by the receiver 2, and the retransmission function is enabled, the retransmission control unit 3 sends a retransmission data request to the output scheduling unit 12, causing the output scheduling unit 12 to retransmit the data frame to the information sending module 11.

[0078] When the checksum of the acknowledgment frame received by the receiving end 2 does not match the checksum generated by the receiving end 2, the communication device of this application can choose to resend the data frame to another communication device, requesting the other communication device to resend the acknowledgment frame, thus making the communication between the two communication devices more reliable. Furthermore, the function of resending data frames can be optionally enabled or disabled, making the communication between the two communication devices more flexible.

[0079] In some embodiments, the retransmission control unit 3 counts the number of times a data frame that needs to be retransmitted is sent to obtain a retransmission count. The retransmission control unit 3 does not send a retransmission data request to the output scheduling unit 12 for data frames whose retransmission count has reached a preset retransmission count. And / or, if the response timeout retransmission function is enabled, the retransmission control unit 3 also receives an output data valid signal, and when it receives the output data valid signal, it times the time when the receiving end 2 receives the response frame to obtain a response time value. When the response time value is greater than the preset response time value, the retransmission control unit 3 sends a retransmission data request to the output scheduling unit 12.

[0080] Specifically, the retransmission control unit 3 sends retransmission data requests to the output scheduling unit 12 in parallel.

[0081] Specifically, the check code verification unit 211 sets the parameters of the received data valid control bit according to the comparison result between the check code and the verification code (set to "1" if the comparison result is consistent, and set to "0" if inconsistent). The check code verification unit 211 also sends a verification completion signal to the retransmission control unit 3.

[0082] Accordingly, the conditions under which the retransmission control unit 3 sends a retransmission data request to the output scheduling unit 12 include:

[0083] (1) The retransmission enable control word P7 is the parameter corresponding to retransmission enable (e.g., "1" means retransmission enable, "0" means no retransmission enable).

[0084] (2) Receive the verification completion signal from the verification code verification unit 211 (e.g., "1" represents verification completion, "0" represents verification incomplete).

[0085] (3) The valid control bit of the received data is in the check error state (e.g., "0" represents a check error, that is, the comparison results are inconsistent).

[0086] (4) If the number of times a data frame is retransmitted is less than the number of times it is retransmitted control word P8, then no further retransmission will be performed when a data frame is retransmitted too many times.

[0087] Optionally, when the number of data frame retransmissions exceeds the retransmission count control word P8, the receive data valid control bit is set to the correct state, but at the same time the count of the check error is incremented by 1, ensuring that the retransmission control unit 3 does not meet the retransmission requirement at this time and does not retransmit the data frame, while also letting the system know that the data frame has a check error.

[0088] Optionally, the corresponding data frame will be retransmitted to the information sending module 11 only when the output scheduling unit 12 receives the retransmission data request and the retransmission data valid signal sent by the retransmission control unit 3.

[0089] Please see Figure 1In some embodiments, when the time for the retransmission control unit 3 to wait for the response frame at the receiving end 2 exceeds the response timeout control word P9, the retransmission control unit 3 sends a retransmission data request to the output scheduling unit 12.

[0090] Specifically, when the retransmission enable control word P7 enables the parameter value corresponding to the retransmission control unit 3, the response timeout control word P9 takes effect. When the transmitting end 1 receives the output data valid signal, it starts timing to obtain the transmission response time. When the transmission response time is greater than the response timeout control word P9, the retransmission control unit 3 sends a retransmission data request to the output scheduling unit 12.

[0091] In some embodiments, a user data processing module 4 is also included, which is used to receive user input data to form user data and send the user data to the sending end 1.

[0092] Specifically, the valid output data signal is issued by the user data processing module 4.

[0093] Specifically, when the verification code is not enabled, the receiving end 2 will receive the user data and then send the user data to the user data processing module 4. The user data processing module 4 will parse the data and then pass it to the user. When the verification code is not enabled, the receiving end 2 will receive the user data, and after comparing the verification code and the check code, it will send the user data to the user data processing module 4. The user data processing module 4 will parse the data and then pass it to the user.

[0094] Optionally, while sending user data to the user data processing module 4, the receiving end 2 also sends a received data validity signal to the user data processing module 4 to inform the user whether the corresponding user data is valid.

[0095] Please see Figure 3 In some embodiments, the transmitter 5 of the communication device of this application uses single-ended to differential signal line transmission, and the receiver 6 uses differential signal line to single-ended reception, which can further improve the reliability of transmission. Furthermore, since only ordinary input and output pins are needed, it is applicable to a wide range of chips, and the interface pin definitions are more flexible. In addition, due to the simplicity of the protocol, the circuit resources required to implement the communication protocol of the communication device of this application are small, and multiple communication interfaces can be flexibly implemented in resource-constrained devices according to requirements.

[0096] Specifically, for the implementation of differential signal lines, if it is a wire harness, it can be implemented using twisted pair cables; if it is a PCB board, it can be implemented using differential routing on the PCB board. This is a technical method well known to those skilled in the art and will not be elaborated further.

[0097] Please see Figure 2The information transmission and reception process of two communication devices of this application is briefly described below:

[0098] S1, the first communication device sends a data frame from the transmitting end 1. If the retransmission control unit 3 of the first communication device is in the start state, then when the second communication device responds and times out, step S4 is executed.

[0099] S2, the receiving end 2 of the second communication device receives the data frame and performs verification. After the verification is successful, the sending end 1 of the second communication device sends the response frame.

[0100] S3, the receiving end 2 of the first communication device receives the response frame and verifies the response frame. If the verification passes, the communication is completed. If the verification fails, step S4 is executed.

[0101] S4, in the first communication device, it is determined that the current data frame retransmission count is greater than the retransmission count control word P8. If so, the data frame is retransmitted to the second communication device by the sending end 1 of the first communication device, and step S2 is executed; otherwise, an error is reported and communication is terminated.

[0102] The experimental data of the communication equipment described in this application are presented below.

[0103] The resource usage of the FPGA's communication core is as follows. The meanings of the parameters in the table header are well known to those skilled in the art and will not be elaborated further:

[0104]

[0105] The above data results indicate that the resource utilization of the communication core in this application is superior to that of existing communication equipment.

[0106] The communication device described in this application has been validated through FPGA practice. Specifically, at baud rates of 6.25Mbps, 12.5Mbps, and 25Mbps, at a distance of 5 meters, it achieved 1 billion read / write cycles with 0 packet loss, 0 errors, and low latency (these figures are related to the baud rate and the clock frequency of the implementation). In terms of transmission rate, reliability, and flexibility, it outperforms existing general-purpose serial asynchronous receivers and transmitters.

[0107] Furthermore, the communication port used by the communication device in this application only requires a general-purpose I / O port. Taking Xilinx's Artix7 series as an example, the general-purpose I / O port can reach a speed of 680MHz and a clock frequency of 628.125MHz. The commonly used LVDS single-ended to differential chip can reach a speed of 400Mbps. According to the Nyquist theorem, the baud rate using this communication protocol and control method can reach approximately 314Mbps, which is much higher than the 230400bps of a general-purpose serial receiver and transmitter. The former is about 1362 times that of the latter, and the speed is significantly improved.

[0108] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A transmitter for transmitting data frames, characterized in that, It includes an information sending module, which comprises a verification code generation unit and a sending unit; The verification code generation unit is used to determine whether to enable verification code generation based on the verification enable control word. If yes, it generates a verification code based on the verification method control word and the received user data, and sends the user data and the verification code to the sending unit. If no, it sends the user data to the sending unit. The sending unit is used to generate and send a data frame based on the received user data and the check code or the user data. Depending on whether the check code exists, the data frame includes a start bit, a check bit, data bits and a stop bit in sequence, or includes a start bit, data bits and a stop bit in sequence. When sending the data frame, the sending unit counts the number of bits in the currently sent data frame in real time to obtain an output count value; When checksum generation is enabled, if the output count value reaches the bit width of the start bit, the sending unit outputs the data of the check bit starting from the next bit; when the output count value reaches the sum of the bit width of the start bit and the bit width of the check bit, the sending unit outputs the data of the data bit starting from the next bit; when the output count value reaches the sum of the bit width of the start bit, the bit width of the check bit, and the bit width of the data bit, the sending unit outputs the value of the stop bit starting from the next bit. When checksum generation is not enabled, if the output count value reaches the bit width of the start bit, the sending unit outputs the data of the data bit starting from the next bit; when the output count value reaches the sum of the bit width of the start bit and the bit width of the data bit, the sending unit outputs the value of the stop bit starting from the next bit.

2. The transmitting end as described in claim 1, characterized in that, It also includes an output scheduling unit; When the transmitting end receives the output data valid signal, it sends the received user data to the output scheduling unit. The output scheduling unit is used to query whether the information sending module is busy when it receives the user data. If it is busy, the user data is stored in the cache; otherwise, the user data is sent to the verification code generator.

3. The transmitting end as described in claim 1, characterized in that, The transmitting unit includes a first baud rate generator and a first counter. The first baud rate generator is used to set a maximum transmit clock count value according to the baud rate control word. The maximum transmit clock count value is equal to the quotient of the clock frequency of the clock signal and the baud rate of the first baud rate generator. The first counter is used to count the clock pulses received by the first baud rate generator to obtain a transmit clock count value. When the transmit clock count value counts from zero to the maximum transmit clock count value minus one, the output count of one bit of the data frame is completed.

4. The transmitting end as described in claim 1, characterized in that, The check code generation unit is configured with a plurality of the check mode control words, and the check code generation unit generates check codes of different forms based on the plurality of check mode control words, at least some of the check codes corresponding to check bits of different lengths.

5. A receiving end, configured to receive a data frame transmitted by a transmitting end as described in any one of claims 1 to 4, characterized in that, The system includes an information receiving module, which comprises a verification code verification unit and a receiving unit. When the receiving port of the information receiving module receives the start receiving signal, the receiving unit begins to receive the data frame, and the receiving unit counts the number of bits of the currently received data frame in real time to obtain a receiving count value. When checksum generation is enabled, if the received count value reaches the bit width value of the start bit, the receiving unit starts receiving the data of the checksum bit of the data frame from the next bit; when the received count value reaches the sum of the bit width value of the start bit and the bit width value of the checksum bit, the receiving unit starts receiving the data of the data bits of the data frame from the next bit; when the received count value reaches the sum of the bit width value of the start bit, the bit width value of the checksum bit, and the bit width value of the data bits of the data frame, the received checksum and the user data are sent to the checksum verification unit. The verification code verification unit generates a verification code based on the user data and the verification method control word, and compares the verification code with the verification code. If the verification code matches the verification code, the received user data is valid data. When checksum generation is not enabled, if the receive count value reaches the bit width value of the start bit, the receiving unit starts receiving the data of the data bit from the next bit; when the receive count value reaches the sum of the bit width value of the start bit and the bit width value of the data bit, the reception of the data frame is completed.

6. The receiving end as described in claim 5, characterized in that, The receiving unit includes a second baud rate generator and a second counter. The second baud rate generator is used to set the maximum value of the receiving clock count according to the baud rate control word. The maximum value of the receiving clock count is equal to the quotient of the clock frequency of the clock signal and the baud rate of the second baud rate generator. The second counter is used to count the clock pulses received by the second baud rate generator to obtain the receiving clock count value. When the receiving clock count value counts from zero to the maximum value of the receiving clock count minus one, the receiving count of one bit of the data frame is completed.

7. The receiving end as described in claim 6, characterized in that, The signal to begin receiving is a falling edge signal; When checksum generation is enabled, if the received clock count value reaches the difference between half of the maximum received clock count value and 1, and the received count value just exceeds the bit width value of the start bit of the data frame, then the receiving unit collects the value of the input port at this time as the next bit of data.

8. A communication device, characterized in that, It includes the transmitting end as described in any one of claims 1 to 4 and the receiving end as described in any one of claims 5 to 7.

9. A communication device, characterized in that, Includes a retransmission control unit, a transmitter as described in claim 2, and a receiver as described in any one of claims 5 to 7. The sending end is used to send the data frame to the receiving end of another communication device, and the receiving end is used to receive the response frame corresponding to the data frame sent by the sending end of the other communication device. When checksum generation is enabled, if the checksum of the response frame is inconsistent with the checksum generated by the receiving end, and the retransmission function is enabled, the retransmission control unit sends a retransmission data request to the output scheduling unit, so that the output scheduling unit retransmits the data frame to the information sending module.

10. The communication device as described in claim 9, characterized in that, The retransmission control unit counts the number of times the data frame that needs to be retransmitted is sent to obtain a retransmission count. The retransmission control unit does not send the retransmission data request to the output scheduling unit for the data frame whose retransmission count has reached a preset retransmission count. And / or, If the response timeout retransmission function is enabled, the retransmission control unit also receives the output data valid signal, and when the output data valid signal is received, it counts the time when the receiving end receives the response frame to obtain the response time value. When the response time value is greater than the preset response time value, the retransmission control unit sends the retransmission data request to the output scheduling unit.

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