A satellite communication system gateway-side transmission link based on DVB-RCS2

Abstract

The present invention discloses a DVB-RCS2-based satellite communication system gateway-side transmission link, comprising an embedded module, a configuration control module, a data processing module, a data storage module, a transmission channelizer, a data transmission module, an asynchronous clock synchronization module, and a GPS / BD synchronization module. The time-division multiplexing design of the data storage module's alternating cache and the data processing module not only effectively shortens the processing time of the data stream, but also reduces system complexity and hardware resource consumption. In addition, the design of the transmission channelizer introduces a time-division multiplexing mechanism of parallel links, and combines it with a multi-phase filtering structure to perform time-division processing on the signals of all channels within the bandwidth, thereby achieving high computational efficiency and real-time processing capabilities. The present invention effectively solves the problems of high hardware resource consumption and large processing delay in the multi-channel signal transmission link on the satellite communication system gateway side, and provides support for efficient and reliable satellite communications.

Description

Technical Field

[0001] The present invention relates to satellite communication technology, in particular to a satellite communication system gateway side transmission link based on DVB-RCS2. Background Art

[0002] In satellite communication systems, the implementation of gateway-side transmission links primarily relies on software control and processing. While this offers significant flexibility, it is limited in processing speed and real-time performance. Especially in high-data-rate transmission scenarios, software-implemented links are prone to bottlenecks and struggle to meet practical application requirements. Field-programmable gate arrays (FPGAs), as parallel processing devices, are becoming an ideal choice for high-performance data processing due to their high speed and flexibility.

[0003] Existing satellite communication system gateway-side transmission links often rely on software processing or ASIC (Application-Specific Integrated Circuit)-based DVB-S2(X) modulators. These solutions, respectively, lack flexibility and cost. FPGA-based implementations not only increase link processing speed through hardware acceleration but also offer flexible programmability to accommodate future standard upgrades and functionality expansions. Combining an embedded module based on a dual-core processor with an FPGA allows for efficient allocation of complex signal processing tasks within the link, ensuring real-time system performance while reducing power consumption.

[0004] In practical applications, the transmit link on the gateway side of a satellite communication system comprises multiple processing modules, each of which requires close collaboration to ensure seamless processing and efficient transmission of data streams. Currently, there is a lack of efficient hardware solutions for effectively interconnecting and controlling these modules, especially in high-speed data transmission scenarios. Therefore, designing an efficient gateway-side transmit link hardware implementation based on FPGA configuration to meet the high-performance requirements of satellite communication systems has become a key technological development. Summary of the Invention

[0005] In view of the problems existing in the prior art, the object of the present invention is to provide an efficient DVB-RCS2 satellite communication system gateway-side transmission link implemented by FPGA hardware.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0007] A satellite communication system gateway-side transmission link based on DVB-RCS2, comprising:

[0008] An embedded module, configured to receive superframe data and payload data including configuration information sent by the protocol layer, and upon receiving a configuration enable signal from the configuration control module, send a configuration instruction including superframe data to the configuration control module, and perform absolute time synchronization according to the time base signal of the GPS / BD synchronization module;

[0009] The configuration control module is used to receive the configuration instructions of the embedded module, parse the superframe data in the configuration instructions, configure the superframe parameters in the register, and generate a configuration enable signal, a superframe enable signal and a data storage timing control signal, and send them to the embedded module, the data processing module and the data storage module respectively;

[0010] The data processing module is configured to obtain payload data from the embedded module upon receiving a superframe enable signal, read superframe parameters from the configuration control module, and perform data movement, scrambling, forward check, turbo encoding, adding known symbols, data mapping, symbol modulation, and matched filtering on the payload data in accordance with the DVB-RCS2 signal processing standard based on the superframe parameters to generate a complex signal.

[0011] The data storage module is used to store the coded data after Turbo coding in the data processing module, and after receiving the data storage timing control signal from the configuration control module, sequentially release the stored coded data to the data processing module, so that the data processing module can perform known symbol addition, data mapping, symbol modulation and matched filtering operations;

[0012] The transmit channelizer is used to combine narrowband sub-signals of the same or different bandwidths into a wideband signal, receive the complex signal generated by the data processing module, and combine the complex signal into a baseband digital signal to send to the data transmission module;

[0013] The data transmission module is used to up-convert the baseband digital signal output from the transmit channelizer, generate an upper sideband RF signal in combination with the local oscillator signal, and convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link through digital-to-analog conversion;

[0014] Asynchronous clock synchronization module, used to connect embedded modules and external hardware modules using bus logic controlled by different clock domains to achieve timing alignment between different clock domains;

[0015] The GPS / BD synchronization module is used to provide a unified time base reference for the entire system by receiving high-precision time signals from GPS / BD satellites.

[0016] Furthermore, the configuration control module specifically includes:

[0017] A register configuration unit is connected to the embedded module and is used to receive and parse configuration instructions sent by the embedded module, parse the configuration instructions, obtain superframe parameters including burst data length and payload waveform, and configure register space through timing control. The register space is divided into public registers and superframe registers. The public registers are configured with public data, and the superframe registers are configured with superframe parameters.

[0018] Timing control unit, used to generate configuration enable signal I config (t), superframe enable signal I frame (t), data storage timing control signal h(t), configure the enable signal I config (t) is sent to the embedded module, and the superframe enable signal I is set when the read and write flag signal F of the data storage module is 1. frame (t) is sent to the data processing module. When the read / write flag signal F of the data storage module is 0 and the working status flag tready of the data processing module is 1, the data storage timing control signal h(t) is sent to the data storage module. tready=1 indicates that the back end of the data processing module is in the read state.

[0019]

[0020] Where M represents the superframe update time interval, S represents the time that the superframe configuration time is ahead of the superframe time, and N sym Indicates the number of symbols read from the data storage module, S sym represents the symbol rate, δ(t) represents the unit pulse sequence, and T[] represents the periodic correlation function;

[0021] The signal reading unit is used to obtain the read / write flag signal F from the data storage module, read the working status flag tready from the data processing module, and send it to the timing control unit.

[0022] Furthermore, the data processing module specifically includes:

[0023] The data transfer unit obtains the payload data from the embedded module upon receiving the superframe enable signal;

[0024] The scrambling unit is used to scramble the data output by the data transfer unit;

[0025] A forward verification unit, used for forward verification of the data output by the scrambling unit;

[0026] A turbo encoding unit, configured to perform turbo encoding on the data output by the forward check unit according to the burst data length in the superframe parameters, and output the encoded data to the data storage module after encoding;

[0027] Adding a known symbol unit, used to add a preamble, a postamble and pilot data to corresponding positions of the coded data output by the data storage module according to the payload waveform data in the superframe parameters;

[0028] A data mapping unit, configured to map the data output by the adding known symbol unit to corresponding points on the constellation diagram according to the payload waveform data in the superframe parameters;

[0029] a symbol modulation unit, configured to modulate the data output from the data mapping unit into symbols according to the payload waveform data in the superframe parameters;

[0030] The matched filtering unit filters the symbols output by the symbol modulation unit according to the entire link information.

[0031] Furthermore, the matched filtering unit includes:

[0032] Memory, cache depth is The symbols output by the receiving symbol modulation unit are used to After the length, all symbols are released to the raised cosine filter, L span represents the cutoff length of the matched filter;

[0033] The matched filter is connected after the memory and is used to perform matched filtering on the symbols. The time domain impulse response of the matched filter is:

[0034]

[0035] Where g(t) is the time domain impulse response, β is the roll-off factor, T is the symbol period, and T L for The length of the cache period.

[0036] Furthermore, the data storage module includes a first memory block and a second memory block for alternately storing the encoded data output by the Turbo encoding unit.

[0037] Furthermore, the first memory block and the second memory block are both stored in burst data units, and an empty and full flag signal empty is set. When the first memory block or the second memory block stores a burst data, the empty and full flag signal empty of the memory block is 0, otherwise it is 1.

[0038] Furthermore, the data storage module is provided with a write selector SEL1 and a read selector SEL2, SEL1 defaults to 0, SEL2 defaults to 0, when the empty value in the first memory block is 1, SEL1 is switched to 1, and SEL2 is switched to 0, thereby writing data to the first memory block and reading data from the second memory block; when the empty value in the second memory block is 1, SEL1 is switched to 0, and SEL2 is switched to 1, thereby writing data to the second memory block and reading data from the first memory block;

[0039] The data storage module generates a read-write flag signal F based on the empty and full flag signals of the first memory block and the second memory block, and sends it to the configuration control module. When the empty and full flag signal of the first memory block or the second memory block is empty=1, F=1, indicating a write state; otherwise, F=0, indicating a read state. When the data storage timing control signal h(t)=1 received by the data storage module, data is read from the corresponding memory block.

[0040] Furthermore, the transmit channelizer is based on a polyphase filtering structure and adopts a time division multiplexing mechanism. It includes an IDFT unit, a complex multiplication unit, a channel filtering unit, a symbol conversion unit, an interpolation unit, and a storage and addition unit connected in sequence to achieve multi-channel data integration and spectrum allocation. The output signal of the transmit channelizer is:

[0041]

[0042] Where Y(n) represents the output signal of the transmit channelizer, X i (n) represents the complex data output by the data processing module after the i-th transmission channel is processed, IDFT[] represents the inverse discrete Fourier transform, K represents the number of channels, h i (n) represents the channel filter, z K-1-i Represents the delay of the i-th transmission channel data.

[0043] Furthermore, the data transmission module includes:

[0044] An up-conversion unit is used to up-convert the baseband digital signal output from the transmit channelizer and generate an upper sideband RF signal in combination with a local oscillator signal;

[0045] The digital-to-analog conversion unit is used to convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link.

[0046] Furthermore, the GPS / BD synchronization module uses an adaptive product difference algorithm to perform clock convergence based on the second pulse generated by the GPS / BD receiving module.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] This paper addresses the application requirements of satellite communication system gateways by designing an efficient transmit link hardware implementation solution that offers significant advantages in resource conservation and performance optimization. By configuring the control module and data storage module, and adopting an alternating caching and alternating configuration mode, the system significantly reduces parameter configuration and parsing time, significantly improving the overall operational efficiency of the system.

[0049] At the same time, the data processing module and the transmit channelizer work together through time-division multiplexing, maximizing the sharing and reuse of hardware resources. This design effectively reduces hardware implementation complexity and production costs, demonstrating superior engineering adaptability and cost-effectiveness.

[0050] Furthermore, the present invention incorporates a matched filtering mechanism for caching header data, taking into account both time slot scheduling and resource allocation. This mechanism not only improves signal processing accuracy and efficiency but also enhances the system's robustness under complex channel conditions, providing a crucial guarantee for link stability.

[0051] The overall design scheme combines flexibility and reliability, embodying innovative advantages in efficient utilization of hardware resources, optimized data processing performance, and improved system stability. It provides an efficient and economical solution for the hardware implementation of the transmission link on the gateway side of the satellite system and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A partial structural block diagram of the transmission link on the gateway side of the satellite communication system based on DVB-RCS2 provided by the present invention;

[0053] Figure 2 It is a structural block diagram of the data storage module;

[0054] Figure 3 Comparison between the block diagram of a traditional transmit channelizer based on a polyphase filter structure (a) and the block diagram of a transmit channelizer based on a polyphase filter structure using a time division multiplexing mechanism (b);

[0055] Figure 4 Comparison of time flows with and without advance configuration;

[0056] Figure 5 Comparison of the burst processing time with and without a storage structure. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0058] The present invention provides a satellite communication system gateway side transmission link based on DVB-RCS2, such as Figure 1 As shown, including:

[0059] Embedded module 1 is configured to receive superframe data and payload data including payload data sent by the protocol layer, and upon receiving a configuration enable signal from the configuration control module 2, send a configuration instruction including superframe data to the configuration control module 2, and perform absolute time synchronization according to the time base signal of the GPS / BD synchronization module;

[0060] Configuration control module 2, used to receive configuration instructions from embedded module 1, parse superframe data in the configuration instructions, configure superframe parameters in registers, and generate a configuration enable signal, a superframe enable signal, and a data storage timing control signal, and send them to embedded module 1, data processing module, and data storage module respectively;

[0061] The data processing module 3 is configured to, upon receiving a superframe enable signal, obtain payload data from the embedded module 1, read superframe parameters from the configuration control module 2, and, based on the superframe parameters and in compliance with the DVB-RCS2 signal processing standard, sequentially perform data movement, scrambling, forward check, turbo encoding, known symbol addition, data mapping, symbol modulation, and matched filtering on the payload data to generate a complex signal;

[0062] The data storage module 4 is used to store the coded data after Turbo coding in the data processing module 3 and, upon receiving the data storage timing control signal from the configuration control module 2, sequentially release the stored coded data to the data processing module, so that the data processing module 3 can perform the operations of adding known symbols, data mapping, symbol modulation, and matched filtering;

[0063] The transmit channelizer 5 is used to combine narrowband sub-signals of the same or different bandwidths into a wideband signal, receive the complex signal generated by the data processing module 3, and combine the complex signal into a baseband digital signal to send to the data transmission module;

[0064] The data transmission module is used to up-convert the baseband digital signal output from the transmit channelizer, generate an upper sideband RF signal in combination with the local oscillator signal, and convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link through digital-to-analog conversion;

[0065] An asynchronous clock synchronization module is used to connect the embedded module 1 and the external hardware module using bus logic controlled by different clock domains to achieve timing alignment between different clock domains;

[0066] The GPS / BD synchronization module is used to provide a unified time base reference for the entire system by receiving high-precision time signals from GPS / BD satellites.

[0067] Each module is described in detail below.

[0068] The embedded module 1 utilizes a Xilinx SoC microprocessor core (such as an ARM Cortex series or MicroBlaze core), offering efficient computing and flexible task processing capabilities. It not only supports complex logical operations and data processing but also efficiently runs embedded operating systems (such as Linux or FreeRTOS) and other high-level control programs.

[0069] Embedded module 1 seamlessly exchanges information and data with the programmable logic via the standardized AXI bus protocol. Through the AXI bus interface, embedded module 1 can efficiently read and write data, perform tasks such as command distribution and parameter configuration, and simultaneously receive data feedback from the programmable logic. This design ensures high-speed communication and task collaboration between modules within the system while reducing system coupling.

[0070] Furthermore, embedded module 1 provides fast access to control signals via the AXI4-Lite interface and real-time transmission of high-speed data streams via the AXI4-Stream interface. This architecture meets the needs of both low-bandwidth control tasks and high-bandwidth data processing tasks, further improving the overall system's operational efficiency and reliability.

[0071] The configuration control module 2 specifically includes:

[0072] The register configuration unit 201 is connected to the embedded module through bus timing and writes into the register space through timing control. It is used to receive and parse the configuration instructions sent by the embedded module 1, parse the configuration instructions, obtain superframe parameters including burst data length and payload waveform, and configure the register space through timing control. The register space is divided into public registers and superframe registers. The public registers configure public data, and the superframe registers configure superframe parameters. Specifically, the public registers and superframe registers have 512 groups of registers respectively, and each register occupies 32 bits. Among them, the public registers mainly include registers such as version number, rate, number of channels, and status; the superframe registers mainly include superframe parameters, and the update time interval is 40ms. To save time during superframe configuration and parameter parsing and allocation, superframe registers are divided into two groups, which alternate configurations. The switching time is 40ms, so the data in one superframe register group is retained for 80ms, resulting in a superframe update interval M = 80ms. Furthermore, superframe parameter configuration must be performed S = 5ms in advance to facilitate parameter parsing and transmission. Furthermore, because the number of bursts varies, the number of superframe registers that need to be configured also changes. Therefore, after each configuration, an update register must be written to notify the superframe configuration is complete.

[0073] Timing control unit 202, used to generate a configuration enable signal I config (t), superframe enable signal I frame (t), data storage timing control signal h(t), configure the enable signal I config (t) is sent to the embedded module 1, and the superframe enable signal I is set when the read and write flag signal F of the data storage module is 1. frame (t) is sent to the data processing module. When the read / write flag signal F of the data storage module is 0 and the working status flag tready of the data processing module is 1, the data storage timing control signal h(t) is sent to the data storage module. tready=1 indicates that the back end of the data processing module is in the read state.

[0074]

[0075] Where M represents the superframe update time interval, S represents the time that the superframe configuration time is ahead of the superframe time, and N sym Indicates the number of symbols read from the data storage module, S symrepresents the symbol rate, δ(t) represents the unit pulse sequence, and T[] represents the periodic correlation function; the configuration enable signal is used to notify the embedded module to configure the superframe register, and is triggered cyclically at a fixed time, t=S ahead of the superframe enable signal, so as to configure and parse the superframe information in advance and prepare for data processing; the superframe enable signal is triggered after the configuration is completed, and is triggered cyclically at a fixed time, with an interval of t=M for stable triggering, and is used to notify the payload data processing module to work; S <M。

[0076] The signal reading unit 203 is used to obtain the read / write flag signal F from the data storage module, read the working status flag tready from the data processing module, and send it to the timing control unit.

[0077] The data processing module 3 specifically includes:

[0078] The data transfer unit 301 obtains the payload data from the embedded module 1 upon receiving the superframe enable signal. It implements the communication bridge function between the data processing module 3 and the embedded module 1, not only supporting bidirectional data transmission but also flexibly adjusting the direction and priority of data flow, thereby achieving efficient collaboration between modules. Through the data transfer function, the system can quickly respond to upper-layer instructions, ensure real-time requirements, and improve the operating efficiency of the entire link.

[0079] The scrambling unit 302 is used to scramble the data output by the data transfer unit 301;

[0080] A forward check unit 303 is used to perform forward check on the data output by the scrambling unit 302;

[0081] A Turbo coding unit 304 is configured to perform Turbo coding on the data output by the forward check unit 303 according to the burst data length in the superframe parameters, and output the coded data to the data storage module 4 after coding;

[0082] The known symbol adding unit 305 is used to add the preamble, postamble and pilot data to the corresponding positions of the coded data output by the data storage module 4 according to the payload waveform data in the superframe parameters;

[0083] The data mapping unit 306 is used to map the data output by the adding known symbols unit 305 to the corresponding point on the constellation diagram according to the payload waveform data in the superframe parameters;

[0084] The symbol modulation unit 307 is used to modulate the data output from the data mapping unit 306 into symbols according to the payload waveform data in the superframe parameters;

[0085] The matched filtering unit 308 filters the symbols output by the symbol modulation unit 307 according to the entire link information.

[0086] The matched filter unit 308 includes:

[0087] Memory, cache depth is The symbols output by the receiving symbol modulation unit are used to After the length, all symbols are released to the raised cosine filter, L span represents the cutoff length of the matched filter;

[0088] The matched filter is connected after the memory and is used to perform matched filtering on the symbols. The time domain impulse response of the matched filter is:

[0089]

[0090] Where g(t) is the time domain impulse response, β is the roll-off factor, T is the symbol period, and T L for The length of the cache period.

[0091] The matched filter unit 308 uses a root raised cosine filter to process the modulated data signal, so that the signal waveform matches the receiving filter characteristics of the receiving end, maximizes the signal-to-noise ratio (SNR), and effectively suppresses inter-symbol interference (ISI). This optimizes the transmission quality of the signal and improves the accuracy of demodulation at the receiving end. At the same time, the input and output interfaces of the raised cosine filter use symbol rate. In order to save data processing time and remove invalid symbols generated by filtering, the input port is connected to The input signal of the filter is input in two parts. The first part is directly input into the memory. Data, the second part of the pipeline inputs symbolic data.

[0092] In order to optimize the efficiency of hardware resource utilization, the entire data processing module adopts a time-division multiplexing operation mode. This design method can significantly reduce the required hardware resource investment while ensuring system performance. By accurately scheduling the data processing process and dividing the module functions in time, each processing unit runs in sequence in different time periods, thereby achieving resource sharing and maximizing utilization. Specifically, the time-division multiplexing method executes all processing links within the data processing module step by step in chronological order. This operating mode eliminates the need for independent hardware logic units for each processing link, but instead shares the same set of hardware resources, significantly reducing the amount of logic gates and memory occupied. In addition, through precise scheduling algorithms and pipeline design, the execution order of each processing link can be seamlessly connected, avoiding resource idleness and task conflicts, and further improving hardware utilization efficiency.

[0093] Among them, Figure 2As shown, the data storage module 4 includes a first memory block FIFO1 and a second memory block FIFO2, which are used to alternately store the encoded data output by the turbo encoding unit. The first and second memory blocks are both stored in bursts of data and set to an empty / full flag signal. When the first or second memory block stores a burst of data, the empty / full flag signal of the memory block is set to 0; otherwise, it is set to 1.

[0094] The data storage module is provided with a write selector SEL1 and a read selector SEL2, SEL1 defaults to 0, SEL2 defaults to 0, when the empty value in the first memory block is 1, SEL1 is switched to 1, and SEL2 is switched to 0, thereby writing data to the first memory block and reading data from the second memory block; when the empty value in the second memory block is 1, SEL1 is switched to 0, and SEL2 is switched to 1, thereby writing data to the second memory block and reading data from the first memory block.

[0095] The data storage module generates a read-write flag signal F based on the empty and full flag signals of the first memory block and the second memory block, and sends it to the configuration control module. When the empty and full flag signal of the first memory block or the second memory block is empty=1, F=1, indicating a write state; otherwise, F=0, indicating a read state. When the data storage timing control signal h(t)=1 received by the data storage module, data is read from the corresponding memory block.

[0096] The transmit channelizer 5 is based on a polyphase filtering structure and includes an IDFT unit 501, a complex multiplication unit 502, a channel filter unit 503, a symbol conversion unit 504, an interpolation unit 505, and a storage and addition unit 506 connected in sequence. It is used to achieve multi-channel data integration and spectrum allocation. The output signal of the transmit channelizer is:

[0097]

[0098] Where Y(n) represents the output signal of the transmit channelizer, X i (n) represents the complex data output by the data processing module after the i-th transmission channel is processed, IDFT[] represents the inverse discrete Fourier transform, K represents the number of channels, h i (n) represents the channel filter, z K-1-i Indicates the delay of the i-th transmission channel data, i increases from 0 to K-1, and the first transmission channel has the largest data delay, thereby realizing time division multiplexing and finally accumulating at the same time. i (n) is the data sequence after passing through the interpolation unit 505.

[0099] Traditional transmit channelizers such as Figure 3As shown, it can be seen that the transmit channelizer 5 of the present invention realizes the integration and spectrum allocation of multi-channel data, ensuring efficient transmission of signals and correct decoding at the receiving end; in order to improve resource utilization, each branch signal adopts a time division multiplexing mode to share the same set of channelizers, and at the same time adopts multi-phase interpolation to improve the efficiency of subsequent filtering and Fourier transform operations.

[0100] The data transmission module includes an up-conversion unit and a digital-to-analog conversion unit. The up-conversion unit is used to up-convert the baseband digital signal output from the transmission channelizer and generate an upper sideband radio frequency signal in combination with a local oscillator signal; the digital-to-analog conversion unit is used to convert the upper sideband radio frequency signal into an analog signal that can be processed by a subsequent radio frequency link.

[0101] The asynchronous clock synchronization module uses bus logic under the control of different clock domains to link embedded modules and external hardware modules, achieving stable data transmission and precise timing alignment between different clock domains.

[0102] The GPS / BD synchronization module uses the high-precision clock signal provided by GPS to achieve system synchronization. By receiving time information from GPS / BD satellites, parsing and extracting UTC time and highly stable pulse signals, it provides an accurate reference clock to calibrate the local clock and unify the time of other modules, ensuring accurate and consistent system timing, thereby meeting high-precision time synchronization requirements.

[0103] Finally, the present invention was subjected to comparative experiments, and the experimental results are as follows. Figure 4 and Figure 5 As shown, Figure 4 Comparing the time flow between those with and without advance configuration, it can be seen that the present invention significantly reduces waiting time and improves efficiency. Figure 5 The comparison of the burst processing time after adopting the data storage module of the present invention and the burst processing time without adopting the present invention shows that the processing time of the present invention is faster and more efficient.

[0104] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0105] It should be understood that the above embodiments and descriptions only describe the principles, main features and advantages of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, and these changes and improvements all fall within the scope of protection of the present invention.

Claims

1. A satellite communication system gateway side transmission link based on DVB-RCS2, characterized in that: include: An embedded module, configured to receive superframe data and payload data including configuration information sent by the protocol layer, and upon receiving a configuration enable signal from the configuration control module, send a configuration instruction including superframe data to the configuration control module, and perform absolute time synchronization according to the time base signal of the GPS / BD synchronization module; The configuration control module is used to receive the configuration instructions of the embedded module, parse the superframe data in the configuration instructions, configure the superframe parameters in the register, and generate a configuration enable signal, a superframe enable signal and a data storage timing control signal, and send them to the embedded module, the data processing module and the data storage module respectively; The data processing module is configured to obtain payload data from the embedded module upon receiving a superframe enable signal, read superframe parameters from the configuration control module, and perform data movement, scrambling, forward check, turbo encoding, adding known symbols, data mapping, symbol modulation, and matched filtering on the payload data in accordance with the DVB-RCS2 signal processing standard based on the superframe parameters to generate a complex signal. a data storage module for storing the coded data after Turbo coding in the data processing module and, upon receiving a data storage timing control signal from the configuration control module, sequentially releasing the stored coded data to the data processing module, thereby enabling the data processing module to perform operations such as adding known symbols, data mapping, symbol modulation, and matched filtering; the data storage module includes a first memory block and a second memory block for alternately storing the coded data output by the Turbo coding unit; The transmit channelizer is used to combine narrowband sub-signals of the same or different bandwidths into a wideband signal, receive the complex signal generated by the data processing module, and synthesize the complex signal into a baseband digital signal to transmit to the data transmission module. The transmit channelizer is based on a polyphase filtering structure and adopts a time division multiplexing mechanism. It includes an IDFT unit, a complex multiplication unit, a channel filtering unit, a symbol conversion unit, an interpolation unit, and a storage and addition unit connected in sequence to achieve multi-channel data integration and spectrum allocation. The output signal of the transmit channelizer is: Where Y(n) represents the output signal of the transmit channelizer, X i (n) represents the complex data output by the data processing module after the i-th transmission channel is processed, IDFT[] represents the inverse discrete Fourier transform, K represents the number of channels, h i (n) represents the channel filter, z K-1-i represents the delay of the i-th transmission channel data; The data transmission module is used to up-convert the baseband digital signal output from the transmit channelizer, generate an upper sideband RF signal in combination with the local oscillator signal, and convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link through digital-to-analog conversion; Asynchronous clock synchronization module, used to connect embedded modules and external hardware modules using bus logic controlled by different clock domains to achieve timing alignment between different clock domains; The GPS / BD synchronization module is used to provide a unified time base reference for the entire system by receiving high-precision time signals from GPS / BD satellites.

2. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The configuration control module specifically includes: A register configuration unit is connected to the embedded module and is used to receive and parse configuration instructions sent by the embedded module, parse the configuration instructions, obtain superframe parameters including burst data length and payload waveform, and configure register space through timing control. The register space is divided into public registers and superframe registers. The public registers are configured with public data, and the superframe registers are configured with superframe parameters. Timing control unit, used to generate configuration enable signal I config (t), superframe enable signal I frame (t), data storage timing control signal h(t), configure the enable signal I config (t) is sent to the embedded module, and the superframe enable signal I is set when the read and write flag signal F of the data storage module is 1. frame (t) is sent to the data processing module. When the read / write flag signal F of the data storage module is 0 and the working status flag tready of the data processing module is 1, the data storage timing control signal h(t) is sent to the data storage module. tready=1 indicates that the back end of the data processing module is in the read state. Where M represents the superframe update time interval, S represents the time that the superframe configuration time is ahead of the superframe time, and N sym Indicates the number of symbols read from the data storage module, S sym represents the symbol rate, δ(t) represents the unit pulse sequence, and T[] represents the periodic correlation function; The signal reading unit is used to obtain the read / write flag signal F from the data storage module, read the working status flag tready from the data processing module, and send it to the timing control unit.

3. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The data processing module specifically includes: The data transfer unit obtains the payload data from the embedded module upon receiving the superframe enable signal; The scrambling unit is used to scramble the data output by the data transfer unit; A forward verification unit, used for forward verification of the data output by the scrambling unit; A turbo encoding unit, configured to perform turbo encoding on the data output by the forward check unit according to the burst data length in the superframe parameters, and output the encoded data to the data storage module after encoding; Adding a known symbol unit, used to add a preamble, a postamble and pilot data to corresponding positions of the coded data output by the data storage module according to the payload waveform data in the superframe parameters; A data mapping unit, configured to map the data output by the adding known symbol unit to corresponding points on the constellation diagram according to the payload waveform data in the superframe parameters; a symbol modulation unit, configured to modulate the data output from the data mapping unit into symbols according to the payload waveform data in the superframe parameters; The matched filtering unit filters the symbols output by the symbol modulation unit according to the entire link information.

4. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 3, characterized in that: The matched filtering unit comprises: Memory, cache depth is The symbols output by the receiving symbol modulation unit are used to After the length, all symbols are released to the raised cosine filter, L span represents the cutoff length of the matched filter; The matched filter is connected after the memory and is used to perform matched filtering on the symbols. The time domain impulse response of the matched filter is: Where g(t) is the time domain impulse response, β is the roll-off factor, T is the symbol period, and T L for The length of the cache period.

5. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The first memory block and the second memory block are both stored in burst data units, and an empty flag signal "empty" is set. When the first memory block or the second memory block stores a burst data, the empty flag signal "empty" of the memory block is "0", otherwise it is "1".

6. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 5, characterized in that: The data storage module is provided with a write selector SEL1 and a read selector SEL2, SEL1 defaults to 0, SEL2 defaults to 0, when the empty value in the first memory block is 1, SEL1 is switched to 1, SEL2 is switched to 0, thereby writing data to the first memory block and reading data from the second memory block; when the empty value in the second memory block is 1, SEL1 is switched to 0, SEL2 is switched to 1, thereby writing data to the second memory block and reading data from the first memory block; The data storage module generates a read-write flag signal F based on the empty and full flag signals of the first memory block and the second memory block, and sends it to the configuration control module. When the empty and full flag signal of the first memory block or the second memory block is empty=1, F=1, indicating a write state; otherwise, F=0, indicating a read state. When the data storage timing control signal h(t)=1 received by the data storage module, data is read from the corresponding memory block.

7. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The data transmission module includes: An up-conversion unit is used to up-convert the baseband digital signal output from the transmit channelizer and generate an upper sideband RF signal in combination with a local oscillator signal; The digital-to-analog conversion unit is used to convert the upper sideband RF signal into an analog signal that can be processed by the subsequent RF link.

8. The satellite communication system gateway side transmission link based on DVB-RCS2 according to claim 1, characterized in that: The GPS / BD synchronization module uses an adaptive product difference algorithm to perform clock convergence based on the second pulse generated by the GPS / BD receiving module.

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