AES operation flow structure and working method supporting multi-mode reuse

Abstract

The present invention discloses an AES operation flow structure and working method supporting multi-mode reuse, and belongs to the technical field of AES algorithm and chip design. The present invention solves the problem that the existing AES algorithm is difficult to support multiple working modes and cannot reasonably optimize between multiple modes. By repeatedly calling the core operation module, the XOR module and the binary Galois field multiplication operation module, it not only simplifies the AES operation logic, but also reduces the complexity of chip design, thereby reducing the chip size and saving manufacturing costs; at the same time, by reusing the same modules between different working modes, repeated operations are reduced, the data processing flow structure is optimized, and the operation efficiency is improved, so that the AES structure design has excellent performance and flexibility in various application scenarios; at the same time, the AES operation flow structure supports the working mode, meeting the different usage needs of users in various scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of AES algorithm and chip design, and specifically to an AES operation flow structure and working method supporting multi-mode multiplexing. Background Art

[0002] AES (Advanced Encryption Standard) AES is an advanced encryption standard, which is a symmetric block encryption algorithm. AES includes ECB, CBC, CFB, OFB, CTR, GCM, GMAC, CCM and other working modes. Among them, ECB is the most basic AES working mode, which groups the input plaintext block into several fixed-length blocks and encrypts them independently, and each block does not affect each other. The CBC cipher block chaining mode introduces an initialization vector, which is XORed with the plaintext for subsequent encryption, and the encrypted result is used as the initialization vector for the next round of operation. CFB and OFB encrypt the initialization vector, and the encryption result is XORed with the plaintext to obtain the ciphertext. For CFB, part of the encryption result and part of the ciphertext are combined as the initialization vector for the next round of operation. For OFB, all encryption results are used as the initialization vector for the next round of operation. The CTR counter mode generates a counter through special rules, and the counter is incremented by 1 in each round of operation and used as the initialization vector for encryption. The GCM, GMAC, CCM counter and CBC-MAC modes are extended from the CTR counter mode, and a message authentication code is generated through special operation steps to verify the integrity and authenticity of the data.

[0003] From a functional perspective, AES should be required to have enough working modes to meet various encryption scenarios that users may face; from a chip cost perspective, the redundancy of logic design should be reduced as much as possible to improve computing efficiency, reduce chip size, and save costs; in response to the demand for AES chips with multiple working modes, due to limitations such as size and design difficulty, there are currently no chips on the market that include all of the above working modes, and it is impossible to reasonably optimize the multiple modes to achieve the idea of ​​AES module structure design that saves chip size and improves computing efficiency.

[0004] Therefore, the existing needs are not met, and we propose an AES operation process structure and working method that supports multi-mode reuse. Summary of the invention

[0005] The purpose of the present invention is to provide an AES operation flow structure and working method that support multi-mode reuse. By repeatedly calling a core operation module, an XOR module, and a binary Galois Field multiplication operation module, the design not only simplifies the AES operation logic, but also reduces the complexity of chip design, reduces the chip size, and saves manufacturing costs; at the same time, since repeated operations are reduced, the operation efficiency is improved, so that the AES structure design has excellent performance and flexibility in a variety of application scenarios, solving the problems raised in the above-mentioned background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions: The AES operation flow structure supporting multi-mode reuse includes: a multi-mode AES operation flow structure, wherein the working modes of the multi-mode AES operation flow structure include: ECB electronic codebook mode, CBC cipher block chaining mode, CFB ciphertext feedback mode, OFB output feedback mode, CTR counter mode, GCM Galois / counter mode, GMAC Galois message authentication code mode, and CCM counter and CBC-MAC mode; the working mode also includes four operation modules: The core operation module is used to encrypt the input data and the input key to obtain the ciphertext output; XOR module, used to perform bitwise XOR on two input 128-bit data blocks to obtain the XOR result output; A binary Galois field operation module is used to perform multiplication operation on input data and a hash operator in the Galois field to obtain a multiplication result output; The authentication tag calculation module is used in the GCM Galois / counter mode and the GMAC Galois message authentication code mode, and reuses the XOR module and the binary Galois field operation module to calculate the authentication tag.

[0007] Furthermore, in the working mode, the core operation module is the basic module of the AES encryption and decryption operation process, and the working mode reuses the core operation module multiple times; in other modes except the ECB electronic code book mode, the XOR module is reused; the CFB ciphertext feedback mode and the OFB output feedback mode share a set of encryption structures, and only distinguish the feedback data, and the number of feedback bits of the CFB ciphertext feedback mode is set by the user; the GCM Galois / counter mode and the GMAC Galois message authentication code mode both reuse the CTR counter mode; the CCM counter and CBC-MAC mode reuse the CTR counter mode and the CBC cipher block chaining mode.

[0008] Furthermore, in the GCM Galois / counter mode, the GMAC Galois message authentication code mode, and the CCM counter and CBC-MAC mode, the operation process is divided into four stages: initialization, header, load, and final, and different stages are distinguished by stage control signals; in the GCM Galois / counter mode and the GMAC Galois message authentication code mode, the data length of the authentication message is automatically calculated in the header stage, and the data length of the plaintext is automatically calculated in the load stage, without the need for additional user input.

[0009] Furthermore, the core operation module includes: a 128-bit input data block, a 128-bit input key block and a 128-bit output data block.

[0010] Furthermore, the XOR module includes: two 128-bit input data blocks and one 128-bit output data block, and the output data block is obtained by performing bitwise XOR on the two input data blocks.

[0011] Furthermore, the binary Galois Field multiplication operation module includes: two 128-bit input data blocks and one 128-bit output data block, and outputs the operation result after multiplying the two input data blocks in the Galois Field.

[0012] Furthermore, the authentication tag calculation module includes: two input data blocks and one output data block; the internal logic is: the two input data blocks are used as two input data blocks of the XOR module, the output data block of the XOR module and the hash operator are used as two input data blocks of the binary Galois Field multiplication operation module, and the output operation result is the authentication tag.

[0013] The working method of the AES operation process supporting multi-mode multiplexing specifically includes the following steps: Based on the ECB electronic codebook mode: the original text and key are directly input into the core operation module for encryption, and the output result is the encrypted result; Based on the CBC cipher block chaining mode: the original text and the initialization vector are bitwise XORed through the XOR module, and then synchronously input into the core operation module with the key for encryption, and the ciphertext and the initialization vector for the next operation are output; Based on the CFB ciphertext feedback mode and OFB output feedback mode: the initialization vector and key are input into the core operation module for encryption, and the output result and the plaintext are bitwise XORed through the XOR module to obtain the ciphertext; Based on the CTR counter mode: the initialization vector is used as the initial value of the counter and is input into the core operation module together with the key for encryption to obtain the ciphertext; and after each operation, the counter value is increased by 1 as the counter input value for the next operation; Based on the GCM Galois / Counter Mode and the GMAC Galois Message Authentication Code Mode: two input data blocks are first input into the XOR module for bitwise XOR, and then the XOR result and the hash operator are used as the input data of the binary Galois Field multiplication module. After the multiplication operation, the intermediate value is output for further calculation of the authentication tag; wherein, in the initialization phase, the hash operator is calculated by using 128-bit all-0 data and the key through the core operation module; in the header phase, the intermediate value of the authentication tag is calculated by repeatedly iterating the authentication tag and the hash operator in the authentication tag calculation module; in the load phase, the CTR counter mode is reused to encrypt the plaintext, and the authentication tag calculation module is continued to be used to calculate the intermediate value of the authentication tag; in the final phase, the authentication tag is continued to be calculated based on the output data of the previous phase; Based on CCM counter and CBC-MAC mode: in the initialization phase, the initialization vector and key are used to generate the initial value required for encryption and calculation of the authentication tag; in the header phase, the CBC cipher block chaining mode is reused to encrypt the authentication data to obtain the intermediate value of the authentication tag; in the payload phase, the CTR counter mode is reused to encrypt the plaintext, and the CBC cipher block chaining mode is used to continue to calculate the intermediate value of the authentication tag; in the final phase, the authentication tag is continued to be calculated based on the output data of the previous phase.

[0014] Furthermore, the operation process of the core operation module includes the following steps: Byte replacement, row shift, column obfuscation, round key addition, each four steps constitute a round of operation, and the encryption operation performs ten rounds of operations in total; wherein the tenth round of operation does not include the column obfuscation step, and before the first round of operation, the input data and the input key must first be subjected to a round key addition step; the operation flow of the core operation module also includes: a key expansion step, which expands the 128 key for round key addition in each round of operation.

[0015] Furthermore, the feedback mechanisms of the CFB ciphertext feedback mode and the OFB output feedback mode are different. The CFB ciphertext feedback mode combines the core operation result and the XOR result as the initialization vector for the next operation; the OFB output feedback mode uses all core operation results as the initialization vector for the next operation.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention repeatedly calls a core operation module, an XOR module, and a binary Galois field multiplication operation module, so that the design not only simplifies the AES operation logic, but also reduces the complexity of chip design, reduces the chip size, and saves manufacturing costs; at the same time, by reusing the same modules between different working modes, repeated operations are reduced, the data processing flow structure is optimized, and the operation efficiency is improved, so that the AES structural design has excellent performance and flexibility in various application scenarios; the AES operation flow structure supports the working mode, and meets the different usage requirements of users in various scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of the ECB working mode of the present invention; Figure 2 It is a flow chart of the CBC working mode of the present invention; Figure 3 It is a flow chart of the CFB and OFB working modes of the present invention; Figure 4 It is a flow chart of the CTR working mode of the present invention; Figure 5 It is a flow chart of the working modes of the GCM Galois / Counter Mode and the GMAC Galois Message Authentication Code Mode of the present invention; Figure 6 It is a flow chart of the CFB and OFB working modes of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] In order to solve the demand for AES chips with multiple working modes in the existing technology, due to the limitations of size, design difficulty and other factors, there are currently no AES chips on the market that include all the above working modes, and it is impossible to reasonably optimize the multiple modes to achieve the idea of ​​AES module structure design that saves chip size and improves computing efficiency. Please refer to Figure 1-6 , this embodiment provides the following technical solutions: In this embodiment, for ease of description, in a specific implementation manner, the input data block of the core operation is referred to as CIN, the input key block is referred to as CKEY, and the output data block is referred to as COUT; the two input data blocks of the XOR block are referred to as XIN1 and XIN2, respectively, and the output data block is referred to as XOUT; the binary Galois Field multiplication operation module is referred to as the GF2mul module, and its two input data blocks are GFIN1 and GFIN2, respectively, and the output data block is GFOUT.

[0020] In addition, in the GCM Galois / counter mode and the GMAC Galois message authentication code mode, the XOR module and the GF2mul module need to be reused to calculate the authentication tag. The multiplexing module is called the authentication tag calculation module, which includes two input data blocks XGFIN1 and XGFIN2, and an output data block XGFOUT; its internal logic is: XGFIN1 and XGFIN2 are used as XIN1 and XIN2 of the XOR module, the XOR result XOUT and the hash operator are used as the GF2mul modules GFIN1 and GFIN2, and the operation result GFOUT is XGFOUT.

[0021] The AES operation flow structure supporting multi-mode reuse includes: a multi-mode AES operation flow structure, which supports the working mode, and the supported working modes include: ECB electronic codebook mode, CBC cipher block chaining mode, CFB ciphertext feedback mode, OFB output feedback mode, CTR counter mode, GCM Galois / counter mode, GMAC Galois message authentication code mode, and CCM counter and CBC-MAC mode; the working mode also includes four operation modules: The core operation module is used to encrypt the input data and the input key to obtain the ciphertext output; the core operation module includes: a 128-bit input data block, a 128-bit input key block and a 128-bit output data block; the input data and the input key are grouped according to a predetermined rule, and each group consists of multiple bytes of data and multiple bytes of keys; and enters a loop to sequentially execute the four-step operation process of the core operation module; it includes the following steps: byte replacement, row shift, column confusion, and round key addition; among them, byte replacement: for each byte of each group, use the key to replace it to obtain a new group of bytes; row shift: for each byte of each group, move it to a new position in the memory to obtain a new group of bytes; column confusion: for Each byte of each group is obfuscated with the key to obtain a new group of bytes; round key addition: for each byte of each group, round key addition is performed with the key to obtain a new group of bytes; every four steps are a round of operation, and the encryption operation performs ten rounds of operations to obtain the final ciphertext; wherein, the tenth round of operation does not include the column obfuscation step, and before the first round of operation, the input data and the input key must be subjected to a round key addition step; the operation process of the core operation module also includes: a key expansion step, which expands the 128 key for round key addition in each round of operation; the input data and the input key are encrypted for multiple rounds by the core operation module, thereby achieving higher information security; at the same time, avoiding potential vulnerabilities in traditional encryption methods.

[0022] The XOR module is used to perform bitwise XOR on two input 128-bit data blocks to obtain an XOR result output; the XOR module includes: two 128-bit input data blocks and one 128-bit output data block. After the two input data blocks are bitwise XORed, an output data block is obtained.

[0023] The binary Galois field operation module is used to perform multiplication operation on input data and a hash operator in the Galois field to obtain a multiplication result output; the binary Galois field multiplication operation module includes: two 128-bit input data blocks and a 128-bit output data block, and after the two input data blocks are multiplied in the Galois field, the operation result is output; specifically, the two 128-bit input data are regarded as a polynomial form with a maximum power of 128, and then a nested loop structure is used to simulate the polynomial multiplication to generate a 256-bit intermediate polynomial result, and finally the above result is modulo an irreducible polynomial operation to obtain a remainder polynomial after modulo, and the 128-bit remainder polynomial is the final multiplication result.

[0024] The authentication tag calculation module is used in the GCM Galois / counter mode and the GMAC Galois message authentication code mode, and the XOR module and the binary Galois field operation module are reused to calculate the authentication tag; the authentication tag calculation module includes: two input data blocks and an output data block; the internal logic is: the two input data blocks are used as the two input data blocks of the XOR module, the output data block of the XOR module and the hash operator are used as the two input data blocks of the binary Galois field multiplication operation module, and the output operation result is the authentication tag; specifically, firstly, the two input data blocks are used as the two input data blocks of the XOR module for XOR operation to obtain the XOR result; then the output data block of the XOR module and the hash operator are used as the two input data blocks of the binary Galois field operation module, and the Galois field multiplication operation is performed to obtain the multiplication result; finally, the multiplication result is used as the output data block and output to an authentication tag; through the above operations, the security and reliability of the authentication tag can be guaranteed, and the strength and difficulty of the authentication tag can be greatly improved, so as to ensure that it can maintain a high degree of security when facing various security threats.

[0025] Among them, in the working mode, the core operation module is the basic module of the AES encryption and decryption operation process, and the working mode reuses the core operation module multiple times; in other modes except the ECB electronic codebook mode, the XOR module is reused; the CFB ciphertext feedback mode and the OFB output feedback mode share a set of encryption structures and only distinguish the feedback data, and the number of feedback bits in the CFB ciphertext feedback mode is set by the user; the GCM Galois / counter mode and the GMAC Galois message authentication code mode both reuse the CTR counter mode; the CCM counter .... The C-MAC mode reuses the CTR counter mode and the CBC cipher block chaining mode; in the GCM Galois / Counter mode, the GMAC Galois Message Authentication Code mode, and the CCM Counter and CBC-MAC mode, the operation process is divided into four stages: initialization, header, payload, and final. Different stages are distinguished by stage control signals; in the GCM Galois / Counter mode and the GMAC Galois Message Authentication Code mode, the data length of the authentication message is automatically calculated in the header stage, and the data length of the plaintext is automatically calculated in the payload stage, without the need for additional user input.

[0026] In order to more conveniently demonstrate the operation steps of the AES operation flow structure supporting multi-mode reuse, the present invention discloses a working method of the AES operation flow supporting multi-mode reuse, which is used to demonstrate the working modes supported by the AES operation flow structure, and specifically includes the following steps: Based on the ECB electronic codebook mode: the original text and the key are directly input into the core operation module for encryption, and the output result is the encrypted result.

[0027] Embodiment 1: When continuous encryption is performed using the ECB electronic codebook mode: Based on the attached Figure 1 :The process structure of ECB electronic codebook mode is as follows Figure 1 As shown, it includes: input plaintext, input key and output ciphertext data block; Step 1: User configures AES, selects ECB electronic codebook working mode, and enters plain text and key data; Step 2: The received plaintext and key data are used as CIN and CKEY of the core operation. The COUT of the core operation module is the encryption result of the ECB electronic codebook mode.

[0028] Based on the CBC cipher block chaining mode: the original text and the initialization vector are bitwise XORed through the XOR module, and then synchronously input into the core operation module with the key for encryption, and the ciphertext and the initialization vector for the next operation are output.

[0029] Example 2: When using CBC cipher block chaining mode for continuous encryption: Based on the attached Figure 2 :The process structure of CBC cipher block chaining mode is as follows Figure 2 As shown, it includes: inputting plain text, inputting initialization vector, inputting key and outputting ciphertext data block; Step 1: User configures AES, selects CBC cipher block chaining mode, and enters plain text, initialization vector, and key data; Step 2: Input the original text and the initialization vector into XIN1 and XIN2 of the XOR module to obtain the XOR result XOUT; then input the XOUT and the key of the previous step into CIN and CKEY of the core operation module to obtain the output result COUT, which is the encryption result of the current plaintext data block; Step 3: If there are still plaintext data blocks to be encrypted, use COUT in step 2 as the initialization vector for the next operation, and repeat steps 1 and 2.

[0030] Based on the CFB ciphertext feedback mode and the OFB output feedback mode: the initialization vector and the key are input into the core operation module for encryption, and the output result is bitwise XORed with the plaintext through the XOR module to obtain the ciphertext; among them, the feedback mechanisms of the CFB ciphertext feedback mode and the OFB output feedback mode are different. The CFB ciphertext feedback mode combines the core operation result and the XOR result as the initialization vector for the next operation; the OFB output feedback mode uses all the core operation results as the initialization vector for the next operation.

[0031] Example 3: When continuous encryption is performed using the CFB ciphertext feedback mode and the OFB output feedback mode: Based on the attached Figure 3:The process structure of CFB ciphertext feedback mode and OFB output feedback mode is as follows Figure 3 As shown, it includes: inputting plain text, inputting initialization vector, inputting key and outputting ciphertext data block; Step 1: The user configures AES to select CFB ciphertext feedback mode or OFB output feedback mode, and enters plaintext, initialization vector and key data; Step 2: Input the initialization vector and key to CIN and CKEY of the core operation module respectively to obtain the XOR output result COUT; then input COUT and the plaintext of the previous step to XIN1 and XIN2 of the XOR module to obtain the XOR result XOUT, which is the encryption result of the current plaintext data block; Step 3: If there are still plaintext data blocks to be encrypted, for the CFB ciphertext feedback mode, it will take a part of COUT and XOUT and combine them into a 128-bit data block as the CIN for the next operation; for the OFB output feedback mode, it will take all of COUT as the CIN for the next operation, and repeat steps 1 and 2 for subsequent data encryption.

[0032] Based on the CTR counter mode: the initialization vector is used as the initial value of the counter and is input into the core operation module together with the key for encryption to obtain the ciphertext; and after each operation, the counter value is increased by 1 as the counter input value for the next operation.

[0033] Example 4: When using CTR counter mode for continuous encryption: Based on the attached Figure 4 :The process structure of CTR counter mode is as follows Figure 4 As shown, it includes: inputting plain text, inputting initialization vector, inputting key and outputting ciphertext data block; Step 1: The user configures AES to select the CTR counter working mode and enters the plaintext, initialization vector and key data; Step 2: Use the initialization vector as the initial value of the counter and the key as CIN and CKEY of the core operation module to obtain the operation result COUT; then input COUT and the plaintext in the previous step into XIN1 and XIN2 of the XOR module, and the XOR result XOUT is the encryption result of the current plaintext block; Step 3: If there are still plaintext data blocks to be encrypted, add 1 to the initial value of the counter in step 2 as the counter value for the next operation, and repeat steps 1 and 2.

[0034] Based on the GCM Galois / counter mode and the GMAC Galois message authentication code mode: the two input data blocks are first input into the XOR module for bitwise XOR, and then the XOR result and the hash operator are used as the input data of the binary Galois field multiplication operation module. After the multiplication operation, the intermediate value is output for continuing to calculate the authentication tag; wherein, in the initialization stage, the hash operator is calculated by using 128-bit all-0 data and the key through the core operation module; in the header stage, the intermediate value of the authentication tag is calculated by repeatedly iterating the authentication tag and the hash operator in the authentication tag calculation module; in the load stage, the CTR counter mode is reused to encrypt the plaintext, and the authentication tag calculation module is continued to be used to calculate the intermediate value of the authentication tag; in the final stage, the authentication tag is continued to be calculated based on the output data of the previous stage.

[0035] Example 5: When continuous encryption is performed using GCM Galois / Counter Mode and GMAC Galois Message Authentication Code Mode: Based on the attached Figure 5 :The process structure of GCM Galois / Counter Mode and GMAC Galois Message Authentication Code Mode is as follows Figure 5 As shown, it includes: inputting plain text, inputting initialization vector, inputting authentication message, inputting key and outputting ciphertext data block; Step 1: The user configures AES to select GCM Galois / Counter Mode or GMAC Galois Message Authentication Code Mode, and enters the initialization vector and key; Step 2: User configures AES to select the initialization phase. The present invention inputs the key and the 128-bit all-0 data block into the CKEY and CIN of the core operation module to obtain the hash operator H; Step 3: The user configures AES to select the header stage, inputs the authentication message AAD0~AADn, and then inputs AAD0 and H into GFIN1 and GFIN2 of GF2mul to obtain the result GFOUT0; then inputs GFOUT0 and AAD1 into XGFIN1 and XGFIN2 of the authentication tag calculation module to obtain the output result XGFOUT1; and then substitutes XGFOUT1 and subsequent AAD2 into the authentication tag calculation module, and repeats this operation until all AADs are processed and XGFOUTn is obtained; then the module automatically calculates the data length of AAD in the header stage, that is, LENA; Step 4. The user configures AES to select the load phase and inputs the plaintext data P1~Pm. It should be noted that: since the GMAC Galois message authentication code mode has no load phase, step 4 can be skipped and step 5 can be directly entered. For the GCM Galois / counter mode, the plaintext, initialization vector and key are used as the input of the CTR counter mode, and the calculation result of the CTR counter mode is the plaintext encryption result of the GCM Galois / counter mode. The encryption result and the output result of the previous authentication tag calculation module are used as the two inputs of the current authentication tag calculation module, and the authentication tag calculation result XGFOUT(n+m) of the load phase is obtained by repeated iterations. In the load phase, the data length of the plaintext, i.e., LENP, is automatically counted by the authentication tag calculation module. Step 5. The user configures the final stage of AES selection, combines the 64-bit LENA and the 64-bit LENP into a 128-bit data block, and inputs it into the authentication tag calculation module together with XGFOUT(n+m). The calculation result is recorded as XFGOUT. At the same time, the initial value of the counter and the key in the CTR counter mode are input into the CIN and CKEY of the core operation module to obtain COUT. Then XFGOUT and COUT are input into the XOR module to calculate XOUT, which is the authentication tag TAG of the GCM Galois / Counter mode or the GMAC Galois Message Authentication Code mode.

[0036] Based on CCM counter and CBC-MAC mode: in the initialization phase, the initialization vector and key are used to generate the initial value required for encryption and calculation of the authentication tag; in the header phase, the CBC cipher block chaining mode is reused to encrypt the authentication data to obtain the intermediate value of the authentication tag; in the payload phase, the CTR counter mode is reused to encrypt the plaintext, and the CBC cipher block chaining mode is used to continue to calculate the intermediate value of the authentication tag; in the final phase, the authentication tag is continued to be calculated based on the output data of the previous phase.

[0037] Example 6: When using CCM counter and CBC-MAC mode for continuous encryption: Based on the attached Figure 5 :The process structure of CCM counter and CBC-MAC mode is as follows Figure 6 As shown, it includes: inputting plain text, inputting initialization vector, inputting authentication message, inputting key and outputting ciphertext data block; Step 1: The user configures AES to select CCM counter and CBC-MAC mode, and enters the initialization vector and key; Step 2: The user configures AES to select the initialization phase, inputs the key and initialization vector into CKEY and CIN of the core operation module, and obtains the ciphertext block COUT0; at the same time, inputs the initialization vector into the counter generation function, Figure 6The mask is used to generate the initial value of the counter. The counter generation function meets the relevant provisions of AES-CCM in the FIPS-197 standard. Step 3: The user configures AES to select the header stage, inputs the authentication message B1~Bn, and the authentication tag calculation module uses B1~Bn, the key and COUT0 in step 2 as the input of the CBC cipher block chaining mode. The encryption result COUTn of the last round of authentication message Bn is the output result of the header stage; Step 4: The user configures AES to select the load phase, inputs the plaintext data P1~Pm, and the authentication tag calculation module uses P1~Pm, the initialization vector and the key as the input of the CTR counter mode. The calculation result of the CTR counter mode is the plaintext encryption result of GCM; then P1~Pm, the key and COUTn in step 3 are used as the input of the CBC cipher block chaining mode. The encryption result of the last round of CBC cipher block chaining mode is used as the processing result of the authentication message in the load phase, recorded as COUT(n+m); Step 5. The user configures the final stage of AES selection. The authentication tag calculation module inputs the initial value of the counter and the key in the CTR counter mode into the CIN and CKEY of the core operation module to obtain COUT. Then COUT and COUT(n+m) in step 4 are input into the XOR module. The XOR result is the authentication tag TAG of the CCM counter and CBC-MAC mode.

[0038] The beneficial effects achieved by the above content are as follows: through the above method, the core operation module, the XOR module and the binary Galois Field multiplication operation module are repeatedly called, so that the design not only simplifies the AES operation logic, but also reduces the complexity of chip design, reduces the chip size, and saves manufacturing costs; at the same time, since repeated operations are reduced, the operation efficiency is improved, so that the AES structure design has excellent performance and flexibility in various application scenarios.

[0039] Working principle: By repeatedly calling the core operation module, XOR module and binary Galois Field multiplication operation module, the AES operation process structure can support the working mode and meet the different usage requirements of users in various scenarios; at the same time, by reusing the same modules between different working modes, the AES operation logic is simplified, repeated operations are reduced, the data processing process structure is optimized, and the complexity of chip design is reduced, so that the AES structure design has excellent performance and flexibility in various application scenarios.

[0040] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0041] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. AES operation flow structure that supports multi-mode reuse, including: A multi-mode AES operation flow structure, characterized in that: the working modes of the multi-mode AES operation flow structure include: ECB electronic codebook mode, CBC cipher block chaining mode, CFB ciphertext feedback mode, OFB output feedback mode, CTR counter mode, GCM Galois / counter mode, GMAC Galois message authentication code mode and CCM counter and CBC-MAC mode; the working mode also includes four operation modules: The core operation module is used to encrypt the input data and the input key to obtain the ciphertext output; XOR module, used to perform bitwise XOR on two input 128-bit data blocks to obtain the XOR result output; A binary Galois field operation module is used to perform multiplication operation on input data and a hash operator in the Galois field to obtain a multiplication result output; The authentication tag calculation module is used in the GCM Galois / Counter mode and the GMAC Galois Message Authentication Code mode to calculate the authentication tag by reusing the XOR module and the binary Galois Field operation module.

2. The AES operation flow structure supporting multi-mode multiplexing according to claim 1, characterized in that: In the working mode, the core operation module is reused multiple times; in other modes except the ECB electronic codebook mode, the XOR module is reused; the CFB ciphertext feedback mode and the OFB output feedback mode share the encryption structure and distinguish the feedback data, and the number of feedback bits in the CFB ciphertext feedback mode is set by the user; the GCM Galois / counter mode and the GMAC Galois message authentication code mode both reuse the CTR counter mode; the CCM counter and CBC-MAC modes reuse the CTR counter mode and the CBC cipher block chaining mode.

3. The AES operation flow structure supporting multi-mode multiplexing according to claim 1, characterized in that: In the GCM Galois / counter mode, the GMAC Galois message authentication code mode and the CCM counter and CBC-MAC mode, the operation process is divided into four stages: initialization, header, load and final, and different stages are distinguished by stage control signals; in the GCM Galois / counter mode and the GMAC Galois message authentication code mode, the data length of the authentication message is automatically calculated in the header stage, and the data length of the plaintext is automatically calculated in the load stage.

4. The AES operation flow structure supporting multi-mode multiplexing according to claim 1, characterized in that: The core operation module includes: a 128-bit input data block, a 128-bit input key block and a 128-bit output data block.

5. The AES operation flow structure supporting multi-mode multiplexing according to claim 1, characterized in that: The XOR module includes: two 128-bit input data blocks and one 128-bit output data block. The output data block is obtained by performing bitwise XOR on the two input data blocks.

6. The AES operation flow structure supporting multi-mode multiplexing according to claim 1, characterized in that: The binary Galois field multiplication operation module includes: two 128-bit input data blocks and one 128-bit output data block. After multiplying the two input data blocks in the Galois field, the operation result is output.

7. The AES operation flow structure supporting multi-mode multiplexing according to claim 1, characterized in that: The authentication tag calculation module includes: two input data blocks and one output data block. The two input data blocks are used as two input data blocks of the XOR module. The output data block of the XOR module and the hash operator are used as two input data blocks of the binary Galois field multiplication operation module. The output operation result is the authentication tag.

8. A working method of an AES operation flow supporting multi-mode multiplexing, applied to the AES operation flow structure supporting multi-mode multiplexing as claimed in any one of claims 1 to 7, characterized in that: The AES operation flow structure supports the working mode, which specifically includes the following steps: Based on the ECB electronic codebook mode: the original text and key are directly input into the core operation module for encryption, and the output result is the encrypted result; Based on the CBC cipher block chaining mode: the original text and the initialization vector are bitwise XORed through the XOR module, and then synchronously input into the core operation module with the key for encryption, and the ciphertext and the initialization vector for the next operation are output; Based on the CFB ciphertext feedback mode and OFB output feedback mode: the initialization vector and key are input into the core operation module for encryption, and the output result and the plaintext are bitwise XORed through the XOR module to obtain the ciphertext; Based on the CTR counter mode: the initialization vector is used as the initial value of the counter and is input into the core operation module together with the key for encryption to obtain the ciphertext; and after each operation, the counter value is increased by 1 as the counter input value for the next operation; Based on the GCM Galois / Counter Mode and the GMAC Galois Message Authentication Code Mode: two input data blocks are first input into the XOR module for bitwise XOR, and then the XOR result and the hash operator are used as the input data of the binary Galois Field multiplication module. After the multiplication operation, the intermediate value is output for further calculation of the authentication tag; wherein, in the initialization phase, the hash operator is calculated by using 128-bit all-0 data and the key through the core operation module; in the header phase, the intermediate value of the authentication tag is calculated by repeatedly iterating the authentication tag and the hash operator in the authentication tag calculation module; in the load phase, the CTR counter mode is reused to encrypt the plaintext, and the authentication tag calculation module is continued to be used to calculate the intermediate value of the authentication tag; in the final phase, the authentication tag is continued to be calculated based on the output data of the previous phase; Based on CCM counter and CBC-MAC mode: in the initialization phase, the initialization vector and key are used to generate the initial value required for encryption and calculation of the authentication tag; in the header phase, the CBC cipher block chaining mode is reused to encrypt the authentication data to obtain the intermediate value of the authentication tag; in the payload phase, the CTR counter mode is reused to encrypt the plaintext, and the CBC cipher block chaining mode is used to continue to calculate the intermediate value of the authentication tag; in the final phase, the authentication tag is continued to be calculated based on the output data of the previous phase.

9. The working method of the AES operation process supporting multi-mode multiplexing according to claim 8, characterized in that: The operation process of the core operation module includes the following steps: Byte replacement, row shift, column obfuscation, round key addition, each four steps constitute a round of operation, and the encryption operation performs ten rounds of operations in total; wherein the tenth round of operation does not include the column obfuscation step, and before the first round of operation, the input data and the input key must first be subjected to a round key addition step; the operation flow of the core operation module also includes: a key expansion step, which expands the 128 key for round key addition in each round of operation.

10. The working method of the AES operation process supporting multi-mode multiplexing according to claim 8, characterized in that: The CFB ciphertext feedback mode combines the core operation result and the XOR result as the initialization vector for the next operation; the OFB output feedback mode uses all core operation results as the initialization vector for the next operation.

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