Loopback test method, device, system, electronic device, medium and program product

Abstract

The present invention discloses a loopback test method, device, system, electronic device, medium and program product, which relates to the field of communication technologies. The loopback test device deployed on a processor that does not support register-controlled loopback read and write at both ends of the transceiver and tests its network quality includes a data cache module and a read-write control logic module. The data cache module is connected to the segmented interface and the network communication module of the processor itself, and caches the data packets received and transmitted through the network communication module and the segmented interface. The read-write control logic module is connected to the data cache module, and according to the end position of the data packet, it can ensure that the last data packet is read and written from the data cache module when the data cache module reaches the critical storage threshold condition. The present invention can solve the problem of complex control logic in the related technology when performing MAC tests on the processor, and can efficiently and simply implement the MAC loopback test on the processor, with simple control logic and less resource occupation.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a loopback test method, device, system, electronic device, computer-readable storage medium, and computer program product. Background Art

[0002] In order to meet the high demand for the transmission rate and processing rate of electronic data, a processor integrates an Ethernet protocol stack and a Segmented (segmented interface) interface to support rates from 200G to 400G. However, the IP (Intellectual Property, intellectual property module) of the Ethernet protocol stack of such processors does not support loopback testing between the receiving end and the sending end.

[0003] Currently, in order to implement MAC (Medium Access Control, medium access control test) of a processor in related technologies, an asynchronous FIFO (First Input First Output, first in first out) is deployed at the receiving end, and a Packet (packet) FIFO is deployed at the sending end. This method has relatively complex control logic and relatively high resource utilization rate. Summary of the Invention

[0004] The present invention provides a loopback test method, device, system, electronic device, computer-readable storage medium, and computer program product, which can efficiently and simply implement MAC loopback testing of a processor, have simple control logic, and less resource occupation.

[0005] To solve the above technical problems, the present invention provides the following technical solutions:

[0006] On the one hand, the present invention provides a loopback test device, including a data cache module and a read / write control logic module; the loopback test device is deployed on a target processor to test the network quality of the target processor; the target processor includes a network communication module, a segmented interface, and a register, and the network communication module does not support data loopback reading and writing between the register and the receiving end and the sending end; wherein, the data cache module is connected to the network communication module through the segmented interface and is configured to cache data packets received and sent through the network communication module and the segmented interface; the read / write control logic module is connected to the data cache module and is configured to read and write the last data packet from the data cache module when the data cache module reaches the critical storage threshold condition according to the packet end position of the data packet.

[0007] On the other hand, the present invention provides a loopback test method, which deploys a loopback test device on a target processor, including: when the network communication module of the target processor is successfully connected to the network card, starting a data packet sending and receiving test; caching the data packets sent and received through the network communication module and the segmented interface into the data cache module of the loopback test device; sending the obtained packet end position to the read-write control logic module, so that the read-write control logic module reads and writes the last data packet from the data cache module when the data cache module reaches the critical storage threshold condition based on the packet end position.

[0008] On the other hand, the present invention provides a loopback test system, including a network card and a target processor; wherein, the network card and the target processor are respectively deployed to different servers, or the network card and the target processor are deployed in different slots of the same server; the network card and the target processor perform data communication through Ethernet; the target processor deploys the loopback test device as described above to test the communication quality between the network card and the target processor.

[0009] The present invention also provides an electronic device, including a memory and a processor, and the processor is used to implement the steps of the above loopback test method when executing the computer program stored in the memory.

[0010] The present invention also provides a computer-readable storage medium, on which a computer program is stored, and the computer program implements the steps of the above loopback test method when executed by a processor.

[0011] Finally, the present invention also provides a computer program product, including computer programs / instructions, and the computer programs / instructions implement the steps of the above loopback test method when executed by a processor.

[0012] The advantages of the technical solution provided by the present invention are as follows. Compared with the related art that requires two FIFOs, namely a common FIFO and a whole-packet buffer FIFO, only one data buffer module is needed to buffer the data stream transmitted and received through the Segmented interface. This simplifies the control logic for the target processor to perform the MAC loopback test, realizes simple and efficient data buffer control. At the same time, according to the end position of the packet, the data read and write status can be fed back to the read and write control logic module in real time, which not only further simplifies the data read and write control logic for the data buffer module, but also ensures that the last packet of data is read and written completely, effectively controlling the integrity of data reading. In addition, the entire loopback test device can be designed using RTL (Register Transfer Level), which is beneficial for later engineering maintenance and resource expansion, with less resource occupation, flexible and efficient design. In addition, the loopback test method, loopback test system, electronic device, computer-readable storage medium, and computer program product of the present invention have corresponding advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the present invention or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0014] Figure 1 It is a schematic diagram of an exemplary application scenario provided by the present invention;

[0015] Figure 2 It is another schematic diagram of an exemplary application scenario provided by the present invention;

[0016] Figure 3 It is a frame schematic diagram of the loopback test device provided by the present invention in an exemplary application scenario;

[0017] Figure 4 It is a waveform schematic diagram of the Segmented interface provided by the present invention in an exemplary application scenario;

[0018] Figure 5 It is a schematic diagram of the critical storage threshold condition provided by the present invention in an exemplary application scenario;

[0019] Figure 6 It is a schematic diagram of the read control logic circuit provided by the present invention in an exemplary application scenario;

[0020] Figure 7 It is a schematic diagram of the write control logic circuit provided by the present invention in an exemplary application scenario;

[0021] Figure 8 Schematic flowchart of a loopback test method provided by the present invention;

[0022] Figure 9 Schematic framework diagram of an electronic device provided by the present invention in an exemplary application scenario;

[0023] Figure 10 Schematic framework diagram of a loopback test system provided by the present invention in an exemplary application scenario;

[0024] Figure 11 Schematic framework diagram of a loopback test system provided by the present invention in another exemplary application scenario. Detailed implementation manners

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Methods, means, elements, and circuits well-known to those skilled in the art are not described in detail to highlight the gist of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0026] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0027] MAC loopback testing is used to test the Ethernet connectivity and network quality of the target processor. Currently, the related art performs MAC loopback testing through the following two methods. The first method is: internal packet sending, loopback through an external self-loop head, and then return for internal verification. This method not only requires self-designing various types of packet sending modules and verification modules inside the target processor, but also requires developing an adapted MAC interface for transceiver control, with high implementation difficulty and a long debugging cycle. The second method is: using an external test board or instrument to send data packets, and the external packet sending is looped back through the MAC internally and then returned to the external board or instrument for verification.

[0028] At present, for processors that integrate a fractal, configurable, and enhanced Ethernet protocol stack and support rates from 10 G to 400G, such as Altera Agilex7 (product name) series FPGAs (Field-Programmable Gate Array) and Xilinx (product name) series FPGAs, the IP modules of such processors provide an Avalon ST (Avalon Streaming Interface, high-speed data stream transmission) interface to support 10G to 100G, and support 200G to 400G through the Segmented interface. The Segmented interface is a "compressed" data stream format, where the data stream exists in the form of "segments", each segment being 8 bytes, that is, 64bit (bits). The interface bit width of the 400G IP is 1024bit, divided into 16 segments, and the interface bit width of the 200G IP is 512bit, divided into 8 segments. Since such processors do not currently support the loopback test from reception to transmission, the receiving end of the Segmented interface does not support backpressure, and the transmitting end supports backpressure but does not support packet fragmentation. The related technology designs the transceiver control logic by itself through external logic based on the above second method. Based on this transceiver control logic, an asynchronous FIFO is used at the receiving end, and a Packet FIFO is used at the transmitting end. The Packet FIFO needs to cache a complete packet of data. However, this method has relatively complex control logic, relatively high resource utilization rate, and relatively cumbersome problem location.

[0029] To solve the problems existing in the related technology, the present invention caches the data stream received and transmitted by the Segmented interface through a data cache module, and at the same time, based on the flag of the packet end position that can reflect the data read and write status, enables the read and write control logic module to perform data packet reading and writing according to the real-time feedback status.

[0030] Based on the technical solution of the present invention described above, one of the application scenarios of the embodiments of the present invention is, for example Figure 1As shown, the MAC loopback test of the target processor can be implemented through the first server 101 and the second server 102. In this application scenario, the target processor can be an acceleration card. The 200G / 400G network card is deployed on the first server 101, and the acceleration card is deployed on the second server 102. The 200G / 400G network card on the first server is connected to the acceleration card on the second server 102 through an optical fiber. The first server 101 can be configured with a data packet processing module. For example, a packet sending and self-testing environment in DPDK (Data Plane Development Kit) can be installed, such as DPDK-pktgen (the application name of DPDK). The data packet processing module is used to implement complex packet sending and verification work. The relevant DPDK parameters are configured, including but not limited to the source IP (Internet Protocol Address), destination IP address, source MAC address, destination MAC address, length, rate, etc. The data cache module and the read-write control logic module of the present invention are deployed in the acceleration card of the second server 102. The data cache module can adopt an asynchronous FIFO, for example, and the registers of the acceleration card are configured, including but not limited to clearing the count statistics, status statistics, and critical storage threshold conditions, to implement the transceiver loopback control. After the 200G / 400G network card is successfully connected to the network communication module of the acceleration card through the optical fiber, DPDK-pktgen is started for packet sending and receiving tests. After the network communication module of the acceleration card receives a data packet, after determining the start position and end position of the data packet, it is then cached in the asynchronous FIFO, and the read-write control of the asynchronous FIFO is completed under the control of the read-write control logic module to achieve the loopback read-write of the data packet.

[0031] Based on the above technical solution of the present invention, the second application scenario of the embodiments of the present invention is as Figure 2As shown, the MAC loopback test of the target processor can be implemented through a server 103. In this application scenario, the target processor can be an acceleration card, and the data cache module uses an asynchronous FIFO. The 200G / 400G network card and the acceleration card are respectively deployed in the first PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus) slot and the second PCIE slot of the server 103. The server 103 is configured with DPDK and relevant DPDK parameters are configured, such as source IP (Internet Protocol Address), destination IP address, source MAC address, destination MAC address, length, rate, etc. An asynchronous FIFO and a read / write control logic module are deployed in the acceleration card, and relevant parameters of the registers of the acceleration card are configured, such as clear count statistics, status statistics, empty threshold and full threshold of the asynchronous FIFO. After the network communication module of the 200G / 400G network card is successfully connected to the acceleration card, DPDK-pktgen is started for packet receiving and sending tests. After the network communication module of the acceleration card receives a data packet, after determining the start position and end position of the data packet, it is then cached in the asynchronous FIFO, and the read / write control of the asynchronous FIFO is completed under the control of the read / write control logic module, realizing the loopback read / write of the data packet.

[0032] It should be noted that the above application scenario is only shown for the convenience of understanding the idea and principle of the present invention, and the embodiments of the present invention are not limited in this regard. On the contrary, the embodiments of the present invention can be applied to any applicable scenario. After introducing the technical solution of the present invention, the various non-limiting embodiments of the present invention will be described in detail below in conjunction with the drawings and specific embodiments.

[0033] First, please refer to Figure 3 , Figure 3 which is a schematic structural framework diagram of the loopback test device provided in this embodiment in an exemplary embodiment. This embodiment may include the following contents:

[0034] The loopback test device is deployed on the target processor to test the connectivity and signal quality of the Ethernet hardware environment of the target processor, that is, the network quality. That is, when the target processor needs to perform a MAC loopback test, the loopback test device of the present invention can be deployed. The target processor referred to in this embodiment refers to a processor that at least includes a network communication module, a segmented interface, and registers, and its network communication module does not support register control of data loopback reading and writing between the receiving end and the sending end. For the sake of convenience of description, the processor that meets this condition is defined as the target processor. For example, the target processor can be an Altera Agilex7 series FPGA, an FPGA of the Xilinx series, and a processor with a large bandwidth and high-speed interface. The network communication module is used to process the high-speed serial interface and protocol in the target processor. For example, for the target processor being an Altera Agilex 7 series FPGA, the network communication module is F-Tile, and F-Tile is used to implement Ethernet and other high-speed communication protocols. The network communication module of this embodiment supports rates from 10G to 400G, and for 200G and 400G, its IP interface provides a Segmented interface. That is to say, the data packets sent to the network communication module of the target processor will be divided into corresponding segments according to the interface bit width and the bytes of each segment of the Segmented interface, and then cached through the Segmented interface. Among them, the bit width refers to the number of data bits that can be processed or transmitted at one time. For example, the interface bit width of 400G IP is 1024bit, divided into 16 segments, the 200G IP interface bit width is 512bit, divided into 8 segments. When the rate is 400G, the data packet will be divided into 16 segments. When the rate is 200G, the data packet will be divided into 8 segments. The register is used to store the configuration information of the target processor, including but not limited to clearing count statistics, status statistics, and critical storage threshold conditions. Among them, the critical storage threshold condition is used to represent the threshold for the data cache module to be about to be full and the threshold for it to be about to be cleared. Taking the data cache module as a FIFO as an example, the critical storage threshold condition can include the almost-empty threshold and the almost-full threshold of the asynchronous FIFO.

[0035] In this embodiment, since the network communication module of the target processor does not support register control for data loopback reading and writing between the receiving end and the sending end, in order to implement the MAC loopback test for the target processor, a loopback test device is deployed in the target processor. The loopback test device can be completely designed using RTL. For example, it can be developed using Verilog (hardware description language) or VHDL (circuit design language). As for which hardware programming language to use, it can be flexibly selected according to the actual situation, which does not affect the implementation of the present invention. The device may include a data cache module 301 and a read / write control logic module 302. The data cache module 301 is connected to the network communication module through a segmented interface, and the read / write control logic module 302 is connected to the data cache module 301. That is, the read / write control logic module is used to control the data reading and writing of the data cache module 301. The data cache module 301 will cache the data received by the network communication module through the segmented interface, and can also first cache the data packets sent by the network communication module to the data cache module 301, and then send them to the network communication module through the segmented interface. The data cache module 301 can coordinate the data transmission between modules operating at different speeds during the MAC loopback test of the target processor, prevent data loss or chaos, and can transfer data between different clock domains to ensure data synchronization and consistency.

[0036] Among them, when the loopback test device is deployed on the target processor, the network hardware environment of the target processor is configured, and a packet receiving and sending test environment for implementing complex packet sending and verification work is configured, such as installing DPDK and configuring DPDK-related parameters such as source IP, destination IP address, source MAC address, destination MAC address, length, and rate. Start DPDK for packet receiving and sending tests. After internal loopback through the network communication module of the target processor, it returns to DPDK for verification.

[0037] Among them, the internal loop control logic of the target processor is as follows: The network communication module receives the data packets sent by DPDK to the target processor, and caches these data packets into the data cache module 301 through the segmented interface. That is, the data cache module 301 is configured to cache the data packets received and sent through the network communication module and the segmented interface. For the convenience of managing and transmitting data packets, custom identifiers will be added to the data packets, such as the start position and end position of the packet. When writing the data packet into the data cache module 301, it is necessary to obtain the end position of the data packet, which can be identified by the end flag of the packet, and then send it to the read-write control logic module 302. When the read-write control logic module 302 writes the data packet into the data cache module 301, it will pay attention to the condition that the data cache module 301 reaches the critical storage threshold in real time. When writing data, it will judge whether the data cache module 301 reaches the almost full threshold, and combine the end flag of the next data packet to be written to control the writing of data, and ensure that the last packet of data is written. When reading the data packet from the data cache module 301 and sending it to DPDK through the segmented interface and the network communication module, it is also necessary to prefetch the end flag of the data packet, and then send it to the read-write control logic module 302. When the read-write control logic module 302 reads the data packet from the data cache module 301, it will pay attention to the condition that the data cache module 301 reaches the critical storage threshold in real time. When reading data, it will judge whether the data cache module 301 reaches the almost empty threshold, and combine the end flag of the next data packet to be output by the data cache module 301 to control the reading of data, and ensure that the last packet of data is read. That is to say, the read-write control logic module 302 is configured to perform real-time feedback control of the state according to the end flag of the data packet. When the data cache module 301 reaches the critical storage threshold condition, the last data packet is read and written from the data cache module 301.

[0038] To make the technical solution of the present invention clearer and more understandable to those skilled in the art, based on the above technical solution, taking the data as an example that is cut into 4 Segmented segments, Figure 4 is a waveform schematic diagram of the corresponding Segmented interface, Figure 4The first row from top to bottom represents the clock signal, that is, the clock signal. The figure shows 17 clock signals; the second row represents the ready signal indicating whether it is ready to receive data, for example, it can be represented as tx_MAC_ready, where tx represents the transmitting end Segmented interface; the third row represents the valid signal indicating whether the data is valid, for example, it can be represented as tx_MAC_valid; the fourth row represents the first Segmented segment data, for example, it can be represented as tx_MAC_data[63:0], and [63:0] indicates that the data bit width of this Segmented segment data is from bit 0 to bit 63. x represents invalid data or random numbers, sop is the start position of the data packet, and eop represents the end position of the data packet; the fifth row represents the second Segmented segment data, for example, it can be represented as tx_MAC_data[127:64], and [127:64] indicates that the data bit width of this Segmented segment data is from bit 64 to bit 127; the sixth row represents the third Segmented segment data, for example, it can be represented as tx_MAC_data[191:128], and [191:128] indicates that the data bit width of this Segmented segment data is from bit 128 to bit 191; the seventh row represents the fourth Segmented segment data, for example, it can be represented as tx_MAC_data[255:192], and [255:192] indicates that the data bit width of this Segmented segment data is from bit 192 to bit 255. Since data packets are sent and received through the Segmented interface, large data packets need to be split into blocks supported by the Segmented interface, such as 64 bytes per segment. To facilitate the management of data packets, each Segmented segment has a representation. The valid identification information corresponding to the Segmented segments into which the data packet is split at one time will generate segmented data identification information, such as it can be represented by inframe. Each bit of inframe corresponds to the valid identification information of a Segmented segment. Taking the 400G MAC as an example, the sending and receiving only support the Segmented interface, the interface bit width is 1024bit, and it is divided into 16 Segmented segments in total. Each Segmented segment is 8 bytes, a total of 64bit, inframe is 16bit, and each bit of inframe corresponds to the valid flag of each Segmented segment.Therefore, the segmented data identification information represented by lines 8 to 11. The eighth line represents the first bit of the segmented data identification information, which can be expressed as tx_MAC_inframe[0]. The ninth line represents the second bit of the segmented data identification information, which can be expressed as tx_MAC_inframe[1]. The tenth line represents the third bit of the segmented data identification information, which can be expressed as tx_MAC_inframe[2]. The eleventh line represents the fourth bit of the segmented data identification information, which can be expressed as tx_MAC_inframe[3]. Lines 12 to 15 represent how many bytes of each Segmented segment are invalid at the eop moment, which can be represented by tx_eop_empty. The twelfth line represents how many bytes of the first Segmented segment are invalid at the eop moment. For example, it can be expressed as tx_eop_empty[2:0], and [2:0] means that the 0th to 2nd bits of this Segmented segment are invalid at the eop moment. The thirteenth line represents how many bytes of the second Segmented segment are invalid at the eop moment. For example, it can be expressed as tx_eop_empty[5:3], and [5:3] means that the 3rd to 5th bits of this Segmented segment are invalid at the eop moment. The fourteenth line represents how many bytes of the third Segmented segment are invalid at the eop moment. For example, it can be expressed as tx_eop_empty[8:6], and [8:6] means that the 6th to 8th bits of this Segmented segment are invalid at the eop moment. The fifteenth line represents how many bytes of the fourth Segmented segment are invalid at the eop moment. For example, it can be expressed as tx_eop_empty[11:9], and [11:9] means that the 9th to 11th bits of this Segmented segment are invalid at the eop moment. Taking 400G MAC as an example, the send and receive only support the Segmented interface. The sending end interface supports backpressure control. After ready is pulled low, data for 1 - 8 clk (clock) can still be sent. When the adjacent bits of inframe change from 0 to 1, it indicates that the start of packet position sop appears in this Segmented; when the adjacent bits of inframe change from 1 to 0, it may not be in the same clk, indicating that the end of packet position eop appears in this Segmented. eop_empty is only valid for the corresponding Segmented segment indicated at the end of the packet, and the rest of the Segmented segments are invalid. During the data packet sending process, if the valid signal is interrupted, the corresponding data and inframe should be maintained, otherwise the integrity of the data packet will be damaged.

[0039] In the technical solution provided in this embodiment, compared with the related art which requires two FIFOs, namely a common FIFO and a whole-packet buffer FIFO, only one data buffer module 301 is needed to buffer the data stream transmitted and received through the Segmented interface. Thus, the control logic for the target processor to perform the MAC loopback test is simplified, realizing simple and efficient data buffer control. At the same time, based on the packet end position, the data read / write status can be fed back to the read / write control logic module 302 in real time, which not only further simplifies the data read / write control logic for the data buffer module 301, but also can ensure that the last packet of data is read and written completely, effectively controlling the integrity of data reading. In addition, the entire loopback test device can be designed using RTL, which is beneficial for later engineering maintenance and resource expansion, with less resource occupancy, flexible and efficient design.

[0040] It can be understood that inappropriate setting of the storage critical threshold may lead to write overflow of the last data packet or the data buffer module being read empty, resulting in packet loss. To avoid write overflow and packet loss, based on the above embodiment, the present invention also provides an implementation method that allows the critical storage threshold condition to be adjusted at any time during the MAC loopback test, which may include the following:

[0041] The read / write control logic module 302 can be connected to the register of the target processor, and the register stores the critical storage threshold condition. The register can be connected to the target peripheral interface of the target processor through a bus; during the MAC test of the target processor, the critical storage threshold condition is adjusted through the target peripheral interface. Among them, the bus can be, for example, APB (Advanced Peripheral Bus), and the target peripheral interface is a predefined external interface, which can be, for example, JTAG (Joint Test Action Group) or UART (Universal Asynchronous Receiver / Transmitter).

[0042] As can be seen from the above, through the first-level data buffer module and the variable threshold control method in this embodiment, not only the problem that the current target processor cannot perform self-loopback verification through the IP module internally is solved, but also the continuous reading and writing of the data packet cache can be ensured, avoiding write overflow and packet loss.

[0043] The above embodiments do not impose any limitations on the data caching module 301. Based on the above embodiments, the present invention also provides an implementation manner in which the data caching module 301 adopts a first-in-first-out storage structure, which can be implemented by a register or a RAM (Random Access Memory). That is, the data caching module 301 can adopt a FIFO. When the downstream module of the target processor cannot process the data output by the upstream module in time, the data caching module 301 can temporarily store the data to prevent data loss. For the problem of data transmission between different clock domains processed by the target processor, such as the transmission clock and the reception clock of the Segmented interface may have a certain phase difference or frequency difference. To avoid the complexity of design and constraints caused by cross-clock domain transmission, or in the scenario where the target processor writes data too fast and the interval is long, or in the scenario of conversion between data interfaces of different widths, such as converting from 8-bit input to 16-bit output, the data caching module 301 can adopt an asynchronous FIFO. In addition, since the present invention needs to obtain the end position of the packet, as a more convenient and effective implementation manner, the data caching module 301 adopts a FWFT (First Word Fall Through) type of FIFO. The FWFT type of FIFO stops reading or writing once when it is about to be empty or full. Thus, before the read enable is effective, the data to be output has been displayed at the output port.

[0044] Based on the above embodiments where the data caching module adopts a FIFO storage structure, the critical storage threshold conditions include the almost-full threshold and the almost-empty threshold of the first-in-first-out. Setting the almost-full threshold of the FIFO too large or the almost-empty threshold too small may cause the last data packet to be written overflow or the FIFO to be read empty, thereby causing the packet break phenomenon. Based on the above embodiments, the present invention also provides an implementation manner in which the thresholds of the FIFO are variable, which may include the following contents:

[0045] When the length of the data packet read and written from the data caching module 301 changes, the almost-full threshold and the almost-empty threshold of the register are adjusted through the target peripheral interface; wherein, the values of the almost-full threshold and the almost-empty threshold increase as the length of the data packet increases.

[0046] In this embodiment, the critical storage threshold conditions include the almost-full threshold and the almost-empty threshold of the FIFO. The almost-full threshold can be expressed as almost_full, and the almost-empty threshold can be expressed as almost_empty, such as Figure 5As shown in the figure, when the data data_cnt contained in the FIFO is greater than or equal to almost_full, the full signal becomes valid, that is, almost_full is 1, and almost_full is transmitted to the upstream module A to notify the upstream module to stop sending data to prevent FIFO transmission overflow. To avoid data loss and ensure that data does not overflow, there are still N beats of data that will be sent to the FIFO one after another. Therefore, the value of almost_full should be at least FIFO depth - M - N. To avoid data overflow, the FIFO depth can be determined according to the transmission rate, the maximum packet interval time, and the data bit width. As an efficient implementation method, when initially determining the almost full threshold, the relational expression transmission rate × maximum packet interval time / data bit width - M - N can be called for calculation. After determining the almost full threshold, for different packet lengths, to avoid discontinuous writing and write overflow of data, the empty threshold and the almost full threshold can be arbitrarily set and modified through the internal apb interface, effectively improving the loopback bandwidth for different lengths of data packets.

[0047] As can be seen from the above, in this embodiment, through the first-level FIFO and the variable threshold control method, the continuous reading and writing of packet caching are ensured, making up for the problem that the current IP internal self-loop verification cannot be carried out. The settings of the almost full threshold and the almost empty threshold of the FIFO are matched with the length of the test data packet. For different lengths of data packets, not only can the loopback test bandwidth be effectively improved, but also the frequent modification of parameters for compilation and debugging can be prevented, improving the overall efficiency, and having the advantages of flexible, simple, efficient design and low resource occupancy.

[0048] Based on the above embodiment, to avoid the situation where the FIFO is full or the FIFO is empty just when half of a data packet is written or read, based on the above embodiment, the values of the almost full threshold and the almost empty threshold are both increased by at least the length value of a data packet through the target peripheral interface. In other words, the values of the almost empty threshold and the almost full threshold of the FIFO should be set to be at least greater than the FIFO depth required for caching the current test packet length.

[0049] Furthermore, the FIFO read and write data packet counts can be performed through registers, and the FIFO empty and full flags and other statuses can be monitored in real time, which is beneficial for the system to quickly locate and debug. Once a problem occurs, it is also helpful to locate the fault in a timely manner.

[0050] As can be seen from the above, in this embodiment, the variable almost full threshold and almost empty threshold of the FIFO are set, and during the switching process of data packets of different sizes, the read and write bandwidth can be effectively improved. Taking at least the length of a data packet for the almost full threshold and the almost empty threshold can ensure that under the premise of not being able to write full and read empty, there will be no situation where the FIFO is full or the FIFO is empty just when half of a data packet is written or read, maintaining the integrity of the packet.

[0051] The above embodiments do not impose any limitations on the read-write control logic module. In order to achieve complete read data and continuous read data for the data cache module, and with simple control logic and less resource occupancy, the present invention also provides a method for implementing the read control of the read-write control logic module using logic gate circuits, which may include the following content:

[0052] The read control logic circuit of the read-write control logic module 302 is constructed based on a logic circuit. The read control logic circuit includes a read enable module, a read condition recognition module, and a read control signal generation module. That is to say, the read enable module, the read condition recognition module, and the read control signal generation module are constructed using various components of digital logic circuits and implement the functions of the corresponding modules through corresponding logical operations.

[0053] In this embodiment, the input signal of the read enable module is the data reception ready signal of the segmented interface. The data reception ready signal means that the receiving end has made preparations for data reception. Taking the basic handshake signal valid / ready as an example, the sending end sets valid to indicate that the data is valid, and the receiving end sets ready to indicate that the data can be received. When both valid / ready are high, the data is valid, such as Figure 4The second line of data shown. To indicate to the receiving end, such as a FIFO or data buffer, that it is ready to receive data from the sending end, a read enable signal can be generated. For example, in a FIFO, when rd_en (read enable) is high, the read enable signal is valid, indicating that the FIFO can be read. Usually, the enable signal and the data signal are one-to-one. Therefore, to ensure that the read enable signal is valid, that is, to ensure that the data is read out, the timing synchronization process can be performed on the data reception ready signal, and the output is a valid read enable signal. When reading data from the data cache module, it is necessary to simultaneously meet the conditions that there is data in the data cache module and a complete data can be read out. Therefore, it is necessary to identify whether this condition is met. In this embodiment, the read condition identification module is used to identify. Correspondingly, the first input signal of the read condition identification module is the critical storage threshold condition, and the second input signal is the prefetch signal of the packet end flag; when the packet end flag is detected and the empty threshold of the critical storage threshold condition is reached, it indicates that the condition for reading data from the data cache module is not met. Correspondingly, a stop read signal is output to indicate to stop the read operation. When the conditions of detecting the packet end flag and reaching the empty threshold are not met simultaneously, it indicates that the condition for reading data from the data cache module is met. Correspondingly, a valid read operation signal is output. After the read condition is met, there must be data readable in the data cache. Correspondingly, when controlling the reading of data, it is also necessary to obtain the signal indicating whether the data cache module is empty. The data non-empty signal indicates that there is data stored in the data cache module, and the data empty signal indicates that there is no data stored in the data cache module. The read control signal generation module, upon receiving the valid read operation signal, splices the valid read enable signal and the data non-empty signal of the data cache module 301 to generate a read control signal; the read control signal controls the reading of the corresponding data packet from the data cache module 301.

[0054] As can be seen from the above, in this embodiment, the read control of the data cache module is implemented through a logic circuit, which can not only ensure the complete and continuous reading of the data in the data cache module, but also has a simple control logic, less resource occupation, is conducive to later engineering maintenance and resource expansion, less resource occupation, flexible and efficient design.

[0055] Furthermore, considering the stability of data transmission, based on the above embodiments, the sender interface, i.e., the Segmented interface, supports backpressure control. In this way, the Segmented interface can dynamically adjust its transmission rate according to the processing capacity of the receiver to avoid speed mismatch problems during data transmission. Correspondingly, the read enable module further includes a plurality of flip-flops, and the total number of flip-flops is determined according to the number of clock signals allowed to be sent by the target processor when data is not accepted. For example, according to the IP manual of Altera Agilex7 series FPGA F-Tile, it supports any setting of 1-8 clks. Each flip-flop is interconnected. Among them, the input terminal of the first flip-flop inputs the data reception ready signal, and the signal is sequentially delayed through each flip-flop, and the last flip-flop outputs the read enable signal. Each flip-flop includes a CLR (clear signal) and a SET (set signal). To ensure that the read enable signal can work in coordination according to certain time requirements, synchronous RS flip-flops can be used. The synchronous RS flip-flop includes three input terminals, input terminal R, input terminal S, and input control terminal CP. Whether the triggers input to input terminal R and input terminal S are effective is controlled by the CP terminal. When the CP terminal is 1, the triggers input to input terminal R and input terminal S are effective, and at this time, the synchronous RS flip-flop is a basic RS flip-flop; when the CP terminal is 0, any trigger of input terminal R and input terminal S cannot change the output state of the flip-flop.

[0056] As can be seen from the above, the processing speeds of the transceiver ends in this embodiment match, which can ensure the stability and reliability of data transmission and determine the reliability of the MAC loopback test of the target processor.

[0057] The above embodiments do not make any limitations on the structure of the read control logic circuit. Based on the above embodiments, the present invention also gives an exemplary implementation manner, which may include the following content:

[0058] For the read enable module, according to whether the input terminal supports backpressure control, it can include two structures: In a schematic structure, the read enable module includes a first flip-flop and a first AND gate; the data reception ready signal is respectively received at the first input terminal S of the first flip-flop and the first input terminal of the first AND gate, and the first output terminal of the first flip-flop The second input terminal of the first AND gate; the first output terminal of the first AND gate outputs a valid read enable signal. In another schematic structure, the read enable module at least includes a first flip-flop, a second flip-flop, a third flip-flop, and a first AND gate; the second input terminal S of the second flip-flop receives a data reception preparation signal, and the second output terminal Q of the second flip-flop is connected to the third input terminal S of the third flip-flop for outputting a delayed signal corresponding to the data reception preparation signal; the third output terminal Q of the third flip-flop is respectively connected to the first input terminal S of the first flip-flop and the first input terminal of the first AND gate to receive the delayed signal corresponding to the data reception preparation signal; the first output terminal of the first flip-flop is connected to the second input terminal of the first AND gate, and the output signals of the first output terminal of the first AND gate and the third output terminal Q of the third flip-flop are used as the valid read enable signal.

[0059] Among them, the read condition recognition module includes a first NAND gate, and the first NAND gate includes a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal receives a signal corresponding to a critical storage threshold condition, and the fourth input terminal receives a prefetch signal of an end-of-pack flag; the second output terminal outputs a valid read operation signal or a stop read signal. The read control signal generation module includes a second AND gate, a first OR gate, a first NOT gate, and a third AND gate; the fifth input terminal of the second AND gate receives a delayed signal, the sixth input terminal receives a valid read operation signal or a stop read signal, and the third output terminal is connected to the seventh input terminal of the first OR gate; the eighth input terminal of the first OR gate receives a rising edge signal corresponding to the read enable signal, the fourth output terminal of the first OR gate is connected to the tenth input terminal of the third AND gate, the ninth input terminal of the first NOT gate receives a data empty signal of the data buffer module 301, the fifth output terminal of the first NOT gate is connected to the eleventh input terminal of the third AND gate, and the sixth output terminal of the third AND gate outputs a read control signal.

[0060] Among them, the NAND gate is used to perform a NAND operation on the input signals. Only when all the inputs are high, the output is a low level; the AND gate is used to perform an AND operation on the input signals. When all the inputs are high, the output is a high level; the NOT gate is used to perform a NOT operation on the input signals. When the input is high, the output is low; when the input is low, the output is high. The OR gate is used to perform an OR operation on the input signals. As long as one of the inputs is high, the output is high. A high level represents a valid signal, and a low level represents an invalid signal.

[0061] To make those skilled in the art more clearly understand the read control logic of the present invention, the present invention also provides an exemplary read control logic circuit, as Figure 6As shown, the sending end of this embodiment supports backpressure control. The read control logic circuit includes a first flip-flop, a second flip-flop, a third flip-flop, a first AND gate, a first NAND gate, a second AND gate, a first OR gate, a first NOT gate, and a third AND gate. Among them, each flip-flop includes a clear signal CLR and a set signal SET. Figure 6 is not shown. The second input terminal S of the second flip-flop receives the data reception ready signal, and the second output terminal Q of the second flip-flop is connected to the third input terminal S of the third flip-flop for outputting a delayed signal corresponding to the data reception ready signal; the third output terminal Q of the third flip-flop is respectively connected to the first input terminal S of the first flip-flop and the first input terminal of the first AND gate to receive the delayed signal corresponding to the data reception ready signal; the first output terminal of the first flip-flop is connected to the second input terminal of the first AND gate, and the output signals of the first output terminal of the first AND gate and the third output terminal Q of the third flip-flop serve as the valid read enable signal. The third input terminal of the first NAND gate receives the signal corresponding to the critical storage threshold condition, the fourth input terminal receives the prefetch signal of the packet end flag; the second output terminal outputs a valid read operation signal or a stop read signal. The fifth input terminal of the second AND gate receives the delayed signal, the sixth input terminal receives the valid read operation signal or the stop read signal, and the third output terminal is connected to the seventh input terminal of the first OR gate; the eighth input terminal of the first OR gate receives the rising edge signal corresponding to the read enable signal, the fourth output terminal of the first OR gate is connected to the tenth input terminal of the third AND gate, the ninth input terminal of the first NOT gate receives the data empty signal of the data buffer module, the fifth output terminal of the first NOT gate is connected to the eleventh input terminal of the third AND gate, and the sixth output terminal of the third AND gate outputs a read control signal. First, the read enable signal comes from the delayed signal of the data reception ready signal of the sending end Segmented interface. The prefetch signal of the eop signal can be understood as the output data of the FWFT FIFO. Only when the signal corresponding to the empty threshold and the prefetch signal at the packet end position are both 1, the position at A will be 0, that is, when the FIFO read operation detects eop and also reaches the empty threshold, the read operation will stop, and the rest of the states are valid, that is, the rest of the states will generate a valid read operation signal. In order to compensate for the first read enable and maintain data integrity, it is necessary to delay the delayed signal by one or more beats and perform an AND calculation with itself. B is the rising edge of the delayed signal. The rising edge signal and the delayed signal together constitute the valid read enable signal. D splices the signals at B and C, that is, performs an OR operation. As long as one of them is valid and the data is not empty, a read control signal for validly controlling the read data can be generated.

[0062] As can be seen from the above, this embodiment constructs a read control logic circuit through flip-flops and logic gate units, simply and efficiently realizing the control of read data. It can not only achieve the integrity and continuity read control of the data in the data buffer module, but also facilitate later engineering maintenance and resource expansion, with less resource occupancy.

[0063] The above embodiments do not make any limitations on the read-write control logic module. In order to achieve the write integrity and continuous writing of the data in the data cache module, and with simple control logic and less resource occupation, the present invention also provides a method for implementing the write control of the read-write control logic module by using logic gate circuits, which may include the following contents:

[0064] The write control logic circuit of the read-write control logic module 302 is constructed based on logic circuits. The write control logic circuit includes a write enable signal generation module and a write control signal generation module. That is to say, the write enable signal generation module and the write control signal generation module are constructed by using various components of digital logic circuits and realize the functions of the corresponding modules through corresponding logical operations.

[0065] Among them, the input signals of the write enable signal generation module are the critical storage threshold condition, the packet end position, and the segmented data identification information. The packet end position can be represented by a packet end identifier such as EOP. Among them, the segmented data identification information includes the valid identification of each segment after the data packet transmitted and received through the segmented interface is segmented. Since data packets are transmitted and received through the Segmented interface, it is necessary to split large data packets into blocks supported by the Segmented interface. For example, each segment is 64 bytes. To facilitate the management of data packets, each Segmented segment has a representation. The valid identification information corresponding to the Segmented segments into which the data packet is split at one time will generate segmented data identification information. For example, it can be represented by inframe. Each bit of inframe corresponds to the valid identification information of a Segmented segment. Taking the 400G MAC as an example, the transmission and reception only support the Segmented interface, the interface bit width is 1024bit, and it is divided into 16 Segmented segments in total. Each Segmented segment is 8 bytes, a total of 64bit, inframe is 16bit, and each bit of inframe corresponds to the valid flag of each Segmented segment. Before the segmented data identification information is input into the write enable signal generation module, the segmented data identification information will be logically ORed bit by bit, and the result of the OR operation will be input into the write enable signal generation module. When the conditions of not reaching the critical storage threshold condition (the full threshold), the bus corresponding to the segmented interface being in the idle state and having no valid data are not satisfied at the same time, it indicates that the write operation condition is met, and a write enable valid signal is output, and the write operation can continue. When the conditions of reaching the critical storage threshold condition (the full threshold), the bus corresponding to the segmented interface being in the idle state and having no valid data are satisfied at the same time, it indicates that the current integrity write or valid write cannot be performed, and a write enable invalid signal is output to stop the write operation. This ensures the integrity of the data packet in the critical write situation. The write control signal generation module outputs a write control signal when receiving the write enable valid signal and the data valid signal, so as to write the corresponding data packet into the data cache module 301 through the write control signal; while when receiving the write enable invalid signal or the data invalid signal, no write control signal is output. The data valid signal can be the valid signal, which is used to indicate the validity of the data output by the FIFO. When the FIFO successfully reads a data item and presents it at the output port, the valid signal will be set high.

[0066] As can be seen from the above, in this embodiment, the write control of the data cache module is implemented through a logic circuit, which can not only ensure the complete and continuous writing into the data cache module, but also has a simple write control logic, less resource occupation, and is conducive to later project maintenance and resource expansion, with less resource occupation.

[0067] The above embodiments do not impose any limitations on the structure of the write control logic circuit. Based on the above embodiments, the present invention also provides an exemplary implementation, which may include the following:

[0068] The write enable signal generation module includes a second OR gate, a second NOT gate, and a second NAND gate; the write control signal generation module includes a fourth AND gate. The second NAND gate is used to perform a NAND operation on the input signals. Only when all inputs are high, the output is at a low level; the fourth AND gate is used to perform an AND operation on the input signals. Only when all inputs are at a high level, the output is at a high level; the second NOT gate is used to perform a NOT operation on the input signals. When the input is at a high level, the output is at a low level; when the input is at a low level, the output is at a high level. The second OR gate is used to perform an OR operation on the input signals. As long as one input is at a high level, the output is at a high level. A high level represents a valid signal, and a low level represents an invalid signal.

[0069] Among them, the twelfth input terminal of the second OR gate receives the segmented data identification information, and the thirteenth input terminal receives the prefetch signal of the packet end position. The second OR gate performs an OR operation on the segmented data identification information and the prefetch signal of the packet end position, and inputs the OR result through the seventh output terminal to the fourteenth input terminal of the second NOT gate; the second NOT gate performs a NOT operation on the OR result, and inputs the NOT operation result through the eighth output terminal to the sixteenth input terminal of the second NAND gate. The fifteenth input terminal of the second NAND gate inputs the almost full threshold signal of the critical storage threshold condition, performs a NAND operation on the almost full threshold signal and the NOT operation result, and uses the generated NAND operation result as the write enable signal, which is output through the ninth output terminal; among them, the write enable signal includes a write enable valid signal and a write enable invalid signal. The seventeenth input terminal of the fourth AND gate receives the data valid signal, and the eighteenth input terminal of the fourth AND gate receives the write enable signal, and outputs the AND operation result of the data valid signal and the write enable signal through the tenth output terminal to the data buffer module 301.

[0070] To make those skilled in the art more clearly understand the write control logic of the present invention, the present invention also provides an exemplary write control logic circuit, as Figure 7As shown, the write control logic circuit includes a second OR gate, a second NOT gate, a second NAND gate, and a fourth AND gate. Among them, the twelfth input terminal of the second OR gate receives the segmented data identification information, and the thirteenth input terminal receives the prefetch signal of the packet end position. The second OR gate performs an OR operation on the segmented data identification information and the prefetch signal of the packet end position, and inputs the OR result to the fourteenth input terminal of the second NOT gate through the seventh output terminal; the second NOT gate performs a NOT operation on the OR result, and inputs the NOT operation result to the sixteenth input terminal of the second NAND gate through the eighth output terminal. The fifteenth input terminal of the second NAND gate inputs the almost full threshold signal of the critical storage threshold condition, and performs a NAND operation on the almost full threshold signal and the NOT operation result to generate a write enable valid signal or a write enable invalid signal, which is output through the ninth output terminal; the seventeenth input terminal receives the data valid signal, and the eighteenth input terminal receives the write enable signal, and the AND operation result of the data valid signal and the write enable signal is output to the data buffer module through the tenth output terminal. Based on this circuit structure, after the segmented identification information is subjected to a bitwise OR operation, it is ORed with the packet end flag or the signal corresponding to the packet end position. Only when both are 0, the position at F can be 1, which means that the current Segmented bus is in the idle state and there is no valid data. G is the NAND operation of F and the almost full signal. Only when both are 1, the position of G will be 0. At this time, the write enable of the FIFO will be invalid. In other cases, they are all 1, that is, a write enable valid signal is generated. And the case where both are 0 means that the current position of writing to the fifo has reached a write threshold and at the same time satisfies the idle state of the Segmented bus. This ensures the integrity of the data packet in the critical write situation.

[0071] As can be seen from the above, in this embodiment, the write control logic circuit is constructed by flip-flops and logic gate units, which simply and efficiently realizes the control of write data. It can not only realize a complete and continuous write data buffer module, but also facilitate later engineering maintenance and resource expansion, with less resource occupation.

[0072] Based on the above embodiment, in order to improve the MAC loopback test efficiency of the target processor, the present invention also provides an implementation method for realizing synchronous loopback tests of different types of packet lengths in multiple channels, which may include the following contents:

[0073] Determine the multi-channel selection device according to the number of channels, data bit width, control signals, and application scenarios. The number of channels is the number of channels to be selected, such as 1 out of 2, 1 out of 4, 1 out of 8, etc.; the data bit width is the data width of each channel, such as 8 bits, 16 bits, 32 bits, etc. The control signals are the number and logic of the selection signals, usually binary encoded, and the application scenario is the signal channel switching. The multi-channel selection device includes but is not limited to multiplexers (MUX), counters, and finite state machines. Among them, a multiplexer can select one output from multiple input channels according to the control signal. In an FPGA, a MUX can be implemented through a LUT (look-up table) and internal logic resources. For example, by cascading multiple LUTs and MUXs, a multi-bit multiplexer can be constructed. By designing a counter and using its output as the channel selection signal, the multi-channel selection function can be achieved. For example, in a multi-channel sampling system, a binary counter can be used, and its output is connected to the address input terminal of an analog switch (such as CD4051) to select different channels for sampling. A finite state machine can implement complex channel selection logic through programming. For example, in a multi-channel sampling system, a finite state machine can generate control signals according to timing requirements to control the switching of the channel selection module. When the used multi-channel selection device is determined, based on the input signal, selection signal, and output signal information, the input signal: 4 data inputs, which can be represented as D0, D1, D2, D3 for example. Selection signal: 2 selection signals, which can be represented as A1, A0 for example, used to select one channel. Output signal: 1 output signal, which can be represented as Y for example. Use a hardware language to perform logical design for channel selection, and a synthesis tool converts the hardware language code into the logic resources inside the target processor such as an FPGA, such as LUTs, registers, etc. When it is confirmed that the hardware language code logic of the multi-channel selection device is correctly mapped to the target processor logic resources, deploy the corresponding hardware results on the target processor. For example, the multi-channel selection device can be deployed between the read control logic circuit and the write control logic circuit of the read-write control logic circuit, that is, the multi-channel selection device is connected to both the read control logic circuit and the write control logic circuit at the same time.

[0074] For example, taking the multi-channel selection device as a MUX and the target processor as an FPGA for example, the LUT (look-up table) in the FPGA is a programmable combinational logic unit that can be used to implement any combinational logic function. For a simple MUX, such as 1 out of 2 or 1 out of 4, the LUT can be directly used to implement it. During synthesis, the FPGA tool will map the above logic to a LUT6. A LUT6 can implement combinational logic with up to 6 inputs, so a 1 out of 4 MUX can be directly implemented with a single LUT6.

[0075] As can be seen from the above, in this embodiment, by deploying a multi-channel selection device, the loopback buffer FIFO can be reused, enabling synchronous loopback testing of different types of packet lengths for multiple channels, and effectively improving the efficiency of the MAC loopback testing of the target processor.

[0076] Based on the above embodiment, when the loopback testing device in the above embodiment is deployed on the target processor and the target processor is subjected to MAC loopback testing, the present invention further provides a loopback testing method. Please refer to Figure 8 , and this embodiment may include the following contents:

[0077] S801: When the network communication module of the target processor is successfully connected to the network card, start the packet sending and receiving test.

[0078] S802: Cache the packets sent and received through the network communication module and the segmented interface into the data cache module of the loopback testing device.

[0079] S803: Send the obtained packet end position to the read-write control logic module, so that the read-write control logic module reads and writes the last packet from the data cache module when the data cache module reaches the critical storage threshold condition based on the packet end position.

[0080] As can be seen from the above, in this embodiment, aiming at the problems that the self-sending and self-receiving loopback design of the Segmented interface of the target processor is complex and the IP does not support the inner loopback test, the network card end is used as the external packet sending and receiving, and the internal self-loopback control of the target processor is used to realize the MAC loopback test of the target processor. Only one-level data cache module is used to realize the data bridging of the sending and receiving interfaces, and the read-write status can be clearly determined in real time through the packet end position, ensuring the continuity and integrity of data reading and writing.

[0081] For the description of the features in the embodiment corresponding to the loopback testing method, reference can be made to the relevant description of the embodiment corresponding to the loopback testing device, which will not be elaborated here one by one. It should be noted that there is no strict order of execution among the steps in the present invention. As long as it conforms to the logical order, these steps can be executed simultaneously or in a certain preset order. Figure 8 It is only a schematic way and does not mean that it can only be such an execution order.

[0082] Exemplarily, this embodiment further provides an exemplary determination method for the packet end position. When the network communication module receives the target packet, at least delay the target packet by one clock cycle to obtain the cached packet; determine the packet start position and packet end position of the target packet according to the segmented data identification information of the target packet and the cached packet.

[0083] Among them, the target data packet is the currently received and parsed data packet, that is, the data packet for which the start and end positions are determined. For the sake of convenience of description, it is defined as the target data packet. The segmented data identification information includes the valid identification of each segment after the data packet transmitted and received by the segmented interface is segmented. After the network communication module of the target processor receives the data packet, it can be cached for one clock cycle, and after parsing the packet start position and packet end position through the segmented data identification information, it is cached into the data cache module. Exemplarily, the packet start position and packet end position can be determined by performing a logical operation on the segmented data identification information before and after caching.

[0084] Exemplarily, when the loopback test device includes a multi-channel switching device, the present invention also provides an implementation process for realizing synchronous loopback testing of different types of packet lengths in multiple channels, which may include the following content:

[0085] When the first type of data packet and the second type of data packet are received simultaneously through the network communication module and the segmented interface; the first type of data packet is cached into the data cache module of the loopback test device through the first channel, and the first packet end position of the first type of data packet is sent to the read-write control logic module through the first channel, so that the read-write control logic module reads and writes the first type of data packet from the data cache module when the data cache module reaches the critical storage threshold condition based on the first packet end position; the second type of data packet is cached into the data cache module of the loopback test device through the second channel, and the second packet end position of the second type of data packet is sent to the read-write control logic module through the second channel, so that the read-write control logic module reads and writes the second type of data packet from the data cache module when the data cache module reaches the critical storage threshold condition based on the second packet end position.

[0086] Among them, the packet lengths of the first type of data packet and the second type of data packet are different. For the sake of distinction, the channel for processing the first type of data packet is the first channel, and the channel for processing the second type of data packet is the second channel.

[0087] As can be seen from the above, the data cache module adopted in this embodiment can be reused to realize synchronous loopback testing of different types of packet lengths in multiple channels, effectively improving the efficiency of the MAC loopback test of the target processor.

[0088] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0089] The loopback test device mentioned above is described from the perspective of functional modules. Further, the present invention also provides an electronic device, which is described from the perspective of hardware. Figure 9Schematic diagram of the electronic device provided by an embodiment of the present invention in an implementation manner. The electronic device includes a memory 901 and a processor 902. A computer program is stored in the memory 901, and the processor 902 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the loopback test method.

[0090] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned embodiments of the loopback test method when running.

[0091] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0092] An embodiment of the present invention further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the loopback test method.

[0093] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the loopback test method.

[0094] Finally, the present invention also provides a loopback test system. Please refer to Figure 10 , which may include a network card 11 and a target processor 12. When performing a loopback test on the target processor 12, the network card 11 and the target processor 12 can be deployed to different servers, or the network card 11 and the target processor 12 can also be deployed in different slots of the same server, such as different PCIE slots. The network card 11 and the target processor 12 communicate data through Ethernet. After the target processor is deployed with the loopback test device described in any of the above embodiments, the communication quality between the network card and the target processor can be tested.

[0095] To make those skilled in the art more clearly understand the implementation manner of the present invention, the present invention also gives a schematic implementation manner. As Figure 11 shown, it may include the following content:

[0096] In this embodiment, the target processor is an Agilex acceleration card, the network card is a 200G / 400G network card, the network communication module is an Agilex network card, the data cache module is an asynchronous FIFO, and the read / write control logic module includes Figure 6 the read control logic circuit shown in Figure 7 and the write control logic circuit shown in. The multi-channel selection device can be a MUX. First, insert the 200G / 400G network card and the Agilex acceleration card into two PCIe slots of the same server respectively. Install and configure the DPDK packet receiving and sending self-test environment on the server where the 200G / 400G network card is located. Connect the 200G / 400G network card to the Agilex network card directly through optical fiber, and configure the relevant parameters of DPDK and the relevant registers of the Agilex acceleration card. When the 200G / 400G network card is successfully connected to the Agilex network card, start the DPDK for packet receiving and sending tests. After receiving the data packet, the Agilex network card caches it for one cycle, parses the start position and end position of the packet through inframe and then caches it into the asynchronous FIFO, and controls the read and write of the asynchronous FIFO through the read / write control logic circuit, thereby realizing the loopback read and write of the data packet. During the MAC loopback test, the register can be connected to the peripheral ports JTAG or UART through the APB bus, and the empty threshold and full threshold of the asynchronous FIFO stored in the register can be adjusted in real time according to data packets of different lengths through the APB bus. The empty threshold and full threshold should satisfy at least a cache depth greater than the length of one data packet. In addition, the register can also monitor the internal state of the target processor in real time during the MAC loopback test. Through the MUX to multiplex the loopback cache FIFO, the synchronous loopback test of different types of packet lengths in multiple channels is realized.

[0097] As can be seen from the above, this embodiment is implemented based on the programmable logic device FPGA as the hardware, realizing the MAC loopback test based on the Segmented interface. The entire circuit is implemented in RTL, which is convenient for system maintenance and function expansion. By prefetching the end position of the data packet and feeding it back to the read control logic in advance, the read integrity of the last packet of data is effectively controlled. At the same time, during the switching process of data packets of different sizes, the empty threshold and full threshold of the asynchronous FIFO are adjusted in real time through the register to match data packets of different lengths, effectively improving the loopback test bandwidth, and can also effectively prevent the cumbersome process of frequent compilation of the engineering verification, saving the engineering debugging time and improving the MAC loopback test efficiency. Compared with the traditional method of asynchronous + synchronous two-level caching, the method of using a first-level asynchronous FIFO and variable threshold control not only saves logic resources but also simplifies the control logic. The read / write control logic ensures that there will be no packet breakage when reading and writing the FIFO. Through real-time monitoring of the internal state, abnormal problems can be quickly located.

[0098] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered as exceeding the scope of the present invention.

[0099] The above has introduced in detail a loopback test method, device, system, electronic device, computer-readable storage medium, and computer program product provided by the present invention. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A loopback test device, characterized in that: Including data cache module and read-write control logic module; The loopback test device is deployed on the target processor to test the network quality of the target processor; the target processor includes a network communication module, a segmented interface and a register, and the network communication module does not support the register to control the data loopback reading and writing between the receiving end and the sending end; The data cache module is connected to the network communication module through the segmented interface and is configured to cache data packets received and sent through the network communication module and the segmented interface; the read-write control logic module is connected to the data cache module and is configured to read and write the last data packet from the data cache module according to the packet end position of the data packet when the data cache module reaches a critical storage threshold condition; Wherein, in the case where the packet end position adopts the packet end mark, the read-write control logic module includes a read control logic circuit; the read control logic circuit includes a read enable module, a read condition identification module and a read control signal generation module; the input signal of the read enable module is the data receiving preparation signal of the segmented interface, the data receiving preparation signal is subjected to timing synchronization processing, and the output is a valid read enable signal; the first input signal of the read condition identification module is the critical storage threshold condition, and the second input signal is the pre-fetch signal of the packet end mark; when the packet end mark is detected and the empty threshold of the critical storage threshold condition is reached, a stop reading signal is output; when the conditions of detecting the packet end mark and reaching the empty threshold are not met at the same time, a read operation valid signal is output; the read control signal generation module, upon receiving the read operation valid signal, splices the valid read enable signal and the data non-empty signal of the data cache module to generate a read control signal; the read control signal controls the reading of the corresponding data packet from the data cache module.

2. The loopback test device according to claim 1, characterized in that: The read-write control logic module is connected to the register, and the register is connected to the target peripheral interface of the target processor through a bus; The register stores the critical storage threshold condition so that the critical storage threshold condition can be adjusted through the target peripheral interface during a loopback test on the target processor.

3. The loopback test device according to claim 2, characterized in that: The data cache module adopts a first-in-first-out storage structure, and the critical storage threshold conditions include a nearly full threshold and a nearly empty threshold of the first-in-first-out; When the length of the data packet read or written from the data cache module changes, adjusting the almost full threshold and the almost empty threshold of the register through the target peripheral interface; The values ​​of the almost full threshold and the almost empty threshold both increase as the length of the data packet increases.

4. The loopback test device according to claim 3, characterized in that: The values ​​of the almost full threshold and the almost empty threshold are both increased by at least a length value of a data packet through the target peripheral interface.

5. The loopback test device according to claim 1, characterized in that: The transmitting end supports back pressure control, the read enable module includes a plurality of triggers, each trigger is interconnected, the input end of the first trigger inputs the data receiving ready signal, and the signal delay processing is performed in turn through each trigger, and the last trigger outputs a read enable signal; The total number of the triggers is determined according to the number of clock signals that the target processor is allowed to send when data is not accepted.

6. The loopback test device according to claim 1, characterized in that: The read enable module includes a first trigger and a first AND gate; The data receiving ready signal is respectively received to the first input terminal S of the first trigger and the first input terminal of the first AND gate, and the first output terminal of the first trigger and a second input terminal of the first AND gate; and a first output terminal of the first AND gate outputs the valid read enable signal.

7. The loopback test device according to claim 5, characterized in that: The read enable module at least includes a first trigger, a second trigger, a third trigger and a first AND gate; The second input terminal S of the second trigger inputs a data receiving ready signal, and the second output terminal Q of the second trigger is connected to the third input terminal S of the third trigger, and is used to output a delay signal corresponding to the data receiving ready signal; The third output terminal Q of the third trigger is respectively connected to the first input terminal S of the first trigger and the first input terminal of the first AND gate to receive the delay signal corresponding to the data receiving ready signal; the first output terminal of the first trigger Connected to the second input terminal of the first AND gate, the first output terminal of the first AND gate and the output signal of the third output terminal Q of the third flip-flop are used as a valid read enable signal.

8. The loopback test device according to claim 1, characterized in that: The read condition identification module includes a first NAND gate, and the first NAND gate includes a third input terminal, a fourth input terminal, and a second output terminal; Among them, the third input terminal receives the signal corresponding to the critical storage threshold condition, the fourth input terminal receives the pre-fetch signal of the packet end mark; the second output terminal outputs the read operation valid signal or the stop reading signal.

9. The loopback test device according to claim 1, characterized in that: The read control signal generating module includes a second AND gate, a first OR gate, a first NOT gate and a third AND gate; The fifth input terminal of the second AND gate receives a delay signal, the sixth input terminal receives the read operation valid signal or the stop reading signal, and the third output terminal is connected to the seventh input terminal of the first OR gate; the eighth input terminal of the first OR gate receives a rising edge signal corresponding to the read enable signal, the fourth output terminal of the first OR gate is connected to the tenth input terminal of the third AND gate, the ninth input terminal of the first NOT gate receives a data empty signal of the data cache module, the fifth output terminal of the first NOT gate is connected to the eleventh input terminal of the third AND gate, and the sixth output terminal of the third AND gate outputs the read control signal.

10. The loopback test device according to any one of claims 1 to 4, characterized in that: The read-write control logic module includes a write control logic circuit; the write control logic circuit includes a write enable signal generation module and a write control signal generation module; Wherein, the input signal of the write enable signal generating module is the critical storage threshold condition, the packet end position and the segmented data identification information, and when the threshold value of reaching the critical storage threshold condition is not satisfied at the same time, and the bus corresponding to the segmented interface is in an idle state and has no valid data, a write enable valid signal is output; when the threshold value of reaching the critical storage threshold condition is satisfied at the same time, and the bus corresponding to the segmented interface is in an idle state and has no valid data, a write enable invalid signal is output; The write control signal generating module outputs a write control signal upon receiving the write enable valid signal and the data valid signal, so as to write a corresponding data packet in the data cache module through the write control signal; The segmented data identification information includes segmented valid identification of each segment after the data packet received and sent through the segmented interface is segmented.

11. The loopback test device according to claim 10, characterized in that: The write enable signal generating module comprises a second OR gate, a second NOT gate and a second NAND gate; The twelfth input terminal of the second OR gate receives the segment data identification information, the thirteenth input terminal receives the packet end mark, the second OR gate performs an OR operation on the segment data identification information and the packet end mark, and inputs the OR result to the fourteenth input terminal of the second NOT gate through the seventh output terminal; the second NOT gate performs a NOT operation on the OR result, and inputs the NOT operation result to the sixteenth input terminal of the second NAND gate through the eighth output terminal, the fifteenth input terminal of the second NAND gate inputs the almost full threshold signal of the critical storage threshold condition, performs an AND NOT operation on the almost full threshold signal and the NOT operation result, and uses the generated AND NOT operation result as a write enable signal, and outputs it through the ninth output terminal; The write enable signal includes a write enable valid signal and a write enable invalid signal.

12. The loopback test device according to claim 10, characterized in that: The write control signal generating module includes a fourth AND gate, and the fourth AND gate includes a seventeenth input terminal and an eighteenth input terminal; The seventeenth input terminal receives a data valid signal, the eighteenth input terminal receives a write enable signal, and outputs an AND operation result of the data valid signal and the write enable signal to the data cache module through the tenth output terminal.

13. A loopback test method, characterized in that: Deploying the loopback test device according to any one of claims 1 to 12 on a target processor comprises: When the network communication module of the target processor is successfully connected to the network card, a data packet sending and receiving test is started; Cache the data packets received and sent through the network communication module and the segmented interface in the data cache module of the loopback test device; The obtained packet end position is sent to the read / write control logic module, so that the read / write control logic module reads and writes the last data packet from the data cache module based on the packet end position when the data cache module reaches a critical storage threshold condition.

14. The loopback test method according to claim 13, characterized in that: Before sending the acquired packet end position to the read-write control logic module, the method further includes: When the network communication module receives the target data packet, the target data packet is delayed by at least one clock time to obtain a cached data packet; Determine the packet start position and packet end position of the target data packet according to the segment data identification information of the target data packet and the cached data packet; The segmented data identification information includes segmented valid identification of each segment after the data packet received and sent by the segmented interface is segmented.

15. The loopback test method according to claim 13, characterized in that: After starting the packet sending and receiving test, it also includes: When a first type of data packet and a second type of data packet are simultaneously received through the network communication module and the segmented interface; wherein the packet lengths of the first type of data packet and the second type of data packet are different; Cache the first type of data packet in the data cache module of the loopback test device through the first channel, and send the first packet end position of the first type of data packet to the read-write control logic module through the first channel, so that the read-write control logic module reads and writes the first type of data packet from the data cache module based on the first packet end position when the data cache module reaches a critical storage threshold condition; The second type of data packet is cached in the data cache module of the loopback test device through the second channel, and the second packet end position of the second type of data packet is sent to the read-write control logic module through the second channel, so that the read-write control logic module reads and writes the second type of data packet from the data cache module based on the second packet end position when the data cache module reaches a critical storage threshold condition.

16. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the loopback test method according to any one of claims 13 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the loopback test method according to any one of claims 13 to 15 are implemented.

18. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the loopback test method described in any one of claims 13 to 15 are implemented.

19. A loopback test system, characterized in that: Includes network card and target processor; The network card and the target processor are respectively deployed to different servers, or the network card and the target processor are deployed in different card slots of the same server; the network card and the target processor perform data communication via Ethernet; The target processor deploys the loopback test device according to any one of claims 1 to 12 to test the communication quality between the network card and the target processor.

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