Semiconductor devices and their fabrication methods, chips, electronic devices

Abstract

This disclosure provides a semiconductor device and its fabrication method, chip, and electronic device, relating to the field of semiconductor technology, and aims to improve the performance of semiconductor devices. The semiconductor device includes a substrate, a first capping layer, a second capping layer, a first gate, a second gate, a first electrode, and a second electrode. The first capping layer and the second capping layer are disposed on one side of the substrate and are spaced apart along a first direction, which is parallel to the substrate. At least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, with the first sublayer disposed on one side of the second sublayer along the first direction. The thickness of the first sublayer is greater than the thickness of the second sublayer. The first gate is disposed on the side of the first capping layer away from the substrate, and the second gate is disposed on the side of the second capping layer away from the substrate. The first electrode and the second electrode are disposed on opposite sides of the structure formed by the first capping layer and the second capping layer along the first direction. The above-described semiconductor device is applied in a chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a chip, and an electronic device. Background Technology

[0002] Gallium nitride (GaN) semiconductor materials are known as third-generation semiconductor materials. Compared with first-generation semiconductor materials represented by silicon, they have higher band gaps, critical breakdown field strengths, and electron saturation drift velocities. They have significant advantages in high frequency, high voltage withstand, high power, and low on-resistance, and can be used as core devices in various power conversion systems.

[0003] Gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs) are widely used in power amplifier devices in electronic devices. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, a chip, and an electronic device, which aim to improve the performance of the semiconductor device and extend its service life.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a first capping layer, a second capping layer, a first gate, a second gate, a first electrode, and a second electrode. The first capping layer and the second capping layer are disposed on one side of the substrate and are spaced apart along a first direction, which is parallel to the substrate. At least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, and along the first direction, the first sublayer is disposed on one side of the second sublayer. The thickness of the first sublayer is greater than the thickness of the second sublayer. The first gate is disposed on the side of the first capping layer away from the substrate, and the second gate is disposed on the side of the second capping layer away from the substrate. At least one of the first gate and the second gate is disposed on the side of the first sublayer away from the substrate. The first electrode and the second electrode are disposed on opposite sides of the structure formed by the first capping layer and the second capping layer along the first direction.

[0007] At least one of the first capping layer and the second capping layer in the semiconductor device provided in the above embodiments of this disclosure includes a first sublayer and a second sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer. On the one hand, when the semiconductor device is turned on, both the first sublayer and the second sublayer can inject holes toward the side closer to the substrate, which is beneficial to improving the range and efficiency of hole injection. Holes neutralize the negatively charged centers in the semiconductor device (e.g., negatively charged centers in the buffer layer of the semiconductor device), which can reduce the repulsive effect of the negatively charged centers on the two-dimensional electron gas in the semiconductor device, thereby suppressing the degradation of the dynamic on-resistance of the semiconductor device and helping to reduce the energy loss of the semiconductor device during the switching process.

[0008] On the other hand, when the first capping layer includes a first sub-layer and a second sub-layer, and the first gate located on the side of the first capping layer away from the substrate is in a forward voltage bias state, the first gate can induce more two-dimensional electron gas in the semiconductor device through the second sub-layer, which is beneficial to increase the concentration of two-dimensional electron gas in the semiconductor device, thereby reducing the on-resistance of the semiconductor device and thus reducing the energy loss of the semiconductor device in the on state.

[0009] When the second capping layer includes a first sublayer and a second sublayer, and the second gate located on the side of the second capping layer away from the substrate is in a forward voltage bias state, the second gate can induce more two-dimensional electron gas in the semiconductor device through the second sublayer, which is beneficial to increase the concentration of two-dimensional electron gas in the semiconductor device, thereby reducing the on-resistance of the semiconductor device and thus reducing the energy loss of the semiconductor device in the on state.

[0010] On the other hand, when both the first capping layer and the second capping layer are disposed on the side of the barrier layer away from the substrate within the semiconductor device, and surface traps exist in the barrier layer, the second sublayer in the first capping layer and / or the second sublayer in the second capping layer can shield the surface traps of the barrier layer, thereby weakening the trapping effect of the surface traps of the barrier layer on electrons. This can suppress the current collapse effect caused by the trapping of electrons by the surface traps of the barrier layer, which is beneficial to improving the performance of the semiconductor device.

[0011] On the other hand, when the first gate in the semiconductor device is in a reverse voltage bias state, the second gate is in a forward voltage bias state, and the voltage at the first electrode is less than the voltage at the second electrode, and the voltage between the first gate and the second electrode is less than the threshold voltage of the semiconductor device, the current in the semiconductor device is cut off. By making the first capping layer include a first sub-layer and a second sub-layer, and the thickness of the first sub-layer is greater than the thickness of the second sub-layer, that is, the thickness of the second sub-layer is smaller, when the voltage at the second electrode is larger, it is beneficial for the second sub-layer to deplete the holes inside it under the action of the electric field. This allows a hole depletion region to be formed in the area where the second sub-layer is located within the first capping layer, which is beneficial to improving the withstand voltage capability of the semiconductor device, reducing the probability of the semiconductor device being broken down, and thus improving the service life of the semiconductor device.

[0012] When the first gate in a semiconductor device is forward biased and the second gate is reverse biased, and the voltage at the first electrode is greater than the voltage at the second electrode, and the voltage between the second gate and the first electrode is less than the threshold voltage of the semiconductor device, the current in the semiconductor device is cut off. By making the second capping layer include a first sub-layer and a second sub-layer, and the thickness of the first sub-layer is greater than the thickness of the second sub-layer (i.e., the thickness of the second sub-layer is smaller), when the voltage at the first electrode is larger, it is beneficial for the second sub-layer to deplete its internal holes under the action of the electric field. This allows a hole depletion region to be formed in the area where the second sub-layer is located within the second capping layer, which helps to improve the withstand voltage capability of the semiconductor device, reduces the probability of semiconductor device breakdown, and thus helps to improve the service life of the semiconductor device.

[0013] In some embodiments, both the first cap layer and the second cap layer include a first sub-layer and a second sub-layer. The second sub-layer is closer to the gap region between the first cap layer and the second cap layer than the first sub-layer.

[0014] In some embodiments, the dimension of the first sublayer along the first direction is smaller than the dimension of the second sublayer along the first direction.

[0015] In some embodiments, the thickness of the second sublayer is uniform.

[0016] In some embodiments, at least two regions within the second sublayer have different thicknesses.

[0017] In some embodiments, the thickness of the second sublayer gradually decreases along the first direction.

[0018] In some embodiments, the first cap layer includes a first sub-layer and a second sub-layer, wherein within the first cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is less than the thickness of the second sub-layer on the side farther from the first sub-layer. And / or, the second cap layer includes a first sub-layer and a second sub-layer, wherein within the second cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is less than the thickness of the second sub-layer on the side farther from the first sub-layer.

[0019] In some embodiments, the first cap layer includes a first sub-layer and a second sub-layer, wherein within the first cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is greater than the thickness of the second sub-layer on the side farther from the first sub-layer. And / or, the second cap layer includes a first sub-layer and a second sub-layer, wherein within the second cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is greater than the thickness of the second sub-layer on the side farther from the first sub-layer.

[0020] In some embodiments, the surface of the second sublayer away from the substrate is arranged in a stepped manner.

[0021] In some embodiments, the surface of the second sublayer away from the substrate is sloped.

[0022] In some embodiments, at least one of the first cap layer and the second cap layer further includes a third sublayer. The third sublayer is located on the side of the first sublayer away from the second sublayer.

[0023] On the other hand, a method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes the following steps:

[0024] A first capping layer and a second capping layer are formed on one side of a substrate. The first capping layer and the second capping layer are spaced apart along a first direction, which is parallel to the substrate. At least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, with the first sublayer disposed on one side of the second sublayer along the first direction. The thickness of the first sublayer is greater than the thickness of the second sublayer.

[0025] A first electrode and a second electrode are formed. The first electrode and the second electrode are disposed on opposite sides of the structure composed of the first cap layer and the second cap layer along a first direction.

[0026] A first gate is formed on the side of the first capping layer away from the substrate, and a second gate is formed on the side of the second capping layer away from the substrate. At least one of the first gate and the second gate is disposed on the side of the first sublayer away from the substrate.

[0027] In some embodiments, forming a first capping layer and a second capping layer on one side of the substrate includes the following steps:

[0028] An initial capping layer is formed on one side of the substrate.

[0029] A portion of the initial capping layer is thinned to form a transition capping layer.

[0030] Remove the transition cap layer in a certain area to form the first cap layer and the second cap layer respectively.

[0031] In another aspect, a chip is provided. The chip includes a semiconductor device as described in any of the above embodiments.

[0032] In another aspect, an electronic device is provided. The electronic device includes a circuit board and a chip as described in the above embodiment. The chip and the circuit board are electrically connected.

[0033] It is understood that the beneficial effects of the semiconductor device fabrication method, chip and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below.

[0035] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments;

[0036] Figure 2 This is a cross-sectional schematic diagram of a chip according to some embodiments;

[0037] Figure 3 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 1 ;

[0038] Figure 4A A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 2 ;

[0039] Figure 4B A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 3 ;

[0040] Figure 5A A schematic cross-sectional view of a semiconductor device according to some embodiments;

[0041] Figure 5B Fifthly, a cross-sectional schematic diagram of a semiconductor device according to some embodiments;

[0042] Figure 6 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 6 ;

[0043] Figure 7 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 7 ;

[0044] Figure 8 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 8 ;

[0045] Figure 9 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 9 ;

[0046] Figure 10 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 10 ;

[0047] Figure 11 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 10 one;

[0048] Figure 12 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 10 two;

[0049] Figure 13 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 10 three;

[0050] Figure 14 A schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 10 Four;

[0051] Figure 15 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments;

[0052] Figure 16 for Figure 15 The flowchart of the semiconductor device fabrication method shows the structure of the semiconductor device corresponding to step S1. Figure 1 ;

[0053] Figure 17 for Figure 15 The flowchart of the semiconductor device fabrication method shows the structure of the semiconductor device corresponding to step S1. Figure 2 ;

[0054] Figure 18 for Figure 15 The schematic diagram of the semiconductor device corresponding to step S2 in the flowchart of the semiconductor device fabrication method;

[0055] Figure 19 for Figure 15 The flowchart of the semiconductor device fabrication method is shown in the schematic diagram of the semiconductor device corresponding to step S3. Detailed Implementation

[0056] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0057] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0058] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0059] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0060] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0061] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] The words “exemplarily” or “for example” used herein are used to indicate examples, illustrations, or explanations. Any embodiment or design described as “exemplarily” or “for example” in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of words such as “exemplarily” or “for example” is intended to present the relevant concepts in a specific manner.

[0063] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0064] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0065] For ease of description below, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0066] like Figure 1 As shown, this application provides an electronic device 1000. The electronic device 1000 may include power supply devices (e.g., power adapters), communication devices (e.g., satellite communication devices, wireless television receivers), radar devices (e.g., millimeter-wave radar, weather radar), radio navigation devices (e.g., GPS receivers), and other devices. This application does not impose any special limitations on the specific form of the electronic device 1000.

[0067] In some embodiments, please continue reading Figure 1 The electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0068] For example, the circuit board 200 within the electronic device 1000 may include at least one of a printed circuit board (PCB) and an on-chip integrated circuit (On-Chip IC).

[0069] For example, a circuit board 200 within an electronic device 1000 may include multiple conductive layers. The multiple conductive layers within the circuit board 200 may be separated from each other by dielectric layers.

[0070] The chip 100 described above will be explained in detail below.

[0071] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic cross-sectional view of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10.

[0072] For example, chip 100 may include a processor chip. For instance, the processor chip may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or it may be any conventional processor.

[0073] The semiconductor device 10 described above will be described in detail below.

[0074] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may include a substrate 1.

[0075] For example, the material of the substrate 1 within the semiconductor device 10 may include one or more (two or more) of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, and diamond.

[0076] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may further include a nucleation layer 5. The nucleation layer 5 may be disposed on one side of the substrate 1.

[0077] For example, the material of the nucleation layer 5 within the semiconductor device 10 may include one or more of aluminum nitride (AlN), GaN, and aluminum gallium nitride (AlGaN).

[0078] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may also include a buffer layer 2. The buffer layer 2 may be disposed on one side of the substrate 1.

[0079] For example, the material of the buffer layer 2 within the semiconductor device 10 may include a variety of nitride Al components. x Iny Ga (1-x-y) N, one or more (greater than or equal to two) of (0≤x,y≤1).

[0080] For example, the material of the buffer layer 2 within the semiconductor device 10 may include GaN.

[0081] When the material of the buffer layer 2 within the semiconductor device 10 includes GaN, the material of the buffer layer 2 may be doped with carbon (C). That is, the material of the buffer layer 2 may include carbon-doped GaN.

[0082] The carbon doping concentration in the material of buffer layer 2 can be greater than or equal to 1e19cm. -3 And less than or equal to 1e20 cm -3 .

[0083] For example, the material of the buffer layer 2 within the semiconductor device 10 may include a superlattice structure composed of one or more of AlN, GaN, and AlGaN.

[0084] For example, the buffer layer 2 within the semiconductor device 10 can be formed by processes such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or physical vapor deposition (PVD).

[0085] For example, please continue reading Figure 2 In the case where the semiconductor device 10 includes a nucleation layer 5, the buffer layer 2 may be disposed on the side of the nucleation layer 5 away from the substrate 1.

[0086] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may also include a channel layer 3. The channel layer 3 may be disposed on one side of the substrate 1.

[0087] For example, please continue reading Figure 2 In the case where the semiconductor device 10 includes a buffer layer 2, the channel layer 3 in the semiconductor device 10 may be disposed on the side of the buffer layer 2 away from the substrate 1.

[0088] For example, the material of the channel layer 3 within the semiconductor device 10 may include GaN.

[0089] For example, the channel layer 3 in the semiconductor device 10 can be formed by processes such as metal-organic chemical vapor deposition, molecular beam epitaxy, or physical vapor deposition.

[0090] In some embodiments, please continue to refer to Figure 2 , the semiconductor device 10 may further include a barrier layer 4. The barrier layer 4 may be disposed on one side of the substrate 1 within the semiconductor device 10.

[0091] Exemplarily, the material of the barrier layer 4 within the semiconductor device 10 may include nitrides Al of various different components x In y Ga (1-x-y) N, one or more of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0092] Exemplarily, the barrier layer 4 within the semiconductor device 10 may be formed by processes such as metalorganic chemical vapor deposition process, molecular beam epitaxy process or physical vapor deposition process.

[0093] Exemplarily, please continue to refer to Figure 2 , the barrier layer 4 within the semiconductor device 10 may be disposed on the side of the channel layer 3 away from the substrate 1. That is, the channel layer 3 may be disposed between the barrier layer 4 and the substrate 1.

[0094] When the barrier layer 4 within the semiconductor device 10 is disposed on the side of the channel layer 3 away from the substrate 1, and the band gap of the material of the barrier layer 4 (for example, AlGaN) is greater than the band gap of the material of the channel layer 3 (for example, GaN), due to the different electron affinities and work functions of the materials of the barrier layer 4 and the channel layer 3, a heterojunction structure will be formed at the connection interface between the barrier layer 4 and the channel layer 3. This heterojunction structure will cause the energy band structure of the channel layer 3 to bend, and then a potential well will be formed in the channel layer 3. In order to balance the charge distribution at the connection interface between the barrier layer 4 and the channel layer 3, the electrons in the barrier layer 4 will transfer to the potential well in the channel layer 3. The potential well in the channel layer 3 can restrict the electrons, making the electrons can only move freely in the direction parallel to the connection interface between the barrier layer 4 and the channel layer 3, thereby inducing the formation of a two-dimensional electron gas (2DEG) near the connection interface between the barrier layer 4 and the channel layer 3, which is beneficial to improving the electron mobility and enhancing the performance of the semiconductor device 10.

[0095] The above-mentioned band gap refers to: in a solid, the electrons' energy cannot take continuous values, but form some discontinuous energy bands, and the energy difference between the conduction band and the valence band is the band gap. Specifically, for a bound electron to become a free electron or a hole, it must obtain enough energy to jump from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0096] For example, please continue reading Figure 2 When a two-dimensional electron gas is formed within the semiconductor device 10, the semiconductor device 10 can be used to form a HEMT.

[0097] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may further include a first capping layer 61 and a second capping layer 62. The first capping layer 61 and the second capping layer 62 are disposed on one side of the substrate 1 and are spaced apart along a first direction X, which is parallel to the substrate 1.

[0098] For example, please continue reading Figure 2 The first capping layer 61 and the second capping layer 62 can both be disposed on the side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1.

[0099] By including a first capping layer 61 and a second capping layer 62 in the semiconductor device 10, and both the first capping layer 61 and the second capping layer 62 being disposed on the side of the barrier layer 4 away from the substrate 1, on the one hand, the two-dimensional electron gas near the connection interface between the barrier layer 4 and the channel layer 3 can be modulated by utilizing the band difference between the first capping layer 61 and the barrier layer 4, and the band difference between the second capping layer 62 and the barrier layer 4. This is beneficial for depleting the two-dimensional electron gas below the first capping layer 61 and the second capping layer 62, thereby enabling the semiconductor device 10 to achieve an enhancement mode.

[0100] On the other hand, due to the depletion effect of the first capping layer 61 and the second capping layer 62 on the two-dimensional electron gas located below the first capping layer 61 and the second capping layer 62 in the semiconductor device 10, the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to improving the threshold voltage of the semiconductor device 10.

[0101] For example, the materials of the first capping layer 61 and the second capping layer 62 in the semiconductor device 10 may both include P-type doped semiconductor materials.

[0102] For example, the materials of the first capping layer 61 and the second capping layer 62 can both include p-type gallium nitride (p-GaN).

[0103] P-type gallium nitride (p-GaN) can be formed by doping GaN materials with elements such as magnesium (Mg). The doping concentration of elements such as magnesium (Mg) in GaN materials can be greater than or equal to 1e19cm. -3 .

[0104] When doping elements such as magnesium (Mg) into GaN materials to form p-type gallium nitride (p-GaN), processes such as gas-phase doping or ion implantation can be used.

[0105] During the formation of the first capping layer 61 and the second capping layer 62 within the semiconductor device 10, a P-type material (e.g., Mg) is incorporated as an impurity into the semiconductor material (e.g., GaN), enabling the first capping layer 61 and the second capping layer 62 to provide hole carriers, thereby adjusting the conductivity of the first capping layer 61 and the second capping layer 62.

[0106] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may further include a first gate G1 and a second gate G2. The first gate G1 may be disposed on the side of the first capping layer 61 away from the substrate 1, and the second gate G2 may be disposed on the side of the second capping layer 62 away from the substrate 1.

[0107] The first gate G1 and the second gate G2 in the semiconductor device 10 are key electrodes for controlling the conductivity of the semiconductor device 10. The first gate G1 and the second gate G2 do not directly participate in the conduction of current, but control the carrier concentration in the channel layer 3 in the semiconductor device 10 through the electric field effect, thereby controlling the current in the semiconductor device 10.

[0108] For example, please continue reading Figure 2 The first gate G1 in the semiconductor device 10 can form an ohmic contact with the first capping layer 61. That is, the first gate G1 in the semiconductor device 10 can form a low-resistance, linear electrical contact with the first capping layer 61, which is beneficial to reducing the contact resistance between the first gate G1 and the first capping layer 61, thereby improving the current transmission efficiency and enhancing the performance of the semiconductor device 10.

[0109] Please continue reading. Figure 2 The second gate G2 within the semiconductor device 10 can form an ohmic contact with the second capping layer 62. That is, the second gate G2 within the semiconductor device 10 can form a low-resistance, linear electrical contact with the second capping layer 62, which helps to reduce the contact resistance between the second gate G2 and the second capping layer 62, thereby improving current transmission efficiency and enhancing the performance of the semiconductor device 10.

[0110] For example, the materials of the first gate G1 and the second gate G2 in the semiconductor device 10 may each include one or more conductive materials such as palladium (Pd), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), titanium (Ti), and titanium nitride (TiN).

[0111] In some embodiments, please continue reading Figure 2 The semiconductor device 10 may further include a first electrode J1 and a second electrode J2. The first electrode J1 and the second electrode J2 are disposed along a first direction X on opposite sides of the structure formed by the first capping layer 61 and the second capping layer 62.

[0112] For example, please continue reading Figure 2 When a two-dimensional electron gas is formed inside the semiconductor device 10, both the first electrode J1 and the second electrode J2 inside the semiconductor device 10 can form ohmic contact with the two-dimensional electron gas. This can reduce the contact resistance between the first electrode J1 and the two-dimensional electron gas, as well as the contact resistance between the second electrode J2 and the two-dimensional electron gas. This can form a low-impedance current path between the first electrode J1, the second electrode J2 and the two-dimensional electron gas inside the semiconductor device 10, allowing the current to flow smoothly and improving the performance of the semiconductor device 10.

[0113] For example, the materials of the first electrode J1 and the second electrode J2 in the semiconductor device 10 may each include one or more conductive materials such as titanium (Ti), aluminum (Al), gold (Au), silicon (Si) and titanium nitride (TiN).

[0114] Please continue reading. Figure 2 and combined Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B All figures are cross-sectional schematic diagrams of a semiconductor device 10 according to some embodiments. When the semiconductor device 10 includes a first electrode J1, a second electrode J2, a first gate G1, and a second gate G2, the operating principle of the semiconductor device 10 is as follows:

[0115] Please continue reading. Figure 2 When both the first gate G1 and the second gate G2 in the semiconductor device 10 are in a reverse voltage bias state, the semiconductor device 10 is in a turned-off state.

[0116] Please continue reading. Figure 3When both the first gate G1 and the second gate G2 in the semiconductor device 10 are in a forward voltage bias state, the semiconductor device 10 is in the turn-on state. Current within the semiconductor device 10 can flow from the first electrode J1 to the second electrode J2, or vice versa.

[0117] Please continue reading. Figure 4A Within the semiconductor device 10, the first gate G1 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is... J1 The voltage V at the second electrode J2 is greater than J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 The threshold voltage V of semiconductor device 10 is greater than TH In this case, the first gate G1 is reverse-biased and the current in the semiconductor device 10 flows from the first electrode J1 to the second electrode J2.

[0118] Please continue reading. Figure 4B Within the semiconductor device 10, the first gate G1 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is... J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 Less than the threshold voltage V of semiconductor device 10 TH In this case, the current in the semiconductor device 10 is cut off, and the semiconductor device 10 is in the off state.

[0119] Please continue reading. Figure 5A Within the semiconductor device 10, the first gate G1 is in a forward-biased state, the second gate G2 is in a reverse-biased state, and the voltage V at the first electrode J1 is... J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the second gate G2 and the first electrode J1 G2J1 The threshold voltage V of semiconductor device 10 is greater than TH In this case, the second gate G2 is reverse-biased and the current in the semiconductor device 10 flows from the second electrode J2 to the first electrode J1.

[0120] Please continue reading. Figure 5B Within the semiconductor device 10, the first gate G1 is in a forward-biased state, the second gate G2 is in a reverse-biased state, and the voltage V at the first electrode J1 is... J1 The voltage V at the second electrode J2 is greater than J2The voltage V between the second gate G2 and the first electrode J1 G2J1 Less than the threshold voltage V of semiconductor device 10 TH In this case, the current in the semiconductor device 10 is cut off, and the semiconductor device 10 is in the off state.

[0121] Please continue reading. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B By including a first electrode J1, a second electrode J2, a first gate G1, and a second gate G2 in the semiconductor device 10, and allowing the same conductive channel for current to flow from the first electrode J1 to the second electrode J2 or from the second electrode J2 to the first electrode J1 in the semiconductor device 10, it is beneficial to optimize the current transmission path in the semiconductor device 10, reduce the space occupied in the semiconductor device 10, and thus improve the space utilization rate in the semiconductor device 10, thereby promoting the miniaturization of the semiconductor device 10.

[0122] The structure of the first cap layer 61 and the second cap layer 62 described above will be explained in detail below.

[0123] In some embodiments, please continue reading Figure 2 and combined Figure 6 , Figure 7 , Figure 8 and Figure 9 , Figure 6 , Figure 7 , Figure 8 and Figure 9 All are schematic cross-sectional views of a semiconductor device 10 according to some embodiments. At least one of the first capping layer 61 and the second capping layer 62 may include a first sublayer 611 and a second sublayer 612. Along a first direction X (i.e., the arrangement direction of the first electrode J1 and the second electrode J2 within the semiconductor device 10), the first sublayer 611 is disposed on one side of the second sublayer 612. The thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612.

[0124] It should be noted that the thickness h611 of the first sublayer 611 mentioned above refers to the dimension of the first sublayer 611 along the third direction Z (i.e., the thickness direction of the substrate 1). The thickness h612 of the second sublayer 612 mentioned above refers to the dimension of the second sublayer 612 along the third direction Z. The following descriptions of the thickness h611 of the first sublayer 611 and the thickness h612 of the second sublayer 612 will also follow this explanation and will not be repeated.

[0125] By including at least one of the first capping layer 61 and the second capping layer 62 within the semiconductor device 10 as a first sublayer 611 and a second sublayer 612, and wherein the thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612, on the one hand, when the semiconductor device 10 is turned on, both the first sublayer 611 and the second sublayer 612 can inject holes toward the side closer to the substrate 1, which is beneficial to improving the range and efficiency of hole injection. Holes neutralize the negative charge centers within the semiconductor device 10 (e.g., the negative charge centers in the buffer layer 2 within the semiconductor device 10), which can reduce the repulsive effect of the negative charge centers on the two-dimensional electron gas within the semiconductor device 10, thereby suppressing the degradation of the dynamic on-resistance of the semiconductor device 10 and helping to reduce the energy loss of the semiconductor device 10 during the switching process.

[0126] On the other hand, when the first capping layer 61 includes a first sub-layer 611 and a second sub-layer 612, and the first gate G1 located on the side of the first capping layer 61 away from the substrate 1 is in a forward voltage bias state, the first gate G1 can induce more two-dimensional electron gas in the semiconductor device 10 through the second sub-layer 612, which is beneficial to increase the concentration of two-dimensional electron gas in the semiconductor device 10, thereby reducing the on-resistance of the semiconductor device 10 and thus reducing the energy loss of the semiconductor device 10 in the on state.

[0127] When the second capping layer 62 includes a first sub-layer 611 and a second sub-layer 612, and the second gate G2 located on the side of the second capping layer 62 away from the substrate 1 is in a forward voltage bias state, the second gate G2 can induce more two-dimensional electron gas in the semiconductor device 10 through the second sub-layer 612, which is beneficial to increase the concentration of two-dimensional electron gas in the semiconductor device 10, thereby reducing the on-resistance of the semiconductor device 10 and thus reducing the energy loss of the semiconductor device 10 in the turn-on state.

[0128] On the other hand, when both the first capping layer 61 and the second capping layer 62 are disposed on the side of the barrier layer 4 away from the substrate 1 within the semiconductor device 10, and when the barrier layer 4 has surface traps, the second sub-layer 612 in the first capping layer 61 and / or the second sub-layer 612 in the second capping layer 62 can shield the surface traps of the barrier layer 4, thereby weakening the trapping effect of the surface traps of the barrier layer 4 on electrons. This can suppress the current collapse effect caused by the trapping of electrons by the surface traps of the barrier layer 4, which is beneficial to improving the performance of the semiconductor device 10.

[0129] On the other hand, when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is...J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 Less than the threshold voltage V of semiconductor device 10 TH When the current in the semiconductor device 10 is cut off, the first capping layer 61 includes a first sub-layer 611 and a second sub-layer 612, and the thickness h611 of the first sub-layer 611 is greater than the thickness h612 of the second sub-layer 612, that is, the thickness h612 of the second sub-layer 612 is smaller. When the voltage V at the second electrode J2 is... J2 When the voltage is large, it is beneficial for the second sub-layer 612 to deplete the holes inside it under the action of the electric field, thereby forming a hole depletion region in the area where the second sub-layer 612 is located within the first capping layer 61. This is beneficial to improving the withstand voltage capability of the semiconductor device 10, reducing the probability of the semiconductor device 10 being broken down, and thus improving the service life of the semiconductor device 10.

[0130] When the first gate G1 in the semiconductor device 10 is in a forward bias state, the second gate G2 is in a reverse bias state, and the voltage V at the first electrode J1 is... J1 The voltage V at the second electrode J2 is greater than J2 The voltage V between the second gate G2 and the first electrode J1 G2J1 Less than the threshold voltage V of semiconductor device 10 TH When the current in the semiconductor device 10 is cut off, the second capping layer 62 includes a first sub-layer 611 and a second sub-layer 612, and the thickness h611 of the first sub-layer 611 is greater than the thickness h612 of the second sub-layer 612, that is, the thickness h612 of the second sub-layer 612 is smaller. When the voltage V at the first electrode J1 is... J1 When the voltage is large, it is beneficial for the second sub-layer 612 to deplete the holes inside it under the action of the electric field, thereby forming a hole depletion region in the area where the second sub-layer 612 is located within the second capping layer 62. This is beneficial to improving the withstand voltage capability of the semiconductor device 10, reducing the probability of the semiconductor device 10 being broken down, and thus improving the service life of the semiconductor device 10.

[0131] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The thickness h611 of the first sublayer 611 can be greater than or equal to 30nm and less than or equal to 100nm.

[0132] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The thickness h611 of the first sublayer 611 can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

[0133] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The thickness h612 of the second sublayer 612 can be greater than or equal to 10 nm and less than or equal to 90 nm.

[0134] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The thickness h612 of the second sublayer 612 can be 10nm, 15nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm or 90nm, etc.

[0135] For example, one of the first cap layer 61 and the second cap layer 62 may include a first sublayer 611 and a second sublayer 612.

[0136] For example, the first capping layer 61 may include a first sublayer 611 and a second sublayer 612, and the second capping layer 62 may be a film structure with uniform thickness.

[0137] For example, the first capping layer 61 can be a film structure with uniform thickness, and the second capping layer 62 can include a first sublayer 611 and a second sublayer 612.

[0138] Alternatively, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 Both the first capping layer 61 and the second capping layer 62 may include a first sublayer 611 and a second sublayer 612.

[0139] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 When at least one of the first capping layer 61 and the second capping layer 62 includes the first sublayer 611 and the second sublayer 612, at least one of the first gate G1 and the second gate G2 may be disposed on the side of the first sublayer 611 away from the substrate 1.

[0140] For details, please continue reading Figure 2 , Figure 6, Figure 7 , Figure 8 and Figure 9 When the first capping layer 61 includes a first sublayer 611, the first gate G1 can be disposed on the side of the first sublayer 611 in the first capping layer 61 away from the substrate 1.

[0141] Please continue reading. Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 When the second capping layer 62 includes the first sublayer 611, the second gate G2 can be disposed on the side of the first sublayer 611 in the second capping layer 62 away from the substrate 1.

[0142] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 When both the first cap layer 61 and the second cap layer 62 include a first sub-layer 611 and a second sub-layer 612, the second sub-layer 612 may be closer to the interval region Q between the first cap layer 61 and the second cap layer 62 than the first sub-layer 611.

[0143] by Figure 2 Taking the semiconductor device 10 shown as an example, and combining it with Figure 4B and Figure 5B When the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is... J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 Less than the threshold voltage V of semiconductor device 10 TH When the current in semiconductor device 10 is cut off, semiconductor device 10 is in the off state. When the voltage V at the second electrode J2 is... J2 When the voltage is large, the two-dimensional electron gas below the gap region Q between the first capping layer 61 and the second capping layer 62 is depleted under the influence of the electric field, thus forming a two-dimensional electron gas depletion region below the gap region Q between the first capping layer 61 and the second capping layer 62. When both the first capping layer 61 and the second capping layer 62 include a first sub-layer 611 and a second sub-layer 612, and the thickness h611 of the first sub-layer 611 is greater than the thickness h612 of the second sub-layer 612, since the thickness h612 of the second sub-layer 612 is smaller, when the voltage V at the second electrode J2... J2When the voltage is large, it is beneficial for the second sub-layer 612 within the first capping layer 61 to deplete its internal holes under the influence of the electric field, thereby forming a hole depletion region in the area where the second sub-layer 612 is located within the first capping layer 61. By making the second sub-layer 612 closer to the gap region Q between the first capping layer 61 and the second capping layer 62 compared to the first sub-layer 611, the gap region Q between the first capping layer 61 and the second capping layer 62 is adjacent to the second sub-layer 612, thereby making the voltage V at the second electrode J2... J2 When the voltage withstand region within the semiconductor device 10 is large, it includes a two-dimensional electron depletion region formed below the spacer region Q and a hole depletion region formed in the region where the second sub-layer 612 is located within the first capping layer 61. This results in the voltage withstand region within the semiconductor device 10 having a dimension Lm along the first direction X that is the sum of the dimensions L612 of the second sub-layer 612 within the first capping layer 61 along the first direction X and the dimension L1 of the spacer region Q along the first direction X. In other words, a larger dimension Lm of the voltage withstand region within the semiconductor device 10 along the first direction X is beneficial for further improving the voltage withstand capability of the semiconductor device 10, further reducing the probability of the semiconductor device 10 being broken down, and thus further improving the service life of the semiconductor device 10.

[0144] When the first gate G1 in the semiconductor device 10 is in a forward bias state, the second gate G2 is in a reverse bias state, and the voltage V at the first electrode J1 is... J1 The voltage V at the second electrode J2 is greater than J2 The voltage V between the second gate G2 and the first electrode J1 G2J1 Less than the threshold voltage V of semiconductor device 10 TH When the current in semiconductor device 10 is cut off, semiconductor device 10 is in the off state. When the voltage V at the first electrode J1... J1 When the voltage is large, the two-dimensional electron gas below the gap region Q between the first capping layer 61 and the second capping layer 62 is depleted under the influence of the electric field, thus forming a two-dimensional electron gas depletion region below the gap region Q between the first capping layer 61 and the second capping layer 62. When both the first capping layer 61 and the second capping layer 62 include a first sub-layer 611 and a second sub-layer 612, and the thickness h611 of the first sub-layer 611 is greater than the thickness h612 of the second sub-layer 612, since the thickness h612 of the second sub-layer 612 is smaller, when the voltage V at the first electrode J1... J1When the voltage is large, it is beneficial for the second sub-layer 612 within the second capping layer 62 to deplete its internal holes under the influence of the electric field, thereby forming a hole depletion region in the area where the second sub-layer 612 is located within the second capping layer 62. By making the second sub-layer 612 closer to the gap region Q between the first capping layer 61 and the second capping layer 62 compared to the first sub-layer 611, the gap region Q between the first capping layer 61 and the second capping layer 62 is adjacent to the second sub-layer 612, thereby making the voltage V at the first electrode J1... J1 When the voltage-resistant region within the semiconductor device 10 is large, it includes a two-dimensional electron depletion region formed below the spacer region Q and a hole depletion region formed in the region where the second sub-layer 612 within the second capping layer 62 is located. This results in the voltage-resistant region within the semiconductor device 10 having a dimension Lm along the first direction X that is the sum of the dimensions L612 of the second sub-layer 612 within the second capping layer 62 along the first direction X and the dimension L1 of the spacer region Q along the first direction X. In other words, a larger dimension Lm of the voltage-resistant region within the semiconductor device 10 along the first direction X is beneficial for further improving the voltage resistance of the semiconductor device 10, further reducing the probability of the semiconductor device 10 being broken down, and thus further improving the lifespan of the semiconductor device 10.

[0145] Please continue reading. Figure 2 The dimension L612 of the second sub-layer 612 within the first cap layer 61 along the first direction X can be equal to the dimension L612 of the second sub-layer 612 within the second cap layer 62 along the first direction X.

[0146] Please continue reading. Figure 4B and Figure 5B When the dimension L612 of the second sub-layer 612 within the first capping layer 61 along the first direction X is equal to the dimension L612 of the second sub-layer 612 within the second capping layer 62 along the first direction X, and when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is... J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 Less than the threshold voltage V of semiconductor device 10 TH When the voltage-resistant region within the semiconductor device 10 has a dimension Lm along the first direction X equal to the voltage of the first gate G1 within the semiconductor device 10 being in a forward voltage bias state, the second gate G2 being in a reverse voltage bias state, and the voltage V at the first electrode J1 being equal to the voltage of the second gate G2 being in a reverse voltage bias state, the voltage of the second gate G1 being in a reverse voltage bias state is V. J1 The voltage V at the second electrode J2 is greater than J2 The voltage V between the second gate G2 and the first electrode J1 G2J1 Less than the threshold voltage V of semiconductor device 10TH At that time, the voltage-resistant region within the semiconductor device 10 has a dimension Lm along the first direction X. That is, in Figure 4B The breakdown voltage capability of the semiconductor device 10 in the shown state, and in Figure 5B The semiconductor devices 10 in the shown states have approximately equal withstand voltage capabilities.

[0147] Alternatively, please continue reading Figure 2 The dimension L612 of the second sub-layer 612 within the first cap layer 61 along the first direction X can be larger than the dimension L612 of the second sub-layer 612 within the second cap layer 62 along the first direction X.

[0148] Please continue reading. Figure 4B and Figure 5B When the dimension L612 of the second sub-layer 612 within the first capping layer 61 along the first direction X is greater than the dimension L612 of the second sub-layer 612 within the second capping layer 62 along the first direction X, and the first gate G1 within the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is... J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 Less than the threshold voltage V of semiconductor device 10 TH When the size Lm of the withstand voltage region in the semiconductor device 10 along the first direction X is greater than a certain value, and when the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V at the first electrode J1 is greater than a certain value. J1 The voltage V at the second electrode J2 is greater than J2 The voltage V between the second gate G2 and the first electrode J1 G2J1 Less than the threshold voltage V of semiconductor device 10 TH At that time, the voltage-resistant region within the semiconductor device 10 has a dimension Lm along the first direction X. That is, in Figure 4B The breakdown voltage of the semiconductor device 10 in the shown state is greater than that in... Figure 5B The withstand voltage capability of the semiconductor device 10 in the shown state.

[0149] Alternatively, please continue reading Figure 2 The dimension L612 of the second sub-layer 612 within the first cap layer 61 along the first direction X can be smaller than the dimension L612 of the second sub-layer 612 within the second cap layer 62 along the first direction X.

[0150] Please continue reading. Figure 4B and Figure 5BWhen the dimension L612 of the second sub-layer 612 within the first capping layer 61 along the first direction X is smaller than the dimension L612 of the second sub-layer 612 within the second capping layer 62 along the first direction X, and when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is... J1 Less than the voltage V at the second electrode J2 J2 The voltage V between the first gate G1 and the second electrode J2 G1J2 Less than the threshold voltage V of semiconductor device 10 TH When the size Lm of the withstand voltage region in the semiconductor device 10 along the first direction X is less than 1, and when the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V at the first electrode J1 is 1, the voltage is 1,000V. J1 The voltage V at the second electrode J2 is greater than J2 The voltage V between the second gate G2 and the first electrode J1 G2J1 Less than the threshold voltage V of semiconductor device 10 TH At that time, the voltage-resistant region within the semiconductor device 10 has a dimension Lm along the first direction X. That is, in Figure 4B The breakdown voltage of the semiconductor device 10 in the shown state is less than that in... Figure 5B The withstand voltage capability of the semiconductor device 10 in the shown state.

[0151] For example, please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 9 The dimension L611 of the first sublayer 611 along the first direction X can be smaller than the dimension L612 of the second sublayer 612 along the first direction X.

[0152] In some embodiments, please continue reading Figure 2 The thickness h612 of the second sublayer 612 is uniform.

[0153] The uniformity of the thickness h612 of the second sub-layer 612 refers to the fact that the difference between the thickness h612 of any two regions within the second sub-layer 612 is within a preset threshold range. The threshold range is a relatively small numerical range; for example, the threshold range can be the range of process precision required to form the second sub-layer 612 with uniform thickness h612.

[0154] When the thickness h612 of the second sublayer 612 is uniform, the difference between the thickness h612 of any two regions within the second sublayer 612 can be 0-2nm.

[0155] For example, when the thickness h612 of the second sublayer 612 is uniform, the difference between the thickness h612 of any two regions within the second sublayer 612 can be 0, 0.3 nm, 0.6 nm, 0.9 nm, 1.2 nm, 1.5 nm, 1.8 nm, or 2 nm, etc.

[0156] In other embodiments, please continue to refer to Figure 6 , Figure 7 , Figure 8 and Figure 9 The thickness h612 of at least two regions within the second sublayer 612 is different.

[0157] For example, please continue reading Figure 6 , Figure 7 , Figure 8 and Figure 9 Along the first direction X, the thickness h612 of the second sublayer 612 can be gradually reduced.

[0158] By gradually reducing the thickness h612 of the second sublayer 612 along the first direction X, it is beneficial to optimize the electric field distribution within the semiconductor device 10, thereby improving the performance of the semiconductor device 10.

[0159] For example, please continue reading Figure 6 and Figure 8 In the case where the first cap layer 61 includes a first sub-layer 611 and a second sub-layer 612, the thickness h612 of the second sub-layer 612 on the side closer to the first sub-layer 611 within the first cap layer 61 can be greater than the thickness h612 of the second sub-layer 612 on the side farther away from the first sub-layer 611.

[0160] And / or, in the case where the second cap layer 62 includes a first sub-layer 611 and a second sub-layer 612, the thickness h612 of the second sub-layer 612 on the side closer to the first sub-layer 611 within the second cap layer 62 may be greater than the thickness h612 of the second sub-layer 612 on the side farther from the first sub-layer 611.

[0161] For example, please continue reading Figure 7 and Figure 9 In the case where the first cap layer 61 includes a first sub-layer 611 and a second sub-layer 612, the thickness h612 of the second sub-layer 612 on the side closer to the first sub-layer 611 within the first cap layer 61 can be less than the thickness h612 of the second sub-layer 612 on the side farther from the first sub-layer 611.

[0162] And / or, in the case where the second cap layer 62 includes a first sub-layer 611 and a second sub-layer 612, the thickness h612 of the second sub-layer 612 on the side closer to the first sub-layer 611 within the second cap layer 62 may be less than the thickness h612 of the second sub-layer 612 on the side farther from the first sub-layer 611.

[0163] When the first capping layer 61 includes a first sub-layer 611 and a second sub-layer 612, within the first capping layer 61, by making the thickness h612 of the side of the second sub-layer 612 close to the first sub-layer 611 smaller than the thickness h612 of the side of the second sub-layer 612 away from the first sub-layer 611, that is, the thickness h612 of the side of the second sub-layer 612 close to the first gate G1 is smaller, it is beneficial to improve the depletion rate of the charge stored in the second sub-layer 612, which in turn is beneficial to the semiconductor device 10 to switch states quickly and reliably under high voltage.

[0164] When the second capping layer 62 includes a first sub-layer 611 and a second sub-layer 612, within the second capping layer 62, by making the thickness h612 of the side of the second sub-layer 612 close to the first sub-layer 611 smaller than the thickness h612 of the side of the second sub-layer 612 away from the first sub-layer 611, that is, by making the thickness h612 of the second sub-layer 612 close to the second gate G2 smaller, it is beneficial to improve the depletion rate of the charge stored in the second sub-layer 612, which in turn is beneficial to the semiconductor device 10 to switch states quickly and reliably under high voltage.

[0165] For example, please continue reading Figure 6 and Figure 7 As the thickness h612 of the second sublayer 612 gradually decreases along the first direction X, the surface of the second sublayer 612 away from the substrate 1 can be arranged in a stepped manner.

[0166] Alternatively, please continue reading Figure 8 and Figure 9 As the thickness h612 of the second sublayer 612 gradually decreases along the first direction X, the surface of the second sublayer 612 away from the substrate 1 can be set in an inclined plane.

[0167] In some embodiments, such as Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 As shown, Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14All are schematic cross-sectional views of a semiconductor device 10 according to some embodiments. At least one of the first capping layer 61 and the second capping layer 62 in the semiconductor device 10 further includes a third sublayer 613. The third sublayer 613 may be located on the side of the first sublayer 611 away from the second sublayer 612.

[0168] The following provides a detailed description of the fabrication method of the semiconductor device 10.

[0169] In some embodiments, such as Figure 15 As shown, Figure 15 These are flowcharts illustrating methods for fabricating the semiconductor device 10 according to some embodiments. It should be noted that... Figure 15 The method for fabricating the semiconductor device 10 shown is not exclusive and can also be used in other ways. Figure 15 Other steps are performed before, after, or between any step in the fabrication method of the semiconductor device 10 shown. The fabrication method of the semiconductor device 10 includes steps S1 to S3.

[0170] S1: As Figure 16 As shown, Figure 16 for Figure 15 The flowchart of the method for fabricating semiconductor device 10 shows a schematic diagram of the semiconductor device 10 corresponding to step S1. A first capping layer 61 and a second capping layer 62 are formed on one side of substrate 1. The first capping layer 61 and the second capping layer 62 are spaced apart along a first direction X, which is parallel to substrate 1. At least one of the first capping layer 61 and the second capping layer 62 includes a first sublayer 611 and a second sublayer 612. Along the first direction X, the first sublayer 611 is disposed on one side of the second sublayer 612. The thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612.

[0171] For example, please continue reading Figure 15 Step S1 (i.e., forming a first capping layer 61 and a second capping layer 62 on one side of the substrate 1) in the method for fabricating semiconductor device 10 may include steps S11-S13.

[0172] S11: As Figure 17 As shown, Figure 17 for Figure 15 The flowchart of the method for fabricating semiconductor device 10 shows a schematic diagram of the structure of semiconductor device 10 corresponding to step S1. An initial capping layer 61a is formed on one side of substrate 1.

[0173] S12: Please continue reading Figure 17 A portion of the initial capping layer 61a is thinned to form a transition capping layer 61b.

[0174] S13: Please continue reading Figure 17Remove a portion of the transition cap layer 61b to form a first cap layer 61 and a second cap layer 62.

[0175] S2: As Figure 18 As shown, Figure 18 for Figure 15 The flowchart of the method for fabricating semiconductor device 10 shows a schematic diagram of the structure of semiconductor device 10 corresponding to step S2. A first electrode J1 and a second electrode J2 are formed. The first electrode J1 and the second electrode J2 are disposed on opposite sides of the structure composed of the first capping layer 61 and the second capping layer 62 along the first direction X.

[0176] S3: As Figure 19 As shown, Figure 19 for Figure 15 The flowchart of the method for fabricating semiconductor device 10 shows a schematic diagram of the structure of semiconductor device 10 corresponding to step S3. A first gate G1 is formed on the side of the first capping layer 61 away from the substrate 1, and a second gate G2 is formed on the side of the second capping layer 62 away from the substrate 1. At least one of the first gate G1 and the second gate G2 is disposed on the side of the first sublayer 611 away from the substrate 1.

[0177] For example, please continue reading Figure 19 When the first capping layer 61 includes a first sublayer 611, the first gate G1 can be disposed on the side of the first sublayer 611 in the first capping layer 61 away from the substrate 1.

[0178] Please continue reading. Figure 19 When the second capping layer 62 includes the first sublayer 611, the second gate G2 can be disposed on the side of the first sublayer 611 in the second capping layer 62 away from the substrate 1.

[0179] It should be noted that, Figure 16 , Figure 17 , Figure 18 and Figure 19 The structural diagrams of the semiconductor device 10 corresponding to each step in the fabrication method of the semiconductor device 10 shown are for illustrative purposes only. Figure 9 The semiconductor device 10 shown is illustrated by way of example, forming Figure 2 , Figure 6 , Figure 7 , Figure 8 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 The semiconductor device 10 can also follow the above steps, and will not be repeated here.

[0180] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first capping layer and a second capping layer are disposed on one side of the substrate and spaced apart along a first direction; the first direction is parallel to the substrate; at least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, the first sublayer being disposed on one side of the second sublayer along the first direction; the thickness of the first sublayer is greater than the thickness of the second sublayer. A first gate and a second gate, wherein the first gate is disposed on the side of the first capping layer away from the substrate, and the second gate is disposed on the side of the second capping layer away from the substrate; at least one of the first gate and the second gate is disposed on the side of the first sublayer away from the substrate; The first electrode and the second electrode are disposed on opposite sides of the structure composed of the first capping layer and the second capping layer along the first direction; Wherein, the first cap layer includes a first sub-layer and a second sub-layer; within the first cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is less than the thickness of the second sub-layer on the side farther from the first sub-layer; and / or, The second cap layer includes the first sub-layer and the second sub-layer; within the second cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is less than the thickness of the second sub-layer on the side farther from the first sub-layer.

2. The semiconductor device according to claim 1, characterized in that, Both the first cap layer and the second cap layer include the first sub-layer and the second sub-layer; The second sublayer is closer to the gap between the first capping layer and the second capping layer than the first sublayer.

3. The semiconductor device according to claim 1, characterized in that, The dimension of the first sublayer along the first direction is smaller than the dimension of the second sublayer along the first direction.

4. The semiconductor device according to claim 1, characterized in that, Along the first direction, the thickness of the second sublayer gradually decreases.

5. The semiconductor device according to claim 4, characterized in that, The surface of the second sublayer away from the substrate is arranged in a stepped manner.

6. The semiconductor device according to claim 4, characterized in that, The surface of the second sublayer away from the substrate is sloped.

7. The semiconductor device according to any one of claims 1-3, characterized in that, At least one of the first cap layer and the second cap layer further includes a third sublayer located on the side of the first sublayer away from the second sublayer.

8. A method for fabricating a semiconductor device, characterized in that, include: A first capping layer and a second capping layer are formed on one side of a substrate; the first capping layer and the second capping layer are spaced apart along a first direction, which is parallel to the substrate; at least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, and along the first direction, the first sublayer is disposed on one side of the second sublayer; the thickness of the first sublayer is greater than the thickness of the second sublayer. A first electrode and a second electrode are formed; the first electrode and the second electrode are disposed on opposite sides of the structure composed of the first capping layer and the second capping layer along the first direction; A first gate is formed on the side of the first capping layer away from the substrate, and a second gate is formed on the side of the second capping layer away from the substrate; at least one of the first gate and the second gate is disposed on the side of the first sublayer away from the substrate; Wherein, the first cap layer includes a first sub-layer and a second sub-layer; within the first cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is less than the thickness of the second sub-layer on the side farther from the first sub-layer; and / or, The second cap layer includes the first sub-layer and the second sub-layer; within the second cap layer, the thickness of the second sub-layer on the side closer to the first sub-layer is less than the thickness of the second sub-layer on the side farther from the first sub-layer.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The formation of a first capping layer and a second capping layer on one side of the substrate includes: An initial capping layer is formed on one side of the substrate; A portion of the initial capping layer is thinned to form a transition capping layer; The transition cap layer in a certain area is removed to form a first cap layer and a second cap layer, respectively.

10. A chip, characterized in that, Includes the semiconductor device as described in any one of claims 1-7.

11. An electronic device, characterized in that, include: Circuit board; The chip as described in claim 10, wherein the chip and the circuit board are electrically connected.

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