Active depletion device based on potential clamping bias coupling and manufacturing method

Abstract

The invention provides an active depletion device based on potential clamping bias coupling and a manufacturing method thereof. The active depletion device comprises a first conductive type substrate, a second conductive type drift region, a resistive polysilicon field plate, an MIS array, a first conductive type well region, a second conductive type well region and a heavily doped region, the control gate polycrystalline silicon electrode, the field oxide layer and the interlayer dielectric are located on the surface of the device. According to the structure, through the combination of the resistive field plate and the MIS array, the MIS array is combined with the resistive field plate, and the MIS array is clamped by using uniform potential distribution on the resistive field plate and bias coupling between the resistive field plate and the MIS array, so that the potential distribution of the MIS array is further optimized, and more excellent device performance and wider design space are brought.

Description

Technical Field

[0001] The invention belongs to the field of power semiconductors, and mainly proposes an active depletion device based on potential clamp bias coupling and a manufacturing method thereof. Background Art

[0002] Lateral power semiconductor devices are widely used in new energy vehicles, photovoltaic power generation and other aspects due to their high input impedance, fast switching speed, low loss, and easy integration with other devices. In order to achieve the optimal index in the design, it is generally required that the drift region of the device can be completely depleted when the withstand voltage is applied. Therefore, passive depletion technologies such as RESURF and super junction depletion through PN junction and active depletion technologies that modulate the internal electric field through MIS array are developed. However, the former relies on strict charge balance and has problems such as small process tolerance; the latter has a certain gap between the capacitive coupling between MIS arrays and the ideal conditions, and is affected by the undepleted area below, and the potential distribution is not uniform enough. In view of this problem, the present invention proposes a new device structure, which combines the MIS array with a resistive field plate, and clamps the MIS array by utilizing the uniform potential distribution on the resistive field plate and the bias coupling between the resistive field plate and the MIS array, thereby changing the global coupling between the electrode and the MIS array to the local coupling between the field plate and the MIS array, thereby further optimizing the potential distribution of the MIS array, and thus bringing better device performance and a wider design space. Summary of the invention

[0003] In view of the problems existing in the background technology, the present invention proposes an active depletion device and a manufacturing method based on potential clamping bias coupling, which clamps the MIS array in the drift region through a resistive field plate, introduces a uniform potential distribution into the drift region of the device, ensures that the drift region can be completely depleted when withstand voltage and has a uniform electric field distribution in the body, and greatly improves the doping concentration of the drift region and the overall process tolerance of the device while ensuring the withstand voltage capability of the device.

[0004] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0005] An active depletion device based on potential clamp bias coupling and a manufacturing process, comprising:

[0006] A first conductive type substrate 11, a second conductive type drift region 21, a first conductive type well region 12 and a second conductive type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, an equipotential ring metal 53, a source metal 54, a gate metal 55, a drain metal 56, a second conductive type source contact region 23, a second conductive type drain contact region 24, and a first conductive type body contact region 13;

[0007] The second conductive type drift region 21 is located above the first conductive type substrate 11, the first conductive type well region 12 is located on the left side of the second conductive type drift region 21, and the second conductive type well region 22 is located on the right side of the second conductive type drift region 21. The second conductive type drain contact region 24 is located in the second conductive type well region 22 and is connected to the drain metal 56 above; the second conductive type source contact region 23 and the first conductive type body contact region 13 are located in the first conductive type well region 12 and are connected to the source metal 54 above. The gate oxide layer 33 is located above the first conductive type well region 12, and the left end of the gate oxide layer 33 is in contact with the second conductive type source contact region 23 and the right end is in contact with the second conductive type drift region 21; the field oxide layer 31 is located on the upper surface of the second conductive type drift region 21 between the left gate oxide layer 33 and the right second conductive type drain contact region 24. The control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and partially extends to the upper surface of the field oxide layer 31, and the resistive field plate polysilicon 42 is spirally coiled on the upper surface of the field oxide layer 31, with the head end extending to the upper surface of the second conductive type drain contact region 24 and connected to the drain metal 56, and the tail end is connected to the control gate polysilicon 41.

[0008] The trench dielectric layer 32 and the drift region metal electrode 51 form a MIS array, which is distributed in the entire second conductive type drift region 21, wherein the drift region metal electrode 51 in the cell region is connected to the equipotential ring metal 53 and the gate metal 55 evenly spaced above through the contact hole metal 52, and the drift region metal electrode 51 in the terminal region is floating; the horizontal direction from the device source region to the drain region is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction, and the MIS array is staggered in the z direction.

[0009] As a preferred embodiment, the first conductive type drift region 21 is formed by epitaxy or implantation.

[0010] As a preferred embodiment, the trench dielectric layer 32 is formed by depositing oxide after grooves are cut, and the cross-sectional shape is circular, trapezoidal, elliptical, or hexagonal; and / or the trench dielectric layer 32 is SiO2, or a low-K or high-K dielectric.

[0011] As a preferred embodiment, the device is a bulk silicon device or a SOI structure; and in addition to LDMOS devices, it is also used for LIGBT devices; and / or the device structure is one of a single RESURF structure, a double RESURF structure, and a triple RESURF structure.

[0012] As a preferred embodiment, the drift region metal electrode 51 may be replaced by doped polysilicon.

[0013] As a preferred embodiment, the first conductive type substrate 11 is an SOI substrate or a sapphire substrate.

[0014] As a preferred embodiment, Si or SiC material can be used as the semiconductor material.

[0015] As a preferred embodiment, the resistive field plate polysilicon 42 is arranged in a single spiral or double spiral shape, or is arranged in a plurality of equally spaced rings, connected by staggered lines in the terminal region.

[0016] As a preferred embodiment, the MIS array in the terminal area is a continuous groove in the shape of a semicircular ring.

[0017] The present invention also provides a second active depletion device based on potential clamp bias coupling, comprising:

[0018] A first conductive type substrate 11, a second conductive type drift region 21, a first conductive type well region 12 and a second conductive type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, a source metal 54, a gate metal 55, a drain metal 56, a second conductive type source contact region 23, a second conductive type drain contact region 24, and a first conductive type body contact region 13;

[0019] Among them, the second conductive type drift region 21 is located above the first conductive type substrate 11, the first conductive type well region 12 is located on the left side of the second conductive type drift region 21, and the second conductive type well region 22 is located on the right side of the second conductive type drift region 21; the second conductive type drain contact region 24 is located in the second conductive type well region 22 and is connected to the drain metal 56 above; the second conductive type source contact region 23 and the first conductive type body contact region 13 are located in the first conductive type well region 12 and are connected to the source metal 54 above; the gate oxide layer 33 is located above the first conductive type well region 12, and the gate oxide layer The left end of 33 is in contact with the second conductive type source contact region 23, and the right end is in contact with the second conductive type drift region 21; the field oxide layer 31 is located on the upper surface of the second conductive type drift region 21 between the left gate oxide layer 33 and the right second conductive type drain contact region 24; the control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and partially extends to the upper surface of the field oxide layer 31; the resistive field plate polysilicon 42 is spirally wound on the upper surface of the field oxide layer 31, and the head end partially extends to the upper surface of the second conductive type drain contact region 24 and is connected to the drain metal 56, and the tail end is connected to the control gate polysilicon 41;

[0020] The trench dielectric layer 32, the drift region metal electrode 51 and the contact hole metal 52 constitute a MIS array, which is distributed in the entire second conductive type drift region 21, wherein the drift region metal electrode 51 in the cell region is connected to the gate metal 55 through the contact hole metal 52, and the drift region metal electrode 51 in the terminal region is floating; the horizontal direction from the device source region to the drain region is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction, and the MIS array is staggered in the z direction.

[0021] The present invention also provides a method for manufacturing an active depletion device based on potential clamp bias coupling, comprising the following steps:

[0022] Step 1: epitaxially grow or implant a second conductivity type drift region 21 on a first conductivity type substrate 11;

[0023] Step 2: thermal oxidation growth field oxide layer 31;

[0024] Step 3: implanting the first conductivity type well region 12 and the second conductivity type well region 22;

[0025] Step 4: Select an etching distance, and form two adjacent and staggered cylindrical groove structures through photolithography and etching;

[0026] Step 5: depositing a trench dielectric layer 32 covering the trench wall;

[0027] Step 6: depositing metal on the lower surface of the field oxide layer to form a drift region metal electrode 51;

[0028] Step 7: Deposit and fill the remaining portion above the groove, and thermally oxidize and grow the gate oxide layer 33;

[0029] Step 8: depositing and etching to form gate polysilicon 41 and resistive field plate polysilicon 42, and implanting and activating the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13;

[0030] Step 9: deposit an interlayer dielectric 34, etch the deposited metal to form a contact hole metal 52, deposit metal again and etch to form an equipotential ring metal 53, a source metal 54, a gate metal 55 and a drain metal 56.

[0031] The present invention also provides a method for manufacturing an active depletion device based on potential clamp bias coupling, wherein the deep trench etching of the MIS array is placed after the formation of the resistive field plate polysilicon 42, and the contact hole metal 52 is used instead of the drift region metal electrode 51 as the in-trench electrode.

[0032] As a preferred embodiment, the method for manufacturing an active depletion device based on potential clamp bias coupling comprises the following steps:

[0033] Step 1: epitaxially grow or implant a second conductivity type drift region 21 on a first conductivity type substrate 11;

[0034] Step 2: thermal oxidation growth field oxide layer 31;

[0035] Step 3: implanting the first conductivity type well region 12 and the second conductivity type well region 22;

[0036] Step 4: thermally oxidize and grow the gate oxide layer 33, deposit and etch to form gate polysilicon 41 and resistive field plate polysilicon 42, and implant and activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13;

[0037] Step 5: Select an etching distance, and form two-by-two adjacent and staggered cylindrical groove structures between the resistive field plate polysilicon 42 by photolithography and etching;

[0038] Step 6: depositing an oxide layer to form a trench dielectric layer 31 and an interlayer dielectric 34;

[0039] Step 7: Etch the deposited metal to form a contact hole metal 52, and make the contact hole metal 52 go deep into the groove, then deposit metal again and etch to form an equipotential ring metal 53, a source metal 54, a gate metal 55 and a drain metal 56.

[0040] The present invention also provides a method for manufacturing an active depletion device based on potential clamp bias coupling, wherein the deep trench etching of the MIS array is placed before the formation of the field oxide layer 31, and the drift region polysilicon electrode 43 is used instead of the drift region metal electrode 51 as the in-trench electrode.

[0041] As a preferred embodiment, the method for manufacturing an active depletion device based on potential clamp bias coupling comprises the following steps:

[0042] Step 1: epitaxially grow or implant a second conductivity type drift region 21 on a first conductivity type substrate 11;

[0043] Step 2: Select an etching distance, and form two adjacent and staggered cylindrical groove structures through photolithography and etching;

[0044] Step 3: depositing oxide in the trench to form a trench dielectric layer 31, and depositing doped polysilicon again after etching to form a drift region polysilicon electrode 43;

[0045] Step 4: thermal oxidation growth field oxide layer 31;

[0046] Step 5: implanting the first conductivity type well region 12 and the second conductivity type well region 22;

[0047] Step 6: thermally oxidize and grow the gate oxide layer 33, deposit and etch to form gate polysilicon 41 and resistive field plate polysilicon 42, and implant and activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13;

[0048] Step 7: deposit an interlayer dielectric 34, etch the deposited metal to form a contact hole metal 52, deposit metal again and etch to form an equipotential ring metal 53, a source metal 54, a gate metal 55 and a drain metal 56.

[0049] The beneficial effects of the present invention are as follows: through the combination of the resistive field plate and the MIS array, the electric potential evenly distributed on the resistive field plate is introduced into the drift region of the device, so that the device obtains a uniform electric field distribution in the entire drift region, effectively ensuring the complete depletion of the drift region of the device during voltage withstand, thereby greatly improving the doping concentration of the drift region and the overall process tolerance of the device while ensuring the voltage withstand capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1(a)-1(g) Schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 1;

[0051] Figure 2(a)-2(b) A schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 2;

[0052] Figure 3(a)-3(b) A schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 3;

[0053] Figure 4 Schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 4;

[0054] Figure 5(a)-5(b) A schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 5;

[0055] Figure 6(a)-6(c) Schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 6;

[0056] Figure 7(a)-7(b) Schematic diagram of the structure of an active depletion device based on potential clamp bias coupling in Example 7;

[0057] Figure 8(a)-8(i) This is a schematic diagram of the process flow of the device described in Example 1;

[0058] Figure 9(a)-9(g) This is a schematic diagram of the process flow of the device described in Example 2;

[0059] Figure 10(a)-10(g)This is a schematic diagram of the process flow of the device described in Example 3;

[0060] 11 is a first conductive type substrate, 21 is a second conductive type drift region, 12 is a first conductive type well region, 22 is a second conductive type well region, 31 is a field oxide layer, 32 is a trench dielectric layer, 33 is a gate oxide layer, 34 is an interlayer dielectric, 41 is a control gate polysilicon, 42 is a resistive field plate polysilicon, 51 is a drift region metal electrode, 52 is a contact hole metal, 53 is an equipotential ring metal, 54 is a source metal, 55 is a gate metal, 56 is a drain metal, 23 is a second conductive type source contact region, 24 is a second conductive type drain contact region 24, and 13 is a first conductive type body contact region. DETAILED DESCRIPTION

[0061] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] Example 1

[0063] Embodiment 1 provides an active depletion device based on potential clamp bias coupling and a manufacturing method thereof, wherein the plan view and top view of the cell region are shown in FIG. 1(a) and FIG. 1(b) respectively, the resistive field plate arrangement, the MIS array and the metal arrangement and their local enlarged views are shown in FIG. 1(c), FIG. 1(d), FIG. 1(e), and FIG. 1(f), and the working mechanism is shown in FIG. (g), which specifically includes:

[0064] A first conductive type substrate 11, a second conductive type drift region 21, a first conductive type well region 12 and a second conductive type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, an equipotential ring metal 53, a source metal 54, a gate metal 55, a drain metal 56, a second conductive type source contact region 23, a second conductive type drain contact region 24, and a first conductive type body contact region 13;

[0065] The second conductive type drift region 21 is located above the first conductive type semiconductor substrate 11, the first conductive type well region 12 is located on the left side of the second conductive type drift region 21, and the second conductive type well region 22 is located on the right side of the second conductive type drift region 21. The second conductive type drain contact region 24 is located in the second conductive type well region 22 and is connected to the drain metal 56 above; the second conductive type source contact region 23 and the first conductive type body contact region 13 are located in the first conductive type well region 12 and are connected to the source metal 54 above. The gate oxide layer 33 is located above the first conductive type well region 12, and the left end of the gate oxide layer 33 is in contact with the second conductive type source contact region 23 and the right end is in contact with the second conductive type drift region 21; the field oxide layer 31 is located on the upper surface of the second conductive type drift region 21 between the left gate oxide layer 33 and the right second conductive type drain contact region 24. The control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and partially extends to the upper surface of the field oxide layer 31, and the resistive field plate polysilicon 42 is spirally coiled on the upper surface of the field oxide layer 31, with the head end extending to the upper surface of the second conductive type drain contact region 24 and connected to the drain metal 56, and the tail end is connected to the control gate polysilicon 41.

[0066] The trench dielectric layer 32 and the drift region metal electrode 51 form a MIS array, which is distributed in the entire second conductive type drift region 21, wherein the drift region metal electrode 51 in the cell region is connected to the equipotential ring metal 53 and the gate metal 55 evenly spaced above through the contact hole metal 52, and the drift region metal electrode 51 in the terminal region is floating; the horizontal direction from the device source region to the drain region is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction, and the MIS array is staggered in the z direction.

[0067] The basic working principle is as follows: Taking the first conductive type semiconductor substrate 11 as P type as an example, when the gate bias voltage V G When it is 0, a larger voltage V is applied to the drain metal 56. D At this time, the PN junction formed by the second conductive type drift region 21, the first conductive type well region 12 and the first conductive type semiconductor substrate 11 is at the drain voltage V D The groove dielectric layer 32 and the drift region metal electrode 51 form a MIS array, which is connected to the equally spaced equipotential ring metal 53 and the gate metal 55 above through the contact hole metal 52, and is coupled with the resistive field plate polysilicon 42 interlaced therebetween. When the device is reversely withstand voltage, a linearly decreasing potential from drain to gate is generated on the resistive field plate polysilicon 42, and the potential is distributed to the MIS array through coupling clamping, and then the electric field in the drift region of the device is modulated through the MIS array. This will produce polarization of charge, and the charge can be adaptively polarized as the doping concentration changes to maintain the charge balance in the drift region, thereby improving the process tolerance of the device.

[0068] In the on state, that is, when the gate bias voltage V G When the voltage is greater than the threshold voltage, inversion layer electrons will appear on the surface of the first conductive type well region 12 near the gate oxide layer 33. D , the inverted electrons will move from the source to the drain along the surface of the longitudinal drift region. Since the MIS array leaves a current path in the z direction, the electrons can quickly flow through the surface of the drift region, and the specific on-resistance can be reduced by increasing the implantation dose of the drift region. In summary, the device proposed by the present invention has a lower specific on-resistance and a higher process tolerance than conventional devices while ensuring sufficient breakdown voltage.

[0069] As shown in FIG8 , it is a schematic diagram of the process flow of Example 1 of the present invention, which specifically includes the following steps:

[0070] Step 1: epitaxially grow or implant a second conductivity type drift region 21 on a first conductivity type substrate 11, as shown in FIG8(a);

[0071] Step 2: thermal oxidation growth field oxide layer 31; as shown in FIG8(b);

[0072] Step 3: implanting the first conductivity type well region 12 and the second conductivity type well region 22; as shown in FIG. 8( c );

[0073] Step 4: Select an etching distance, and form two adjacent and staggered cylindrical groove structures by photolithography and etching; as shown in FIG8(d);

[0074] Step 5: Deposit a trench dielectric layer 32 covering the trench wall, as shown in FIG. 8( e );

[0075] Step 6: Deposit metal onto the lower surface of the field oxide layer to form a drift region metal electrode 51; as shown in FIG8(f);

[0076] Step 7: Deposition to fill the empty part above the groove, and thermally oxidize the gate oxide layer 33, as shown in FIG8(g);

[0077] Step 8: deposit and etch to form control gate polysilicon 41 and resistive field plate polysilicon 42, and implant and activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13; as shown in FIG8(h);

[0078] Step 9: deposit interlayer dielectric 34, etch the deposited metal to form contact hole metal 52, deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56; as shown in FIG8(i).

[0079] Preferably, the first conductive type drift region 21 is formed by epitaxy or implantation.

[0080] Preferably, the trench dielectric layer 32 is formed by depositing oxide after grooves are cut, and the cross-sectional shape is circular, trapezoidal, elliptical, or hexagonal; and / or the trench dielectric layer 32 is SiO2; and / or the trench dielectric layer 32 is a low-K or high-K dielectric.

[0081] Preferably, the device is a bulk silicon device, or a SOI structure; and in addition to LDMOS devices, it is also used for LIGBT devices; and / or the device structure is one of a single RESURF structure, a double RESURF structure, and a triple RESURF structure.

[0082] Preferably, the drift region metal electrode 51 may be replaced by doped polysilicon.

[0083] Preferably, the first conductive type substrate 11 is an SOI substrate or a sapphire substrate.

[0084] Preferably, the semiconductor material may be Si or SiC.

[0085] Example 2

[0086] Embodiment 2 provides an active depletion device based on potential clamp bias coupling and a manufacturing method thereof, the plan view and top view of the cell region are shown in FIG. 2(a) and FIG. 2(b) respectively; the difference between this embodiment and the embodiment 1 is that the size of the groove and the overall process are adjusted, the deep groove etching of the MIS array is placed after the formation of the resistive field plate polysilicon 42, and the contact hole metal 52 is used instead of the drift region metal electrode 51 as the groove electrode. Its working principle is basically the same as that of embodiment 1.

[0087] As shown in FIG9 , it is a schematic diagram of the process flow of Example 2 of the present invention, which specifically includes the following steps:

[0088] Step 1: epitaxially grow or implant a second conductivity type drift region 21 on a first conductivity type substrate 11, as shown in FIG. 9(a);

[0089] Step 2: thermal oxidation growth field oxide layer 31; as shown in FIG9(b);

[0090] Step 3: implanting the first conductivity type well region 12 and the second conductivity type well region 22; as shown in FIG. 9( c );

[0091] Step 4: thermally oxidize and grow the gate oxide layer 33, deposit and etch to form the control gate polysilicon 41 and the resistive field plate polysilicon 42, and implant and activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13; as shown in FIG9(d);

[0092] Step 5: Select an etching distance, and form two-by-two adjacent and staggered cylindrical groove structures between the resistive field plate polysilicon 42 by photolithography and etching; as shown in FIG. 9( e );

[0093] Step 6: depositing an oxide layer to form a trench dielectric layer 31 and an interlayer dielectric 34; as shown in FIG. 9( f );

[0094] Step 7: Etch the deposited metal to form a contact hole metal 52, and make the contact hole metal 52 go deep into the groove, then deposit metal again and etch to form an equipotential ring metal 53, a source metal 54, a gate metal 55 and a drain metal 56; as shown in Figure 9(g).

[0095] Example 3

[0096] Embodiment 3 provides an active depletion device based on potential clamp bias coupling and a manufacturing method thereof, the plan view and top view of the cell region are shown in FIG3 (a) and (b) respectively; the difference between this embodiment and the embodiment 1 is that the overall process is adjusted, the deep trench etching of the MIS array is placed before the formation of the field oxide layer 31, and the drift region polysilicon electrode 43 is used instead of the drift region metal electrode 51 as the electrode in the trench. Its working principle is basically the same as that of embodiment 1.

[0097] As shown in FIG10 , it is a schematic diagram of the process flow of Example 3 of the present invention, which specifically includes the following steps:

[0098] Step 1: epitaxially grow or implant a second conductive type drift region 21 on a first conductive type substrate 11, as shown in FIG. 10(a);

[0099] Step 2: Select an etching distance, and form two adjacent and staggered cylindrical groove structures by photolithography and etching; as shown in FIG10(b);

[0100] Step 3: Depositing oxide in the trench to form a trench dielectric layer 31, and depositing doped polysilicon again after etching to form a drift region polysilicon electrode 43; as shown in FIG10(c);

[0101] Step 4: thermal oxidation growth field oxide layer 31; as shown in FIG10( d );

[0102] Step 5: implanting the first conductivity type well region 12 and the second conductivity type well region 22; as shown in FIG. 10( e );

[0103] Step 6: thermally oxidize and grow the gate oxide layer 33, deposit and etch to form the control gate polysilicon 41 and the resistive field plate polysilicon 42, and implant and activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13; as shown in FIG. 10(f);

[0104] Step 7: deposit interlayer dielectric 34, etch the deposited metal to form contact hole metal 52, deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56; as shown in FIG. 10(g).

[0105] Preferably, the drift region polysilicon electrode 43 may be replaced by metal.

[0106] Example 4

[0107] like Figure 4 FIG. 1 is a schematic diagram of an active depletion device structure based on potential clamp bias coupling according to Embodiment 4. The difference between this embodiment and Embodiment 1 is that: this embodiment does not provide an equipotential ring metal 53, and only the contact hole metal 52 is coupled to the resistive polysilicon field plate 42. The rest of the manufacturing process and working principle are consistent with Embodiment 1.

[0108] include:

[0109] A first conductive type substrate 11, a second conductive type drift region 21, a first conductive type well region 12 and a second conductive type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, a source metal 54, a gate metal 55, a drain metal 56, a second conductive type source contact region 23, a second conductive type drain contact region 24, and a first conductive type body contact region 13;

[0110] Among them, the second conductive type drift region 21 is located above the first conductive type substrate 11, the first conductive type well region 12 is located on the left side of the second conductive type drift region 21, and the second conductive type well region 22 is located on the right side of the second conductive type drift region 21; the second conductive type drain contact region 24 is located in the second conductive type well region 22 and is connected to the drain metal 56 above; the second conductive type source contact region 23 and the first conductive type body contact region 13 are located in the first conductive type well region 12 and are connected to the source metal 54 above; the gate oxide layer 33 is located above the first conductive type well region 12, and the gate oxide layer The left end of 33 is in contact with the second conductive type source contact region 23, and the right end is in contact with the second conductive type drift region 21; the field oxide layer 31 is located on the upper surface of the second conductive type drift region 21 between the left gate oxide layer 33 and the right second conductive type drain contact region 24; the control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and partially extends to the upper surface of the field oxide layer 31; the resistive field plate polysilicon 42 is spirally wound on the upper surface of the field oxide layer 31, and the head end partially extends to the upper surface of the second conductive type drain contact region 24 and is connected to the drain metal 56, and the tail end is connected to the control gate polysilicon 41;

[0111] The trench dielectric layer 32, the drift region metal electrode 51 and the contact hole metal 52 constitute a MIS array, which is distributed in the entire second conductive type drift region 21, wherein the drift region metal electrode 51 in the cell region is connected to the gate metal 55 through the contact hole metal 52, and the drift region metal electrode 51 in the terminal region is floating; the horizontal direction from the device source region to the drain region is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction, and the MIS array is staggered in the z direction.

[0112] Example 5

[0113] As shown in FIG. 5( a ) and FIG. 5( b ), it is a schematic diagram of an active depletion device structure based on potential clamp bias coupling of Example 5. The difference between this example and Example 1 is that the resistive polysilicon field plate 42 of this example is a double spiral arrangement with both ends of the terminal leading out at the same time. Its working principle is basically the same as that of Example 1.

[0114] Example 6

[0115] As shown in FIG. 6(a), FIG. 6(b), and FIG. 6(c), it is a schematic diagram of an active depletion device structure based on potential clamp bias coupling of Example 6. The difference between this example and Example 1 is that the resistive polysilicon field plate 42 of this example is a plurality of equally spaced rings connected by wires staggered in the terminal region. The rest of the working principle is the same as that of Example 1.

[0116] Example 7

[0117] As shown in FIG. 7( a ) and FIG. 7( b ), it is a schematic diagram of an active depletion device structure based on potential clamp bias coupling of Example 7. The difference between this example and Example 1 is that the MIS array in the terminal area of ​​this example is changed from discrete grooves to semicircular continuous grooves, which has a stronger terminal withstand voltage capability. The rest of the working principle is the same as that of Example 1.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An active depletion device based on potential clamp bias coupling, characterized in that include: A first conductive type substrate (11), a second conductive type drift region (21), a first conductive type well region (12) and a second conductive type well region (22), a field oxide layer (31), a trench dielectric layer (32), a gate oxide layer (33), an interlayer dielectric (34), a control gate polysilicon (41), a resistive field plate polysilicon (42), a drift region metal electrode (51), a contact hole metal (52), an equipotential ring metal (53), a source metal (54), a gate metal (55), a drain metal (56), a second conductive type source contact region (23), a second conductive type drain contact region (24), and a first conductive type body contact region (13); The second conductive type drift region (21) is located above the first conductive type substrate (11), the first conductive type well region (12) is located on the left side of the second conductive type drift region (21), and the second conductive type well region (22) is located on the right side of the second conductive type drift region (21); the second conductive type drain contact region (24) is located in the second conductive type well region (22) and is connected to the drain metal (56) above; the second conductive type source contact region (23) and the first conductive type body contact region (13) are located in the first conductive type well region (12) and are connected to the source metal (54) above; the gate oxide layer (33) is located above the first conductive type well region (12), and the gate oxide layer (33) is located above the first conductive type well region (12), and the gate oxide layer (33) is located above the first conductive type well region (12). (33) is in contact with the second conductive type source contact region (23) at the left end and is in contact with the second conductive type drift region (21) at the right end; the field oxide layer (31) is located on the upper surface of the second conductive type drift region (21) between the left gate oxide layer (33) and the right second conductive type drain contact region (24); the control gate polysilicon (41) covers the upper surface of the gate oxide layer (33) and partially extends to the upper surface of the field oxide layer (31); the resistive field plate polysilicon (42) is spirally wound on the upper surface of the field oxide layer (31), and the head end partially extends to the upper surface of the second conductive type drain contact region (24) and is connected to the drain metal (56), and the tail end is connected to the control gate polysilicon (41); The trench dielectric layer (32) and the drift region metal electrode (51) form an MIS array, which is distributed in the entire second conductive type drift region (21), wherein the drift region metal electrode (51) in the cell region is connected to the equipotential ring metal (53) and the gate metal (55) distributed at equal intervals above through the contact hole metal (52), and the drift region metal electrode (51) in the terminal region is floating; the horizontal direction from the device source region to the drain region is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction, and the MIS array is staggered in the z direction.

2. An active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: The first conductive type drift region (21) is formed by epitaxy or implantation.

3. The active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: The trench dielectric layer (32) is formed by depositing oxide after the trench is cut, and the cross-sectional shape is circular, trapezoidal, elliptical, or hexagonal; and / or the trench dielectric layer (32) is SiO2, or a low-K or high-K dielectric.

4. The active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: The device is a bulk silicon device or a SOI structure; and in addition to LDMOS devices, it is also used for LIGBT devices; and / or the device structure is one of a single RESURF structure, a double RESURF structure, and a triple RESURF structure.

5. The active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: The first conductive type substrate (11) is an SOI substrate or a sapphire substrate.

6. The active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: As the semiconductor material, Si or SiC material is used.

7. The active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: The resistive field plate polysilicon (42) is arranged in a single spiral or double spiral shape, or in a plurality of equally spaced rings, connected by staggered lines in the terminal region.

8. The active depletion device based on potential clamp bias coupling according to claim 1, characterized in that: The MIS array in the terminal area is a continuous groove in the shape of a semicircular ring.

9. An active depletion device based on potential clamp bias coupling, characterized in that: include: A first conductive type substrate (11), a second conductive type drift region (21), a first conductive type well region (12) and a second conductive type well region (22), a field oxide layer (31), a trench dielectric layer (32), a gate oxide layer (33), an interlayer dielectric (34), a control gate polysilicon (41), a resistive field plate polysilicon (42), a drift region metal electrode (51), a contact hole metal (52), a source metal (54), a gate metal (55), a drain metal (56), a second conductive type source contact region (23), a second conductive type drain contact region (24), and a first conductive type body contact region (13); The second conductive type drift region (21) is located above the first conductive type substrate (11), the first conductive type well region (12) is located on the left side of the second conductive type drift region (21), and the second conductive type well region (22) is located on the right side of the second conductive type drift region (21); the second conductive type drain contact region (24) is located in the second conductive type well region (22) and is connected to the drain metal (56) above; the second conductive type source contact region (23) and the first conductive type body contact region (13) are located in the first conductive type well region (12) and are connected to the source metal (54) above; the gate oxide layer (33) is located above the first conductive type well region (12), and the gate oxide layer (33) is located above the first conductive type well region (12), and the gate oxide layer (33) is located above the first conductive type well region (12). (33) is in contact with the second conductive type source contact region (23) at the left end and is in contact with the second conductive type drift region (21) at the right end; the field oxide layer (31) is located on the upper surface of the second conductive type drift region (21) between the left gate oxide layer (33) and the right second conductive type drain contact region (24); the control gate polysilicon (41) covers the upper surface of the gate oxide layer (33) and partially extends to the upper surface of the field oxide layer (31); the resistive field plate polysilicon (42) is spirally wound on the upper surface of the field oxide layer (31), and the head end partially extends to the upper surface of the second conductive type drain contact region (24) and is connected to the drain metal (56), and the tail end is connected to the control gate polysilicon (41); The trench dielectric layer (32) and the drift region metal electrode (51) and the contact hole metal (52) form a MIS array, which is distributed in the entire second conductive type drift region (21), wherein the drift region metal electrode (51) in the cell region is connected to the gate metal (55) through the contact hole metal (52), and the drift region metal electrode (51) in the terminal region is floating; the horizontal direction from the device source region to the drain region is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction, and the MIS array is staggered in the z direction.

10. A method for manufacturing an active depletion device based on potential clamp bias coupling, used to prepare the active depletion device according to any one of claims 1 to 8, characterized in that The steps include: Step 1: epitaxially growing or implanting a second conductivity type drift region (21) on a first conductivity type substrate (11); Step 2: thermally oxidize and grow a field oxide layer (31); Step 3: implanting a first conductivity type well region (12) and a second conductivity type well region (22); Step 4: Select an etching distance, and form two adjacent and staggered cylindrical groove structures through photolithography and etching; Step 5: depositing a trench dielectric layer (32) covering the trench wall; Step 6: depositing metal onto the lower surface of the field oxide layer to form a drift region metal electrode (51); Step 7: Deposit to fill the empty part above the groove, and thermally oxidize the gate oxide layer (33); Step 8: depositing and etching to form gate polysilicon (41) and resistive field plate polysilicon (42), and implanting and activating the second conductivity type source contact region (23), the second conductivity type drain contact region (24) and the first conductivity type body contact region (13); Step 9: depositing an interlayer dielectric (34), etching the deposited metal to form a contact hole metal (52), depositing metal again and etching to form an equipotential ring metal (53), a source metal (54), a gate metal (55) and a drain metal (56).

11. A method for manufacturing an active depletion device based on potential clamp bias coupling, used to prepare the active depletion device according to any one of claims 1 to 8, characterized in that: The deep trench etching of the MIS array is placed after the formation of the resistive field plate polysilicon (42), and the contact hole metal (52) is used to replace the drift region metal electrode (51) as the in-trench electrode.

12. A method for manufacturing an active depletion device based on potential clamp bias coupling according to claim 11, characterized in that The steps include: Step 1: epitaxially growing or implanting a second conductivity type drift region (21) on a first conductivity type substrate (11); Step 2: thermally oxidize and grow a field oxide layer (31); Step 3: implanting a first conductivity type well region (12) and a second conductivity type well region (22); Step 4: thermally oxidizing and growing a gate oxide layer (33), depositing and etching to form gate polysilicon (41) and resistive field plate polysilicon (42), and implanting and activating a second conductivity type source contact region (23), a second conductivity type drain contact region (24) and a first conductivity type body contact region (13); Step 5: Select an etching distance, and form two adjacent and staggered cylindrical groove structures between the resistive field plate polysilicon (42) by photolithography and etching; Step 6: depositing an oxide layer to form a trench dielectric layer (31) and an interlayer dielectric (34); Step 7: Etching the deposited metal to form contact hole metal (52), and making the contact hole metal (52) deep into the groove, and then depositing metal again and etching to form equipotential ring metal (53), source metal (54), gate metal (55) and drain metal (56).

13. A method for manufacturing an active depletion device based on potential clamp bias coupling, used to prepare the active depletion device according to any one of claims 1 to 8, characterized in that: The deep trench etching of the MIS array is placed before the field oxide layer (31) is formed, and the drift region polysilicon electrode (43) is used to replace the drift region metal electrode (51) as the groove electrode.

14. A method for manufacturing an active depletion device based on potential clamp bias coupling according to claim 13, characterized in that The steps include: Step 1: epitaxially growing or implanting a second conductivity type drift region (21) on a first conductivity type substrate (11); Step 2: Select an etching distance, and form two adjacent and staggered cylindrical groove structures through photolithography and etching; Step 3: depositing oxide in the trench to form a trench dielectric layer (31), and depositing doped polysilicon again after etching to form a drift region polysilicon electrode (43); Step 4: thermally oxidize and grow a field oxide layer (31); Step 5: implanting a first conductivity type well region (12) and a second conductivity type well region (22); Step 6: thermally oxidize and grow a gate oxide layer (33), deposit and etch to form gate polysilicon (41) and resistive field plate polysilicon (42), and implant and activate a second conductivity type source contact region (23), a second conductivity type drain contact region (24) and a first conductivity type body contact region (13); Step 7: depositing an interlayer dielectric (34), etching the deposited metal to form a contact hole metal (52), depositing metal again and etching to form an equipotential ring metal (53), a source metal (54), a gate metal (55) and a drain metal (56).

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