Active depletion device based on potential clamped bias coupling and method of manufacture

Abstract

The application provides an active depletion device based on potential clamping bias coupling and a manufacturing method, which comprises a first conductive type substrate, a second conductive type drift region, a resistive polysilicon field plate, an MIS array, first and second conductive type well regions and heavily doped regions located on both sides of the drift region, a control gate polysilicon electrode located on the surface of the device, a field oxide layer and an interlayer dielectric. The structure combines the MIS array and the resistive field plate, clamps the MIS array by using the uniform potential distribution on the resistive field plate and the bias coupling between the resistive field plate and the MIS array, further optimizes the potential distribution of the MIS array, and thus brings better device performance and wider design space.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductors, and mainly proposes an active depletion device based on potential clamping bias coupling and its manufacturing method. Background Technology

[0002] Lateral power semiconductor devices are widely used in new energy vehicles, photovoltaic power generation, and other fields due to their high input impedance, fast switching speed, low loss, and ease of integration with other devices. To achieve optimal performance, the drift region of the device is generally required to be completely depleted at the withstand voltage. Therefore, passive depletion technologies such as RESURF and superjunctions (using PN junction depletion) and active depletion technologies (modulating the bulk electric field through a MIS array) have been developed. However, the former relies on strict charge balance and suffers from small process tolerances; the latter's capacitive coupling between MIS arrays still deviates from ideal conditions and is affected by the undepleted region below, resulting in an uneven potential distribution. This invention addresses these issues by proposing a novel device structure that combines an MIS array with a resistive field plate. The uniform potential distribution on the resistive field plate and the bias coupling between the resistive field plate and the MIS array are used to clamp the MIS array, transforming the global coupling between the electrodes and the MIS array into a local coupling between the field plate and the MIS array. This further optimizes the potential distribution of the MIS array, leading to superior device performance and a wider design scope. Summary of the Invention

[0003] This invention addresses the problems existing in the background technology by proposing an active depletion device based on potential clamping bias coupling and its manufacturing method. By clamping the MIS array in the drift region with a resistive field plate, a uniform potential distribution is introduced into the drift region of the device, ensuring that the drift region can be completely depleted and has a uniform internal electric field distribution when the voltage withstand capability is maintained. This significantly improves the doping concentration of the drift region and the overall process tolerance of the device while ensuring the device's voltage withstand capability.

[0004] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0005] An active depletion device based on potential clamping bias coupling and its manufacturing process, comprising:

[0006] The system comprises a first conductivity type substrate 11, a second conductivity type drift region 21, a first conductivity type well region 12 and a second conductivity type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, an equipotential ring metal 53, a source metal 54, a gate metal 55, a drain metal 56, a second conductivity type source contact region 23, a second conductivity type drain contact region 24, and a first conductivity type body contact region 13.

[0007] The second conductivity type drift region 21 is located above the first conductivity type substrate 11, the first conductivity type well region 12 is located to the left of the second conductivity type drift region 21, and the second conductivity type well region 22 is located to the right of the second conductivity type drift region 21. The second conductivity type drain contact region 24 is located in the second conductivity type well region 22 and is connected to the drain metal 56 above it; the second conductivity type source contact region 23 and the first conductivity type body contact region 13 are located in the first conductivity type well region 12 and are connected to the source metal 54 above them. The gate oxide layer 33 is located above the first conductivity type well region 12, and the left end of the gate oxide layer 33 contacts the second conductivity type source contact region 23, and the right end contacts the second conductivity type drift region 21; the field oxide layer 31 is located on the upper surface of the second conductivity type drift region 21 between the left gate oxide layer 33 and the right second conductivity type drain contact region 24. The control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and extends partially to the upper surface of the field oxide layer 31. The resistive field plate polysilicon 42 is spirally coiled on the upper surface of the field oxide layer 31, with its first end extending to the upper surface of the second conductivity type drain contact region 24 and connecting to the drain metal 56, and its tail end connecting to the control gate polysilicon 41.

[0008] The trench dielectric layer 32 and the drift region metal electrode 51 constitute a MIS array, which is distributed throughout the drift region 21 of the second conductivity type. The drift region metal electrode 51 of the cell region is connected to the equipotential ring metal 53 and gate metal 55 distributed at equal intervals above through the contact hole metal 52, while the drift region metal electrode 51 of the terminal region is floating. The horizontal direction from the source region to the drain region of the device is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction. The MIS array is staggered in the z direction.

[0009] As a preferred embodiment, the first conductivity type drift region 21 is formed by epitaxy or injection push junction.

[0010] As a preferred embodiment, the trench dielectric layer 32 is formed by depositing oxide after trenching, and the cross-sectional shape is circular, trapezoidal, elliptical, or hexagonal; and / or the trench dielectric layer 32 is SiO2, or a low-K or high-K dielectric.

[0011] As a preferred embodiment, the device is a bulk silicon device or an SOI structure; and in addition to LDMOS devices, it is also used for LIGBT devices; and / or the device structure is one of a single RESURF structure, a double RESURF structure, or a triple RESURF structure.

[0012] As a preferred embodiment, the drift region metal electrode 51 can be replaced with doped polycrystalline silicon.

[0013] As a preferred embodiment, the first conductivity type substrate 11 is an SOI substrate or a sapphire substrate.

[0014] As a preferred approach, the semiconductor material can be Si or SiC.

[0015] As a preferred embodiment, the resistive field plate polysilicon 42 is arranged in a single spiral or double spiral shape, or in multiple equally spaced rings connected by staggered lines in the terminal area.

[0016] As a preferred embodiment, the MIS array in the terminal area is a continuous semi-circular groove.

[0017] This invention also provides a second type of active depletion device based on potential clamping bias coupling, comprising:

[0018] The system comprises a first conductivity type substrate 11, a second conductivity type drift region 21, a first conductivity type well region 12 and a second conductivity type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, a source metal 54, a gate metal 55, a drain metal 56, a second conductivity type source contact region 23, a second conductivity type drain contact region 24, and a first conductivity type body contact region 13.

[0019] In this configuration, the second conductivity type drift region 21 is located above the first conductivity type substrate 11, the first conductivity type well region 12 is located to the left of the second conductivity type drift region 21, and the second conductivity type well region 22 is located to the right of the second conductivity type drift region 21; the second conductivity type drain contact region 24 is located in the second conductivity type well region 22 and is connected to the drain metal 56 above it; the second conductivity type source contact region 23 and the first conductivity type body contact region 13 are located in the first conductivity type well region 12 and are connected to the source metal 54 above them; the gate oxide layer 33 is located above the first conductivity type well region 12, and the gate oxide layer... The left end of the gate oxide layer 33 is in contact with the source contact region 23 of the second conductivity type, and the right end is in contact with the drift region 21 of the second conductivity type. The field oxide layer 31 is located on the upper surface of the drift region 21 of the second conductivity type between the left gate oxide layer 33 and the right second conductivity type drain contact region 24. The control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and extends to the upper surface of the field oxide layer 31 in part. The resistive field plate polysilicon 42 is spirally coiled on the upper surface of the field oxide layer 31, and the first end extends to the upper surface of the drain contact region 24 of the second conductivity type and is connected to the drain metal 56, and the tail end is connected to the control gate polysilicon 41.

[0020] The trench dielectric layer 32, the drift region metal electrode 51, and the contact hole metal 52 constitute a MIS array, which is distributed throughout the drift region 21 of the second conductivity type. The drift region metal electrode 51 of the cell region is connected to the gate metal 55 through the contact hole metal 52, while the drift region metal electrode 51 of the terminal region is floating. The horizontal direction from the source region to the drain region of the device is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction. The MIS array is staggered in the z direction.

[0021] The present invention also provides a method for manufacturing an active depletion device based on potential clamping bias coupling, comprising the following steps:

[0022] Step 1: Epitaxial growth or implantation push-junction on the first conductivity type substrate 11 to obtain the second conductivity type drift region 21;

[0023] Step 2: Thermal oxidation growth of field oxide layer 31;

[0024] Step 3: Inject the first conductivity type well region 12 and the second conductivity type well region 22;

[0025] Step 4: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure through photolithography and etching;

[0026] Step 5: Deposit to form a tank medium layer 32 covering the tank wall;

[0027] Step 6: Deposit metal onto the lower surface of the field oxide layer to form the drift region metal electrode 51;

[0028] Step 7: Deposit and fill the empty space above the trench, and thermally oxidize to grow the gate oxide layer 33;

[0029] Step 8: Deposit and etch to form gate polysilicon 41 and resistive field plate polysilicon 42, and implant to activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13;

[0030] Step 9: Deposit interlayer dielectric 34, etch deposited metal to form contact hole metal 52, deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56.

[0031] The present invention also provides a method for manufacturing an active depletion device based on potential clamping bias coupling, wherein the deep trench etching of the MIS array is placed after the formation of the resistive field plate polysilicon 42, and the contact hole metal 52 is used to replace the drift region metal electrode 51 as the in-trench electrode.

[0032] As a preferred embodiment, the method for manufacturing an active depletion device based on potential clamping bias coupling includes the following steps:

[0033] Step 1: Epitaxial growth or implantation push-junction on the first conductivity type substrate 11 to obtain the second conductivity type drift region 21;

[0034] Step 2: Thermal oxidation growth of field oxide layer 31;

[0035] Step 3: Inject the first conductivity type well region 12 and the second conductivity type well region 22;

[0036] Step 4: Thermal oxidation to grow gate oxide layer 33, deposition and etching to form gate polysilicon 41 and resistive field plate polysilicon 42, and implantation to activate second conductivity type source contact region 23, second conductivity type drain contact region 24 and first conductivity type body contact region 13;

[0037] Step 5: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure between the polysilicon 42 resistive field plates through photolithography and etching;

[0038] Step 6: Deposit an oxide layer to form the tank medium layer 31 and the interlayer medium 34;

[0039] Step 7: Etch the deposited metal to form contact hole metal 52, and make the contact hole metal 52 extend into the trench. Then deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56.

[0040] The present invention also provides a method for manufacturing an active depletion device based on potential clamping bias coupling, wherein the deep trench etching of the MIS array is placed before the formation of the field oxide layer 31, and the drift region polysilicon electrode 43 is used instead of the drift region metal electrode 51 as the in-trench electrode.

[0041] As a preferred embodiment, the method for manufacturing an active depletion device based on potential clamping bias coupling includes the following steps:

[0042] Step 1: Epitaxial growth or implantation push-junction on the first conductivity type substrate 11 to obtain the second conductivity type drift region 21;

[0043] Step 2: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure through photolithography and etching;

[0044] Step 3: Deposit oxide in the tank to form the tank dielectric layer 31, and after etching, deposit doped polysilicon again to form the drift region polysilicon electrode 43.

[0045] Step 4: Thermal oxidation growth of field oxide layer 31;

[0046] Step 5: Inject the first conductivity type well region 12 and the second conductivity type well region 22;

[0047] Step 6: Thermally oxidize to grow gate oxide layer 33, deposit and etch to form gate polysilicon 41 and resistive field plate polysilicon 42, and implant to activate second conductivity type source contact region 23, second conductivity type drain contact region 24 and first conductivity type body contact region 13;

[0048] Step 7: Deposit interlayer dielectric 34, etch deposited metal to form contact hole metal 52, deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56.

[0049] The beneficial effects of this invention are as follows: by combining the resistive field plate with the MIS array, the potential uniformly distributed on the resistive field plate is introduced into the device drift region, so that the device obtains a uniform electric field distribution in the entire drift region, effectively ensuring the complete depletion of the device drift region during breakdown voltage, thereby significantly improving the doping concentration of the drift region and the overall process tolerance of the device while ensuring the device breakdown voltage capability. Attached Figure Description

[0050] Figure 1(a)-1(g) This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 1;

[0051] Figures 2(a)-2(b) This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 2;

[0052] Figures 3(a)-3(b) This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 3;

[0053] Figure 4 This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 4;

[0054] Figures 5(a)-5(b) This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 5;

[0055] Figures 6(a)-6(c) This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 6;

[0056] Figures 7(a)-7(b) This is a schematic diagram of an active depletion device structure based on potential clamping bias coupling in Example 7;

[0057] Figure 8(a)-8(i) This is a schematic diagram of the process flow of the device described in Example 1;

[0058] Figures 9(a)-9(g) This is a schematic diagram of the process flow of the device described in Example 2;

[0059] Figures 10(a)-10(g)This is a schematic diagram of the process flow for the device described in Example 3;

[0060] 11 is a substrate of the first conductivity type, 21 is a drift region of the second conductivity type, 12 is a well region of the first conductivity type, 22 is a well region of the second conductivity type, 31 is a field oxide layer, 32 is a trench dielectric layer, 33 is a gate oxide layer, 34 is an interlayer dielectric, 41 is a control gate polysilicon, 42 is a resistive field plate polysilicon, 51 is a drift region metal electrode, 52 is a contact hole metal, 53 is an equipotential ring metal, 54 is a source metal, 55 is a gate metal, 56 is a drain metal, 23 is a source contact region of the second conductivity type, 24 is a drain contact region of the second conductivity type, and 13 is a body contact region of the first conductivity type. Detailed Implementation

[0061] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] Example 1

[0063] Example 1 provides an active depletion device based on potential clamping bias coupling and its manufacturing method. The cross-sectional view and top view of its cell region are shown in Figure 1(a) and Figure 1(b), respectively. The resistive field plate arrangement, MIS array, and metal arrangement, along with their enlarged partial views, are shown in Figures 1(c), 1(d), 1(e), and 1(f). The working mechanism is shown in Figure (g), specifically including:

[0064] The system comprises a first conductivity type substrate 11, a second conductivity type drift region 21, a first conductivity type well region 12 and a second conductivity type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, an equipotential ring metal 53, a source metal 54, a gate metal 55, a drain metal 56, a second conductivity type source contact region 23, a second conductivity type drain contact region 24, and a first conductivity type body contact region 13.

[0065] The second conductivity type drift region 21 is located above the first conductivity type semiconductor substrate 11, the first conductivity type well region 12 is located to the left of the second conductivity type drift region 21, and the second conductivity type well region 22 is located to the right of the second conductivity type drift region 21. The second conductivity type drain contact region 24 is located in the second conductivity type well region 22 and is connected to the drain metal 56 above it; the second conductivity type source contact region 23 and the first conductivity type body contact region 13 are located in the first conductivity type well region 12 and are connected to the source metal 54 above them. The gate oxide layer 33 is located above the first conductivity type well region 12, and the left end of the gate oxide layer 33 contacts the second conductivity type source contact region 23, and the right end contacts the second conductivity type drift region 21; the field oxide layer 31 is located on the upper surface of the second conductivity type drift region 21 between the left gate oxide layer 33 and the right second conductivity type drain contact region 24. The control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and extends partially to the upper surface of the field oxide layer 31. The resistive field plate polysilicon 42 is spirally coiled on the upper surface of the field oxide layer 31, with its first end extending to the upper surface of the second conductivity type drain contact region 24 and connecting to the drain metal 56, and its tail end connecting to the control gate polysilicon 41.

[0066] The trench dielectric layer 32 and the drift region metal electrode 51 constitute a MIS array, which is distributed throughout the drift region 21 of the second conductivity type. The drift region metal electrode 51 of the cell region is connected to the equipotential ring metal 53 and the gate metal 55 distributed at equal intervals above through the contact hole metal 52, while the drift region metal electrode 51 of the terminal region is floating. The horizontal direction from the source region to the drain region of the device is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction. The MIS array is staggered in the z direction.

[0067] Its basic working principle is as follows: Taking the first conductivity type semiconductor substrate 11 as a P-type as an example, under the gate bias voltage V G When the voltage is 0, a large voltage V is applied across the drain metal 56. D At this time, the PN junction formed by the second conductivity type drift region 21, the first conductivity type well region 12, and the first conductivity type semiconductor substrate 11 is at the drain voltage V D Under the influence of the current, the energy begins to deplete. The trench dielectric layer 32 and the drift region metal electrode 51 constitute a MIS array, which is connected to the equipotential ring metal 53 and the gate metal 55 distributed at equal intervals above through contact hole metal 52, and is coupled to the resistive field plate polysilicon 42 interspersed therebetween. When the device is under reverse breakdown voltage, a potential that decreases linearly from drain to gate is generated on the resistive field plate polysilicon 42, and the potential is distributed to the MIS array through coupling clamping, thereby modulating the electric field of the device drift region through the MIS array. This generates charge polarization, and the charge can adaptively polarize with changes in doping concentration to maintain charge balance in the drift region, thereby improving the device's process tolerance.

[0068] In the on state, that is, when the gate bias voltage V G When the voltage exceeds the threshold voltage, inversion electrons will appear on the surface of the first conductivity type well region 12 near the gate oxide layer 33. A bias voltage V is applied to the drain metal 56. D Inverted electrons move from the source to the drain along the surface of the longitudinal drift region. Since the MIS array has a current path in the z-direction, electrons can flow rapidly across the drift region surface, and the specific on-resistance can be reduced by increasing the injection dose into the drift region. In summary, the device proposed in this invention offers lower specific on-resistance and higher process tolerance compared to conventional methods while maintaining sufficient breakdown voltage.

[0069] Figure 8 shows a schematic diagram of the process flow of Embodiment 1 of the present invention, which specifically includes the following steps:

[0070] Step 1: Epitaxial growth or implantation and push-junction on the first conductivity type substrate 11 to obtain the second conductivity type drift region 21; as shown in Figure 8(a);

[0071] Step 2: Thermal oxidation growth of field oxide layer 31; as shown in Figure 8(b);

[0072] Step 3: Inject the first conductivity type well region 12 and the second conductivity type well region 22; as shown in Figure 8(c);

[0073] Step 4: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure through photolithography and etching; as shown in Figure 8(d);

[0074] Step 5: Deposit to form a tank medium layer 32 covering the tank wall; as shown in Figure 8(e);

[0075] Step 6: Deposit metal onto the lower surface of the field oxide layer to form the drift region metal electrode 51; as shown in Figure 8(f);

[0076] Step 7: Deposit and fill the empty space above the trench, and thermally oxidize to grow the gate oxide layer 33; as shown in Figure 8(g);

[0077] Step 8: Deposit and etch to form control gate polysilicon 41 and resistive field plate polysilicon 42, and implant and activate the second conductivity type source contact region 23, the second conductivity type drain contact region 24 and the first conductivity type body contact region 13; as shown in Figure 8(h);

[0078] Step 9: Deposit interlayer dielectric 34, etch deposited metal to form contact hole metal 52, deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56; as shown in Figure 8(i).

[0079] Preferably, the first conductivity type drift region 21 is formed by epitaxy or injection push junction.

[0080] Preferably, the trench dielectric layer 32 is formed by depositing oxide after trenching, and the cross-sectional shape is circular, trapezoidal, elliptical, or hexagonal; and / or the trench dielectric layer 32 is SiO2; and / or the trench dielectric layer 32 is a low-K or high-K dielectric.

[0081] Preferably, the device is a bulk silicon device or an SOI structure; and in addition to LDMOS devices, it is also used for LIGBT devices; and / or the device structure is one of a single RESURF structure, a double RESURF structure, or a triple RESURF structure.

[0082] Preferably, the drift region metal electrode 51 can be replaced with doped polycrystalline silicon.

[0083] Preferably, the first conductivity type substrate 11 is an SOI substrate or a sapphire substrate.

[0084] Preferably, the semiconductor material can be Si or SiC.

[0085] Example 2

[0086] Example 2 provides an active depletion device based on potential clamping bias coupling and its manufacturing method. The cross-sectional view and top view of its cell region are shown in Figures 2(a) and 2(b), respectively. The structural difference between this example and Example 1 is that the size of the trench and the overall process are adjusted. The deep trench etching of the MIS array is placed after the formation of the resistive field plate polysilicon 42, and the contact hole metal 52 replaces the drift region metal electrode 51 as the electrode within the trench. Its working principle is basically the same as that of Example 1.

[0087] Figure 9 shows a schematic diagram of the process flow of Embodiment 2 of the present invention, which specifically includes the following steps:

[0088] Step 1: Epitaxial growth or implantation push junction is performed on the first conductivity type substrate 11 to obtain the second conductivity type drift region 21; as shown in Figure 9(a);

[0089] Step 2: Thermal oxidation growth of field oxide layer 31; as shown in Figure 9(b);

[0090] Step 3: Inject the first conductivity type well region 12 and the second conductivity type well region 22; as shown in Figure 9(c);

[0091] Step 4: Thermally oxidize to grow gate oxide layer 33, deposit and etch to form control gate polysilicon 41 and resistive field plate polysilicon 42, and implant to activate second conductivity type source contact region 23, second conductivity type drain contact region 24 and first conductivity type body contact region 13; as shown in Figure 9(d);

[0092] Step 5: Select the etching distance and form adjacent, staggered cylindrical groove structures between the polysilicon 42 resistive field plates through photolithography and etching; as shown in Figure 9(e);

[0093] Step 6: Deposit an oxide layer to form the tank medium layer 31 and the interlayer medium 34; as shown in Figure 9(f);

[0094] Step 7: Etch the deposited metal to form contact hole metal 52 and make the contact hole metal 52 extend into the trench. Then deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56; as shown in Figure 9(g).

[0095] Example 3

[0096] Example 3 provides an active depletion device based on potential clamping bias coupling and its manufacturing method. The cross-sectional view and top view of its cell region are shown in Figures 3(a) and (b), respectively. The structural difference between this example and Example 1 is that the overall process is adjusted, placing the deep trench etching of the MIS array before the formation of the field oxide layer 31, and using the drift region polysilicon electrode 43 instead of the drift region metal electrode 51 as the in-trench electrode. Its working principle is basically the same as that of Example 1.

[0097] Figure 10 shows a schematic diagram of the process flow of Embodiment 3 of the present invention, which specifically includes the following steps:

[0098] Step 1: Epitaxial growth or implantation push junction is performed on the substrate 11 of the first conductivity type to obtain the drift region 21 of the second conductivity type; as shown in Figure 10(a);

[0099] Step 2: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure through photolithography and etching; as shown in Figure 10(b);

[0100] Step 3: Deposit oxide in the tank to form the tank dielectric layer 31, and after etching, deposit doped polysilicon again to form the drift region polysilicon electrode 43; as shown in Figure 10(c);

[0101] Step 4: Thermal oxidation growth of field oxide layer 31; as shown in Figure 10(d);

[0102] Step 5: Inject the first conductivity type well region 12 and the second conductivity type well region 22; as shown in Figure 10(e);

[0103] Step 6: Thermally oxidize to grow gate oxide layer 33, deposit and etch to form control gate polysilicon 41 and resistive field plate polysilicon 42, and implant to activate second conductivity type source contact region 23, second conductivity type drain contact region 24 and first conductivity type body contact region 13; as shown in Figure 10(f);

[0104] Step 7: Deposit interlayer dielectric 34, etch deposited metal to form contact hole metal 52, deposit metal again and etch to form equipotential ring metal 53, source metal 54, gate metal 55 and drain metal 56; as shown in Figure 10(g).

[0105] Preferably, the polycrystalline silicon electrode 43 in the drift region can be replaced with metal.

[0106] Example 4

[0107] like Figure 4 The diagram shown is a schematic of an active depletion device structure based on potential clamping bias coupling in Example 4. The difference between this example and Example 1 is that this example does not include an equipotential ring metal 53; instead, it is coupled to the resistive polysilicon field plate 42 only by the contact hole metal 52. The remaining fabrication process and working principle are consistent with Example 1.

[0108] include:

[0109] The system comprises a first conductivity type substrate 11, a second conductivity type drift region 21, a first conductivity type well region 12 and a second conductivity type well region 22, a field oxide layer 31, a trench dielectric layer 32, a gate oxide layer 33, an interlayer dielectric 34, a control gate polysilicon 41, a resistive field plate polysilicon 42, a drift region metal electrode 51, a contact hole metal 52, a source metal 54, a gate metal 55, a drain metal 56, a second conductivity type source contact region 23, a second conductivity type drain contact region 24, and a first conductivity type body contact region 13.

[0110] In this configuration, the second conductivity type drift region 21 is located above the first conductivity type substrate 11, the first conductivity type well region 12 is located to the left of the second conductivity type drift region 21, and the second conductivity type well region 22 is located to the right of the second conductivity type drift region 21; the second conductivity type drain contact region 24 is located in the second conductivity type well region 22 and is connected to the drain metal 56 above it; the second conductivity type source contact region 23 and the first conductivity type body contact region 13 are located in the first conductivity type well region 12 and are connected to the source metal 54 above them; the gate oxide layer 33 is located above the first conductivity type well region 12, and the gate oxide layer... The left end of the gate oxide layer 33 is in contact with the source contact region 23 of the second conductivity type, and the right end is in contact with the drift region 21 of the second conductivity type. The field oxide layer 31 is located on the upper surface of the drift region 21 of the second conductivity type between the left gate oxide layer 33 and the right second conductivity type drain contact region 24. The control gate polysilicon 41 covers the upper surface of the gate oxide layer 33 and extends to the upper surface of the field oxide layer 31 in part. The resistive field plate polysilicon 42 is spirally coiled on the upper surface of the field oxide layer 31, and the first end extends to the upper surface of the drain contact region 24 of the second conductivity type and is connected to the drain metal 56, and the tail end is connected to the control gate polysilicon 41.

[0111] The trench dielectric layer 32, the drift region metal electrode 51, and the contact hole metal 52 constitute a MIS array, which is distributed throughout the drift region 21 of the second conductivity type. The drift region metal electrode 51 of the cell region is connected to the gate metal 55 through the contact hole metal 52, while the drift region metal electrode 51 of the terminal region is floating. The horizontal direction from the source region to the drain region of the device is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction. The MIS array is staggered in the z direction.

[0112] Example 5

[0113] Figures 5(a) and 5(b) show schematic diagrams of an active depletion device structure based on potential clamping bias coupling in Example 5. The difference between this example and Example 1 is that the resistive polysilicon field plate 42 in this example is a double-helix arrangement with simultaneous leads at both ends. Its working principle is basically the same as that of Example 1.

[0114] Example 6

[0115] Figures 6(a), 6(b), and 6(c) show schematic diagrams of an active depletion device structure based on potential clamping bias coupling in Example 6. The difference between this example and Example 1 is that the resistive polysilicon field plate 42 in this example consists of multiple equally spaced rings connected by staggered lines in the terminal region. The remaining working principle is the same as in Example 1.

[0116] Example 7

[0117] Figures 7(a) and 7(b) show schematic diagrams of an active depletion device structure based on potential clamping bias coupling in Example 7. The difference between this example and Example 1 is that the MIS array in the terminal region is changed from discrete slots to a continuous semi-circular annular slot, which has a stronger terminal withstand voltage capability. The rest of the working principle is the same as in Example 1.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An active depletion device based on potential clamping bias coupling, characterized in that... include: The substrate (11) of the first conductivity type, the drift region (21) of the second conductivity type, the well region (12) of the first conductivity type and the well region (22) of the second conductivity type, the field oxide layer (31), the trench dielectric layer (32), the gate oxide layer (33), the interlayer dielectric (34), the control gate polysilicon (41), the resistive field plate polysilicon (42), the drift region metal electrode (51), the contact hole metal (52), the equipotential ring metal (53), the source metal (54), the gate metal (55), the drain metal (56), the source contact region (23) of the second conductivity type, the drain contact region (24) of the second conductivity type and the body contact region (13) of the first conductivity type; Among them, the second conductivity type drift region (21) is located above the first conductivity type substrate (11), the first conductivity type well region (12) is located to the left of the second conductivity type drift region (21), and the second conductivity type well region (22) is located to the right of the second conductivity type drift region (21); the second conductivity type drain contact region (24) is located in the second conductivity type well region (22) and is connected to the drain metal (56) above it; the second conductivity type source contact region (23) and the first conductivity type body contact region (13) are located in the first conductivity type well region (12) and are connected to the source metal (54) above them; the gate oxide layer (33) is located above the first conductivity type well region (12), and the gate oxide layer... (33) The left end is in contact with the source contact region (23) of the second conductivity type, and the right end is in contact with the drift region (21) of the second conductivity type; the field oxide layer (31) is located on the upper surface of the drift region (21) of the second conductivity type between the left gate oxide layer (33) and the right second conductivity type drain contact region (24); the control gate polysilicon (41) covers the upper surface of the gate oxide layer (33) and extends to the upper surface of the field oxide layer (31); the resistive field plate polysilicon (42) is spirally coiled on the upper surface of the field oxide layer (31), and the first end extends to the upper surface of the second conductivity type drain contact region (24) and is connected to the drain metal (56), and the tail end is connected to the control gate polysilicon (41); The trench dielectric layer (32) and the drift region metal electrode (51) constitute a MIS array, which is distributed throughout the second conductivity type drift region (21). The drift region metal electrode (51) of the cell region is connected to the equipotential ring metal (53) and gate metal (55) distributed at equal intervals above through the contact hole metal (52), while the drift region metal electrode (51) of the terminal region is floating. The horizontal direction from the source region to the drain region of the device is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction. The MIS array is staggered in the z direction.

2. The active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: The first conductivity type drift region (21) is formed by epitaxy or injection push junction.

3. The active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: The trench dielectric layer (32) is formed by depositing oxide after grooving, and the cross-sectional shape is circular, trapezoidal, elliptical or hexagonal; and / or the trench dielectric layer (32) is SiO2, or a low K or high K dielectric.

4. The active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: The device is a bulk silicon device or an SOI structure; and in addition to LDMOS devices, it is also used for LIGBT devices; and / or the device structure is one of a single RESURF structure, a double RESURF structure, or a triple RESURF structure.

5. An active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: The first type of conductive substrate (11) is an SOI substrate or a sapphire substrate.

6. An active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: Semiconductor materials use Si or SiC materials.

7. An active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: The resistive field plate polycrystalline silicon (42) is arranged in a single spiral or double spiral shape, or in multiple equally spaced rings connected by staggered lines in the terminal area.

8. An active depletion device based on potential clamping bias coupling according to claim 1, characterized in that: The MIS array in the terminal area is a continuous semi-circular groove.

9. An active depletion device based on potential clamping bias coupling, characterized in that: include: The substrate (11) of the first conductivity type, the drift region (21) of the second conductivity type, the well region (12) of the first conductivity type and the well region (22) of the second conductivity type, the field oxide layer (31), the trench dielectric layer (32), the gate oxide layer (33), the interlayer dielectric (34), the control gate polysilicon (41), the resistive field plate polysilicon (42), the drift region metal electrode (51), the contact hole metal (52), the source metal (54), the gate metal (55), the drain metal (56), the source contact region (23) of the second conductivity type, the drain contact region (24) of the second conductivity type and the body contact region (13) of the first conductivity type; Among them, the second conductivity type drift region (21) is located above the first conductivity type substrate (11), the first conductivity type well region (12) is located to the left of the second conductivity type drift region (21), and the second conductivity type well region (22) is located to the right of the second conductivity type drift region (21); the second conductivity type drain contact region (24) is located in the second conductivity type well region (22) and is connected to the drain metal (56) above it; the second conductivity type source contact region (23) and the first conductivity type body contact region (13) are located in the first conductivity type well region (12) and are connected to the source metal (54) above them; the gate oxide layer (33) is located above the first conductivity type well region (12), and the gate oxide layer... (33) The left end is in contact with the source contact region (23) of the second conductivity type, and the right end is in contact with the drift region (21) of the second conductivity type; the field oxide layer (31) is located on the upper surface of the drift region (21) of the second conductivity type between the left gate oxide layer (33) and the right second conductivity type drain contact region (24); the control gate polysilicon (41) covers the upper surface of the gate oxide layer (33) and extends to the upper surface of the field oxide layer (31); the resistive field plate polysilicon (42) is spirally coiled on the upper surface of the field oxide layer (31), and the first end extends to the upper surface of the second conductivity type drain contact region (24) and is connected to the drain metal (56), and the tail end is connected to the control gate polysilicon (41); The trench dielectric layer (32), the drift region metal electrode (51), and the contact hole metal (52) constitute a MIS array, which is distributed throughout the second conductivity type drift region (21). The drift region metal electrode (51) of the cell region is connected to the gate metal (55) through the contact hole metal (52), while the drift region metal electrode (51) of the terminal region is floating. The horizontal direction from the source region to the drain region of the device is the x direction, the downward direction of the drift region polysilicon electrode is the y direction, and the inward direction perpendicular to the xy plane is the z direction. The MIS array is staggered in the z direction.

10. A method for manufacturing an active depletion device based on potential clamping bias coupling, used to prepare the active depletion device according to any one of claims 1 to 8, characterized in that... Includes the following steps: Step 1: Epitaxial growth or implantation push junction is performed on the first conductivity type substrate (11) to obtain the second conductivity type drift region (21); Step 2: Thermal oxidation growth of field oxide layer (31); Step 3: Inject the first conductivity type well region (12) and the second conductivity type well region (22); Step 4: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure through photolithography and etching; Step 5: Deposit to form a tank medium layer (32) covering the tank wall; Step 6: Deposit metal onto the lower surface of the field oxide layer to form a drift region metal electrode (51); Step 7: Deposit and fill the empty space above the trench, and thermally oxidize to grow a gate oxide layer (33); Step 8: Deposit and etch to form gate polysilicon (41) and resistive field plate polysilicon (42), and implant to activate the second conductivity type source contact region (23), the second conductivity type drain contact region (24) and the first conductivity type body contact region (13); Step 9: Deposit interlayer dielectric (34), etch deposited metal to form contact hole metal (52), deposit metal again and etch to form equipotential ring metal (53), source metal (54), gate metal (55) and drain metal (56).

11. A method for manufacturing an active depletion device based on potential clamping bias coupling, used to prepare the active depletion device according to any one of claims 1 to 8, characterized in that: The deep trench etching of the MIS array is performed after the formation of the resistive field plate polysilicon (42), and the contact hole metal (52) is used instead of the drift region metal electrode (51) as the in-trench electrode.

12. The method for manufacturing an active depletion device based on potential clamping bias coupling according to claim 11, characterized in that... Includes the following steps: Step 1: Epitaxial growth or implantation push junction is performed on the first conductivity type substrate (11) to obtain the second conductivity type drift region (21); Step 2: Thermal oxidation growth of field oxide layer (31); Step 3: Inject the first conductivity type well region (12) and the second conductivity type well region (22); Step 4: Thermal oxidation to grow gate oxide layer (33), deposition and etching to form gate polysilicon (41) and resistive field plate polysilicon (42), and implantation to activate second conductivity type source contact region (23), second conductivity type drain contact region (24) and first conductivity type body contact region (13); Step 5: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure between the resistive field plate polysilicon (42) through photolithography and etching; Step 6: Deposit an oxide layer to form a tank medium layer (31) and an interlayer medium (34); Step 7: Etch the deposited metal to form contact hole metal (52) and make the contact hole metal (52) penetrate into the trench. Then deposit metal again and etch to form equipotential ring metal (53), source metal (54), gate metal (55) and drain metal (56).

13. A method for manufacturing an active depletion device based on potential clamping bias coupling, used to prepare the active depletion device according to any one of claims 1 to 8, characterized in that: The deep trench etching of the MIS array is placed before the formation of the field oxide layer (31), and the drift region polysilicon electrode (43) is used instead of the drift region metal electrode (51) as the in-trench electrode.

14. A method for manufacturing an active depletion device based on potential clamping bias coupling according to claim 13, characterized in that... Includes the following steps: Step 1: Epitaxial growth or implantation push junction is performed on the first conductivity type substrate (11) to obtain the second conductivity type drift region (21); Step 2: Select the etching distance and form a pair of adjacent, staggered cylindrical groove structure through photolithography and etching; Step 3: Deposit oxide in the tank to form a tank dielectric layer (31), and after etching, deposit doped polysilicon again to form a drift region polysilicon electrode (43); Step 4: Thermal oxidation growth of field oxide layer (31); Step 5: Inject the first conductivity type well region (12) and the second conductivity type well region (22); Step 6: Thermal oxidation to grow gate oxide layer (33), deposition and etching to form gate polysilicon (41) and resistive field plate polysilicon (42), and implantation to activate second conductivity type source contact region (23), second conductivity type drain contact region (24) and first conductivity type body contact region (13); Step 7: Deposit interlayer dielectric (34), etch deposited metal to form contact hole metal (52), deposit metal again and etch to form equipotential ring metal (53), source metal (54), gate metal (55) and drain metal (56).

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