Solar cell, photovoltaic module and method for preparing solar cell

Abstract

The present application relates to a solar cell, a photovoltaic module and a method for preparing a solar cell. The solar cell includes a semiconductor substrate having a first surface and a second surface arranged opposite to each other; a first doping layer arranged on the first surface; wherein the first doping layer includes a plurality of sub-doping layers arranged along the thickness direction of the semiconductor substrate, and the crystallization rates of the plurality of sub-doping layers increase in sequence along the direction away from the semiconductor substrate. Therefore, the solar cell, photovoltaic module and method for preparing a solar cell provided in the present application can improve the conversion efficiency of the solar cell.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a method for preparing a solar cell. Background Art

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that convert sunlight directly into electrical energy. As they are green and environmentally friendly products that do not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] Among the related technologies, heterojunction cells have the advantages of simple structure, low process temperature, good passivation effect, high open circuit voltage, good temperature characteristics, and double-sided power generation. They are one of the hot directions of high-conversion-efficiency silicon-based solar cells.

[0004] However, the conversion efficiency of the above heterojunction solar cells needs to be improved. Summary of the invention

[0005] Based on this, it is necessary to provide a solar cell, a photovoltaic module and a method for preparing a solar cell, which can improve the conversion efficiency of the solar cell.

[0006] In a first aspect, an embodiment of the present application provides a solar cell, comprising:

[0007] A semiconductor substrate having a first surface and a second surface arranged opposite to each other;

[0008] A first doping layer, disposed on the first surface;

[0009] The first doped layer includes a plurality of sub-doped layers arranged along the thickness direction of the semiconductor substrate, and the crystallinity rates of the plurality of sub-doped layers increase in sequence along a direction away from the semiconductor substrate.

[0010] The solar cell provided in the embodiment of the present application comprises a plurality of sub-doping layers arranged along the thickness direction of the semiconductor substrate through the first doping layer, and the crystallization rates of the plurality of sub-doping layers increase successively along the direction away from the semiconductor substrate. On the one hand, the crystallization rate of the sub-doping layer closest to the semiconductor substrate is lower, which can make up for the insufficient passivation of the film layer on the first side, improve the field effect passivation capability of the film layer on the first side, and thus improve the battery conversion efficiency. It can also increase the barrier height and width of the valence band part of the film layer on the first side, improve the carrier extraction capability and the open circuit voltage. On the other hand, the crystallization rate of the sub-doping layer farthest from the semiconductor substrate is higher, which is beneficial to reduce the resistance of the first doping layer, increase the fill factor of the first doping layer, and improve the battery conversion efficiency.

[0011] In one embodiment, among the multiple sub-doping layers, the sub-doping layer closest to the semiconductor substrate is the first sub-doping layer, the first sub-doping layer is an amorphous doping layer, and the sub-doping layer farthest from the semiconductor substrate is the second sub-doping layer, the second sub-doping layer is a microcrystalline doping layer.

[0012] In one embodiment, the plurality of sub-doping layers further include a third sub-doping layer, and the third sub-doping layer is disposed between the first sub-doping layer and the second sub-doping layer;

[0013] The crystallinity of the third sub-doping layer is between that of the first sub-doping layer and the second sub-doping layer.

[0014] In one embodiment, among the multiple sub-doped layers, the crystallization rate of the sub-doped layer closest to the semiconductor substrate is 0, and the crystallization rate of the sub-doped layer farthest from the semiconductor substrate is less than or equal to 60%.

[0015] In one embodiment, the thickness of the first doping layer is in the range of 13 nm to 18 nm;

[0016] and / or, a ratio of the thickness of the first sub-doped layer to the thickness of the first doped layer is less than or equal to 20%;

[0017] And / or, the doping type of the first doping layer is the same as the doping type of the semiconductor substrate.

[0018] In one embodiment, the solar cell further comprises a first doped contact layer, the first doped contact layer being disposed on a side of the first doped layer facing away from the semiconductor substrate;

[0019] The doping concentration of the first doped contact layer is greater than the doping concentration of the first doping layer.

[0020] In one embodiment, the solar cell includes a second doping layer, the second doping layer is disposed on the second surface, and the doping type of the second doping layer is opposite to the doping type of the first doping layer;

[0021] The second doped layer includes a seed layer and a main layer arranged in a direction away from the semiconductor substrate, and the crystallization rate of the seed layer is greater than the crystallization rate of the main layer.

[0022] In one embodiment, the solar cell further comprises a second doped contact layer, and the second doped contact layer is disposed on a side of the second doped layer facing away from the semiconductor substrate;

[0023] The crystallization rate of the second doped contact layer is lower than the crystallization rate of the seed layer; and / or the doping concentration of the second doped contact layer is higher than the doping concentration of the main layer.

[0024] In one embodiment, the crystallization rate of the seed layer is greater than or equal to 50%;

[0025] and / or, the thickness of the seed layer is greater than or equal to 1 nm;

[0026] and / or, the crystallinity of the main layer is greater than or equal to 20%;

[0027] And / or, the thickness of the main layer is greater than or equal to 10 nm.

[0028] In one embodiment, the crystallinity of the second doped contact layer is greater than or equal to 20%;

[0029] And / or, the thickness of the second doped contact layer is greater than or equal to 1 nm.

[0030] In one embodiment, the solar cell includes a first grid line and a second grid line, the first grid line is arranged on a side of the first doped layer away from the semiconductor substrate, and the second grid line is arranged on a side of the second doped layer away from the semiconductor substrate;

[0031] The arrangement density of the first gate lines is less than the arrangement density of the second gate lines.

[0032] In a second aspect, an embodiment of the present application provides a photovoltaic assembly, comprising the solar cell of the first aspect.

[0033] The photovoltaic module provided in the embodiment of the present application includes a solar cell, in which the first doping layer includes multiple sub-doping layers arranged along the thickness direction of the semiconductor substrate, and the crystallization rates of the multiple sub-doping layers increase successively in the direction away from the semiconductor substrate. On the one hand, the crystallization rate of the sub-doping layer closest to the semiconductor substrate is lower, which can make up for the insufficient passivation of the film layer on the first side, improve the field effect passivation ability of the film layer on the first side, and thus improve the battery conversion efficiency. It can also increase the barrier height and width of the valence band part of the film layer on the first side, improve the carrier extraction ability and open circuit voltage. On the other hand, the crystallization rate of the sub-doping layer farthest from the semiconductor substrate is higher, which is beneficial to reduce the resistance of the first doping layer, increase the fill factor of the first doping layer, and improve the battery conversion efficiency.

[0034] In a third aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0035] Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other;

[0036] A plurality of sub-doping layers are deposited on the first surface to form a first doping layer; wherein different sub-doping layers have different deposition powers, and during the deposition process of the plurality of sub-doping layers, the deposition powers are sequentially increased.

[0037] The method for preparing a solar cell provided in an embodiment of the present application is used to prepare a solar cell. The first doping layer includes multiple sub-doping layers arranged along the thickness direction of the semiconductor substrate. The crystallization rates of the multiple sub-doping layers increase successively in the direction away from the semiconductor substrate. On the one hand, the crystallization rate of the sub-doping layer closest to the semiconductor substrate is lower, which can make up for the insufficient passivation of the film layer on the first side, improve the field effect passivation ability of the film layer on the first side, and thus improve the battery conversion efficiency. It can also increase the barrier height and width of the valence band part of the film layer on the first side, improve the carrier extraction ability and open circuit voltage. On the other hand, the crystallization rate of the sub-doping layer farthest from the semiconductor substrate is higher, which is beneficial to reducing the resistance of the first doping layer, increasing the fill factor of the first doping layer, and improving the battery conversion efficiency.

[0038] In one of the embodiments, during the deposition of the plurality of sub-doped layers, the deposition power is increased from 130 mW / cm2 to 400 mW / cm2.

[0039] In one embodiment, the process gas of the deposition process includes a silicon-containing gas and an oxygen-containing gas, and the ratio of the flow rate of the oxygen-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 0.6;

[0040] and / or, the process gas of the deposition process includes a silicon-containing gas and a phosphorus-containing gas, and the ratio of the flow rate of the phosphorus-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 0.05;

[0041] And / or, the process gas of the deposition process includes a silicon-containing gas and a hydrogen-containing gas, and the ratio of the flow rate of the hydrogen-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 150;

[0042] and / or, the process gas of the deposition process includes a hydrogen-containing gas, and the flow rate of the hydrogen-containing gas is greater than or equal to 30,000 sccm;

[0043] And / or, the chamber pressure of the deposition process is greater than or equal to 3 mbar. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A cross-sectional view of a solar cell provided in an embodiment of the present application.

[0045] Figure 2 A cross-sectional view of a second doping group provided in an embodiment of the present application.

[0046] Figure 3 A schematic diagram of the process of preparing a solar cell provided in an embodiment of the present application.

[0047] Figure 4 A schematic diagram of the structure after providing a semiconductor substrate is provided in an embodiment of the present application.

[0048] Figure 5A schematic diagram of the structure after the first doping layer is formed according to an embodiment of the present application.

[0049] Description of reference numerals:

[0050] 100, solar cell; 102, second doping group; 110, first doping layer; 111a, sub-doping layer; 111, first sub-doping layer; 112, second sub-doping layer; 113, third sub-doping layer; 120, second doping layer; 121, seed layer; 122, main layer; 131, first doped contact layer; 132, second doped contact layer; 141, first gate line; 142, second gate line; 151, first intrinsic semiconductor layer; 152, second intrinsic semiconductor layer; 161, first transparent conductive layer; 162, second transparent conductive layer; 170, semiconductor substrate; 171, first surface; 172, second surface. DETAILED DESCRIPTION

[0051] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0052] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0053] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0054] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0055] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0056] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0057] In the related art, a heterojunction cell may include a semiconductor substrate having a first surface and a second surface arranged opposite to each other, an intrinsic passivation layer and an N-type microcrystalline silicon layer are arranged on the first surface, and the N-type microcrystalline silicon layer is located on the side of the intrinsic passivation layer away from the semiconductor substrate. The intrinsic passivation layer can improve the photoelectric conversion efficiency by reducing the surface recombination rate, and can also protect the heterojunction cell from the erosion of the external environment and enhance the stability of the heterojunction cell. Among them, the intrinsic passivation layer and the N-type microcrystalline silicon layer can be arranged close to the light-facing surface of the heterojunction cell.

[0058] However, in order to reduce the parasitic absorption of the intrinsic passivation layer, the thickness of the intrinsic passivation layer is set to be relatively small, which results in insufficient passivation of the heterojunction battery and further leads to low photoelectric conversion efficiency.

[0059] To solve the above problems, the embodiments of the present application provide a solar cell, a photovoltaic module and a method for preparing a solar cell, which can improve the insufficient passivation of the solar cell and thus improve the photoelectric conversion efficiency.

[0060] The following will be combined Figure 1-Figure 5 The solar cell 100, the photovoltaic module and the method for preparing the solar cell 100 provided in the embodiments of the present application are described.

[0061] The embodiment of the present application provides a solar cell 100, which may include a heterojunction cell (HJT), an interdigitated back contact cell (IBC), a heterojunction back contact cell (HBC), or a tunnel oxide passivating contact cell (TOPCON). The embodiment of the present application is described by taking a heterojunction cell as an example.

[0062] See also Figure 1 The solar cell 100 includes a semiconductor substrate 170, which can provide support for the film layers to be formed subsequently. The semiconductor substrate 170 can be used to receive incident light and generate photogenerated carriers.

[0063] For example, see Figure 1 The semiconductor substrate 170 may have a thickness along the thickness direction of the semiconductor substrate 170 (ie Figure 1 The solar cell 100 includes a first surface 171 and a second surface 172 that are arranged opposite to each other in a direction Z, and at least one of the first surface 171 and the second surface 172 can be used to receive sunlight. The embodiment of the present application is described by taking the first surface 171 being used to receive sunlight as an example, that is, the first surface 171 is close to the light-facing surface of the solar cell 100, and the second surface 172 is close to the backlight surface of the solar cell 100.

[0064] For example, the semiconductor substrate 170 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon and polycrystalline silicon. The present application embodiment is described by taking single crystal silicon as an example.

[0065] Exemplarily, the doping type of the semiconductor substrate 170 may be N-type doping, which may be achieved by doping N-type ions, and the N-type ions may include at least one of phosphorus, arsenic, and antimony. Alternatively, the doping type of the semiconductor substrate 170 may be P-type doping, which may be achieved by doping P-type ions, and the P-type ions may include at least one of aluminum and boron. The embodiment of the present application is described by taking the doping type of the semiconductor substrate 170 as N-type doping as an example.

[0066] In some embodiments, at least one of the first surface 171 and the second surface 172 may have a velvet structure. The velvet structure may be a pyramid velvet, an etched pit velvet, etc. The velvet structure has a lower reflectivity to incident light, and thus has a higher absorption rate to incident light, so that the photoelectric conversion efficiency of the solar cell 100 is higher.

[0067] Exemplarily, the size of the textured structure along the thickness direction of the semiconductor substrate 170 ranges from 1 μm to 3 μm.

[0068] For example, the crystal phase of the textured structure may be a 111 crystal phase.

[0069] See also Figure 1 The solar cell 100 includes a first doping layer 110, which is disposed on the first surface 171. The first doping layer 110 has a relatively low resistance, and can effectively reduce the current loss and increase the conductivity. The doping type of the first doping layer 110 may be the same as the doping type of the semiconductor substrate 170, and the doping type of the first doping layer 110 may be N-type doping.

[0070] For example, see Figure 1 The first doping layer 110 includes a plurality of sub-doping layers 111a arranged along the thickness direction of the semiconductor substrate 170, and the crystallinity of the plurality of sub-doping layers 111a increases in sequence along the direction from the second surface 172 to the first surface 171. Among the plurality of sub-doping layers 111a, the sub-doping layer 111a closest to the semiconductor substrate 170 is the first sub-doping layer 111, and the sub-doping layer 111a farthest from the semiconductor substrate 170 is the second sub-doping layer 112. On the one hand, the crystallinity of the first sub-doping layer 111 is low, which can make up for the insufficient passivation of the film layer on the first surface 171, improve the field effect passivation ability of the film layer on the first surface 171, and thus improve the battery conversion efficiency. It can also increase the barrier height and width of the valence band part of the film layer on the first surface 171, improve the carrier extraction ability and the open circuit voltage. On the other hand, the crystallinity of the second sub-doping layer 112 is high, which is conducive to reducing the resistance of the first doping layer 110, increasing the filling factor of the first doping layer 110, and improving the battery conversion efficiency.

[0071] In some embodiments, the first sub-doped layer 111 is an amorphous doped layer, and the crystallization rate of the first sub-doped layer 111 is 0, which can better compensate for the insufficient passivation of the film layer on the first surface 171, enhance the field effect passivation capability of the film layer on the first surface 171, and thereby enhance the battery conversion efficiency. In addition, the barrier height and width of the valence band portion of the film layer on the first surface 171 can also be increased to enhance the open circuit voltage.

[0072] In some embodiments, the second sub-doping layer 112 is a microcrystalline doping layer, and the crystallization rate of the second sub-doping layer 112 can be set to be higher, which is beneficial to reducing the resistance of the first doping layer 110, improving the carrier transmission efficiency, increasing the fill factor of the first doping layer 110, and improving the battery conversion efficiency.

[0073] Exemplarily, the crystallization rate of the second sub-doped layer 112 is less than or equal to 60%, thereby preventing the crystallization rate of the second sub-doped layer 112 from being too large, which helps to reduce the difficulty of preparing the second sub-doped layer 112. For example, the crystallization rate of the second sub-doped layer 112 can be 20%, 30%, 40%, 50%, 60%, or any value less than 60%.

[0074] In some embodiments, see Figure 1 The multiple sub-doping layers 111a may further include a third sub-doping layer 113, the crystallization rate of the third sub-doping layer 113 is between the first sub-doping layer 111 and the second sub-doping layer 112, the first sub-doping layer 111 and the second sub-doping layer 112 are transitioned through the third sub-doping layer 113, so that the crystallization rate between the first sub-doping layer 111 and the third sub-doping layer 113 changes less, so that the energy band can transition smoothly, making it easier for carriers to pass through the first doping layer 110, which is beneficial to the transmission of carriers.

[0075] Exemplarily, the number of sub-doping layers 111a in the first doping layer 110 may be 2, 3, 4, 5 or any number greater than 5. For example, at least one sub-doping layer 111a may be disposed between the second sub-doping layer 112 and the third sub-doping layer 113 .

[0076] The embodiment of the present application is described by taking the number of the sub-doping layers 111a in the first doping layer 110 as 5 as an example. A fourth sub-doping layer 114 and a fifth sub-doping layer 115 may be further provided between the second sub-doping layer 112 and the third sub-doping layer 113, wherein the crystallization rates of the third sub-doping layer 113, the fourth sub-doping layer 114, the fifth sub-doping layer 115 and the second sub-doping layer 112 increase in sequence, and all of them are microcrystalline doping layers.

[0077] Exemplarily, the thickness of the first doping layer 110 ranges from 13 nm to 18 nm, so that the thickness of the first doping layer 110 can be prevented from being too thin, the difficulty of preparing the multiple sub-doping layers 111 a of the first doping layer 110 can be reduced, and the thickness of the first doping layer 110 can be prevented from being too thick, so as to avoid excessive parasitic absorption and resulting in reduced current. For example, the thickness of the first doping layer 110 can be 13 nm, 15 nm, 17 nm, 18 nm, or any value between 13 nm and 18 nm.

[0078] It should be noted that the first sub-doping layer 111 is an amorphous doping layer, the material of the amorphous doping layer includes amorphous material. The second sub-doping layer 112 is a microcrystalline doping layer, the material of the microcrystalline doping layer includes amorphous material and microcrystalline material, that is, the microcrystalline doping layer is a mixture of amorphous material and microcrystalline material.

[0079] Exemplarily, the ratio of the thickness of the first sub-doping layer 111 to the thickness of the first doping layer 110 is less than or equal to 20%, so that the thickness of the first sub-doping layer 111 can be prevented from being too thick, so as to prevent excessive parasitic absorption and thus reduce the current. For example, the ratio of the thickness of the first sub-doping layer 111 to the thickness of the first doping layer 110 is 5%, 10%, 15%, 20%, or any value less than 20%.

[0080] In some embodiments, see Figure 1 The solar cell 100 further includes a first doped contact layer 131, which is located on the side of the first doped layer 110 away from the semiconductor substrate 170. The doping concentration of the first doped contact layer 131 is greater than the doping concentration of the first doped layer 110, which is beneficial to improve the conductivity of the first doped contact layer 131, so that the first doped contact layer 131 forms a good ohmic contact with the first transparent conductive layer 161, and reduces the contact resistance between the first doped contact layer 131 and the first transparent conductive layer 161. The doping type of the first doped contact layer 131 is the same as the doping type of the first doped layer 110.

[0081] Exemplarily, the thickness of the first doped contact layer 131 is less than or equal to 3 nm, so that the thickness of the first doped contact layer 131 can be avoided to be too large, so as to avoid excessive parasitic absorption and resulting in a decrease in current.

[0082] Exemplarily, the first doped contact layer 131 may be an amorphous doped layer or a microcrystalline doped layer with a high crystallinity.

[0083] In some embodiments, see Figure 1 and Figure 2The solar cell 100 includes a second doping group 102. The second doping group 102 may include a second doping layer 120. The second doping layer 120 is disposed on the second surface 172. For example, the doping type of the second doping layer 120 is opposite to the doping type of the first doping layer 110.

[0084] The doping type of one of the first doping layer 110 and the second doping layer 120 is N-type doping, and the other is P-type doping. The present embodiment is described by taking the first doping layer 110 as N-type doping and the second doping layer 120 as P-type doping as an example.

[0085] In some embodiments, see Figure 1 and Figure 2 The second doping layer 120 includes a seed layer 121 and a main layer 122 arranged in sequence from the first surface 171 to the second surface 172. The crystallization rate of the seed layer 121 is greater than that of the main layer 122. The seed layer 121 can be formed on the semiconductor substrate 170 before the main layer 122. Setting the crystallization rate of the seed layer 121 to be higher can accelerate the subsequent crystallization of the main layer 122, so as to improve the crystallization rate of the main layer 122.

[0086] In some embodiments, see Figure 1 and Figure 2 The second doping group 102 may further include a second doped contact layer 132, which is located on the side of the second doped layer 120 away from the semiconductor substrate 170, and the doping concentration of the second doped contact layer 132 is greater than the doping concentration of the main layer 122, thereby facilitating the improvement of the conductivity of the second doped contact layer 132, so that the second doped contact layer 132 forms a good ohmic contact with the second transparent conductive layer 162, and reduces the contact resistance between the second doped contact layer 132 and the second transparent conductive layer 162. For example, the doping type of the second doped contact layer 132 is the same as the doping type of the second doped layer 120.

[0087] In some embodiments, the crystallization rate of the second doped contact layer 132 is less than the crystallization rate of the seed layer 121. For example, the crystallization rate of the second doped contact layer 132 is approximately the same as the crystallization rate of the main layer 122, thereby facilitating the transmission of carriers between the second doped contact layer 132 and the main layer 122.

[0088] Exemplarily, the thickness of the second doping group 102 may range from 20 nm to 40 nm. For example, the thickness of the second doping group 102 may be 20 nm, 29.5 nm, 30 nm, 40 nm, or any value between 20 nm and 40 nm.

[0089] Exemplarily, the crystallization rate of the seed layer 121 is greater than or equal to 50%, so that the crystallization rate of the seed layer 121 is relatively large, which can accelerate the subsequent crystallization of the main layer 122, so as to improve the crystallization rate of the main layer 122. For example, the crystallization rate of the seed layer 121 can be 50%, 55%, 60%, 65% or any value greater than 50%.

[0090] Exemplarily, the thickness of the seed layer 121 is greater than or equal to 1 nm, so as to avoid the seed layer 121 being too thin, which is conducive to reducing the difficulty of preparing the seed layer 121. For example, the thickness of the seed layer 121 can be 1 nm, 1.5 nm, 2 nm, 3 nm or any value greater than 1 nm.

[0091] Exemplarily, the crystallization rate of the main layer 122 is greater than or equal to 20%, which is beneficial to reduce the resistance of the main layer 122, improve the carrier transmission efficiency, increase the fill factor of the main layer 122, and improve the battery conversion efficiency. For example, the crystallization rate of the main layer 122 can be 20%, 30%, 40% or any value greater than 20%.

[0092] Exemplarily, the thickness of the main layer 122 is greater than or equal to 10 nm, so that the thickness of the main layer 122 is relatively large, which is beneficial to reduce the resistance of the main layer 122, improve the carrier transmission efficiency, and improve the battery conversion efficiency. For example, the thickness of the main layer 122 can be 10 nm, 15 nm, 20 nm, 25 nm, or any value greater than 10 nm.

[0093] Exemplarily, the crystallization rate of the second doped contact layer 132 is greater than or equal to 20%, which is beneficial to reduce the resistance of the second doped contact layer 132, improve the carrier transmission efficiency, and help improve the battery conversion efficiency. For example, the crystallization rate of the second doped contact layer 132 can be 20%, 30%, 40% or any value greater than 20%.

[0094] Exemplarily, the thickness of the second doped contact layer 132 is greater than or equal to 1 nm, so that the thickness of the second doped contact layer 132 can be prevented from being too thin, which is helpful to reduce the difficulty of preparing the second doped contact layer 132. For example, the thickness of the second doped contact layer 132 can be 1 nm, 2 nm, 3 nm, or any value greater than 1 nm.

[0095] The first transparent conductive layer 161 and the second transparent conductive layer 162 provided in the embodiment of the present application are described below.

[0096] In some embodiments, see Figure 1The solar cell 100 may include a first transparent conductive layer 161 , which may be located on a side of the first doped contact layer 131 away from the semiconductor substrate 170 . The first transparent conductive layer 161 may collect current generated by the cell and transmit it to the first gate line 141 .

[0097] In some embodiments, see Figure 1 and Figure 2 The solar cell 100 may include a second transparent conductive layer 162 , which may be located on a side of the second doped contact layer 132 away from the semiconductor substrate 170 . The second transparent conductive layer 162 may collect current generated by the cell and transmit it to the second gate line 142 .

[0098] Exemplarily, the material of the transparent conductive layer (the first transparent conductive layer 161 and / or the second transparent conductive layer 162) may include at least one of indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium aluminum zinc oxide (GAZO), tin oxide (SnO2), antimony tin oxide (ATO), fluorine tin oxide (FTO), cerium indium oxide (ICO), and aluminum indium oxide (IWO).

[0099] Exemplarily, the thickness of the transparent conductive layer (the first transparent conductive layer 161 and / or the second transparent conductive layer 162) is less than or equal to 80 nm, which is beneficial to improve the light transmittance of the transparent conductive layer. For example, the thickness of the transparent conductive layer can be 68 nm, 70 nm, 77 nm, 80 nm, or any value less than 80 nm. The thickness of the first transparent conductive layer 161 and the second transparent conductive layer 162 can be the same or different.

[0100] Exemplarily, the refractive index of the transparent conductive layer (the first transparent conductive layer 161 and / or the second transparent conductive layer 162) is less than or equal to 2, which is beneficial to improve the transmittance of the transparent conductive layer. For example, the refractive index of the transparent conductive layer can be 1.7, 1.9, 1.97 or any value less than 2.

[0101] The first intrinsic semiconductor layer 151 and the second intrinsic semiconductor layer 152 provided in the embodiment of the present application are described below.

[0102] In some embodiments, see Figure 1 The solar cell 100 may include a first intrinsic semiconductor layer 151, which is disposed between the semiconductor substrate 170 and the first doping layer 110. The first intrinsic semiconductor layer 151 may play a passivation role, thereby improving the photoelectric conversion efficiency by reducing the surface recombination rate, and protecting the solar cell 100 from the erosion of the external environment, thereby enhancing the stability of the solar cell 100.

[0103] Exemplarily, the thickness of the first intrinsic semiconductor layer 151 ranges from 5nm to 8nm, thereby preventing the first intrinsic semiconductor layer 151 from being too thin, which is beneficial to improving the passivation effect of the first intrinsic semiconductor layer 151, and can also prevent the first intrinsic semiconductor layer 151 from being too thick to avoid excessive parasitic absorption leading to reduced current. In addition, in the embodiment of the present application, the crystallization rate of multiple sub-doped layers 111a is increased successively from the second surface 172 to the first surface 171, which can improve the passivation effect of the film layer on the first surface 171 of the solar cell 100. Therefore, the thickness of the first intrinsic semiconductor layer 151 can be set to be smaller, which is beneficial to reducing the parasitic absorption of the first intrinsic semiconductor layer 151.

[0104] In some embodiments, see Figure 1 and Figure 2 The solar cell 100 includes a second intrinsic semiconductor layer 152, which is disposed between the semiconductor substrate 170 and the second doping layer 120, that is, the second intrinsic semiconductor layer 152 is disposed between the semiconductor substrate 170 and the second doping group 102. The second intrinsic semiconductor layer 152 can play a passivation role, which can improve the photoelectric conversion efficiency by reducing the surface recombination rate, and can also protect the solar cell 100 from erosion by the external environment and enhance the stability of the solar cell 100.

[0105] Exemplarily, the thickness of the second intrinsic semiconductor layer 152 is in the range of 9-12 nm, thereby preventing the second intrinsic semiconductor layer 152 from being too thin, which is beneficial to improving the passivation effect of the second intrinsic semiconductor layer 152, and also preventing the second intrinsic semiconductor layer 152 from being too thick to avoid excessive series resistance.

[0106] The first gate line 141 and the second gate line 142 provided in the embodiment of the present application are described below.

[0107] In some embodiments, the solar cell 100 includes a first gate line 141 , which is located on a side of the first transparent conductive layer 161 away from the semiconductor substrate 170 . The first gate line 141 can collect and transmit photogenerated carriers, thereby realizing solar energy to electrical energy conversion.

[0108] In some embodiments, the solar cell 100 includes a second gate line 142 , which is located on a side of the second transparent conductive layer 162 away from the semiconductor substrate 170 . The second gate line 142 can collect and transmit photogenerated carriers, thereby realizing solar energy to electrical energy conversion.

[0109] Exemplarily, the arrangement density of the first grid lines 141 is less than that of the second grid lines 142, so that the arrangement density of the first grid lines 141 is smaller, which is beneficial to reduce the shielding of the first grid lines 141 on the incident light, so that more light can enter the solar cell 100. In addition, the density of the second grid lines 142 can also be made larger, which is beneficial to the collection and transmission of photogenerated carriers by the second grid lines 142.

[0110] The photovoltaic module provided in the embodiments of the present application is described below.

[0111] The embodiment of the present application further provides a photovoltaic module, which may include the solar cell 100 in the above embodiment. There may be at least one solar cell 100 in the photovoltaic module. The embodiment of the present application is described by taking the case where there are multiple solar cells 100 in the photovoltaic module as an example, and the multiple solar cells 100 together constitute a battery string layer.

[0112] In some embodiments, the photovoltaic module may include a first encapsulation member and a second encapsulation member located on both sides of the battery string layer, and the first encapsulation member and the second encapsulation member encapsulate the battery string layer to protect the battery string layer. The first encapsulation member and the second encapsulation member may include an encapsulation adhesive layer and a cover plate, the encapsulation adhesive layer is located on the side of the cover plate facing the battery string layer, the cover plate can protect the battery string layer, and the encapsulation adhesive layer can be used to connect the cover plate and the battery string layer.

[0113] The following is an explanation of a method for preparing the solar cell 100 provided in an embodiment of the present application.

[0114] The present application embodiment provides a method for preparing a solar cell 100, which can be used to prepare the solar cell 100 in the above embodiment. Figure 3 , the preparation method may include:

[0115] S100: providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface that are opposite to each other.

[0116] First, see Figure 4 , providing a semiconductor substrate 170. The semiconductor substrate 170 has a first surface 171 and a second surface 172 that are opposite to each other.

[0117] Exemplarily, at least one of the first surface 171 and the second surface 172 of the semiconductor substrate 170 may be textured so that at least one of the first surface 171 and the second surface 172 forms a texture structure.

[0118] For example, the velvet structure can be prepared by wet chemical etching, for example, an alkaline solution can be used for velvet preparation, such as a NaOH solution, or chemical etching, laser etching, mechanical method, plasma etching, etc. can be used to prepare the velvet structure.

[0119] Exemplarily, providing the semiconductor substrate 170 may include cleaning and removing damage from a 100 crystalline phase N-type single crystal silicon substrate, then texturing to form a pyramid texture structure of uniform size, then cleaning and removing organic matter and metal ions on the surface of the semiconductor substrate 170, then smoothing the pyramid texture structure, and then removing the oxide layer on the surface of the semiconductor substrate 170 using an HF (hydrofluoric acid) solution.

[0120] S200: depositing a plurality of sub-doping layers on the first surface to form a first doping layer; wherein different sub-doping layers have different deposition powers, and during the deposition of the plurality of sub-doping layers, the deposition powers are sequentially increased.

[0121] See also Figure 5 After providing the semiconductor substrate 170, the method may include depositing a plurality of sub-doping layers 111a on the first surface 171, wherein the plurality of sub-doping layers 111a together constitute the first doping layer 110. The deposition powers of different sub-doping layers 111a are different, and during the deposition of the plurality of sub-doping layers 111a, the deposition powers may be increased sequentially, so that the crystallization rates of the plurality of sub-doping layers 111a are increased sequentially along the direction from the second surface 172 to the first surface 171. Among the multiple sub-doping layers 111a, the sub-doping layer 111a closest to the semiconductor substrate 170 is the first sub-doping layer 111, and the sub-doping layer 111a farthest from the semiconductor substrate 170 is the second sub-doping layer 112. On the one hand, the crystallization rate of the first sub-doping layer 111 is relatively low, which can make up for the insufficient passivation of the film layer on the first surface 171, improve the field effect passivation ability of the film layer on the first surface 171, and improve the conversion efficiency. It can also increase the barrier height and width of the valence band part of the film layer on the first surface 171, and improve the carrier extraction ability and open circuit voltage. On the other hand, the crystallization rate of the second sub-doping layer 112 is relatively high, which is beneficial to reduce the resistance of the first doping layer 110, increase the filling factor of the first doping layer 110, and improve the conversion efficiency.

[0122] Exemplarily, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or reactive plasma deposition (RPD). Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which will not be described in detail.

[0123] For example, during the deposition of the plurality of sub-doped layers 111a, the deposition power is 130 mW / cm 2 Increased to 400mW / cm 2 , so that the crystallization rate of the plurality of sub-doped layers 111a increases from 0 to 50% in the direction away from the semiconductor substrate 170. For example, the deposition power of the first sub-doped layer 111 is 130 mW / cm 2 The deposition power of the third sub-doping layer 113 is 200 mW / cm 2 The deposition power of the fourth sub-doping layer 114 is 260 mW / cm 2 The deposition power of the fifth sub-doping layer 115 is 330 mW / cm 2 The deposition power of the second sub-doping layer 112 is 400 mW / cm 2 .

[0124] Exemplarily, during the deposition of the plurality of sub-doped layers 111a, the process gas of the deposition process includes a silicon-containing gas and an oxygen-containing gas, and the ratio of the flow rate of the oxygen-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 0.6. For example, the ratio may be 0.6, 0.65, 0.7, or any value greater than 0.6.

[0125] Exemplarily, during the deposition of the plurality of sub-doped layers 111a, the process gas of the deposition process includes a silicon-containing gas and a phosphorus-containing gas, and the ratio of the flow rate of the phosphorus-containing gas to the flow rate of the silicon-containing gas (a first ratio) is greater than or equal to 0.05. For example, the ratio may be 0.05, 0.055, 0.06, or any value greater than 0.05.

[0126] Exemplarily, during the deposition of the plurality of sub-doped layers 111a, the process gas of the deposition process includes a silicon-containing gas and a hydrogen-containing gas, and the ratio of the flow rate of the hydrogen-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 150. The ratio may be 150, 160, 170, or any value greater than 150.

[0127] For example, during the deposition of the plurality of sub-doped layers 111a, the process gas of the deposition process includes a hydrogen-containing gas, and the flow rate of the hydrogen-containing gas is greater than or equal to 30,000 sccm. The flow rate of the hydrogen-containing gas can be 30,000, 32,000, 35,000, or any value greater than 30,000.

[0128] Exemplarily, the chamber pressure of the deposition process is greater than or equal to 3 mbar. For example, the chamber pressure of the deposition process may be 3 mbar, 3.5 mbar, 4 mbar, or any value greater than 3 mbar.

[0129] For example, the silicon-containing gas may include silane, the oxygen-containing gas may include carbon dioxide, the phosphorus-containing gas may include phosphine, and the hydrogen-containing gas may include hydrogen.

[0130] In some embodiments, see Figure 5 After providing the semiconductor substrate 170 , before depositing a plurality of sub-doped layers 111 a on the first surface 171 , the method may include forming a first intrinsic semiconductor layer 151 on the first surface 171 .

[0131] In some embodiments, see Figure 1 After forming the first doping layer 110 , the process may include forming a first doped contact layer 131 on a side of the first doping layer 110 facing away from the semiconductor substrate 170 .

[0132] Exemplarily, the process gas used in the formation process of the first doped contact layer 131 includes a silicon-containing gas and a phosphorus-containing gas, and the ratio of the flow rate of the phosphorus-containing gas to the flow rate of the silicon-containing gas (the second ratio) is greater than or equal to 0.06, which is beneficial to increase the phosphorus doping concentration of the first doped contact layer 131 and improve the conductivity. For example, the second ratio can be greater than the first ratio, so that the doping concentration of the first doped contact layer 131 is greater than the doping concentration of the first doping layer 110.

[0133] In some embodiments, see Figure 1 After forming the first doped contact layer 131 , the method may include forming a first transparent conductive layer 161 on a side of the first doped contact layer 131 facing away from the semiconductor substrate 170 .

[0134] In some embodiments, see Figure 1 After forming the first transparent conductive layer 161 , the method may include forming a first gate line 141 on a side of the first transparent conductive layer 161 away from the semiconductor substrate 170 .

[0135] In some embodiments, see Figure 1 The method for preparing the solar cell 100 may further include forming a second intrinsic semiconductor layer 152 on the second surface 172 .

[0136] In some embodiments, see Figure 1 and Figure 2 After forming the second intrinsic semiconductor layer 152 , the method may include forming a second doping layer 120 on a side of the second intrinsic semiconductor layer 152 facing away from the semiconductor substrate 170 .

[0137] Exemplarily, forming the second doping layer 120 may include sequentially forming a seed layer 121 and a body layer 122 , and a crystallization rate of the seed layer 121 is greater than a crystallization rate of the body layer 122 .

[0138] Exemplarily, the process gas used in the formation of the main layer 122 includes a silicon-containing gas and a boron-containing gas, and the ratio of the flow rate of the boron-containing gas to the flow rate of the silicon-containing gas (third ratio) is greater than or equal to 0.02.

[0139] In some embodiments, see Figure 1 and Figure 2 After forming the second doping layer 120 , the method may include forming a second doped contact layer 132 on a side of the second doping layer 120 facing away from the semiconductor substrate 170 .

[0140] Exemplarily, the process gas used in the formation process of the second doped contact layer 132 includes a silicon-containing gas and a boron-containing gas, and the ratio of the flow rate of the boron-containing gas to the flow rate of the silicon-containing gas (the fourth ratio) is greater than or equal to 0.03. For example, the fourth ratio may be greater than the third ratio, so that the doping concentration of the second doped contact layer 132 is greater than the doping concentration of the second doping layer 120.

[0141] In some embodiments, see Figure 1 and Figure 2 After forming the second doped contact layer 132 , the method may include forming a second transparent conductive layer 162 on a side of the second doped contact layer 132 facing away from the semiconductor substrate 170 .

[0142] In some embodiments, see Figure 1 After forming the second transparent conductive layer 162, the second gate line 142 may be formed on a side of the second transparent conductive layer 162 away from the semiconductor substrate 170. For example, the preparation process of the first gate line 141 and the second gate line 142 may include screen printing, laser transfer or copper electroplating.

[0143] Exemplarily, after providing the semiconductor substrate 170, a second intrinsic semiconductor layer 152 can be prepared on the second surface 172 by radio frequency enhanced plasma chemical vapor deposition (RF-PECVD), then turned over and a first intrinsic semiconductor layer 151 is prepared on the first surface 171, and then a plurality of sub-doped layers 111a and a first doped contact layer 131 are sequentially prepared by very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD), and then turned over again to prepare a seed layer 121 and a main layer 122 of a second doped layer 120, and a second doped contact layer 132, and then a first transparent conductive layer 161 and a second transparent conductive layer 162 are formed by PVD / RPD, and then a first gate line 141 and a second gate line 142 are prepared, and then the first gate line 141 and the second gate line 142 are cured / annealed.

[0144] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface arranged opposite to each other; A first doping layer, disposed on the first surface; The first doping layer includes a plurality of sub-doping layers arranged along the thickness direction of the semiconductor substrate, and the crystallinity rates of the plurality of sub-doping layers increase in sequence along a direction away from the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that: Among the multiple sub-doping layers, the sub-doping layer closest to the semiconductor substrate is the first sub-doping layer, which is an amorphous doping layer, and the sub-doping layer farthest from the semiconductor substrate is the second sub-doping layer, which is a microcrystalline doping layer.

3. The solar cell according to claim 2, characterized in that: The plurality of sub-doping layers further include a third sub-doping layer, wherein the third sub-doping layer is disposed between the first sub-doping layer and the second sub-doping layer; The crystallinity of the third sub-doping layer is between that of the first sub-doping layer and that of the second sub-doping layer.

4. The solar cell according to any one of claims 1 to 3, characterized in that: Among the multiple sub-doped layers, the crystallization rate of the sub-doped layer closest to the semiconductor substrate is 0, and the crystallization rate of the sub-doped layer farthest from the semiconductor substrate is less than or equal to 60%.

5. The solar cell according to claim 2 or 3, characterized in that: The thickness of the first doping layer is in the range of 13nm-18nm; and / or, a ratio of the thickness of the first sub-doped layer to the thickness of the first doped layer is less than or equal to 20%; And / or, the doping type of the first doping layer is the same as the doping type of the semiconductor substrate.

6. The solar cell according to any one of claims 1 to 3, characterized in that: The solar cell further comprises a first doped contact layer, wherein the first doped contact layer is disposed on a side of the first doped layer facing away from the semiconductor substrate; The doping concentration of the first doped contact layer is greater than the doping concentration of the first doping layer.

7. The solar cell according to any one of claims 1 to 3, characterized in that: The solar cell comprises a second doping layer, the second doping layer is arranged on the second surface, and the doping type of the second doping layer is opposite to the doping type of the first doping layer; The second doping layer includes a seed layer and a main layer arranged in a direction away from the semiconductor substrate, and a crystallization rate of the seed layer is greater than a crystallization rate of the main layer.

8. The solar cell according to claim 7, characterized in that: The solar cell further comprises a second doped contact layer, wherein the second doped contact layer is arranged on a side of the second doped layer away from the semiconductor substrate; The crystallization rate of the second doped contact layer is lower than the crystallization rate of the seed layer; and / or the doping concentration of the second doped contact layer is higher than the doping concentration of the main layer.

9. The solar cell according to claim 7, characterized in that: The crystallization rate of the seed layer is greater than or equal to 50%; And / or, the thickness of the seed layer is greater than or equal to 1 nm; and / or, the crystallinity rate of the main layer is greater than or equal to 20%; And / or, the thickness of the main layer is greater than or equal to 10 nm.

10. The solar cell according to claim 8, characterized in that: The crystallinity rate of the second doped contact layer is greater than or equal to 20%; And / or, the thickness of the second doped contact layer is greater than or equal to 1 nm.

11. The solar cell according to claim 7, characterized in that: The solar cell includes a first grid line and a second grid line, wherein the first grid line is arranged on a side of the first doped layer away from the semiconductor substrate, and the second grid line is arranged on a side of the second doped layer away from the semiconductor substrate; the arrangement density of the first grid line is less than the arrangement density of the second grid line.

12. A photovoltaic module, characterized in that: A solar cell comprising any one of claims 1 to 11.

13. A method for preparing a solar cell, characterized in that: include: Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other; A plurality of sub-doping layers are deposited on the first surface to form a first doping layer; wherein different sub-doping layers have different deposition powers, and during the deposition of the plurality of sub-doping layers, the deposition powers are sequentially increased.

14. The method for preparing a solar cell according to claim 13, characterized in that: During the deposition of the plurality of sub-doped layers, the deposition power was 130 mW / cm 2 Increased to 400mW / cm 2 .

15. The method for preparing a solar cell according to claim 13, characterized in that: The process gas of the deposition process includes a silicon-containing gas and an oxygen-containing gas, and the ratio of the flow rate of the oxygen-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 0.6; And / or, the process gas of the deposition process includes a silicon-containing gas and a phosphorus-containing gas, and the ratio of the flow rate of the phosphorus-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 0.05; And / or, the process gas of the deposition process includes a silicon-containing gas and a hydrogen-containing gas, and the ratio of the flow rate of the hydrogen-containing gas to the flow rate of the silicon-containing gas is greater than or equal to 150; And / or, the process gas of the deposition process includes a hydrogen-containing gas, and the flow rate of the hydrogen-containing gas is greater than or equal to 30000 sccm; And / or, the chamber pressure of the deposition process is greater than or equal to 3 mbar.

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