Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the steps of providing a semiconductor substrate; forming a first tunneling layer on one side of the semiconductor substrate; forming a first intrinsic semiconductor layer on one side, far away from the semiconductor substrate, of the first tunneling layer; forming a first doping source layer containing a gallium element on one side, far away from the semiconductor substrate, of the first intrinsic semiconductor layer, and forming a first intermediate form body; and performing annealing treatment on the first intermediate morphological body to enable at least part of the gallium element to be diffused into the first intrinsic semiconductor layer, and forming a first doped semiconductor layer. The manufacturing cost of the solar cell can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of solar photovoltaic cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] With the continuous development of solar cell technology, people have higher and higher requirements for the photoelectric conversion efficiency of cells. However, the improvement of industrial cell efficiency is still facing many challenges. Among them, the contact recombination between metal and silicon contact area and the Auger recombination and deep energy level recombination caused by diffusion in the silicon matrix are the main factors restricting the improvement of cell efficiency. TOPCon (Tunnel Oxide Passivated Contact) cells reduce the recombination of surface carriers by setting a passivation contact structure on the back of the silicon substrate. At present, how to reduce the production cost of TOPCon cells has become the research focus of technicians in this field. Summary of the invention

[0003] Based on this, it is necessary to provide a solar cell and a preparation method thereof, and a photovoltaic module to address the above problems.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0005] providing a semiconductor substrate;

[0006] forming a first tunneling layer on one side of the semiconductor substrate;

[0007] forming a first intrinsic semiconductor layer on a side of the first tunneling layer away from the semiconductor substrate;

[0008] forming a first doping source layer containing gallium elements on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and forming a first intermediate form;

[0009] The first intermediate form is annealed to diffuse at least a portion of the gallium element into the first intrinsic semiconductor layer and form a first doped semiconductor layer.

[0010] The method for preparing a solar cell provided in an embodiment of the present application forms a first doping source layer containing gallium elements on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and then performs annealing to diffuse at least part of the gallium elements into the first intrinsic semiconductor layer, and forms a first doped semiconductor layer. Compared with the preparation of the first doped semiconductor layer by a solution method, ion implantation and other processes, the embodiment of the present application, on the one hand, is not only conducive to reducing the difficulty of doping, facilitating the adjustment of the doping concentration, but also conducive to achieving high-concentration doping; on the other hand, the first doping source layer can be used as a mask layer for subsequent processes, which is conducive to reducing the process steps of the solar cell and reducing the production cost of the solar cell.

[0011] In one embodiment, forming a first doping source layer containing gallium elements on a side of the first intrinsic semiconductor layer away from the semiconductor substrate and forming a first intermediate form includes:

[0012] The first doping source layer containing gallium oxide is formed on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and the first intermediate form is formed; the thickness of the first doping source layer is 5nm-300nm.

[0013] In one embodiment, forming a first doping source layer containing gallium oxide on a side of the first intrinsic semiconductor layer away from the semiconductor substrate and forming the first intermediate form includes:

[0014] The first doping source layer is formed by a chemical vapor deposition process; the precursor of the chemical vapor deposition process includes trimethyl gallium and an oxidizing gas.

[0015] In one embodiment, forming a first doping source layer containing gallium oxide on a side of the first intrinsic semiconductor layer away from the semiconductor substrate and forming the first intermediate form includes:

[0016] The first doping source layer is formed by a physical vapor deposition process; the precursor of the physical vapor deposition process includes oxygen and a gallium-containing target material.

[0017] In one embodiment, the molar ratio of gallium to oxygen in the precursor of the physical vapor deposition process is 1:(0.5-2).

[0018] In one embodiment, the annealing of the first intermediate form so as to diffuse at least a portion of the gallium element into the first intrinsic semiconductor layer and form a first doped semiconductor layer comprises:

[0019] performing a first annealing treatment on the first intermediate form under a nitrogen atmosphere;

[0020] The first intermediate form is subjected to a second annealing treatment in an oxygen atmosphere.

[0021] In one embodiment, the processing time of the first annealing treatment is greater than the processing time of the second annealing treatment;

[0022] And / or, the annealing temperature of the first annealing treatment is higher than the annealing temperature of the second annealing treatment.

[0023] In one embodiment, the first annealing treatment takes 15 minutes to 60 minutes; the second annealing treatment takes 10 minutes to 30 minutes;

[0024] And / or, the annealing temperature of the first annealing treatment is 800°C-1500°C; the annealing temperature of the second annealing treatment is 800°C-1500°C.

[0025] In a second aspect, an embodiment of the present application provides a solar cell, comprising:

[0026] Semiconductor substrate;

[0027] A first tunneling layer, disposed on one side of the semiconductor substrate;

[0028] A first doped semiconductor layer is provided on a side of the first tunneling layer away from the semiconductor substrate; wherein the first doped semiconductor layer is configured such that: after the first doping source layer containing gallium is annealed, at least part of the gallium element diffuses into the first intrinsic semiconductor layer to form the first doped semiconductor layer; the doping concentration of gallium element in the first doped semiconductor layer is 1×10 16 cm -3 -1×10 21 cm -3 .

[0029] The solar cell provided in the embodiment of the present application is subjected to annealing treatment to diffuse at least part of the gallium element in the first doping source layer into the first intrinsic semiconductor layer to form the first doped semiconductor layer. In this way, on the one hand, it is not only conducive to reducing the difficulty of doping, but also conducive to achieving high-concentration doping; on the other hand, the doping concentration of the gallium element in the first doped semiconductor layer can be made 1×10 16 cm -3 -1×10 21 cm -3 , which makes it easy for process personnel to adjust the doping concentration according to actual needs, which is beneficial to improving battery efficiency; on the other hand, the first doping source layer can be used as a mask layer for subsequent processes, which is beneficial to reducing the process steps of solar cells and reducing the production cost of solar cells.

[0030] In one of the embodiments, the doping concentration of the first doped semiconductor layer gradually increases in a direction away from the semiconductor substrate.

[0031] In one embodiment, the first doped semiconductor layer includes a first sub-portion and a second sub-portion stacked in sequence in a direction away from the semiconductor substrate; a distance between a surface of the first sub-portion close to the semiconductor substrate and a surface of the first sub-portion away from the semiconductor substrate is T1, T1≥10nm, a distance between a surface of the second sub-portion close to the semiconductor substrate and a surface of the second sub-portion away from the semiconductor substrate is T2, 10nm<T2≤80nm;

[0032] The doping concentration of the gallium element in the first sub-section is 1×10 17 cm -3 -4×10 19 cm -3 ;

[0033] The doping concentration of the gallium element in the second sub-section is 4×10 19 cm -3 -8×10 19 cm -3 .

[0034] In one of the embodiments, the first doped semiconductor layer includes at least two sub-doped layers and at least one sub-oxidized layer alternately stacked in a direction away from the semiconductor substrate.

[0035] In one embodiment, the first doped semiconductor layer includes two sub-doped layers, wherein the doping concentration of gallium in the sub-doped layer close to the semiconductor substrate is 5×10 19 cm -3 -9×10 19 cm -3 The doping concentration of gallium in the sub-doping layer away from the semiconductor substrate is 4×10 19 cm -3 -6×10 19 cm -3 .

[0036] In one embodiment, the thickness of the sub-oxide layer is 0.5nm-2nm;

[0037] And / or, the thickness of the first doped semiconductor layer is 10nm-300nm;

[0038] And / or, the thickness of the first tunneling layer is 0.5nm-3nm.

[0039] In one embodiment, the solar cell further comprises:

[0040] A first passivation layer is disposed on a side of the first doped semiconductor layer away from the semiconductor substrate; the material of the first passivation layer includes oxide;

[0041] A second passivation layer is disposed on a side of the first passivation layer away from the semiconductor substrate; the material of the second passivation layer includes nitride;

[0042] Wherein, the thickness of the first passivation layer is 2nm-20nm, the thickness of the second passivation layer is 70nm-90nm; and / or, the refractive index of the second passivation layer is 1.8-2.1.

[0043] In a third aspect, an embodiment of the present application provides a photovoltaic module, comprising the solar cell in any embodiment of the second aspect. The photovoltaic module provided by the embodiment of the present application can reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of a process for preparing a solar cell provided in one embodiment of the present application.

[0046] Figure 2 for Figure 1 A schematic diagram of the process of S500 in the preparation method shown.

[0047] Figure 3 for Figure 1 A schematic diagram of the local cross-sectional structure after the first tunneling layer and the first intrinsic semiconductor layer are formed during the preparation method shown.

[0048] Figure 4 for Figure 1 A schematic diagram of the local cross-sectional structure after the first doping source layer is formed during the preparation method shown.

[0049] Figure 5 for Figure 1 Schematic diagram of the local cross-sectional structure after the pyramid velvet surface is formed during the preparation method shown.

[0050] Figure 6 for Figure 1 A schematic diagram of the local cross-sectional structure after the second tunneling layer, the second doped semiconductor layer and the transparent conductive layer are formed during the preparation method shown.

[0051] Figure 7 for Figure 1 A schematic diagram of the local cross-sectional structure after the first electrode and the second electrode are formed during the preparation method shown.

[0052] Figure 8 A schematic diagram of a partial cross-sectional structure of a solar cell provided in one embodiment of the present application.

[0053] Reference numerals:

[0054] 1. Solar cell; 11. Semiconductor substrate; 11-1. First surface; 11-2. Second surface; 12. First tunneling layer; 13. First doped semiconductor layer; 13a. First sub-section; 13b. Second sub-section; 131. Sub-doped layer; 132. Sub-oxidation layer; 14. First passivation layer; 15. Second passivation layer; 16. First electrode; 17. Second tunneling layer; 18. Second doped semiconductor layer; 19. Transparent conductive layer; 110. Second electrode; 21. First intrinsic semiconductor layer; 211. Sub-intrinsic material layer; 212. Sub-oxidation material layer; 22. First doping source layer. DETAILED DESCRIPTION

[0055] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0058] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0061] First, refer to Figure 1 As shown, an embodiment of the present application provides a method for preparing a solar cell 1 , and the solar cell 1 may be a TOPCon (Tunnel Oxide Passivated Contact) cell or a back contact (BC) cell.

[0062] The preparation method specifically comprises the following steps:

[0063] S100: Provide a semiconductor substrate 11. Exemplarily, the material of the semiconductor substrate 11 can be silicon, a compound semiconductor, and a wide bandgap semiconductor material. Exemplarily, silicon includes crystalline silicon and amorphous silicon. Compound semiconductors include selenium, selenide, etc. Wide bandgap semiconductor materials include silicon carbide, gallium nitride, diamond, etc. It should be noted that the semiconductor substrate 11 can be double-sided polished in this step to remove the cutting damage area. Specifically, the semiconductor substrate 11 includes a first surface 11-1 and a second surface 11-2 that are oppositely arranged. Here, one of the first surface 11-1 and the second surface 11-2 is a light-facing surface, and the other is a backlight surface.

[0064] Further, the doping type of the semiconductor substrate 11 is N-type or P-type. When the doping type of the semiconductor substrate 11 is N-type, the doping element may include any one or more of phosphorus (P), arsenic (As), bismuth (Bi) and antimony (Sb) in the V group elements; when the doping type of the semiconductor substrate 11 is P-type, the doping element may include any one or more of boron (B), aluminum (Al), gallium (Ga) and indium (In) in the III group elements.

[0065] S200: forming a first tunneling layer 12 on one side of the semiconductor substrate 11. Exemplarily, the material of the first tunneling layer 12 may be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide or titanium oxide. It is understandable that the first tunneling layer 12 may be prepared by processes such as ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), and LPCVD (Low Pressure Chemical Vapor Deposition). Specifically, the first tunneling layer 12 is formed by depositing the first surface 11-1 of the semiconductor substrate 11 using a PECVD process, wherein the reaction gases are nitrous oxide and argon.

[0066] S300: forming a first intrinsic semiconductor layer 21 on a side of the first tunneling layer 12 away from the semiconductor substrate 11. Specifically, the material of the first intrinsic semiconductor layer 21 may be amorphous silicon. It is understood that the first intrinsic semiconductor layer 21 may be prepared by ALD, PECVD, PEALD, LPCVD and other processes. It should be noted that, here, the first intrinsic semiconductor layer 21 may be a composite film layer structure or a single film layer structure. The structure after the first tunneling layer 12 and the first intrinsic semiconductor layer 21 are formed is as follows: Figure 3 shown.

[0067] S400: forming a first doping source layer 22 containing gallium elements on a side of the first intrinsic semiconductor layer 21 away from the semiconductor substrate 11, and forming a first intermediate form. Figure 4 The structure shown is a first intermediate form. It should be noted that the first doping source layer 22 can be prepared by a solution method, PVD, LPCVD, PECVD, CVD and metal-organic chemical vapor deposition (MOCVD) process.

[0068] S500: annealing the first intermediate form so that at least part of the gallium element diffuses into the first intrinsic semiconductor layer 21, and forms the first doped semiconductor layer 13. It is understood that the annealing process may be laser annealing, microwave annealing, heating annealing, and the like.

[0069] It should be noted that in the related art, when the first doped semiconductor layer 13 is prepared by solution method or ion implantation, it is difficult to dope the gallium element, resulting in problems such as difficulty in controlling the doping concentration, difficulty in performing high-concentration doping, and high doping costs.

[0070] The method for preparing the solar cell 1 provided in the embodiment of the present application forms a first doping source layer 22 containing gallium elements on the side of the first intrinsic semiconductor layer 21 away from the semiconductor substrate 11, and then performs annealing to diffuse at least part of the gallium elements into the first intrinsic semiconductor layer 21, and forms the first doped semiconductor layer 13. In this way, on the one hand, the gallium element can be easily introduced into the first intrinsic semiconductor layer 21, which is not only conducive to reducing the difficulty of doping, facilitating the adjustment of the doping concentration, but also conducive to achieving high-concentration doping; on the other hand, the first doping source layer 22 can be used as a mask layer for subsequent processes, so that there is no need to make additional masks in the subsequent processes, which is conducive to reducing the process steps of the solar cell 1 and reducing the production cost of the solar cell 1.

[0071] In one embodiment, the first doping source layer 22 may be doped with at least one of nitrogen and oxygen. During the annealing process, the nitrogen and / or oxygen in the first doping source layer 22 may diffuse into the first intrinsic semiconductor layer 21, thereby helping to reduce the risk of film explosion.

[0072] In one embodiment, S400: forming a first doping source layer 22 containing gallium elements on a side of the first intrinsic semiconductor layer 21 away from the semiconductor substrate 11, and forming a first intermediate form, specifically includes the following steps:

[0073] S410: forming a first doping source layer 22 containing gallium oxide on a side of the first intrinsic semiconductor layer 21 away from the semiconductor substrate 11, and forming a first intermediate form. It is understandable that the first doping source layer 22 may also include materials other than gallium oxide, and the present embodiment of the application does not limit the materials other than gallium oxide. In one example, the material of the first doping source layer 22 is gallium oxide.

[0074] It should be noted that the gallium oxide in the embodiment of the present application refers to an oxide including gallium and oxygen. Generally, the molar ratio of gallium to oxygen in gallium oxide is 2:3, and the molar ratio of gallium to oxygen in the gallium oxide in the embodiment of the present application may be greater than or less than 2:3. In a preferred embodiment, the molar ratio of gallium to oxygen in the gallium oxide is greater than 2:3, which is conducive to diffusing the gallium in the gallium oxide into the first intrinsic semiconductor layer 21.

[0075] In one embodiment, the thickness of the first doping source layer 22 is 5nm-300nm. Exemplarily, the thickness of the first doping source layer 22 can be 5nm, 15nm, 30nm, 60nm, 100nm, 150nm, 220nm, 250nm, 300nm, or between any two of the above values. By making the thickness of the first doping source layer 22 within the above range, on the one hand, it is beneficial to have sufficient gallium elements in the first doping source layer 22, so that sufficient gallium elements can be diffused into the first intrinsic semiconductor layer 21 during annealing; on the other hand, the first doping source layer 22 can be multi-purpose, such as serving as a mask layer for subsequent processes.

[0076] In one embodiment, S410: forming a first doping source layer 22 containing gallium oxide on a side of the first intrinsic semiconductor layer 21 away from the semiconductor substrate 11, and forming a first intermediate form, specifically includes the following steps:

[0077] S411A: Forming a first doping source layer 22 by using a chemical vapor deposition process.

[0078] In one embodiment, the precursor of the chemical vapor deposition process includes trimethylgallium and an oxidizing gas. Thus, on the one hand, the first doping source layer 22 can be prepared at a lower cost; on the other hand, it is helpful to form the first doping source layer 22 with better film quality.

[0079] In one embodiment, the oxidizing gas includes oxygen, ozone, etc. In one example, the precursor of the chemical vapor deposition process includes trimethyl gallium and oxygen. In another example, the precursor of the chemical vapor deposition process includes trimethyl gallium and ozone.

[0080] In one embodiment, S410: forming a first doping source layer 22 containing gallium oxide on a side of the first intrinsic semiconductor layer 21 away from the semiconductor substrate 11, and forming a first intermediate form, specifically includes the following steps:

[0081] S411B: forming a first doping source layer 22 by adopting a physical vapor deposition process.

[0082] In one embodiment, the precursor of the physical vapor deposition process includes oxygen and a gallium-containing target material. In this way, on the one hand, the first doping source layer 22 can be prepared at a lower cost; on the other hand, it is helpful to form the first doping source layer 22 with better film quality.

[0083] It should be noted that the gallium-containing target material may be gallium oxide or a material containing gallium elements.

[0084] In one embodiment, the molar ratio of gallium to oxygen in the precursor of the physical vapor deposition process is 1:(0.5-2). For example, the molar ratio of gallium to oxygen can be 1:0.5, 1:0.8, 1:1.5, 1:1.8, 1:2, etc. The above configuration helps to form a first doping source layer 22 with good film quality.

[0085] In one embodiment, referring to Figure 2 As shown, S500: annealing the first intermediate form so that at least part of the gallium element diffuses into the first intrinsic semiconductor layer 21 and forms the first doped semiconductor layer 13, specifically including the following steps:

[0086] S510: performing a first annealing treatment on the first intermediate body in a nitrogen atmosphere.

[0087] S520: performing a second annealing treatment on the first intermediate form under an oxygen atmosphere.

[0088] In this way, the annealing process is equivalent to being divided into two stages, namely the first annealing process and the second annealing process. In the first annealing process, on the one hand, the gallium element is diffused into the first intrinsic semiconductor layer 21, and on the other hand, the first intrinsic semiconductor layer 21 is gradually crystallized. In the second annealing process, on the one hand, the doping concentration of the gallium element is adjusted so that the doping concentration of the gallium element in the first intrinsic semiconductor layer 21 reaches a preset concentration, and on the other hand, the crystallization rate of the first intrinsic semiconductor layer 21 is further improved and the defect state density is reduced.

[0089] In one embodiment, the processing time of the first annealing treatment is greater than the processing time of the second annealing treatment. In this way, during the first annealing treatment, it is helpful to diffuse the gallium element into the first intrinsic semiconductor layer 21, and the first intrinsic semiconductor layer 21 reaches a certain crystallization rate. During the second annealing treatment, on the one hand, the doping concentration of the gallium element can be adjusted so that the doping concentration of the gallium element in the first intrinsic semiconductor layer 21 reaches a preset concentration, and on the other hand, the crystallization rate can be further improved and the defect state density can be reduced.

[0090] In one embodiment, the annealing temperature of the first annealing treatment is higher than the annealing temperature of the second annealing treatment. Thus, during the first annealing treatment, it is helpful to diffuse gallium into the first intrinsic semiconductor layer 21 and make the first intrinsic semiconductor layer 21 reach a certain crystallization rate. During the second annealing treatment, on the one hand, the doping concentration of gallium can be adjusted so that the doping concentration of gallium in the first intrinsic semiconductor layer 21 reaches a preset concentration, and on the other hand, the crystallization rate can be further improved and the defect state density can be reduced.

[0091] In one embodiment, the processing time of the first annealing treatment is 15min-60min. The processing time of the second annealing treatment is 10min-30min. Exemplarily, the processing time of the first annealing treatment is 15min, 20min, 30min, 40min, 50min, 60min or between any two of the above values. The processing time of the second annealing treatment is 10min, 15min, 20min, 25min, 30min or between any two of the above values.

[0092] By making the processing time of the first annealing treatment and the second annealing treatment respectively fall within the above two ranges, it is helpful to form the first doped semiconductor layer 13 with better doping quality on the one hand, and it is helpful to reduce the manufacturing cost on the other hand.

[0093] In one embodiment, the annealing temperature of the first annealing treatment is 800°C-1500°C. The annealing temperature of the second annealing treatment is 800°C-1500°C. Exemplarily, the annealing temperature of the first annealing treatment is 800°C, 1000°C, 1200°C, 1300°C, 1400°C, 1500°C, or between any two of the above values. The annealing temperature of the second annealing treatment is 800°C, 900°C, 1100°C, 1250°C, 1420°C, 1500°C, or between any two of the above values.

[0094] By making the annealing temperatures of the first annealing treatment and the second annealing treatment within the above range, it helps to form a first doped semiconductor layer 13 with better doping quality, helps to reduce the production cost, and helps to reduce the defect state density of the first doped semiconductor layer 13.

[0095] In one embodiment, the first intrinsic semiconductor layer 21 is a composite film layer structure. S300: forming the first intrinsic semiconductor layer 21 on a side of the first tunneling layer 12 away from the semiconductor substrate 11, specifically comprising the following steps:

[0096] S310 : forming a sub-intrinsic material layer 211 on a side of the first tunneling layer 12 away from the semiconductor substrate 11 .

[0097] S320: forming at least one layer of sub-oxidation material layer 212 and at least one layer of sub-intrinsic material layer 211 on a side of the sub-intrinsic material layer 211 away from the semiconductor substrate 11. The sub-intrinsic material layer 211 and the sub-oxidation material layer 212 are alternately stacked in sequence. In this way, a first intrinsic semiconductor layer 21 of a composite structure can be formed.

[0098] It should be noted that the method for preparing the solar cell 1 provided in the embodiment of the present application can be used to prepare a TOPCon cell or a BC cell. The present embodiment of the present application takes the method for preparing a TOPCon cell as an example to introduce the process steps after S500.

[0099] Specifically, S500: after annealing the first intermediate form to diffuse at least a portion of the gallium element into the first intrinsic semiconductor layer 21 and forming the first doped semiconductor layer 13, the following steps are also included:

[0100] S600: Performing a texturing process on the second surface 11-2 of the semiconductor substrate 11 to form a pyramid texture structure. Figure 5 As shown, during the texturing process, the first doping source layer 22 can be used as a mask layer to protect the first doped semiconductor layer 13 .

[0101] S700: forming a second tunneling layer 17 and a second doped semiconductor layer 18 stacked in sequence on the second surface 11-2. It should be noted that the manufacturing process of the second tunneling layer 17 can be the same as the manufacturing process of the first tunneling layer 12, and the manufacturing process of the second doped semiconductor layer 18 can be the same as the manufacturing process of the first doped semiconductor layer 13. The structure of the second tunneling layer 17 and the second doped semiconductor layer 18 after formation is as follows: Figure 6 shown.

[0102] S800: forming a first passivation layer 14 and a second passivation layer 15 stacked in sequence on a side of the first doped semiconductor layer 13 away from the semiconductor substrate 11. The first passivation layer 14 may be made of aluminum oxide, and the second passivation layer 15 may be made of silicon nitride.

[0103] S900: forming a transparent conductive layer 19, a first electrode 16 and a second electrode 110. The transparent conductive layer 19 is located on the side of the second doped semiconductor layer 18 away from the semiconductor substrate 11, the first electrode 16 penetrates the first passivation layer 14, the second passivation layer 15 and is in ohmic contact with the first doped semiconductor layer 13, and the second electrode 110 is in ohmic contact with the transparent conductive layer 19. It should be noted that the transparent conductive layer 19 can be made before the first electrode 16 and the second electrode 110, or after the first electrode 16 is made, or in S700. The embodiment of the present application does not specifically limit the order of making the transparent conductive layer 19, the first electrode 16 and the second electrode 110. Furthermore, the first electrode 16 and the second electrode 110 can be made by printing and sintering processes.

[0104] Second, refer to Figure 7 or Figure 8As shown, an embodiment of the present application provides a solar cell 1, which may be a TOPCon (Tunnel Oxide Passivated Contact) cell or a back contact (BC) cell.

[0105] Specifically, the solar cell 1 includes a semiconductor substrate 11, a first tunneling layer 12, and a first doped semiconductor layer 13. The first tunneling layer 12 is disposed on one side of the semiconductor substrate 11. The first doped semiconductor layer 13 is disposed on the side of the first tunneling layer 12 away from the semiconductor substrate 11. The first doped semiconductor layer 13 is configured as follows: after the first doping source layer 22 containing gallium is annealed, at least part of the gallium element diffuses into the first intrinsic semiconductor layer 21 to form the first doped semiconductor layer 13. The doping concentration of gallium in the first doped semiconductor layer 13 is 1×10 16 cm -3 -1×10 21 cm -3 For example, the doping concentration of gallium element may be 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 , 1×10 21 cm -3 Or between any two of the above values.

[0106] In a specific embodiment, the semiconductor substrate 11 includes a first surface 11-1 and a second surface 11-2 that are opposite to each other. One of the first surface 11-1 and the second surface 11-2 may be a light-facing surface, and the other may be a light-backed surface. The first tunneling layer 12 is disposed on the first surface 11-1.

[0107] It should be noted that in the related art, when the first doped semiconductor layer 13 is prepared by solution method or ion implantation, it is difficult to dope the gallium element, resulting in problems such as difficulty in controlling the doping concentration, difficulty in performing high-concentration doping, and high doping costs.

[0108] The solar cell 1 provided in the embodiment of the present application diffuses at least part of the gallium element in the first doping source layer 22 into the first intrinsic semiconductor layer 21 to form the first doped semiconductor layer 13 through annealing. In this way, on the one hand, it is not only conducive to reducing the difficulty of doping, but also conducive to achieving high-concentration doping; on the other hand, the doping concentration of the gallium element in the first doped semiconductor layer 13 can be made 1×10 16cm -3 -1×10 21 cm -3 , which makes it easy for process personnel to adjust the doping concentration according to actual needs, which is beneficial to improving battery efficiency; on the other hand, the first doping source layer 22 can be used as a mask layer for subsequent processes, which is beneficial to reducing the process steps of the solar cell 1 and reducing the production cost of the solar cell 1.

[0109] In one embodiment, the doping concentration of the first doped semiconductor layer 13 gradually increases in a direction away from the semiconductor substrate 11. That is, the closer to the semiconductor substrate 11, the lower the doping concentration of the first doped semiconductor layer 13. In this way, during the doping process, it is helpful to reduce damage to the semiconductor substrate 11 and improve the battery efficiency.

[0110] In one embodiment, if Figure 8 As shown, the first doped semiconductor layer 13 includes a first sub-portion 13a and a second sub-portion 13b stacked in sequence in a direction away from the semiconductor substrate 11. The distance between the surface of the first sub-portion 13a close to the semiconductor substrate 11 and the surface of the first sub-portion 13a away from the semiconductor substrate 11 is T1, T1≥10nm, and the distance between the surface of the second sub-portion 13b close to the semiconductor substrate 11 and the surface of the second sub-portion 13b away from the semiconductor substrate 11 is T2, 10nm<T2≤80nm. Here, T1 can be considered as the thickness of the first sub-portion 13a, and T2 can be considered as the thickness of the second sub-portion 13b.

[0111] Furthermore, the doping concentration of the gallium element in the first sub-section 13a is 1×10 17 cm -3 -4×10 19 cm -3 The doping concentration of gallium in the second subsection 13b is 4×10 19 cm -3 -8×10 19 cm -3 For example, the doping concentration of the first sub-section 13a may be 1×10 17 cm -3 , 1×10 18 cm -3 , 2×10 19 cm -3 , 4×10 19 cm -3 Or between any two of the above values. The doping concentration of the second sub-section 13b can be 4×10 19 cm -3 , 5×10 19 cm -3 ,7×10 19 cm -3, 8×10 19 cm -3 Or between any two of the above values.

[0112] In this way, during the doping process, it is beneficial to reduce the damage to the semiconductor substrate 11 and improve the battery efficiency.

[0113] In one embodiment, referring to Figure 7 As shown, the first doped semiconductor layer 13 includes at least two sub-doped layers 131 and at least one sub-oxidized layer 132 alternately stacked in a direction away from the semiconductor substrate 11. That is, a sub-oxidized layer 132 is provided between any two adjacent sub-doped layers 131. By providing the sub-oxidized layer 132, the gallium element can be blocked from diffusing toward the semiconductor substrate 11, the damage to the semiconductor substrate 11 can be reduced, and the battery efficiency can be improved.

[0114] It should be noted that the number of the sub-doped layers 131 is greater than the number of the sub-oxidized layers 132 by 1. The embodiment of the present application does not specifically limit the number of the sub-doped layers 131 to be greater than the number of the sub-oxidized layers 132.

[0115] In one embodiment, of any two adjacent sub-doping layers 131, the thickness of the sub-doping layer 131 close to the semiconductor substrate 11 is greater than the thickness of the sub-doping layer 131 far from the semiconductor substrate 11. This is beneficial to blocking the diffusion of gallium elements toward the semiconductor substrate 11, reducing damage to the semiconductor substrate 11, and improving battery efficiency.

[0116] In one embodiment, the first doped semiconductor layer 13 includes two sub-doped layers 131, wherein the doping concentration of gallium in the sub-doped layer 131 close to the semiconductor substrate 11 is 5×10 19 cm -3 -9×10 19 cm -3 The doping concentration of the gallium element in the sub-doping layer 131 away from the semiconductor substrate 11 is 4×10 19 cm -3 -6×10 19 cm -3 For example, the doping concentration of the gallium element in the sub-doping layer 131 close to the semiconductor substrate 11 may be 5×10 19 cm -3 , 6×10 19 cm -3 ,7×10 19 cm -3 ,9×10 19 cm -3 Or between any two of the above values. The doping concentration of the gallium element in the sub-doping layer 131 away from the semiconductor substrate 11 can be 4×10 19 cm-3 , 5×10 19 cm -3 , 6×10 19 cm -3 Or between any two of the above values. It should be noted that this structure can be applied in BC batteries.

[0117] The above configuration can make the first doped semiconductor layer 13 have a better passivation effect and a better ohmic contact effect, and can also reduce the difficulty of manufacturing the first doped semiconductor layer 13 .

[0118] In one embodiment, the thickness of the sub-oxide layer 132 is 0.5 nm-2 nm. For example, the thickness of the sub-oxide layer 132 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm, or between any two of the above values. In this way, on the one hand, the ohmic contact effect of the first doped semiconductor layer 13 can be better, and on the other hand, the sub-oxide layer 132 can have a better blocking effect.

[0119] In one embodiment, the thickness of the first doped semiconductor layer 13 is 10 nm-300 nm. For example, the thickness of the first doped semiconductor layer 13 can be 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, or between any two of the above values. In this way, the first doped semiconductor layer 13 can have a better passivation effect and a better ohmic contact effect.

[0120] In one embodiment, the thickness of the first tunnel layer 12 is 0.5 nm-3 nm. For example, the thickness of the first tunnel layer 12 can be 0.5 nm, 1.5 nm, 2.5 nm, 3 nm, or between any two of the above values. In this way, the passivation effect of the first tunnel layer 12 can be better.

[0121] In one embodiment, the solar cell 1 further includes a first passivation layer 14 and a second passivation layer 15, wherein the first passivation layer 14 is disposed on a side of the first doped semiconductor layer 13 away from the semiconductor substrate 11; the material of the first passivation layer 14 includes oxide. The second passivation layer 15 is disposed on a side of the first passivation layer 14 away from the semiconductor substrate 11; the material of the second passivation layer 15 includes nitride. Exemplarily, the material of the first passivation layer 14 is aluminum oxide, and the material of the second passivation layer 15 is silicon nitride.

[0122] The thickness of the first passivation layer 14 is 2nm-20nm, and the thickness of the second passivation layer 15 is 70nm-90nm. For example, the thickness of the first passivation layer 14 can be 2nm, 5nm, 10nm, 15nm, 20nm, or between any two of the above values. The thickness of the second passivation layer 15 can be 70nm, 75nm, 80nm, 85nm, 90nm, or between any two of the above values.

[0123] The above configuration can make the manufacturing process and performance of the first passivation layer 14 and the second passivation layer 15 compatible, which is beneficial to increase the H content and improve the passivation effect.

[0124] In one embodiment, the refractive index of the second passivation layer 15 is 1.8-2.1. For example, the refractive index of the second passivation layer 15 can be 1.8, 1.9, 2.0, 2.1, or between any two of the above values. This is conducive to improving the passivation effect of the second passivation layer 15.

[0125] In one embodiment, the solar cell 1 is a TOPCon cell, and the solar cell 1 further includes a second tunneling layer 17 , a second doped semiconductor layer 18 , and a transparent conductive layer 19 which are sequentially stacked on the second surface 11 - 2 .

[0126] Furthermore, the solar cell 1 further comprises a first electrode 16 and a second electrode 110 , wherein the first electrode 16 penetrates the first passivation layer 14 and the second passivation layer 15 and is in ohmic contact with the first doped semiconductor layer 13 , and the second electrode 110 is in ohmic contact with the transparent conductive layer 19 .

[0127] In a third aspect, an embodiment of the present application provides a photovoltaic assembly, comprising the solar cell in any embodiment of the second aspect.

[0128] For example, the photovoltaic module includes a plurality of solar cells, which can be connected in series by welding ribbons, so that the electricity generated by the individual solar cells can be collected for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked in a shingled form.

[0129] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate, wherein the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string. The solar cells are electrically connected in the form of a whole piece or multiple pieces to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel. Specifically, in some embodiments, the plurality of battery strings can be electrically connected by a conductive tape. The encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastic film, or a polyethylene terephthalate film. The cover plate can be a cover plate with a light-transmitting function such as a glass cover plate, a plastic cover plate, etc.

[0130] It should be understood that in the embodiments of the present application, at least part of the steps in the drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0131] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: providing a semiconductor substrate; forming a first tunneling layer on one side of the semiconductor substrate; forming a first intrinsic semiconductor layer on a side of the first tunneling layer away from the semiconductor substrate; forming a first doping source layer containing gallium elements on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and forming a first intermediate form; The first intermediate form is annealed to diffuse at least a portion of the gallium element into the first intrinsic semiconductor layer and form a first doped semiconductor layer.

2. The method for preparing a solar cell according to claim 1, characterized in that: The first doping source layer containing gallium is formed on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and a first intermediate form is formed, including: The first doping source layer containing gallium oxide is formed on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and the first intermediate form is formed; the thickness of the first doping source layer is 5nm-300nm.

3. The method for preparing a solar cell according to claim 2, characterized in that: The first doping source layer containing gallium oxide is formed on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and the first intermediate form is formed, including: The first doping source layer is formed by a chemical vapor deposition process; the precursor of the chemical vapor deposition process includes trimethyl gallium and an oxidizing gas.

4. The method for preparing a solar cell according to claim 3, characterized in that: The first doping source layer containing gallium oxide is formed on a side of the first intrinsic semiconductor layer away from the semiconductor substrate, and the first intermediate form is formed, comprising: The first doping source layer is formed by a physical vapor deposition process; the precursor of the physical vapor deposition process includes oxygen and a gallium-containing target material.

5. The method for preparing a solar cell according to claim 4, characterized in that: The molar ratio of gallium element to oxygen element in the precursor of the physical vapor deposition process is 1:(0.5-2).

6. The method for preparing a solar cell according to claim 1, characterized in that: The annealing treatment of the first intermediate form so as to diffuse at least a portion of the gallium element into the first intrinsic semiconductor layer and form a first doped semiconductor layer comprises: performing a first annealing treatment on the first intermediate form under a nitrogen atmosphere; The first intermediate form is subjected to a second annealing treatment in an oxygen atmosphere.

7. The method for preparing a solar cell according to claim 6, characterized in that: The processing time of the first annealing treatment is greater than the processing time of the second annealing treatment; And / or, the annealing temperature of the first annealing treatment is higher than the annealing temperature of the second annealing treatment.

8. The method for preparing a solar cell according to claim 6, characterized in that: The processing time of the first annealing treatment is 15min-60min; the processing time of the second annealing treatment is 10min-30min; And / or, the annealing temperature of the first annealing treatment is 800°C-1500°C; the annealing temperature of the second annealing treatment is 800°C-1500°C.

9. A solar cell, characterized in that: include: Semiconductor substrate; A first tunneling layer, disposed on one side of the semiconductor substrate; A first doped semiconductor layer is provided on a side of the first tunneling layer away from the semiconductor substrate; wherein the first doped semiconductor layer is configured such that: after the first doping source layer containing gallium is annealed, at least part of the gallium element diffuses into the first intrinsic semiconductor layer to form the first doped semiconductor layer; the doping concentration of gallium element in the first doped semiconductor layer is 1×10 16 cm -3 -1×10 21 cm -3 .

10. The solar cell according to claim 9, characterized in that: The doping concentration of the first doped semiconductor layer gradually increases in a direction away from the semiconductor substrate.

11. The solar cell according to claim 10, characterized in that The first doped semiconductor layer includes a first sub-portion and a second sub-portion stacked in sequence in a direction away from the semiconductor substrate; a distance between a surface of the first sub-portion close to the semiconductor substrate and a surface of the first sub-portion away from the semiconductor substrate is T1, T1≥10nm, and a distance between a surface of the second sub-portion close to the semiconductor substrate and a surface of the second sub-portion away from the semiconductor substrate is T2, 10nm<T2≤80nm; The doping concentration of the gallium element in the first sub-section is 1×10 17 cm -3 -4×10 19 cm -3 ; The doping concentration of the gallium element in the second sub-section is 4×10 19 cm -3 -8×10 19 cm -3 .

12. The solar cell according to claim 9, characterized in that: The first doped semiconductor layer includes at least two sub-doped layers and at least one sub-oxidized layer alternately stacked in a direction away from the semiconductor substrate.

13. The solar cell according to claim 12, characterized in that: The first doped semiconductor layer includes two sub-doped layers, wherein the doping concentration of gallium in the sub-doped layer close to the semiconductor substrate is 5×10 19 cm -3 -9×10 19 cm -3 The doping concentration of gallium in the sub-doping layer away from the semiconductor substrate is 4×10 19 cm -3 -6×10 19 cm -3 .

14. The solar cell according to claim 12, characterized in that: In any two adjacent sub-doping layers, the thickness of the sub-doping layer close to the semiconductor substrate is greater than the thickness of the sub-doping layer far from the semiconductor substrate.

15. The solar cell according to claim 12, characterized in that: The thickness of the sub-oxide layer is 0.5nm-2nm; And / or, the thickness of the first doped semiconductor layer is 10nm-300nm; And / or, the thickness of the first tunneling layer is 0.5nm-3nm.

16. The solar cell according to any one of claims 9 to 15, characterized in that: The solar cell further comprises: A first passivation layer is disposed on a side of the first doped semiconductor layer away from the semiconductor substrate; the material of the first passivation layer includes oxide; A second passivation layer is disposed on a side of the first passivation layer away from the semiconductor substrate; the material of the second passivation layer includes nitride; Wherein, the thickness of the first passivation layer is 2nm-20nm, the thickness of the second passivation layer is 70nm-90nm; and / or, the refractive index of the second passivation layer is 1.8-2.

1.

17. A photovoltaic module, characterized in that: Comprising a solar cell as described in any one of claims 9 to 16.

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