Back contact HBC solar cell structure and preparation method thereof, photovoltaic module

Abstract

The present invention belongs to the technical field of crystalline silicon solar cells, and specifically relates to a back-contact HBC solar cell structure and a preparation method thereof, and a photovoltaic module, comprising the following steps: step S1, double-sided polishing of a silicon wafer; step S2, depositing a layer of i: a-Si layer, P: a-Si layer and SiO2 from top to bottom on the back of the silicon wafer; 2 mask layer; step S3, laser etching the P region on the back of the silicon wafer; step S4, alkaline polishing and cleaning the back of the silicon wafer; step S5, depositing a layer of i: a-Si layer, N: a-Si layer and SiO 2 Mask layer; step S6, laser etching the P area on the back side of the silicon wafer; step S7, texturing the front side of the silicon wafer to form a pyramid texture surface; step S8, preparing the FSF field passivation area of ​​the silicon wafer, and depositing a silicon nitride laminated gradient film, and then depositing a TCO layer on the back side of the silicon wafer; step S9, laser etching the back side of the silicon wafer; step S10, printing metal slurry on the back side of the silicon wafer and curing light injection to complete the preparation of the battery.

Description

Technical Field

[0001] The present invention belongs to the technical field of crystalline silicon solar cells, and in particular relates to a back-contact HBC solar cell structure and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Photovoltaic power generation is a system that uses solar cells to directly convert sunlight into electricity based on the photovoltaic effect. The basic structure of a solar cell is a large, planar PN junction. When sunlight strikes the PN junction, it absorbs the energy and excites electrons and holes, generating a voltage across the junction, achieving photoelectric conversion. Therefore, the PN junction is the core structure that converts sunlight into electricity in crystalline silicon cells.

[0003] As Perc cells approach their efficiency limit of 24.5%, the industry is seeking next-generation crystalline silicon cell technology. Currently, the mainstream technologies being promoted include Topcon (tunneling oxide passivation contact), HJT (heterojunction), and IBC (interdigitated back contact). Unlike Topcon and HJT, which improve cell efficiency by changing the passivation method, IBC cells shift all the cell grid lines to the back, reducing the grid line shading area, increasing current density, and boosting cell efficiency. IBC cells are a platform technology. When combined with Topcon technology, they become TBC, and when combined with HJT technology, they become HBC.

[0004] However, because the grid lines of the HBC battery are integrated on the back side, the shading area on the back side increases, the efficiency of the front side varies greatly, and the bifaciality is insufficient. Therefore, how to overcome the defect of insufficient bifaciality of the HBC battery is a technical problem that needs to be solved urgently in this field.

[0005] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the Invention

[0006] The embodiments of the present disclosure at least provide a back-contact HBC solar cell structure and a preparation method thereof, and a photovoltaic module.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for preparing a back-contact HBC solar cell, comprising the following steps: step S1, double-sided polishing of a silicon wafer to prepare a clean silicon wafer surface with a low-reflection lubricating alkali-polished tower base morphology; step S2, depositing a layer of i:a-Si on the back side of the silicon wafer from top to bottom, performing HPT cleaning on the deposited surface, and then depositing a P:a-Si layer and a SiO2 mask layer from top to bottom; step S3, laser etching the P region on the back side of the silicon wafer to remove the SiO2 mask layer and the P:a-Si layer in the etched area; step S4, alkali-polishing the back side of the silicon wafer to remove the deposited layer in the unmasked area, and etching the silicon base to clean the silicon wafer; step S5, depositing a layer of i:a on the back side of the silicon wafer from top to bottom -Si layer, perform HPT cleaning on the deposited surface and then deposit N:a-Si layer and SiO2 mask layer in sequence from top to bottom; step S6, laser etching the P area on the back of the silicon wafer to expose the SiO2 mask layer underneath; step S7, texturing the front of the silicon wafer to form a pyramid texturing surface, and cleaning and removing the patterned silicon oxide mask on the back; step S8, after H ion cleaning on the front of the silicon wafer, inject P atoms to prepare the FSF field passivation area, and deposit a silicon nitride stacked gradient film, and then deposit a TCO layer on the back of the silicon wafer; step S9, laser etching the back of the silicon wafer to isolate the P area from the N area on the back to prepare an interdigitated arrangement structure; step S10, printing metal slurry on the back of the silicon wafer and curing the light injection to complete the preparation of the battery.

[0008] In an optional embodiment, the reflectivity of the surface of the silicon wafer after polishing in step S1 is 30-40%; and the size of the tower base is 2-6 μm.

[0009] In an optional embodiment, the thickness of the i:a-Si layer in step S2 is 2-10 nm; the P:a-Si layer includes P:a-Si layers and P-uc-SiO x C y Layered; wherein the thickness of the P: a-Si layer is 10-20nm and the doping concentration is 1E+18cm -3 ~5E+18cm -3 :The P-uc-SiO x C y The thickness of the layer is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The thickness of the i:a-Si mask layer is 10-200nm.

[0010] In an optional embodiment, the width of the laser etching in step S3 is 100-500 μm; the width of the laser etching in step S6 is 100-500 μm; and the width of the laser etching in step S9 is 10-100 μm.

[0011] In an optional embodiment, the reflectivity of the corroded area in step S4 is 35-45%; the tower base size of the corroded area is 8-15 μm; and the corrosion depth of the corroded area is 0.5-2 μm.

[0012] In an optional embodiment, the thickness of the i:a-Si layer in step S5 is 2-10 nm; the N:a-Si layer includes a N:a-Si layer and a N-uc-Si layer; wherein the thickness of the N:a-Si layer is 10-20 nm and the doping concentration is 1E+18 cm -3 ~5E+18cm -3 :The thickness of the N-uc-Si layer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The thickness of the i:a-Si mask layer is 10-200nm.

[0013] In an optional embodiment, the reflectivity of the velvet surface after the front surface texturing in step S7 is 9-12%.

[0014] In an optional embodiment, the doping concentration of the FSF field passivation region in step S8 is 1E+18cm -3 ~3E+18cm -3 ; The thickness of the silicon nitride laminated gradient film is 75-105nm; the refractive index of the silicon nitride laminated gradient film is 1.8-2.2; the thickness of the TCO layer is 70-150nm; the square resistance of the TCO layer is 50-120.

[0015] In a second aspect, an embodiment of the present disclosure also provides a back-contact HBC solar cell structure prepared by the method described above, comprising: the back P region of the cell structure comprises a low-reflection alkali-poled morphology, the N region comprises a high-reflection alkali-poled morphology, and an interdigitated arrangement structure is formed between the back P region and the N region.

[0016] In a third aspect, the embodiments of the present disclosure further provide a photovoltaic module that adopts the back-contact HBC solar cell structure as described above.

[0017] The beneficial effect of the present invention is that the P region of the back-contact HBC solar cell structure and its preparation method, and the photovoltaic module use a low-reflection alkali-polished tower base morphology, and the N region uses a high-reflection alkali-polished tower base morphology, which improves the back reflectivity without affecting the passivation. At the same time, the N region and the P region use substrates with different morphologies, which is more conducive to laser grooving positioning and identification, and prepares the amorphous interdigitated arrangement structure of the N region and the P region, reducing the risk of battery leakage and offset.

[0018] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A process flow chart of an HBC solar cell provided in an embodiment of the present disclosure;

[0022] Figure 2 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0023] Figure 3 A process flow chart of an HBC solar cell provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0026] Figure 6 A process flow chart of an HBC solar cell provided in an embodiment of the present disclosure;

[0027] Figure 7 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0028] Figure 8 A process flow chart of an HBC solar cell provided in an embodiment of the present disclosure;

[0029] Figure 9 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0030] Figure 10A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0031] Figure 11 A process flow chart of an HBC solar cell provided in an embodiment of the present disclosure;

[0032] Figure 12 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0033] Figure 13 A process flow chart of an HBC solar cell provided in an embodiment of the present disclosure;

[0034] Figure 14 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0035] Figure 15 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure;

[0036] Figure 16 A schematic structural diagram of an HBC solar cell provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0038] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Thus, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations, aspects, or designs. Instead, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0039] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0040] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limiting. As used herein, the singular articles "a", "an" and "the" may also be intended to include plural forms, unless otherwise clearly indicated herein. The terms "comprise", "include" and "have" are inclusive and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the particular order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0041] IBC cells are characterized by the absence of electrodes on the front side, with positive and negative electrode grid lines integrated in a forked pattern on the back side. Key features include: 1. High-minority-carrier-lifetime silicon wafers are used to prevent carrier recombination before reaching the PN junction; 2. Positive and negative electrodes are integrated on the back side, with a grid line pattern and a large design window; 3. Front-side anti-reflection stacking and front-surface field design maximize optical utilization and reduce front-surface recombination; 4. The back-side N and P regions are arranged in a forked pattern, with the P region (emitter) collecting holes and the N region (back field) capturing electrons; 5. Thin-film heterojunction (HJT) technology is used to fabricate the N-region field electrode and the P-region emitter, improving the cell's passivation level.

[0042] The advantages of IBC cells include: 1. No grid lines blocking the front, resulting in high photon absorption and current density. 2. Combined with HJT technology, this improves cell current density and efficiency without passivation losses. 3. With both positive and negative electrodes on the back, grid line width can be increased, contact resistance can be reduced, and FF can be improved without significantly affecting current. 4. The grid line-free design on the front of the cell makes the cell aesthetically pleasing and offers clear advantages in BIPV (building-integrated photovoltaic) applications.

[0043] The challenges of HBC batteries are as follows: 1. Low bifaciality (the gate lines are integrated on the back side, resulting in an increase in the back side shading area and a large difference in efficiency between the front and back sides); 2. Complex process, multiple steps, expensive equipment, high cost and low yield (the traditional HBC battery preparation process includes: texturing and cleaning--front i: a-Si--front SiNx--back i: a-Si--back P: a-Si--back mask--laser grooving--etching--back i: a-Si--back N: a-Si--laser film opening--etching--back TCO--laser film opening to isolate PN area--printing and curing--light injection); 3. The amorphous interdigitated structure of the back N and P regions is difficult to prepare (it is difficult for the laser to accurately locate the film opening area and the film opening depth); 4. HBC batteries have high requirements for silicon wafer quality and front surface passivation (carriers are separated from the PN junction and need to pass through the front surface and body of the silicon wafer to reach the back. Defects in the front surface of the battery will recombine the carriers before they reach the PN junction).

[0044] Prior art 1: Patent No. CN 115050855 A

[0045] Scheme steps: 1. Double-sided texturing; 2. Back-side polishing; 3. Double-sided deposition of i:a-Si; 4. Back-side patterned boron paste printing and drying; 5. Back-side patterned phosphorus paste printing and drying; 6. Laser doping of N and P regions; 7. Ultrasonic cleaning of slurry with organic water mixed solution; 8. Back-side TCO deposition; 9. Laser grooving to isolate N and P regions; 10. Front-side deposition of SiO / SiON / SiN stacked films; 11. Screen printing, curing and sintering.

[0046] Concept: 1. From top to bottom: SiN / SiON / SiO---i:a-Si---suede surface---silicon base---polished surface---i:a-Si---P:a-Si---Na:Si---TCO---silver paste HBC battery structure;

[0047] 2. Deposit i:a-Si on the back of the battery, use a screen to cross-print boron slurry and phosphorus slurry, then dry, laser dope, and clean to complete the poly interdigitated arrangement structure in the N and P regions on the back of the battery.

[0048] shortcoming:

[0049] 1. Using doping slurry as the doping source. Due to its special fluidity and corrosiveness, the doping source slurry requires the use of professional scrapers, scrapers, special non-metallic mesh, and non-market mass production auxiliary materials;

[0050] 2. To meet printing requirements, doping pastes often add more organic solvents to achieve curing. Organic solvents will affect the diffusion effect of boron and phosphorus doping, resulting in poor diffusion uniformity.

[0051] 3. To meet printing requirements, doping slurry often requires more organic solvents, which have a strong odor and require higher ventilation and protective measures for employees;

[0052] 4. Laser boron-phosphorus slurry doping amorphous silicon makes it difficult to control the doping amount and doping depth, which can easily damage the underlying hydrogenated amorphous silicon and affect battery passivation.

[0053] 5. The ARC anti-reflection film is prepared at a high temperature of >200°C on the front side, which can easily lead to a decrease in the passivation of amorphous silicon;

[0054] 6. The front side adopts SiNx+i:a-Si anti-reflection passivation film design, which has large parasitic absorption and large battery current loss;

[0055] 7. In this process, amorphous silicon is exposed for a long time without a protective film, which affects the passivation of the battery.

[0056] Prior art 2: CN 218849510 U

[0057] The scheme steps are as follows: 1. Cleaning and texturing; 2. Preparation of silicon oxide and intrinsic amorphous silicon on the back; 3. High-temperature phosphorus diffusion, crystallization of the amorphous on the back into phosphorus-doped polysilicon; 4. Laser etching; 5. Poly cleaning, de-plating and expansion, alkaline polishing and cleaning of the laser ablation area until the N-type silicon base is washed; 6. Deposition of intrinsic amorphous silicon on the front; 7. Preparation of silicon nitride on the front; 8. Preparation of intrinsic amorphous silicon and P:a-Si by back mask-grooving-deposition-etching technology; 9. Preparation of TCO by back mask-grooving-deposition-etching technology; 10. Screen electrode printing and curing.

[0058] concept:

[0059] The back N and P regions are prepared by the traditional mask-grooving-deposition-etching method. The N region adopts a polo passivation contact structure of SiO and N+poly to replace the i:a-Si+N:a:Si battery structure.

[0060] shortcoming:

[0061] 1. The front side adopts the anti-reflection passivation film design of SiNx+i:a-Si, which has large parasitic absorption and large battery current loss;

[0062] 2. The back N region uses SiO and N+poly polo passivation contact structure interface H passivation effect is poor;

[0063] 3. The N+poly preparation of the back N area uses high-temperature tubular equipment, which involves wrap-around expansion and wrap-around plating.

[0064] The defects in the above solutions are the results obtained by the inventors after practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by this disclosure for the above problems below should be the contributions made by the inventors to this disclosure during the disclosure process.

[0065] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0066] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0067] Step S1. Double-sided polishing of the silicon wafer to prepare a low-reflection smooth alkali-polished tower base morphology and a clean silicon wafer surface. Figure 1 The process flow shown in Figure 2 The specific process of the silicon wafer shown is as follows:

[0068] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0069] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0070] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to polish the surface of the silicon wafer to form an alkali polishing tower base morphology and remove cutting damage. The process temperature is 60°C-85°C and the process time is 3min-5min.

[0071] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0072] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the silicon wafer surface to remove additive residues. The process temperature is 55°C-70°C and the process time is 2min-5min.

[0073] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0074] A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%), and O3 (10ppm-50ppm) is used to clean the silicon wafer surface. At the same time, the weak etching system of O3 and HF lubricates the silicon wafer surface, reduces burrs on the silicon wafer surface, and is more conducive to the passivation of amorphous silicon. The process temperature is 15℃-25℃, and the process time is 2min-3min.

[0075] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0076] Use a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) to clean the silicon wafer surface. The process temperature is room temperature and the process time is 3min-5min.

[0077] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0078] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0079] Place the silicon wafer in a drying tank and purge it at high temperature to dry the surface of the silicon wafer. The purge gas is nitrogen or compressed air. The temperature is 80℃-100℃ and the drying time is 5min-15min.

[0080] Wafer weight reduction: 0.3g-0.6g (taking 182.2 size wafer as an example)

[0081] Surface reflectivity: 30%-40%;

[0082] Tower base size: 2um-6um.

[0083] Step S2, deposition of ia:Si / P:a-Si / SiO2 mask 1 on the back of the silicon wafer, see Figure 3 The process flow shown in Figure 4 The specific process of the silicon wafer shown is as follows:

[0084] The flat-plate PECVD method is used to deposit a layer of i: a-Si from top to bottom on the back of the double-sided alkali-polished silicon wafer, and then the deposited surface is cleaned by HPT (H ion cleaning). Then, the flat-plate PECVD method is used to deposit P: a-Si on the back of the silicon wafer from top to bottom. The deposition includes (a layer of P: a-Si, a layer of P-uc-SiO x C y ), and finally a layer of SiO2 mask is deposited on the back of the silicon wafer from top to bottom by PVD;

[0085] After double-sided alkaline polishing, the silicon wafer is placed on a hollow carrier plate, and the gate valve 1 is opened to transfer it into the loading chamber for evacuation. The gate valve 2 is opened to transfer it into the buffer preheating chamber 1, and then transferred to the PECVD1 reaction chamber 1 to deposit ia:Si from top to bottom. Then, it is transferred to the buffer HPT cleaning chamber 2, and the deposited surface is cleaned with H ions to complete the i:a-Si preparation.

[0086] Open gate valve 3, transfer the carrier into transition chamber 1 (gas isolation), open gate valve 4, first transfer it to buffer 3, and then transfer it to PECVD2 reaction chamber 2 to deposit a layer of P: a-Si and a layer of P-uc-SiO from top to bottom. x C y , and then transferred to buffer 4 to complete the P: a-Si preparation;

[0087] Open gate valve 5, transfer the carrier to transition chamber 2 (gas isolation), open gate valve 6, first transfer to buffer chamber 5, then transfer to PVD1 reaction chamber 1 to deposit a layer of SiO2 from top to bottom, and then transfer to buffer chamber 6 to complete the preparation of SiO2 mask 1;

[0088] PECVD1 reaction chamber 1: Preparation of i:a-Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0089] PECVD2 reaction chamber 3: P:a-Si is prepared by PECVD method. P:a-Si is divided into two layers: conventional B-doped amorphous silicon (Pa:Si) and B-doped microcrystalline carbon oxycarbon silicon (P-uc-SiOxCy);

[0090] Conventional B-doped amorphous silicon (P: a-Si) is prepared using SiH4, H2, and B2H6 as process gases, process temperature: 100°C-250°C, process pressure: 10Pa-50Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0091] Preparation of B-doped microcrystalline silicon oxycarbide (P-uc-SiOxCy), using SiH4, H2, B2H6, CO2, and TMB as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:30:10-1:60:30, CO2 and TMB as micro-doping gas flow: 5sccm-20sccm, power: 300w-500W;

[0092] Buffered HPT cleaning chamber 2: uses PECVD to ionize H to clean the deposited surface of the silicon wafer. H2 is used as the process gas. The process temperature is 100℃-250℃, the process pressure is 50Pa-100Pa, and the power is 50W-400W.

[0093] PVD1 reaction chamber 3: When SiO2 is prepared by PVD method, a silicon target is used, and argon and oxygen are used as working gases. The process temperature is 100-250°C, the process pressure is 0.2Pa-2Pa, the power is 1000W-40000W, and the Ar:O2 flow ratio is 100:1-100:5;

[0094] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0095] P: a-Si thickness: 10nm-20nm, P-uc-SiOxCy thickness: 20nm-50nm, thickness can be freely adjusted;

[0096] P: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 :P-uc-SiO x C y Doping concentration: 5E+18cm -3 ~2E+19cm -3 , the doping amount can be freely controlled;

[0097] SiO2 mask 1 thickness: 10nm-200nm, freely adjustable;

[0098] Specifically, the vacuum blocking technology of "transition-isolation-coating-isolation" is adopted to meet the process pressure of different film layer preparations, while avoiding process abnormalities caused by "cross-gas" between process gases of different film layer preparations. A single machine can meet the requirements of different film layer preparations, combining i: a-Si deposition & P: a-Si deposition & HPT cleaning into one.

[0099] Function of the transition chamber: adjust the pressure to meet the switching of different process pressure conditions / block the gas medium of different process chambers;

[0100] Function of buffer chamber: secondary isolation and blocking of different gas media.

[0101] Step S3, patterning laser etching of the back P region, removing the SiO2 mask 1 and part of the P:a-Si in the etching region, and obtaining Figure 5 The specific process of the silicon wafer shown is as follows:

[0102] Laser ablation technology is used to pattern the back silicon oxide mask. The battery is placed on a horizontal platform. A pulsed ultraviolet nanosecond laser is used to partially etch the SiO2 mask 1 and pattern the back film layer.

[0103] Laser power: 300w-600w;

[0104] Etching width: 100um-500um, freely adjustable.

[0105] Step S4, alkali polishing to remove the unmasked area on the back side i: a-Si / P: a-Si / P-uc-SiO x N y , and corrode the silicon base to a certain depth, please refer to Figure 6 The process flow shown in Figure 7 The specific process of the silicon wafer shown is as follows:

[0106] Use potassium hydroxide (1%-10%) and alkaline polishing additive (0.5%-5%) mixed solution to clean, potassium hydroxide corrodes the back unmasked area i: a-Si / P: a-Si / P-uc-SiO x N y , process temperature: 55℃-70℃, process time: 0.5min-1.5min;

[0107] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0108] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the silicon wafer surface to remove additive residues. The process temperature is 55°C-70°C and the process time is 2min-5min.

[0109] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0110] Use hydrochloric acid (1%-10%) solution to clean the silicon wafer surface to remove alkali residue; process temperature: room temperature, process time: 3min-5min;

[0111] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0112] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0113] Place the silicon wafer in a drying tank and purge it at high temperature to dry the surface of the silicon wafer. The purge gas is nitrogen or compressed air. The temperature is 80℃-100℃ and the drying time is 5min-15min.

[0114] Cleaning method: The silicon wafer enters the solution vertically, and the direction of the laser line on the silicon wafer is perpendicular to the solution surface. The drug residue on the silicon wafer surface is separated without being affected by the groove morphology on the back side.

[0115] Reflectivity of corroded area: 35%-45%;

[0116] The size of the tower base in the corroded area: 8um-15um;

[0117] Corrosion depth of corroded area: 0.5um-2um.

[0118] Step S5, deposition of ia:Si / Na:Si / N-uc-Si / SiO2 mask 2 on the back of the silicon wafer, see Figure 8 The process flow shown in Figure 9 The specific process of the silicon wafer shown is as follows:

[0119] A layer of i:a-Si is first deposited on the back of the alkali-washed silicon wafer from top to bottom using a flat-plate PECVD method, and then the deposited surface is cleaned by HPT (H ion cleaning). Then, a layer of Na:Si is first deposited on the back of the silicon wafer from top to bottom using a flat-plate PECVD method (a layer of Na:Si and a layer of N-uc-Si). Finally, a layer of SiO2 is deposited on the back of the silicon wafer from top to bottom using a PVD method.

[0120] After double-sided alkaline cleaning, the silicon wafer is placed on a hollow carrier plate, the gate valve 9 is opened, and the wafer is transferred to the loading chamber for evacuation. The gate valve 10 is opened, and the wafer is transferred to the buffer preheating chamber 7. The wafer is then transferred to the PECVD3 reaction chamber 4 to deposit ia:Si from top to bottom, and then transferred to the buffer HPT cleaning chamber 8. The deposition surface is cleaned with H ions to complete the i:a-Si preparation.

[0121] Open the gate valve 11, transfer the carrier into the transition chamber 3 (gas isolation), open the gate valve 12, first transfer it to the buffer 9, then transfer it to the PECVD4 reaction chamber 5 to deposit a layer of Na:Si and a layer of N-uc-Si from top to bottom, and then transfer it to the buffer 10 to complete the Na:Si preparation;

[0122] Open the gate valve 13, transfer the carrier to the transition chamber 4 (gas isolation), open the gate valve 14, first transfer it to the buffer chamber 11, then transfer it to the PVD2 reaction chamber 6 to deposit a layer of SiO2 from top to bottom, and then transfer it to the buffer chamber 12 to complete the SiO2 mask preparation;

[0123] PECVD3 reaction chamber 4: Preparation of i:a-Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0124] PECVD4 reaction chamber 5: Na:Si is prepared by PECVD method. Na:Si is divided into two layers: conventional P-doped amorphous silicon (Na:Si) and P-doped microcrystalline silicon (N-uc-Si);

[0125] Conventional P-doped amorphous silicon (P:a-Si) is prepared using SiH4, H2, and PH3 as process gases, process temperature: 100°C-250°C, process pressure: 10Pa-50Pa, SiH4:H2:PH3 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0126] Preparation of P-doped microcrystalline silicon oxycarbide (P-uc-Si), using SiH4, H2, and PH3 as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2:PH3 (2%) flow ratio: 1:30:10-1:60:30, power: 300w-500W;

[0127] Buffered HPT cleaning chamber 8: uses PECVD method to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0128] PVD2 reaction chamber 6: When SiO2 is prepared by PVD method, a silicon target is used, and argon and oxygen are used as working gases. The process temperature is 100-250°C, the process pressure is 0.2Pa-2Pa, the power is 1000W-40000W, and the Ar:O2 flow ratio is 100:1-100:5;

[0129] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0130] N: a-Si thickness: 10nm-20nm, N-uc-Si thickness: 20nm-50nm, thickness can be freely adjusted;

[0131] N: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 ,N-uc-Si doping concentration: 5E+18cm -3 ~2E+19cm -3 , the doping amount can be freely controlled;

[0132] SiO2 mask 2 thickness: 10nm-200nm, freely adjustable.

[0133] Step S6, patterning laser etching of the back P region, etching the SiO2 mask 2 to part of the SiO2 mask 1, and obtaining the following Figure 10 The specific process of the silicon wafer shown is as follows:

[0134] Laser ablation technology is used to pattern-etch the back silicon oxide mask 2 to the SiO2 mask 1. The battery is placed on a horizontal platform. A pulsed ultraviolet nanosecond laser is used to partially etch the SiO2 mask 2 to the SiO2 mask 1.

[0135] Laser power: 300w-600w;

[0136] Etching width: 100um-500um, freely adjustable.

[0137] Step S7, front surface texturing, back SiO2 mask removal, please refer to Figure 11 The process flow shown in Figure 12 The specific process of the silicon wafer shown is as follows:

[0138] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 1min-3min.

[0139] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0140] A mixed solution of potassium hydroxide (1%-10%) and a texturing additive (0.5%-5%) is used to form a pyramid velvet surface on the front side of the silicon wafer. The process temperature is 70°C-85°C and the process time is 3min-5min.

[0141] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0142] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the silicon wafer surface to remove additive residues. The process temperature is 55℃-70℃ and the process time is 1min-3min.

[0143] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0144] Use a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) to clean the silicon wafer surface. The process temperature is room temperature and the process time is 3min-5min.

[0145] Use water washing to remove drug residue and dirt on the surface. The cleaning time is 2-3 minutes.

[0146] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0147] Place the silicon wafer in a drying tank and purge it at high temperature to dry the surface of the silicon wafer. The purge gas is nitrogen or compressed air. The temperature is 80℃-100℃ and the drying time is 5min-15min.

[0148] Wafer weight reduction: 0.2g-0.3g (taking 182.2 size wafer as an example)

[0149] Suede reflectivity: 9%-12%;

[0150] Cleaning method: The silicon wafer enters the solution vertically, the direction of the laser line on the silicon wafer is perpendicular to the solution surface, and the drug residue on the silicon wafer surface is separated without being affected by the groove morphology on the back side.

[0151] Step S8: Prepare the FSF field passivation area on the front side of the silicon wafer, deposit a laminated graded silicon nitride anti-reflection passivation film on the front side, and deposit a TCO transparent conductive film on the back side. Figure 13 The process flow shown in Figure 14 The specific process of the silicon wafer shown is as follows:

[0152] The front of the silicon wafer is cleaned with H ions using a flat-plate PECVD method, while P atoms are implanted. A silicon nitride layered gradient film is then deposited on the front of the silicon wafer using PECVD. Finally, a TCO transparent conductive film is deposited on the back of the silicon wafer using PVD.

[0153] The textured silicon wafer is placed on a hollow carrier with the textured surface facing upwards. The gate valve 12 is opened and the wafer is transferred into the loading chamber for evacuation. The gate valve 18 is opened and the wafer is transferred into the ion deposition preheating buffer chamber 13 for H ion cleaning and then P ion implantation to complete the preparation of the front FSF field passivation area.

[0154] The carrier is transferred to the PECVD5 reaction chamber 7, where a layer of high H content SiNx, a layer of high Si content SiNx, and a layer of high N content SiNx are deposited from top to bottom. The carrier is then transferred to the buffer chamber 13 to complete the preparation of the laminated graded silicon nitride anti-reflection passivation film.

[0155] Open the gate valve 19, transfer the carrier to the transition chamber 14 (gas isolation), open the gate valve 20, first transfer it to the buffer chamber 14, then transfer it to the PVD3 reaction chamber 8, deposit a layer of TCO from bottom to top, and then transfer it to the buffer chamber 15 to complete the preparation of the TCO transparent conductive film;

[0156] Ion deposition preheating buffer chamber 13: First, PECVD method is used to ionize H2, and H ions are used to clean the deposition surface of the silicon wafer. H2 is used as the process gas, the process temperature is: 100℃-250℃, and the process pressure is: 50Pa-100Pa; then, PECVD method is used to ionize PH3 and H2 mixed gas, and P ions are implanted into the front side of the silicon wafer. PH3 and H2 are used as the process gases, the process temperature is: 100℃-250℃, and the process pressure is: 50Pa-100Pa;

[0157] PECVD5 reaction chamber 7: SiNx laminated gradient passivation anti-reflection film is prepared by PECVD method, which is divided into three layers;

[0158] SiNx-1: Using SiH4, H2, and NH3 as process gases, high H2 ratio, high pressure, and high power to prepare high-H content silicon nitride and passivate the silicon wafer interface. Process temperature: 100°C-250°C, process pressure: 80Pa-120Pa, SiH4 / NH3 / H2 flow ratio: 1:1:6-2:2:20; power: 200W-300W;

[0159] SiNx-2: Using SiH4 and NH3 as process gases, high Si content and high density silicon nitride is prepared at low pressure and low power with high SiH4 ratio to protect high H content silicon nitride. At the same time, low power coating reduces SiNx-1 passivation damage. Process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH4 / NH3 flow ratio: 2:1-6:1;

[0160] SiNx-3: Using SiH4 and NH3 as process gases, high NH3 ratio, low pressure and low power are used to prepare high-N content silicon nitride, which reduces the overall film refractive index, reduces the front reflectivity of the battery, and increases the current density. The process temperature is 100℃-250℃, the process pressure is 30Pa-50Pa, and the SiH4 / NH3 flow ratio is 1:2-1:6.

[0161] PVD3 reaction chamber 8: When preparing TCO by PVD method, ITO target material (In2O3 / SnO2 mass ratio: 90:10-97:3) is used, and argon and oxygen are used as working gases. The process temperature is 100-250℃, the process pressure is 0.2Pa-2Pa, the Ar / O2 flow ratio is 200:1-100:1, and the power is 5000W-40000W.

[0162] FSF doping concentration: 1E+18cm -3 ~1E+19cm -3 ;

[0163] SiNx thickness: 75nm-105nm;

[0164] SiNx refractive index: 1.8-2.2;

[0165] TCO thickness: 70nm-150nm;

[0166] TCO square resistance: 50-120.

[0167] Specifically, the present invention uses a low-temperature stacked silicon nitride film structure on the front side to replace the traditional i:a-Si+SiNx passivation anti-reflection structure, which reduces parasitic absorption without losing passivation, increases battery current density, and improves battery efficiency.

[0168] Step S9: laser etching on the back side to isolate the P and N regions and prepare an interdigitated structure. Figure 15 The specific process of the silicon wafer shown is as follows:

[0169] Laser ablation technology is used to pattern the interface between the P and N regions on the back side. TCO / P: a-Si / P-uc-SiOxCy / N: a-Si / N-uc-Si is used to keep i: a-Si. The battery is placed on a horizontal platform. A pulsed ultraviolet nanosecond laser is used to pattern the interface between the P and N regions on the back side. TCO / P:

[0170] a-Si / P-uc-SiOxCy / N: a-Si / N-uc-Si, reserved i: a-Si

[0171] Laser power: 300w-600w;

[0172] Etching width: 10um-100um, freely adjustable.

[0173] 10. Screen printing curing light injection, get Figure 16 The specific process of the silicon wafer shown is as follows:

[0174] Print metal paste on the amorphous silicon film layer in the N and P regions on the back side;

[0175] After printing, the silicon wafer is transferred to a curing oven, dried and cured to form an ohmic contact with the TCO;

[0176] The battery is transferred to the annealing furnace, where annealing light is injected to excite H and enhance passivation;

[0177] Complete HBC battery preparation.

[0178] In summary, the back-contact HBC solar cell structure and its preparation method, and the photovoltaic module use a low-reflection alkali-polished tower base morphology in the P region, and a high-reflection alkali-polished tower base morphology in the N region, which improves the back reflectivity without affecting the passivation. At the same time, the N region and the P region use substrates with different morphologies, which is more conducive to laser grooving positioning and identification, and prepares the amorphous cross-finger arrangement structure in the N region and the P region, reducing the risk of battery leakage and offset.

[0179] With the above-described preferred embodiments of the present invention as a guide, and with reference to the above description, relevant personnel are fully capable of making various changes and modifications without departing from the technical scope of this invention. The technical scope of this invention is not limited to the contents of the specification and must be determined according to the scope of the claims.

Claims

1. A method for preparing a back-contact HBC solar cell, characterized in that: The steps include: Step S1, double-sided polishing of the silicon wafer to prepare a clean silicon wafer surface with a low-reflection lubricating alkali polishing tower base morphology; Step S2, depositing an i: a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing a P: a-Si layer and a SiO2 mask layer from top to bottom in sequence; Step S3, laser etching the P region on the back side of the silicon wafer to remove the SiO2 mask layer and the P:a-Si layer in the etching region; Step S4, cleaning the back side of the silicon wafer by alkaline polishing to remove the deposited layer in the unmasked area, and etching the silicon base to clean the silicon wafer; Step S5, depositing an i: a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing an N: a-Si layer and a SiO2 mask layer from top to bottom in sequence; Step S6, laser etching the P region on the back side of the silicon wafer to expose the SiO2 mask layer underneath; Step S7, texturing the front side of the silicon wafer to form a pyramid texture surface, and cleaning and removing the patterned silicon oxide mask on the back side; Step S8, after H ion cleaning on the front side of the silicon wafer, P atoms are implanted to prepare a FSF field passivation region, and a silicon nitride laminated gradient film is deposited, and then a TCO layer is deposited on the back side of the silicon wafer; Step S9, laser etching the back side of the silicon wafer to isolate the P region from the N region on the back side, thereby preparing an interdigitated arrangement structure; Step S10, printing metal paste on the back side of the silicon wafer, curing and light injection, and completing the preparation of the battery.

2. The preparation method according to claim 1, characterized in that The reflectivity of the surface of the silicon wafer after polishing in step S1 is 30-40%; The size of the tower base is 2-6μm.

3. The preparation method according to claim 1, characterized in that: In step S2 The thickness of the i:a-Si layer is 2-10 nm; The P:a-Si layer includes a P:a-Si layer and a P-uc-SiO x C y Layering; in The thickness of the P:a-Si layer is 10-20nm, and the doping concentration is 1E+18cm -3 ~5E+18cm -3 : The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The thickness of the i:a-Si mask layer is 10-200 nm.

4. The preparation method according to claim 1, characterized in that: In step S3 The width of laser etching is 100-500μm; In step S6 The width of laser etching is 100-500μm; In step S9 The width of the laser etching is 10-100 μm.

5. The preparation method according to claim 1, characterized in that: In step S4 The reflectivity of the corroded area is 35-45%; The size of the tower base in the corroded area is 8-15 μm; The corrosion depth of the corroded area is 0.5-2μm.

6. The preparation method according to claim 1, characterized in that: In step S5 The thickness of the i:a-Si layer is 2-10 nm; The N:a-Si layer includes N:a-Si layer and N-uc-Si layer; wherein The thickness of the N:a-Si layer is 10-20 nm, and the doping concentration is 1E+18 cm -3 ~5E+18cm -3 : The thickness of the N-uc-Si layer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 ; The thickness of the i:a-Si mask layer is 10-200 nm.

7. The preparation method according to claim 1, characterized in that: In step S7 The reflectivity of the velvet surface after velveting on the front side is 9-12%.

8. The preparation method according to claim 1, characterized in that: In step S8 The doping concentration of the FSF field passivation region is 1E+18cm -3 ~3E+18cm -3 ; The thickness of the silicon nitride laminated gradient film is 75-105nm; The refractive index of the silicon nitride laminated gradient film is 1.8-2.2; The thickness of the TCO layer is 70-150 nm; The sheet resistance of the TCO layer is 50-120.

9. A back-contact HBC solar cell structure prepared by the method according to any one of claims 1 to 8, characterized in that: include: The back P region of the battery structure includes a low-reflection alkaline-powder-based morphology, the N region includes a high-reflection alkaline-powder-based morphology, and an interdigitated arrangement structure is formed between the back P region and the N region.

10. A photovoltaic module, characterized in that: A back contact HBC solar cell structure as described in claim 9 is adopted.

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