A solar cell and a method for preparing the same

Abstract

The present invention discloses a solar cell and a preparation method thereof, and relates to the technical field of solar cells. The preparation method comprises: polishing a silicon-based substrate, and forming a tower base on the surface of the silicon-based substrate, the surface of the silicon-based substrate comprises a relative front and back surface, and the back surface comprises a first area, a second area, and an isolation area between the first area and the second area; a wet oxide layer, a thermal oxide layer, a doped polysilicon layer, and a mask layer are formed in the first area and the second area respectively, and the wet oxide layer and the thermal oxide layer in the first area and the second area respectively constitute a tunneling oxide layer; removing the mask layer in the first area and the second area; forming a passivation layer and an anti-reflection layer in the front, the first area, the second area, and the isolation area in sequence; and forming electrodes in contact with doped polysilicon in the first area and the second area respectively. The present invention can accurately control the thickness and uniformity of the tunneling oxide layer, thereby improving the performance of the solar cell.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] In recent years, with the rapid development of photovoltaic technology, the requirements for the conversion efficiency of solar cells have been continuously improved. Among them, back contact (BC) crystalline silicon solar cells, as a high-efficiency photovoltaic cell, have become a hot topic in current research.

[0003] In the structure of BC cells, the passivation level of the back P and N regions plays a key role in the performance of the cell. In the prior art, by forming an ultra-thin tunneling oxide layer and a doped polysilicon layer on the surface of the cell, the passivation performance of the cell surface can be effectively improved, thereby increasing the open circuit voltage and short circuit current of the cell, and improving the overall performance of the solar cell.

[0004] However, since the thickness and uniformity of the tunneling oxide layer directly affect the surface passivation level of the battery and the stability of the contact resistance, how to control the thickness and uniformity of the tunneling oxide layer has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a solar cell and a preparation method thereof, so as to accurately control the thickness and uniformity of a tunneling oxide layer in the solar cell, thereby improving the performance of the solar cell.

[0006] A first aspect of the present invention provides a method for preparing a solar cell, the method for preparing a solar cell comprising:

[0007] Polishing a silicon-based substrate and forming a tower base on the surface of the silicon-based substrate; the surface of the silicon-based substrate at least includes a front side and a back side opposite to each other; the back side includes a first area, a second area, and an isolation area between the first area and the second area;

[0008] A first wet oxide layer, a first thermal oxide layer, a first doped polysilicon layer and a first mask layer are sequentially formed in the first region; the first wet oxide layer and the first thermal oxide layer constitute a first tunneling oxide layer;

[0009] forming a second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer in sequence in the second region; the second wet oxide layer and the second thermal oxide layer constitute a second tunneling oxide layer;

[0010] removing the first mask layer in the first area and the second mask layer in the second area;

[0011] forming a passivation layer and an anti-reflection layer in the front surface, the first area, the second area and the isolation area in sequence;

[0012] A first electrode is formed in the first region in contact with the first doped polysilicon layer, and a second electrode is formed in the second region in contact with the second doped polysilicon layer.

[0013] Optionally, forming a first wet oxide layer, a first thermal oxide layer, a first doped polysilicon layer and a first mask layer in sequence in the first region includes:

[0014] Using a mixed solution of hydrochloric acid and hydrogen peroxide to wet-oxidize the surface of the silicon-based substrate to form a first wet oxide layer on the surface of the silicon-based substrate;

[0015] Thermally oxidizing the silicon-based substrate at a first preset temperature to form a first thermal oxide layer that is combined with the first wet oxide layer to form a first tunnel oxide layer, and forming an intrinsic polysilicon layer on a surface of the first tunnel oxide layer that is away from the silicon-based substrate;

[0016] At a second preset temperature, the intrinsic polysilicon layer is doped with a first type of material to form a first doped polysilicon layer and a first mask layer.

[0017] Optionally, before sequentially forming a second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer in the second region, the method further includes:

[0018] The first mask layer, the first doped polysilicon layer and the first tunneling oxide layer on the surface of the silicon-based substrate except the first region are removed.

[0019] Optionally, removing the first mask layer, the first doped polysilicon layer, and the first tunneling oxide layer on the surface of the silicon-based substrate except the first region includes:

[0020] removing the first mask layer in the second region and the isolation region by using laser;

[0021] removing the first mask layer on the front surface by using hydrofluoric acid;

[0022] An alkaline polishing tank machine is used to remove the first doped polysilicon layer and the first tunneling oxide layer in the second region and the front side expansion.

[0023] Optionally, after removing the first mask layer, the first doped polysilicon layer and the first tunneling oxide layer on the surface of the silicon-based substrate except the first region, the method further includes:

[0024] The exposed surface of the silicon-based substrate is polished, and a tower base is formed on the exposed surface of the silicon-based substrate.

[0025] Optionally, a second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer are sequentially formed in the second region; the second wet oxide layer and the second oxide layer constitute a second tunneling oxide layer, including:

[0026] Using a mixed solution of hydrochloric acid and hydrogen peroxide to wet-oxidize the surface of the silicon-based substrate in the second region to form a second wet oxide layer on the surface of the silicon-based substrate in the second region;

[0027] Thermally oxidizing the silicon-based substrate in the second region at a third preset temperature to form a second thermal oxide layer that is combined with the second wet oxide layer to form a second tunneling oxide layer, and forming an intrinsic polysilicon layer on a surface of the second tunneling oxide layer that is away from the silicon-based substrate;

[0028] At a fourth preset temperature, the intrinsic polysilicon layer is doped with a second type of material to form a second doped polysilicon layer and a second mask layer.

[0029] Optionally, before removing the first mask layer in the first area and the second mask layer in the second area, the method further includes:

[0030] The second mask layer, the second doped polysilicon layer and the second tunneling oxide layer on the surface of the silicon-based substrate except the second region are removed.

[0031] Optionally, removing the second mask layer, the second doped polysilicon layer and the second tunneling oxide layer on the surface of the silicon-based substrate except the second region comprises:

[0032] removing the second mask layer in the first area and the isolation area by using laser;

[0033] removing the second mask layer on the front side by using hydrofluoric acid;

[0034] An alkali polishing tank machine is used to remove the second doped polysilicon layer and the second tunneling oxide layer in the first area and the front side expansion.

[0035] Optionally, after removing the second mask layer, the second doped polysilicon layer and the second tunneling oxide layer on the surface of the silicon-based substrate except the second region, the method further includes:

[0036] The exposed surface of the silicon-based substrate is polished, and a tower base is formed on the exposed surface of the silicon-based substrate.

[0037] A second aspect of the present invention provides a solar cell, which is manufactured using the above-mentioned method for manufacturing a solar cell, and the solar cell comprises:

[0038] A silicon-based substrate; the surface of the silicon-based substrate comprises at least a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region;

[0039] A first tunneling oxide layer and a first doped polysilicon layer are sequentially stacked in the first region; the first tunneling oxide layer is composed of a first wet oxide layer and a first thermal oxide layer;

[0040] A second tunneling oxide layer and a second doped polysilicon layer are sequentially stacked in the second region; the second tunneling oxide layer is composed of a second wet oxide layer and a second thermal oxide layer;

[0041] a passivation layer covering the first region, the second region, the isolation region and the front side;

[0042] an anti-reflection layer covering the passivation layer;

[0043] A first electrode and a second electrode; the first electrode is located in the first region and contacts the first doped polysilicon layer, and the second electrode is located in the second region and contacts the second doped polysilicon layer.

[0044] The technical solution of the present invention is to form a wet oxide layer, a thermal oxide layer, a doped polysilicon layer and a mask layer in the first area and the second area on the back of the silicon-based substrate in sequence after polishing the silicon-based substrate and forming a tower base on the surface of the silicon-based substrate, and the film layers formed in the first area and the second area are isolated from each other by the isolation area, so that the photogenerated carriers generated by the solar cell can form a loop between the film layers in the first area and the second area; at the same time, the wet oxide layer and the thermal oxide layer in the first area jointly constitute the tunneling oxide layer in the first area, and the wet oxide layer and the thermal oxide layer in the second area jointly constitute the tunneling oxide layer in the second area, so that the tunneling oxide The oxide layer is formed by wet oxidation and high temperature oxidation. The thickness and uniformity of the tunnel oxide layer can be controlled by wet oxidation. The overall density of the tunnel oxide layer can be improved by subsequent high temperature oxidation to ensure that the tunnel oxide layer formed has high density, uniformity and appropriate thickness. After forming the first electrode in contact with the doped polysilicon in the first area and the second electrode in contact with the doped polysilicon layer in the second area, the passivation contact effect can be guaranteed, which is conducive to reducing the contact resistance, increasing the open circuit voltage of the solar cell, and thus improving the conversion efficiency of the solar cell. In addition, before forming the first electrode and the second electrode, the mask layer used to protect the doped polysilicon layer in the first area and the second area is removed, and after removing the mask layer, a passivation layer and an anti-reflection layer are formed to cover the front side of the silicon-based substrate, the first area, the second area, and the isolation area between the first area and the second area, so as to improve the photoelectric conversion efficiency of the solar cell under the premise of being able to play a certain protective role on the solar cell, so that the solar cell has a higher output power and stability.

[0045] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 is a schematic flow chart of a method for preparing a solar cell provided by an embodiment of the present invention;

[0048] Figure 2 is a structural schematic diagram of a solar cell manufacturing process provided by an embodiment of the present invention;

[0049] Figure 3 is a schematic flow chart of a method for preparing each film layer in the first zone provided by an embodiment of the present invention;

[0050] Figure 4 is a structural schematic diagram of the preparation process of each film layer in the first zone provided by an embodiment of the present invention;

[0051] Figure 5 It is a structural schematic diagram of a process of removing each film layer on the surface of a silicon-based substrate except the first region provided by an embodiment of the present invention;

[0052] Figure 6 is a schematic flow chart of a method for preparing each film layer in the second zone provided in an embodiment of the present invention;

[0053] Figure 7 is a structural schematic diagram of a preparation process of each film layer in the second zone provided by an embodiment of the present invention;

[0054] Figure 8 It is a structural schematic diagram of a process of removing each film layer on the surface of a silicon-based substrate except the second region provided by an embodiment of the present invention;

[0055] Fig. 9 It is a schematic diagram of the structure of a solar cell provided by an embodiment of the present invention.

[0056] In the figure: 00. Silicon-based substrate; 01. Front side; 02. Back side; 1. First area; 2. Second area; 3. Isolation area; 001. Tower base; 11. First wet oxide layer; 12. First thermal oxide layer; 13. First doped polysilicon layer; 14. First mask layer; 111. First tunneling oxide layer; 21. Second wet oxide layer; 22. Second thermal oxide layer; 23. Second doped polysilicon layer; 24. Second mask layer; 211. Second tunneling oxide layer; 4. Passivation layer; 5. Anti-reflection layer; 15. First electrode; 25. Second electrode. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] An embodiment of the present invention provides a method for preparing a solar cell, which is used to prepare the solar cell provided by the embodiment of the present invention. The solar cell prepared by the method for preparing a solar cell can have a reduced passivation contact resistance and a higher open circuit voltage, thereby ensuring that the solar cell has a higher conversion efficiency. Figure 1 is a schematic diagram of a process for preparing a solar cell provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a solar cell manufacturing process provided by an embodiment of the present invention, and is combined with reference to Figure 1 and Figure 2 , the preparation method of the solar cell may include:

[0060] S101, polishing the silicon-based substrate, and forming a tower base on the surface of the silicon-based substrate.

[0061] The surface of the silicon-based substrate 00 at least includes a front side 01 and a back side 02 opposite to each other; the back side 02 includes a first region 1 , a second region 2 , and an isolation region 3 located between the first region 1 and the second region 2 .

[0062] It is understandable that the silicon-based substrate 00 may be an N-type silicon-based substrate or a P-type silicon-based substrate, and the doping type and doping concentration of the silicon-based substrate may be designed according to actual needs, and the embodiment of the present invention does not specifically limit this. In an exemplary embodiment, the silicon-based substrate 00 may be an N-type silicon-based substrate, and the resistivity of the silicon-based substrate 00 may be greater than or equal to 0.3Ω·cm and less than or equal to 7Ω·cm, for example, the resistivity of the silicon-based substrate 00 may be 3Ω·cm.

[0063] Specifically, the silicon-based substrate 00 can be polished on both sides by an alkaline polishing tank machine, and when the silicon-based substrate 00 is polished by an alkaline polishing liquid, the alkaline polishing liquid corrodes the surface of the silicon-based substrate 00, thereby forming a microstructure on the surface of the silicon-based substrate 00. The microstructure is a tower base formed on the surface of the silicon-based substrate. The presence of the tower base enables the silicon-based substrate 00 to have a larger surface area, thereby enabling the silicon-based substrate 00 to have a larger light contact surface, which is beneficial to improving the photoelectric conversion efficiency of the silicon-based substrate 00. Among them, the size d of the tower base 001 formed on the surface of the silicon-based substrate 00 can be designed according to actual needs, and the embodiment of the present invention does not make specific limitations on this. In an exemplary embodiment, the value range of the size d of the tower base 001 can be 10μm≤d≤20μm. For example, the size d of the tower base 001 can be 15μm.

[0064] As a feasible embodiment, when polishing the surface of the silicon-based substrate 00, the alkaline polishing liquid used may include a NaOH solution, which may contain appropriate additives. The concentration of the NaOH solution may be 0.5%-2%, and the concentration of the additive may be 0.5%-1%. For example, the concentration of the NaOH solution may be 1%, and the concentration of the additive may be 0.5%. The polishing reaction time may be 300S.

[0065] In addition, the back side of the silicon-based substrate 00 includes a first region 1 and a second region 2, one of which is a P region and the other is an N region. It should be noted that, for the convenience of description, without special limitations, the embodiments of the present invention all take the silicon-based substrate 00 as an N-type silicon-based substrate, the first region 1 as a P region, and the second region 2 as an N region as an example to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0066] The back side of the silicon-based substrate 00 also includes a spacing region 3 between the first region 1 and the second region 2. The isolation region 3 can be formed by a process such as wet etching. The isolation region 3 between the first region 1 and the second region 2 can isolate the P region and the N region from each other to prevent leakage caused by a short circuit between the first region 1 and the second region 2. Wherein, under the premise of isolating the first region 1 and the second region 2 from each other, the size of the isolation region 3 should be as small as possible. In an exemplary embodiment, the width of the isolation region 3 can range from 50 μm to 150 μm, for example, the width of the isolation region 3 can be 100 μm.

[0067] S102 , sequentially forming a first wet oxide layer, a first thermal oxide layer, a first doped polysilicon layer and a first mask layer in the first region.

[0068] The first wet oxide layer 11 and the first thermal oxide layer 12 form a first tunneling oxide layer 111 .

[0069] It can be understood that the first wet oxide layer 11 and the first thermal oxide layer 12 are formed in different steps in different processes, and the step of forming the first wet oxide layer 11 is located before the step of forming the first thermal oxide layer 12. The first wet oxide layer 11 can be formed by a wet oxidation process, that is, the silicon-based substrate 00 can be placed in a high oxygen solution to oxidize the surface of the silicon-based substrate 00, thereby forming the first wet oxide layer 11, and the first wet oxide layer 11 can include, for example, SiO2. Exemplarily, the specific formation method of the first wet oxide layer 11 can include: using a mixed solution of hydrochloric acid and hydrogen peroxide to wet oxidize the first area 1 of the silicon-based substrate 00 to form a layer of silicon oxide film, and the silicon oxide film is the first wet oxide layer 11. The volume concentration of hydrochloric acid or hydrogen peroxide used to form the first wet oxide layer 11 is 5%-10%, and the thickness of the formed first wet oxide layer can range from 0.5nm to 1.5nm.

[0070] After the first wet oxide layer 11 is formed, a high temperature oxidation process may be used to continue oxidizing the surface of the silicon-based substrate 00, that is, oxygen is introduced while heating the silicon-based substrate 00, so that the silicon-based substrate is in a high temperature and high oxygen environment, so as to form a first thermal oxide layer 12, and the first thermal oxide layer 12 may also include SiO2, etc.; after the preparation of the first thermal oxide layer 12 is completed, the first wet oxide layer 11 is combined with the first thermal oxide layer 12 to form a first tunneling oxide layer 111. Exemplarily, the specific formation method of the first thermal oxide layer 12 may include: placing the silicon-based substrate after the first wet oxide layer 11 is formed in a tubular diffusion furnace, heating the silicon-based substrate 00 after the first wet oxide layer 11 is formed, and introducing oxygen, so that in the high temperature and high oxygen environment, oxygen reacts with the silicon-based substrate 00 to generate a silicon oxide layer that penetrates into the first wet oxide layer 11, and the silicon oxide is the first thermal oxide layer 12. The temperature for forming the first thermal oxide layer 12 can be controlled within the range of 600°C-650°C, the flow rate of the introduced oxygen can be within the range of 5000sccm-10000sccm, and the thickness of the generated first thermal oxide layer 12 can be within the range of 1nm-2nm.

[0071] Among them, by controlling the concentration of the high oxygen solution used to form the first wet oxide layer 11, the reaction time, etc., the thickness of the formed first wet oxide layer 11 can be controlled, that is, the overall thickness of the first tunnel oxide layer 111 can be controlled, and by controlling the temperature when forming the first thermal oxide layer 12 and the flow rate of oxygen, etc., the uniformity of the finally formed first tunnel oxide layer 111 can be controlled. In this way, by forming the first wet oxide layer 11 and the first thermal oxide layer 12 in steps, it can be ensured that the first tunnel oxide layer 111 has a suitable thickness and high uniformity, so that the thickness and uniformity of the first tunnel oxide layer 111 can be accurately controlled, so that the first tunnel oxide layer 111 can reduce the recombination loss of electrons and holes, which helps to improve the open circuit voltage of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0072] It can also be understood that when the first region 1 is a P region, the first doped polysilicon layer 13 can be specifically understood as a polysilicon layer doped with boron, and the first doped polysilicon layer 13 can form a tunnel junction with the first tunnel oxide layer 111 and the N-type silicon-based substrate 00. The presence of the tunnel junction can improve the electron transmission efficiency of the solar cell. The first mask layer 14 can be used to protect the first doped polysilicon layer 13 to prevent subsequent processes from damaging the first doped polysilicon layer 13, and the first mask layer 14 can include borosilicate glass. Among them, the first mask layer 14 can be formed in the same process as the first doped polysilicon layer 13. For example, since the formation temperature of the first thermal oxide layer 12 is close to the formation temperature of polysilicon, silane can be introduced while forming the first thermal oxide layer 12, and a polysilicon layer can be formed by low-pressure chemical vapor deposition (LPCVD). After the polysilicon layer is formed, the doping temperature can be adjusted, for example, the temperature can be controlled within the range of 900°C-1000°C, and BCl3 or BBr3 can be used as a boron diffusion source to diffuse boron atoms into the polysilicon to achieve doping of the polysilicon and form a first doped polysilicon layer 13. While the polysilicon layer is being diffused with boron, a diffusion by-product will be formed on the surface of the polysilicon layer, that is, borosilicate glass will be formed. The borosilicate glass can protect the first doped polysilicon from being corroded by the alkaline and / or acidic solutions used in the wet process in subsequent processes.

[0073] The first doped polysilicon may be a lightly doped polysilicon layer or a heavily doped polysilicon layer, and the specific doping concentration may be designed according to actual needs, which is not specifically limited in the embodiment of the present invention. In an exemplary embodiment, the first doped polysilicon may be a lightly doped polysilicon layer, and the value range of its surface doping concentration may be 1×10 18 cm -3 -1×10 20 cm -3The square resistance of the first doped polysilicon can be in the range of 50ohm / sq-400ohm / sq; the thickness of the first doped polysilicon layer 13 can be in the range of 100nm-400nm, and the thickness of the first mask layer 14 can be in the range of 30nm-150nm.

[0074] S103 , forming a second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer in sequence in the second region.

[0075] The second wet oxide layer and the second thermal oxide layer constitute a second tunneling oxide layer.

[0076] It can be understood that the second wet oxide layer 21 and the second thermal oxide layer 22 can also be formed in different steps in different processes, and the step of forming the second wet oxide layer 21 is located before the step of forming the second thermal oxide layer 22. The second wet oxide layer 21 can be formed by a wet oxidation process, that is, the silicon-based substrate 00 can be placed in a high oxygen solution to oxidize the surface of the silicon-based substrate 00, thereby forming a second wet oxide layer 21, and the second wet oxide layer 21 can include, for example, SiO2. Exemplarily, the specific formation method of the second wet oxide layer 21 may include: using a mixed solution of hydrochloric acid and hydrogen peroxide to wet oxidize the second area 2 of the silicon-based substrate 00 to form a layer of silicon oxide film, and the silicon oxide film is the second wet oxide layer 21. Among them, the volume concentration of hydrochloric acid or hydrogen peroxide used to form the second wet oxide layer 21 is 5%-10%, and the thickness of the formed first wet oxide layer can range from 0.5nm to 1.5nm.

[0077] After the second wet oxide layer 21 is formed, a high temperature oxidation process can be used to continue to oxidize the surface of the silicon-based substrate 00, that is, oxygen is introduced while heating the silicon-based substrate 00, so that the silicon-based substrate is in a high temperature and high oxygen environment to form a second thermal oxide layer 22, and the second thermal oxide layer 22 can also include SiO2, etc.; after the preparation of the second thermal oxide layer 22 is completed, the second wet oxide layer 21 is combined with the second thermal oxide layer 22 to form a second tunneling oxide layer. Exemplarily, the specific formation method of the second thermal oxide layer 22 may include: placing the silicon-based substrate after the second wet oxide layer 21 is formed in a tubular diffusion furnace, heating the silicon-based substrate 00 after the second wet oxide layer 21 is formed, and introducing oxygen, so that in the high temperature and high oxygen environment, oxygen reacts with the silicon-based substrate 00 to generate a silicon oxide layer that penetrates into the second wet oxide layer 21, and the silicon oxide is the second thermal oxide layer 22. The temperature for forming the second thermal oxide layer 22 can be controlled within the range of 600°C-650°C, the flow rate of the introduced oxygen can be within the range of 5000sccm-10000sccm, and the thickness of the generated second thermal oxide layer 22 can be within the range of 1nm-2nm.

[0078] Among them, by controlling the concentration of the high oxygen solution used to form the second wet oxide layer 21, the reaction time, etc., the thickness of the formed second wet oxide layer 21 can be controlled, that is, the overall thickness of the second tunnel oxide layer 211 can be controlled, and by controlling the temperature when forming the second thermal oxide layer 22 and the flow rate of oxygen, etc., the uniformity of the finally formed second tunnel oxide layer 211 can be controlled. In this way, by forming the second wet oxide layer 21 and the second thermal oxide layer 22 in steps, it can be ensured that the second tunnel oxide layer 211 has a suitable thickness and high uniformity, so that the thickness and uniformity of the second tunnel oxide layer 211 can be accurately controlled, so that the second tunnel oxide layer 211 can reduce the recombination loss of electrons and holes, which helps to improve the open circuit voltage of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0079] It can also be understood that when the second region 2 is an N region, the second doped polysilicon layer 23 can be specifically understood as a polysilicon layer doped with phosphorus. The second mask layer 24 can be used to protect the second doped polysilicon layer 23 to prevent subsequent processes from damaging the second doped polysilicon layer 23, and the second mask layer 24 can include phosphorus silicon glass. Among them, the second mask layer 24 can be formed in the same process as the second doped polysilicon layer 23. For example, since the formation temperature of the second thermal oxide layer 22 is close to the formation temperature of polysilicon, silane can be introduced while forming the second thermal oxide layer 22, and a polysilicon layer can be formed by low-pressure chemical vapor deposition (LPCVD). After the polysilicon layer is formed, the doping temperature can be adjusted, for example, the temperature can be controlled within the range of 900°C-1000°C, and PH3 can be used as a phosphorus diffusion source to diffuse phosphorus atoms into the polysilicon to achieve doping of the polysilicon and form a second doped polysilicon layer 23. While phosphorus is being diffused into the polysilicon layer, a diffusion by-product will be formed on the surface of the polysilicon layer, that is, phosphosilicate glass will be formed. The phosphosilicate glass can protect the second doped polysilicon from being corroded by the alkaline and / or acidic solutions used in the wet process in subsequent processes.

[0080] The second doped polysilicon may be a lightly doped polysilicon layer or a heavily doped polysilicon layer, and the specific doping concentration may be designed according to actual needs, which is not specifically limited in the embodiment of the present invention. In an exemplary embodiment, the second doped polysilicon may be a lightly doped polysilicon layer, and the value range of its surface doping concentration may be 2×10 20 cm -3 -3×10 21 cm -3The square resistance of the second doped polysilicon can be in the range of 20ohm / sq-70ohm / sq; the thickness of the second doped polysilicon layer 23 can be in the range of 100nm-200nm, and the thickness of the second mask layer 24 can be in the range of 10nm-50nm.

[0081] S104 , removing the first mask layer in the first area and the second mask layer in the second area.

[0082] It can be understood that in the process of manufacturing solar cells, the first mask layer 14 is used to include the first doped polysilicon layer 13 in the first zone 1, and the second mask layer 24 is used to include the second doped polysilicon layer 23. Before completing the process of the solar cell, it is necessary to remove the first mask layer 14 in the first zone 1 and the second mask layer 24 in the second zone 2 to prevent the presence of the first mask layer 14 and the second mask layer 24 from affecting the conversion efficiency of the solar cell, while providing a good foundation for subsequent processes.

[0083] Among them, the method of removing the first mask layer 14 and the second mask layer 24 may include but is not limited to laser removal or wet removal. By way of example, when the first mask layer 14 includes a borosilicate glass layer and the second mask layer 24 includes a phosphosilicate glass layer, the method of wet removal of the first mask layer 14 and the second mask layer 24 may include: using hydrofluoric acid to corrode the first mask layer 14 and the second mask layer 24 to remove the borosilicate glass layer of the first area 1 and the phosphosilicate glass layer of the second area 2.

[0084] In an optional embodiment, after removing the first mask layer 14 and the second mask layer 24, residual mask materials and / or other impurities may exist on the surface of the first doped polysilicon layer 13 and the second doped polysilicon layer 23, which is not conducive to subsequent passivation contact. Therefore, after removing the first mask layer 14 and the second mask layer 24, the surface of the first doped polysilicon layer 14 and the second doped polysilicon layer 24 can also be cleaned by wet chemical cleaning to remove various pollutants and impurities on the surface of the first doped polysilicon layer 13 and the second doped polysilicon layer 23. The cleaning solution of the wet chemical cleaning may include hydrofluoric acid, etc.

[0085] S105 , forming a passivation layer and an anti-reflection layer in sequence in the front side, the first area, the second area and the isolation area.

[0086] Among them, the passivation layer 4 is used to protect the film layer below it, preventing the silicon-based substrate 00, the first doped polysilicon layer 13, the second doped polysilicon layer 23, etc. from being directly exposed to the air and being polluted by impurities, water oxygen, etc. in the air. At the same time, the storage of the passivation layer 4 can also improve the surface recombination effect, thereby reducing the loss of photogenerated carriers and improving the efficiency and performance of solar cells. The passivation layer 4 can include aluminum oxide, etc., and aluminum oxide can be deposited on the surface of the front surface 01, the first area 1, the second area 2 and the isolation area 3 by atomic layer deposition (ALD) to form a passivation layer. The thickness of the passivation layer can range from 2nm to 7nm. For example, the thickness of the passivation layer 4 can be 3nm.

[0087] The anti-reflection layer 5 can reduce the reflectivity of light, so that more light is absorbed by the solar cell, thereby improving the photoelectric conversion efficiency, and improving the efficiency and performance of the solar cell. The anti-reflection layer 5 may include a laminated structure of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and may be formed on the side of the passivation layer 4 away from the silicon-based substrate 00 by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the anti-reflection layer 5 may range from 60 nm to 130 nm, for example, the thickness of the anti-reflection layer 5 may be 80 nm.

[0088] S106 , forming a first electrode in contact with the first doped polysilicon layer in the first region, and forming a second electrode in contact with the second doped polysilicon layer in the second region.

[0089] The first electrode 15 and the second electrode 25 may include silver electrodes, etc., and the silver paste may be printed on the surface of the anti-reflection layer 5 of the first area 1 and the second area 2 away from the silicon-based substrate 00 by screen printing, and then the silver paste of the first area 1 and the second area 2 is sintered by laser sintering technology to form the first electrode 15 in contact with the first doped polysilicon and the second electrode 25 in contact with the second doped polysilicon, respectively, to form a passivation contact structure. In an exemplary embodiment, the wavelength of the laser used in laser sintering may be 1064nm or 532nm, and the width of the laser may be 100μm or 1mm-2mm.

[0090] Optionally, while forming the first electrode 15 and the second electrode 25, a main gate electrode on the back side is also formed, and the first electrode 15 and the second electrode 25 can be electrically connected to an external device or other solar cell through the main gate electrode. The main gate electrode can be formed in a similar manner to the first electrode 15 and the second electrode 25, that is, the main gate electrode, the first electrode 15 and the second electrode 25 can be manufactured in the same process, and the specific implementation method can be designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0091] In addition, after the preparation of solar cells is completed, the electrical properties of the solar cells need to be tested, such as the open circuit voltage, maximum output power, conversion efficiency, etc. of the solar cells, so as to sort and store the solar cells.

[0092] In this embodiment, after polishing the silicon-based substrate and forming a tower base on the surface of the silicon-based substrate, a wet oxide layer, a thermal oxide layer, a doped polysilicon layer and a mask layer are sequentially formed in the first area and the second area on the back of the silicon-based substrate, and the film layers formed in the first area and the second area are isolated from each other by the isolation area, so that the photogenerated carriers generated by the solar cell can form a circuit between the film layers in the first area and the second area; at the same time, the wet oxide layer and the thermal oxide layer in the first area together constitute the tunneling oxide layer in the first area, and the wet oxide layer and the thermal oxide layer in the second area together constitute the tunneling oxide layer in the second area, so that the tunneling oxide layer The formation is carried out by wet oxidation and high temperature oxidation. The thickness and uniformity of the tunneling oxide layer can be controlled by wet oxidation. The overall density of the tunneling oxide layer can be improved by subsequent high temperature oxidation to ensure that the formed tunneling oxide layer has a high density, uniformity and suitable thickness. After forming the first electrode in contact with the doped polysilicon in the first area and the second electrode in contact with the doped polysilicon layer in the second area, the passivation contact effect can be ensured, which is conducive to reducing the contact resistance, increasing the open circuit voltage of the solar cell, and thus improving the conversion efficiency of the solar cell. In addition, before forming the first electrode and the second electrode, the mask layer used to protect the doped polysilicon layer in the first area and the second area is removed, and after removing the mask layer, a passivation layer and an anti-reflection layer are formed to cover the front side of the silicon-based substrate, the first area, the second area, and the isolation area between the first area and the second area, so as to improve the photoelectric conversion efficiency of the solar cell under the premise of being able to play a certain protective role on the solar cell, so that the solar cell has a higher output power and stability.

[0093] Optionally, based on the above embodiment, this embodiment exemplarily illustrates the formation method of the first wet oxide layer 11 , the first thermal oxide layer 12 , the first doped polysilicon layer 13 and the first mask layer 14 in the first region 1 . Figure 3A schematic flow chart of a method for preparing each film layer in the first zone provided in an embodiment of the present invention, Figure 4 is a schematic diagram of the structure of the preparation process of each film layer in the first zone provided by an embodiment of the present invention, combined with Figure 3 and Figure 4 As shown, the method of sequentially forming the first wet oxide layer 11, the first thermal oxide layer 12, the first doped polysilicon layer 13 and the first mask layer 14 in the first region 1 may specifically include:

[0094] S201, wet-oxidizing the surface of the silicon-based substrate using a mixed solution of hydrochloric acid and hydrogen peroxide to form a first wet oxide layer on the surface of the silicon-based substrate.

[0095] The mixed solution of hydrochloric acid and hydrogen peroxide is an acidic etching solution with high oxygen content. The mixed solution is used to wet-oxidize the silicon-based substrate 00, so that the silicon-based substrate 00 reacts with the mixed solution, thereby forming a silicon oxide film layer on the surface of the silicon-based substrate 00, and the silicon oxide film layer is the first wet oxide layer 11. Exemplarily, the volume concentration of hydrochloric acid or hydrogen peroxide used to form the first wet oxide layer 11 is 5%-10%, for example, the volume concentration of hydrochloric acid or hydrogen peroxide can be 5%; the thickness of the first wet oxide layer 11 can range from 0.5nm to 1.5nm, for example, the thickness of the first wet oxide layer 11 can be 1nm. After the first wet oxide layer is formed, the corrosion of the silicon-based substrate by external impurities and pollutants can be prevented, and the purity and integrity of the surface of the silicon-based substrate can be maintained.

[0096] S202. Thermally oxidize the silicon-based substrate at a first preset temperature to form a first thermal oxide layer that is combined with the first wet oxide layer to form a first tunneling oxide layer, and form an intrinsic polysilicon layer on a surface of the first tunneling oxide layer that is away from the silicon-based substrate.

[0097] Specifically, the silicon-based substrate 00 after forming the first wet oxide layer 11 is placed in a tubular diffusion furnace, the temperature is adjusted to a first preset temperature, and a certain flow of oxygen is introduced, so that the oxygen reacts with the silicon-based substrate 00 at a high temperature to generate silicon oxide, and the silicon oxide constitutes the first thermal oxide layer 12. At the same time, at the first preset temperature, the first wet oxide layer 11 is also annealed, so that the first wet oxide layer 11 and the first thermal oxide layer 12 constitute a first tunneling oxide layer 111 with a relatively high density.

[0098] Exemplarily, the first preset temperature can range from 600°C to 650°C, for example, the first preset temperature can be 625°C; the flow rate of oxygen introduced at the first preset temperature can range from 5000sccm to 10000sccm, for example, the flow rate of oxygen can be 8000sccm; the thickness of the first tunneling oxide layer 111 formed after the first thermal oxide layer 12 is combined with the first wet oxide layer 11 can range from 1nm to 2nm, for example, the thickness of the first tunneling oxide layer 111 can be 1.5nm.

[0099] Among them, the first tunnel oxide layer 111 can selectively transmit the corresponding carriers, thereby effectively preventing the recombination of electrons and holes, and improving the efficiency and performance of the solar cell. At the same time, by controlling the concentration of the mixed solution composed of hydrochloric acid and hydrogen peroxide, and the reaction time between the mixed solution and the silicon-based substrate, the thickness of the formed first wet oxide layer 11 can be controlled, so that the thickness and uniformity of the formed first tunnel oxide layer 111 can be controlled, thereby ensuring that by accurately controlling the thickness and uniformity of the first tunnel oxide layer 111, the recombination loss of electrons and holes can be minimized, which helps to maximize the use of light energy, thereby improving the performance of solar cells.

[0100] In addition, at the first preset temperature, silane may be introduced to decompose silane into silicon and hydrogen by chemical vapor deposition. Silicon may be deposited on the surface of the first tunneling oxide layer 111 facing away from the silicon-based substrate 00 to form an intrinsic polysilicon layer 130 .

[0101] S203 , performing a first type of doping on the intrinsic polysilicon layer at a second preset temperature to form a first doped polysilicon layer and a first mask layer.

[0102] It is understood that when the first region is a P region, the first type of doping may be boron doping. The second preset temperature may be the same as or different from the first preset temperature, and the present embodiment does not specifically limit this. In an optional embodiment, the second preset temperature may be greater than the first preset temperature, and illustratively, the second preset temperature may range from 900°C to 1000°C.

[0103] Specifically, the silicon-based substrate formed with the intrinsic polysilicon layer is placed in a tubular diffusion furnace, and the temperature is raised to a second preset temperature. BCl3 or BBr3 is used as a boron diffusion source to diffuse boron atoms into the intrinsic polysilicon layer 130, and the intrinsic polysilicon layer 130 is doped with the first type. At the same time, due to the process of boron atom diffusion, oxygen exists in the environment of the silicon-based substrate 130, so that the intrinsic polysilicon layer 130 reacts with oxygen to form a layer of silicon dioxide on its surface, and BCl3 is used at a high temperature to diffuse boron atoms into the intrinsic polysilicon layer 130. 3 or BBr3 will also react with oxygen to form B2O3, some boron atoms enter the intrinsic polysilicon layer 130 to replace silicon to form P-type polysilicon, and some remain in the silicon dioxide on the surface of the intrinsic polysilicon layer 130, so that after doping the intrinsic polysilicon 130, a first doped polysilicon layer 13 and a borosilicate glass layer located on the surface of the first doped polysilicon layer 13 are formed at the same time, and the borosilicate glass layer can be used as a first mask layer 14 to protect the first doped polysilicon layer 13 in the subsequent wet process.

[0104] The square resistance of the first doped polysilicon 13 may be in the range of 50 ohm / sq-400 ohm / sq, for example, 200 ohm / sq, and the surface doping concentration may be in the range of 1×10 18 cm -3 -1×10 20 cm -3 , for example, it can be 1×10 19 cm -3 The thickness of the first doped polysilicon layer 13 may range from 100 nm to 400 nm, for example, 250 nm, and the thickness of the first mask layer 14 may range from 30 nm to 150 nm.

[0105] In this embodiment, a mixed solution of hydrochloric acid and hydrogen peroxide is used to wet-oxidize a silicon-based substrate to form a first wet oxide layer, and a first preset temperature is used to thermally oxidize the silicon-based substrate to form a first thermal oxide layer, so that the first wet oxide layer and the first thermal oxide layer are combined to form a first tunneling oxide layer. The formation thickness and uniformity of the first tunneling oxide layer can be controlled by wet oxidation, and the overall density of the first tunneling oxide layer can be improved by subsequent high-temperature oxidation to ensure that the formed first tunneling oxide layer has a high density, uniformity and appropriate thickness, thereby improving the open circuit voltage of the solar cell and improving the conversion efficiency of the solar cell. After the preparation of the first tunneling oxide layer and the intrinsic polysilicon is completed, the intrinsic polysilicon layer can be doped at a second preset temperature to form a first doped polysilicon layer and a first mask layer, so that the first mask layer can protect the first doped polysilicon layer in the subsequent wet process, ensuring that the solar cell has a better passivation contact effect, which is beneficial to improving the preparation yield and conversion efficiency of the solar cell.

[0106] Optional, continue to refer to Figure 3 Before the second wet oxide layer 21, the second thermal oxide layer 22, the second doped polysilicon layer 23 and the second mask layer 24 are sequentially formed in the second area 2, the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 on the surface of the silicon-based substrate 00 except the first area 1 are removed.

[0107] Specifically, due to process limitations, while the first tunneling oxide layer 111, the first doped polysilicon layer 13 and the first mask layer 14 are formed in the first region 1, the first tunneling oxide layer 111, the first doped polysilicon layer 13 and the first mask layer 14 are also formed on other surfaces of the silicon-based substrate 00. To ensure the performance of the prepared solar cell, it is necessary to remove the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 at other locations on the surface of the silicon-based substrate 00 except the first region 1.

[0108] Among them, the method of removing the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 may include wet etching, laser etching and other processes, which can be designed according to actual needs and are not specifically limited in the embodiment of the present invention.

[0109] Optional, such as Figure 5As shown, the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 on the surface of the silicon-based substrate 00 except the first region 1 are removed, which can include: using a laser to remove the first mask layer 14 of the second region 2 and the isolation region 3; using hydrofluoric acid to remove the first mask layer 14 of the front side 01; using an alkaline polishing tank machine to remove the first doped polysilicon layer 13 and the first tunneling oxide layer 111 extending around the second region 2 and the front side 01.

[0110] Specifically, laser is used to perform laser film opening on the second region 2 and the isolation region 3 on the back side of the silicon-based substrate 00, and the first mask layer 14 of the second region 2 and the isolation region 3 is removed according to the patterns of the second region 2 and the isolation region 3 to expose the first doped polysilicon layer 13 of the second region 2 and the isolation region 3. Exemplarily, the laser used to perform laser film opening on the second region 2 and the isolation region 3 on the back side of the silicon-based substrate 00 may include an ultraviolet picosecond laser and / or a green picosecond laser. Among them, when the laser includes an ultraviolet picosecond laser, the spot power of the laser can range from 3W to 20W, for example, it can be 15W, the spot size can range from 100um to 150um, for example, it can be 100μm, the frequency can range from 500kHZ to 600kHz, for example, it can be 500kHz, and the scanning speed can range from 40000mm / s to 70000mm / s, for example, it can be 60000mm / s; when the laser includes a green light picosecond laser, the spot power of the laser can range from 5W to 50W, for example, it can be 30W, the spot size can range from 100um to 500um, for example, it can be 100μm, the frequency can range from 500kHZ to 600kHz, for example, it can be 500kHz, and the scanning speed can range from 40000mm / s to 70000mm / s, for example, it can be 50000mm / s. It can be understood that in the embodiment of the present invention, the first mask layer 14 of the second region 2 and the isolation region 3 is removed by laser, and the first mask layer 14 is not removed by wet etching, which can avoid the hydrofluoric acid used in the wet etching from damaging the first mask layer 14 of the first region 1, so that the first mask layer 14 of the first region 1 can have a complete structure, the first mask layer 14 of the first region 1 will not be thinned, and a thicker first mask layer 14 is retained in the first region 1, so that the first mask layer can better protect the first region in the subsequent wet process, thereby preventing the first doped polysilicon layer in the first region from being corroded to cause yield and efficiency problems.

[0111] After removing the first mask layer 14 of the second region 2 and the isolation region 3, the first mask layer 14 of the front side 01 can be removed by single-sided wet etching. For example, the first mask layer 14 of the front side 01 can be removed by single-sided chain equipment using hydrofluoric acid to save resources and improve production efficiency.

[0112] After removing the second region 2, the isolation region 3 and the first mask layer 14 of the front side 01, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 extending around the second region 2, the isolation region 3 and the front side 01 are removed by an alkaline polishing tank machine. It can be understood that when the silicon-based substrate 00 is subjected to alkali polishing, there is a first mask layer 14 on the surface of the first region 1, so that the first doped polysilicon layer 13 and the first tunneling oxide layer 111 in the first region 1 can be protected by the first mask layer 14 without being etched, and the first mask layer 14 on the surface of the first doped polysilicon layer 13 and the first tunneling oxide layer 111 around the second region 2, the isolation region 3 and the front 01 has been removed in the above process, so that the first doped polysilicon layer 13 and the first tunneling oxide layer 111 around the second region 2, the isolation region 3 and the front 01 are not protected by the mask layer, and are directly in contact with the alkali and are easily etched, so that the first doped polysilicon layer 13 and the first tunneling oxide layer 111 around the second region 2, the isolation region 3 and the front 01 can be removed. In this way, in the wet process, the first mask layer 14 of the first region 1 can play a certain protective role in the first doped polysilicon 13 thereunder, which is beneficial to improving the efficiency and production yield of solar cells.

[0113] In addition, when an alkaline solution is used to remove the first doped polysilicon layer 13 and the first tunneling oxide layer 111 of the second region 2, the isolation region 3 and the front side 01 of the silicon-based substrate 00, if the etching thickness of the second region 2, the isolation region 3 and the front side 01 is shallow, there may be a certain amount of residue, which is not conducive to the formation of the film layer and the control of the thickness in the subsequent process. Therefore, when removing the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 of the second region 2, the isolation region 3 and the front side 01 of the silicon-based substrate 00, the etching will be carried out as much as possible to completely expose the silicon-based substrate 00. For example, the etching thickness can be 15μm, which is greater than the total thickness of the first doped polysilicon layer 13 and the first tunneling oxide layer 111, so that the residues in the second region 2, the isolation region 3, and the front side 01 can be completely removed.

[0114] Optional, continue to refer to Figure 5 After removing the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 on the surface of the silicon-based substrate 00 except the first region 1, the method further includes: polishing the surface of the exposed silicon-based substrate 00 and forming a tower base 001 on the surface of the exposed silicon-based substrate 00.

[0115] It can be understood that after removing the first mask layer 14, the first doped polysilicon layer 13 and the first tunneling oxide layer 111 on the surface of the silicon-based substrate 00 except the first area 1, the second area 2, the isolation area 3, and the front side 01 of the silicon-based substrate 00 can be exposed, and by further polishing the silicon-based substrate 00 with an alkaline solution, the second area 2, the isolation area 3, and the front side 01 of the silicon-based substrate 00 can be corroded, thereby forming a tower base again in the second area 2, the isolation area 3, and the front side 01 of the silicon-based substrate 00, ensuring that the surface of the silicon-based substrate 00 has a larger light receiving area; at the same time, after polishing the surface of the silicon-based substrate 00, the impurities on the surface of the silicon-based substrate 00 can be removed, thereby ensuring the cleanliness of the surface of the silicon-based substrate 00 and improving the yield of the film layer formed in the subsequent process.

[0116] In an exemplary embodiment, the process for polishing the surface of the exposed silicon-based substrate can be the same as the process for removing the first doped polysilicon layer and the first tunneling oxide layer, that is, the second region, the isolation region and the front silicon-based substrate can continue to be etched using an alkaline solution such as NaOH in an alkaline polishing tank machine, so that the second region, the isolation region and the front silicon-based substrate form a tower base, and the size of the tower base can be 25μm.

[0117] Optionally, based on the above embodiment, this embodiment exemplarily illustrates the formation method of the second wet oxide layer 21 , the second thermal oxide layer 22 , the second doped polysilicon layer 23 and the second mask layer 24 in the second region 2 . Figure 6 is a schematic flow chart of a method for preparing each film layer in the second zone provided in an embodiment of the present invention, Figure 7 is a schematic diagram of the structure of the preparation process of each film layer in the second zone provided by an embodiment of the present invention, combined with Figure 6 and Figure 7 As shown, the method of sequentially forming the second wet oxide layer 21, the second thermal oxide layer 22, the second doped polysilicon layer 23 and the second mask layer 24 in the second region 2 may specifically include:

[0118] S301 , wet-oxidizing the surface of the silicon-based substrate in the second region using a mixed solution of hydrochloric acid and hydrogen peroxide to form a second wet oxide layer on the surface of the silicon-based substrate in the second region.

[0119] The mixed solution of hydrochloric acid and hydrogen peroxide is an acidic etching solution with high oxygen content. The mixed solution is used to wet-oxidize the silicon-based substrate 00 in the second zone 2, so that the silicon-based substrate 00 reacts with the mixed solution, thereby forming a silicon oxide film layer on the surface of the silicon-based substrate 00 in the second zone 2. The silicon oxide film layer is the second wet oxide layer 21. Exemplarily, the volume concentration of hydrochloric acid or hydrogen peroxide used to form the second wet oxide layer 21 is 5%-10%, for example, the volume concentration of hydrochloric acid or hydrogen peroxide can be 8%; the thickness of the first wet oxide layer 21 can range from 0.5nm to 1.5nm, for example, the thickness of the second wet oxide layer 21 can be 1nm. After the second wet oxide layer is formed, the erosion of the silicon-based substrate by external impurities and pollutants can be prevented, and the purity and integrity of the surface of the silicon-based substrate can be maintained.

[0120] It can also be understood that when the second wet oxide layer 21 is formed on the silicon-based substrate 00 in the second area 2, a mixed solution of hydrochloric acid and hydrogen peroxide is used for wet oxidation. The hydrochloric acid has less damage to the first mask layer 14, so that the first area can retain a thicker first mask layer 14. For example, the thickness of the retained first mask layer 14 can be 78nm. The thicker first mask layer 14 has a stronger corrosion resistance. Therefore, when the silicon-based substrate 00 in the isolation area 3 and the front side 01 is polished and other wet processes are performed, the first mask layer 14 can effectively protect the underlying first doped polysilicon layer 13 from corrosion by the alkaline or acidic solution used in the wet process, thereby improving the stability and reliability of the solar cell. It can also be understood that wet oxidation using a mixed solution of hydrochloric acid and hydrogen peroxide can retain a relatively thick first mask layer 14, which means that the thickness of the original first mask layer 14 generated can be thinned when the first doped polysilicon layer 13 is formed. Therefore, the first doped polysilicon layer 13 can be lightly doped. When a laser is used to remove the first mask layer 14 in the second region 2 and the isolation region 3, the power of the laser film opening can be reduced, thereby reducing the damage of the laser to the first doped polysilicon layer 13, thereby improving the photoelectric conversion efficiency of the solar cell.

[0121] S302, thermally oxidizing the silicon-based substrate in the second region at a third preset temperature to form a second thermal oxide layer that is combined with the second wet oxide layer to form a second tunneling oxide layer, and forming an intrinsic polysilicon layer on a surface of the second tunneling oxide layer that is away from the silicon-based substrate.

[0122] Specifically, the silicon-based substrate 00 after forming the second oxide layer 21 is placed in a tubular diffusion furnace, the temperature is adjusted to a third preset temperature, and a certain flow of oxygen is introduced, so that the oxygen reacts with the silicon-based substrate 00 at a high temperature to generate silicon oxide, and the silicon oxide constitutes the second thermal oxide layer 22. At the same time, at the third preset temperature, the second wet oxide layer 21 is also annealed, so that the second wet oxide layer 21 and the second thermal oxide layer 22 constitute a second tunneling oxide layer 211 with a higher density. Among them, the third preset temperature can be the same as or different from the first preset temperature, and the embodiment of the present invention does not specifically limit this.

[0123] Exemplarily, the value range of the third preset temperature can be 600°C-650°C, for example, the third preset temperature can be 600°C; the flow rate range of the oxygen introduced at the third preset temperature can be 5000sccm-10000sccm, for example, the flow rate of oxygen can be 10000sccm; the thickness range of the second tunneling oxide layer 211 formed after the second thermal oxide layer 22 and the second wet oxide layer 21 are combined can be 1nm-2nm, for example, the thickness of the second tunneling oxide layer can be 1nm.

[0124] Among them, the second tunnel oxide layer 211 can selectively transmit the corresponding carriers, thereby effectively preventing the recombination of electrons and holes, and improving the efficiency and performance of the solar cell. At the same time, by controlling the concentration of the mixed solution composed of hydrochloric acid and hydrogen peroxide, and the reaction time between the mixed solution and the silicon-based substrate 00, the thickness of the formed second wet oxide layer 21 can be controlled, so that the thickness and uniformity of the formed second tunnel oxide layer 211 can be controlled, thereby ensuring that by accurately controlling the thickness and uniformity of the second tunnel oxide layer 211, the recombination loss of electrons and holes can be minimized, which helps to maximize the use of light energy, thereby improving the performance of solar cells.

[0125] In addition, at the third preset temperature, silane may be introduced to decompose silane into silicon and hydrogen by chemical vapor deposition. Silicon may be deposited on the surface of the second tunneling oxide layer 211 facing away from the silicon-based substrate 00 to form an intrinsic polysilicon layer 230 .

[0126] S303 , performing a second type of doping on the intrinsic polysilicon layer at a fourth preset temperature to form a second doped polysilicon layer and a second mask layer.

[0127] It is understandable that when the second region is an N region, the second type of doping may be phosphorus doping. The fourth preset temperature may be the same as or different from the third preset temperature, and the present embodiment does not specifically limit this. In an optional embodiment, the fourth preset temperature may be greater than the third preset temperature, and illustratively, the value range of the fourth preset temperature may be 900°C-1000°C.

[0128] Specifically, the silicon-based substrate 00 formed with the intrinsic polysilicon layer is placed in the tubular diffusion furnace, and the temperature is raised to the fourth preset temperature, PH3 is used as a phosphorus diffusion source, phosphorus atoms are diffused into the intrinsic polysilicon layer 230, and the second type of doping is performed on the intrinsic polysilicon layer 230; at the same time, due to the process of phosphorus atom diffusion, oxygen exists in the environment of the silicon-based substrate 00, so that the intrinsic polysilicon 230 reacts with oxygen to form a layer of silicon dioxide on its surface, and PH3 is used at a high temperature. It will also react with oxygen to form H3PO4. Some phosphorus atoms enter the intrinsic polysilicon layer 230 to replace silicon to form N-type polysilicon, and some remain in the silicon dioxide on the surface of the intrinsic polysilicon layer 230. Therefore, after the intrinsic polysilicon layer 230 is doped, a second doped polysilicon layer 23 and a phosphosilicate glass layer on the surface of the second doped polysilicon layer are formed at the same time. The phosphosilicate glass layer can be used as a second mask layer 24 to protect the second doped polysilicon layer 23 in the subsequent wet process.

[0129] The square resistance of the second doped polysilicon 23 may be in the range of 20 ohm / sq-70 ohm / sq, for example, 50 ohm / sq, and the surface doping concentration may be in the range of 2×10 20 cm -3 -3×10 21 cm -3 , for example, it can be 5×10 20 cm -3 The thickness of the second doped polysilicon layer 23 may be in the range of 100 nm-200 nm, for example, 150 nm, and the thickness of the second mask layer 24 may be in the range of 10 nm-50 nm, for example, 40 nm.

[0130] In this embodiment, a mixed solution of hydrochloric acid and hydrogen peroxide is used to wet-oxidize the silicon-based substrate to form a second wet oxide layer, and at a third preset temperature, the silicon-based substrate is thermally oxidized to form a second thermal oxide layer, so that the second wet oxide layer and the second thermal oxide layer are combined to form a second tunnel oxide layer. The thickness and uniformity of the second tunnel oxide layer can be controlled by wet oxidation, and the overall density of the second tunnel oxide layer can be improved by subsequent high-temperature oxidation to ensure that the formed second tunnel oxide layer can have a high density, uniformity and appropriate thickness, thereby improving the open circuit voltage of the solar cell and improving the conversion efficiency of the solar cell. At the same time, the use of a mixed solution of hydrochloric acid and hydrogen peroxide for wet oxidation causes less damage to the first mask layer, retaining a thicker first mask layer, and the thicker first mask layer can effectively protect the underlying first doped polysilicon layer from being eroded by the alkaline polishing solution, thereby improving the stability and reliability of the solar cell. In addition, retaining a thicker first mask layer means that the thickness of the original first mask layer can be reduced when forming the first doped polysilicon layer, and the first doped polysilicon layer can be lightly doped, thereby reducing the power of the laser film opening to reduce the damage of the laser to the first doped polysilicon layer, thereby improving the photoelectric conversion efficiency of the solar cell. After completing the preparation of the second tunneling oxide layer and the intrinsic polysilicon, the intrinsic polysilicon layer can be doped at a fourth preset temperature to form a second doped polysilicon layer and a second mask layer, so that the second mask layer can protect the second doped polysilicon layer in the subsequent wet process, ensuring that the solar cell can have a better passivation contact effect, thereby facilitating the improvement of the preparation yield and conversion efficiency of the solar cell.

[0131] Optional, continue to refer to Figure 7 Before removing the first mask layer 14 of the first area 1 and the second mask layer 24 of the second area 2, the method further includes: removing the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 on the surface of the silicon-based substrate 00 except the second area 2.

[0132] Specifically, due to process limitations, while the second tunneling oxide layer 211, the second doped polysilicon layer 23 and the second mask layer 24 are formed in the second zone 2, the second tunneling oxide layer 211, the second doped polysilicon layer 23 and the second mask layer 24 are also formed on other surfaces of the silicon-based substrate 00. To ensure the performance of the prepared solar cell, it is necessary to remove the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 at other locations on the surface of the silicon-based substrate 00 except the second zone 2.

[0133] Among them, the method of removing the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 may include wet etching, laser etching and other processes, which can be designed according to actual needs and are not specifically limited in the embodiment of the present invention.

[0134] Optional, such as Figure 8 As shown, the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 on the surface of the silicon-based substrate 00 except the second region 2 are removed, which can include: using a laser to remove the second mask layer 24 of the first region 1 and the isolation region 3; using hydrofluoric acid to remove the second mask layer 24 of the front side 01; using an alkaline polishing tank machine to remove the second doped polysilicon layer 23 and the second tunneling oxide layer 211 extending around the first region 1 and the front side 01.

[0135] Specifically, laser is used to perform laser film opening on the first region 1 and the isolation region 3 on the back side of the silicon-based substrate 00, and the second mask layer 24 of the first region 1 and the isolation region 3 is removed according to the patterns of the first region 1 and the isolation region 3 to expose the second doped polysilicon layer 23 of the first region 1 and the isolation region 3. Exemplarily, the laser used to perform laser film opening on the first region 1 and the isolation region 3 on the back side of the silicon-based substrate 00 may include an ultraviolet picosecond laser and / or a green picosecond laser. Among them, when the laser includes an ultraviolet picosecond laser, the spot power of the laser can range from 3W to 20W, for example, it can be 15W, the spot size can range from 100um to 150um, for example, it can be 100μm, the frequency can range from 500kHZ to 600kHz, for example, it can be 500kHz, and the scanning speed can range from 40000mm / s to 70000mm / s, for example, it can be 60000mm / s; when the laser includes a green light picosecond laser, the spot power of the laser can range from 5W to 50W, for example, it can be 30W, the spot size can range from 100um to 500um, for example, it can be 100μm, the frequency can range from 500kHZ to 600kHz, for example, it can be 500kHz, and the scanning speed can range from 40000mm / s to 70000mm / s, for example, it can be 50000mm / s. It can be understood that in the embodiment of the present invention, the second mask layer 24 of the first region 1 and the isolation region 3 is removed by laser, and the second mask layer 24 is not removed by wet etching, which can avoid the hydrofluoric acid used in the wet etching from damaging the second mask layer 24 of the second region 2, so that the second mask layer 24 of the second region 2 can have a complete structure, the second mask layer 24 of the second region 2 will not be thinned, and a thicker second mask layer 24 is retained in the second region 2, so that the second mask layer can better protect the second region in the subsequent wet process, thereby preventing the second doped polysilicon layer in the second region from being corroded to cause yield and efficiency problems.

[0136] After removing the second mask layer 24 of the first area 1 and the isolation area 3, the second mask layer 24 of the front side 01 can be removed by single-sided wet etching. For example, the second mask layer 24 of the front side 01 can be removed by single-sided chain equipment using hydrofluoric acid to save resources and improve production efficiency.

[0137] After removing the first region 1, the isolation region 3 and the second mask layer 24 of the front side 01, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 extending around the first region 1, the isolation region 3 and the front side 01 are removed by an alkali polishing tank machine. It can be understood that when the silicon-based substrate 00 is subjected to alkali polishing, there is a second mask layer 24 on the surface of the second region 2, so that the second doped polysilicon layer 23 and the second tunneling oxide layer 211 in the second region 2 can be protected by the second mask layer 24 without being etched, and the second mask layer 24 on the surface of the second doped polysilicon layer 14 and the second tunneling oxide layer 211 around the first region 1, the isolation region 3 and the front 01 has been removed in the above process, so that the second doped polysilicon layer 23 and the second tunneling oxide layer 211 around the first region 1, the isolation region 3 and the front 01 are not protected by the mask layer, and are directly in contact with the alkali and easily etched, so that the second doped polysilicon layer 23 and the second tunneling oxide layer 211 around the first region 1, the isolation region 3 and the front 01 can be removed. In this way, in the wet process, the second mask layer 24 of the second region 2 can play a certain protective role in the second doped polysilicon 23 thereunder, which is beneficial to improving the efficiency and production yield of solar cells.

[0138] In addition, when an alkaline solution is used to remove the first region 1, the isolation region 3 and the second doped polysilicon layer 23 and the second tunneling oxide layer 211 of the front side 01 of the silicon-based substrate 00, if the etching thickness of the first region 1, the isolation region 3 and the front side 01 is shallow, there may be a certain amount of residue, which is not conducive to the formation of the film layer and the control of the thickness in the subsequent process. Therefore, when removing the first region 1, the isolation region 3 and the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 of the front side 01 of the silicon-based substrate 00, the etching will be carried out as much as possible to completely expose the silicon-based substrate 00. For example, the etching thickness can be 15μm, which is greater than the total thickness of the second doped polysilicon layer 23 and the second tunneling oxide layer 211, so that the residues in the first region, the isolation region, and the front side can be completely removed.

[0139] Optional, continue to refer to Figure 8 After removing the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 on the surface of the silicon-based substrate 00 except the second region 2, the method further includes: polishing the surface of the exposed silicon-based substrate 00 and forming a tower base 001 on the surface of the exposed silicon-based substrate 00.

[0140] It can be understood that after removing the second mask layer 24, the second doped polysilicon layer 23 and the second tunneling oxide layer 211 on the surface of the silicon-based substrate 00 except the second area 2, the isolation area 3 and the front side 01 of the silicon-based substrate 00 can be exposed, and by further polishing the silicon-based substrate 00 with an alkaline solution, the isolation area 3 and the front side 01 of the silicon-based substrate 00 can be corroded, thereby forming a tower base again in the isolation area 3 and the front side 01 of the silicon-based substrate 00, ensuring that the surface of the silicon-based substrate 00 has a larger light receiving area; at the same time, after polishing the surface of the silicon-based substrate 00, the impurities on the surface of the silicon-based substrate 00 can be removed, thereby ensuring the cleanliness of the surface of the silicon-based substrate 00 and improving the yield of the film layer formed in the subsequent process.

[0141] In an exemplary embodiment, the process for polishing the surface of the exposed silicon-based substrate can be the same as the process for removing the second doped polysilicon layer and the second tunneling oxide layer, that is, the isolation area and the front silicon-based substrate can continue to be etched using an alkaline solution such as NaOH in an alkaline polishing tank machine, so that the isolation area and the front silicon-based substrate form a tower base, and the size of the tower base can be 2μm.

[0142] Based on the same inventive concept, an embodiment of the present invention further provides a solar cell, which is manufactured using the solar cell manufacturing method in the above example, such as Fig. 9 As shown, the solar cell includes: a silicon-based substrate 00; the surface of the silicon-based substrate 00 includes at least a front side 01 and a back side 02 opposite to each other; the back side includes a first area 1, a second area 2, and an isolation area 3 located between the first area 1 and the second area 2; a first tunneling oxide layer 111 and a first doped polysilicon layer 13 are stacked in sequence in the first area 1; the first tunneling oxide layer 111 is composed of a first wet oxide layer 11 and a first thermal oxide layer 12; a second tunneling oxide layer 211 and a second doped polysilicon layer 23 are stacked in sequence in the second area 2; the second tunneling oxide layer 211 is composed of a second wet oxide layer 21 and a second thermal oxide layer 22; a passivation layer 4 covering the first area 1, the second area 2, the isolation area 3 and the front side 01; an anti-reflection layer 5 covering the passivation layer 4; a first electrode 15 and a second electrode 25; the first electrode 15 is located in the first area 1 and contacts the first doped polysilicon layer 13, and the second electrode 25 is located in the second area 2 and contacts the second doped polysilicon layer 23.

[0143] The silicon-based substrate 00 may be an N-type silicon-based substrate or a P-type silicon-based substrate, which is not specifically limited in the embodiment of the present invention. The back side of the silicon-based substrate 00 includes a first region 1 and a second region 2, one of which is a P region and the other is an N region. The back side of the silicon-based substrate 00 also includes an isolation region 3 between the first region 1 and the second region 2, and the isolation region 3 can isolate the P region and the N region from each other to prevent a short circuit between the first region 1 and the second region 2 and leakage.

[0144] The first wet oxide layer 11 can be formed by a wet oxidation process. After the first wet oxide layer 11 is formed, a high temperature oxidation process can be used to form the first thermal oxide layer 12. The first wet oxide layer 11 is combined with the first thermal oxide layer 12 to form the first tunnel oxide layer 111. By forming the first wet oxide layer 11 and the first thermal oxide layer 12 in steps, it can be ensured that the first tunnel oxide layer 111 has a suitable thickness and high uniformity, so that the thickness and uniformity of the first tunnel oxide layer 111 can be accurately controlled, thereby improving the photoelectric conversion efficiency of the solar cell. The first doped polysilicon layer 13 can be a boron-doped polysilicon layer, and the first mask layer 14 can include borosilicate glass. The first mask layer 14 is used to protect the first doped polysilicon layer 13 in the wet process.

[0145] The second wet oxide layer 21 can be formed by a wet oxidation process. After the second wet oxide layer 21 is formed, a high temperature oxidation process can be used to form a second thermal oxide layer 22. The second wet oxide layer 21 is combined with the second thermal oxide layer 22 to form a second tunnel oxide layer 211. By forming the second wet oxide layer 21 and the second thermal oxide layer 22 in steps, it can be ensured that the second tunnel oxide layer 211 has a suitable thickness and high uniformity, so that the thickness and uniformity of the second tunnel oxide layer 211 can be accurately controlled, thereby improving the photoelectric conversion efficiency of the solar cell. The second doped polysilicon layer 23 can be a polysilicon layer doped with phosphorus, and the second mask layer 24 can include phosphorus silicon glass. The second mask layer 24 is used to protect the second doped polysilicon layer 23 in the wet process.

[0146] The passivation layer 4 may include aluminum oxide. The passivation layer 4 is used to protect the film layer below it, preventing the silicon-based substrate 00, the first doped polysilicon layer 13, the second doped polysilicon layer 23, etc. from being directly exposed to the air and being polluted by impurities, water oxygen, etc. in the air. At the same time, the storage of the passivation layer 4 can also improve the surface recombination effect, thereby reducing the loss of photogenerated carriers and improving the efficiency and performance of solar cells. The anti-reflection layer 5 may include a stacked structure of one or more of silicon nitride, silicon oxynitride, and silicon oxide. The anti-reflection layer 5 can reduce the reflectivity of light, so that more light is absorbed by the solar cell, thereby improving the photoelectric conversion efficiency and improving the efficiency and performance of the solar cell.

[0147] The first electrode 15 and the second electrode 25 may include silver electrodes, etc. The first electrode 15 contacts the first doped polysilicon, and the second electrode 25 contacts the second doped polysilicon, thereby forming a passivation contact structure. The first electrode 15 and the second electrode 25 may be electrically connected to external devices or other solar cells through a main gate electrode.

[0148] The above solar cell can be prepared by the method for preparing a solar cell provided by any embodiment of the present invention, and has the corresponding beneficial effects of the method for preparing a solar cell. For technical details not described in detail in this embodiment, please refer to the method for preparing a solar cell provided by any embodiment of the present invention.

[0149] Since the solar cell introduced above can be prepared by the method for preparing a solar cell provided by any embodiment of the present invention, based on the method for preparing a solar cell introduced in the embodiment of the present invention, a person skilled in the art can understand the specific implementation of the solar cell of the present embodiment and its various variations, so how to prepare the solar cell by the method for preparing a solar cell provided by any embodiment of the present invention is not described in detail here. As long as a person skilled in the art implements the method for preparing a solar cell provided by any embodiment of the present invention to prepare a solar cell, it falls within the scope of protection of this application.

[0150] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: include: Polishing a silicon-based substrate and forming a tower base on the surface of the silicon-based substrate; the surface of the silicon-based substrate at least includes a front side and a back side opposite to each other; the back side includes a first area, a second area, and an isolation area between the first area and the second area; A first wet oxide layer, a first thermal oxide layer, a first doped polysilicon layer and a first mask layer are sequentially formed in the first region; the first wet oxide layer and the first thermal oxide layer constitute a first tunneling oxide layer; forming a second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer in sequence in the second region; the second wet oxide layer and the second thermal oxide layer constitute a second tunneling oxide layer; removing the first mask layer in the first area and the second mask layer in the second area; forming a passivation layer and an anti-reflection layer in the front surface, the first area, the second area and the isolation area in sequence; A first electrode is formed in the first region in contact with the first doped polysilicon layer, and a second electrode is formed in the second region in contact with the second doped polysilicon layer.

2. The method for preparing a solar cell according to claim 1, characterized in that: A first wet oxide layer, a first thermal oxide layer, a first doped polysilicon layer and a first mask layer are sequentially formed in the first region, including: Using a mixed solution of hydrochloric acid and hydrogen peroxide to wet-oxidize the surface of the silicon-based substrate to form a first wet oxide layer on the surface of the silicon-based substrate; Thermally oxidizing the silicon-based substrate at a first preset temperature to form a first thermal oxide layer that is combined with the first wet oxide layer to form a first tunnel oxide layer, and forming an intrinsic polysilicon layer on a surface of the first tunnel oxide layer that is away from the silicon-based substrate; At a second preset temperature, the intrinsic polysilicon layer is doped with a first type of material to form a first doped polysilicon layer and a first mask layer.

3. The method for preparing a solar cell according to claim 2, characterized in that: Before sequentially forming a second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer in the second region, the method further includes: The first mask layer, the first doped polysilicon layer and the first tunneling oxide layer on the surface of the silicon-based substrate except the first region are removed.

4. The method for preparing a solar cell according to claim 3, characterized in that: Removing the first mask layer, the first doped polysilicon layer, and the first tunneling oxide layer on the surface of the silicon-based substrate except the first region, comprising: removing the first mask layer in the second region and the isolation region by using laser; removing the first mask layer on the front surface by using hydrofluoric acid; An alkaline polishing tank machine is used to remove the first doped polysilicon layer and the first tunneling oxide layer in the second region and the front side expansion.

5. The method for preparing a solar cell according to claim 3, characterized in that: After removing the first mask layer, the first doped polysilicon layer and the first tunneling oxide layer on the surface of the silicon-based substrate except the first region, the method further includes: The exposed surface of the silicon-based substrate is polished, and a tower base is formed on the exposed surface of the silicon-based substrate.

6. The method for preparing a solar cell according to claim 1, characterized in that: A second wet oxide layer, a second thermal oxide layer, a second doped polysilicon layer and a second mask layer are sequentially formed in the second region; the second wet oxide layer and the second oxide layer constitute a second tunneling oxide layer, including: Using a mixed solution of hydrochloric acid and hydrogen peroxide to wet-oxidize the surface of the silicon-based substrate in the second region to form a second wet oxide layer on the surface of the silicon-based substrate in the second region; Thermally oxidizing the silicon-based substrate in the second region at a third preset temperature to form a second thermal oxide layer that is combined with the second wet oxide layer to form a second tunneling oxide layer, and forming an intrinsic polysilicon layer on a surface of the second tunneling oxide layer that is away from the silicon-based substrate; At a fourth preset temperature, the intrinsic polysilicon layer is doped with a second type of material to form a second doped polysilicon layer and a second mask layer.

7. The method for preparing a solar cell according to claim 6, characterized in that: Before removing the first mask layer in the first area and the second mask layer in the second area, the method further includes: The second mask layer, the second doped polysilicon layer and the second tunneling oxide layer on the surface of the silicon-based substrate except the second region are removed.

8. The method for preparing a solar cell according to claim 7, characterized in that: Removing the second mask layer, the second doped polysilicon layer and the second tunneling oxide layer on the surface of the silicon-based substrate except the second region, comprising: removing the second mask layer in the first area and the isolation area by using laser; removing the second mask layer on the front side by using hydrofluoric acid; An alkali polishing tank machine is used to remove the second doped polysilicon layer and the second tunneling oxide layer in the first area and the front side expansion.

9. The method for preparing a solar cell according to claim 7, characterized in that: After removing the second mask layer, the second doped polysilicon layer and the second tunneling oxide layer on the surface of the silicon-based substrate except the second region, the method further includes: The exposed surface of the silicon-based substrate is polished, and a tower base is formed on the exposed surface of the silicon-based substrate.

10. A solar cell, prepared by the method for preparing a solar cell according to any one of claims 1 to 9, characterized in that: include: A silicon-based substrate; the surface of the silicon-based substrate comprises at least a front side and a back side opposite to each other; the back side comprises a first region, a second region, and an isolation region between the first region and the second region; A first tunneling oxide layer and a first doped polysilicon layer are sequentially stacked in the first region; the first tunneling oxide layer is composed of a first wet oxide layer and a first thermal oxide layer; A second tunneling oxide layer and a second doped polysilicon layer are sequentially stacked in the second region; the second tunneling oxide layer is composed of a second wet oxide layer and a second thermal oxide layer; a passivation layer covering the first region, the second region, the isolation region and the front side; an anti-reflection layer covering the passivation layer; A first electrode and a second electrode; the first electrode is located in the first region and contacts the first doped polysilicon layer, and the second electrode is located in the second region and contacts the second doped polysilicon layer.

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