Double-sided TOPCon photovoltaic cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a double-sided TOPCon photovoltaic cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of photovoltaic cells. The preparation method comprises the following steps: obtaining a double-sided TOPCon photovoltaic cell through laser and wet processing, wherein the front surface of the photovoltaic cell is sequentially provided with a P + emitter layer, a first tunneling oxide layer, a first doped polycrystalline silicon layer, a first oxide layer, a second doped polycrystalline silicon layer, an aluminum oxide layer, a first antireflection film layer and a front surface electrode; wherein the first tunneling oxide layer, the first doped polycrystalline silicon layer, the first oxide layer and the second doped polycrystalline silicon layer are arranged in a grid line area on the front surface of the silicon wafer; a second tunneling oxide layer, a third doped polycrystalline silicon layer, a second oxide layer, a fourth doped polycrystalline silicon layer, a second antireflection film layer and a back electrode are sequentially arranged on the back surface of the photovoltaic cell; wherein the second oxide layer and the fourth doped polycrystalline silicon layer are arranged in a grid line area on the back surface of the silicon wafer.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic cell technology, and in particular to a double-sided TOPCon photovoltaic cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] The existing double-sided TOPCon cell structure is a passivation layer formed by a tunneling oxide layer and a doped polysilicon layer covering the front and back of the entire silicon wafer. The bandgap width and defect band of the polysilicon in this cell structure will lead to the deterioration of the cell performance; and polysilicon has a relatively serious parasitic absorption. When used on the front of the silicon wafer, it will absorb sunlight of a certain wavelength and reduce the short-circuit current, while when used on the back, it will cause parasitic absorption in the long-wave band, which will lead to problems such as poor long-wave response of the cell and low bifaciality.

[0003] However, if the polysilicon on the existing passivation structure is directly thinned, since high-temperature doping is required on the polysilicon layer later, if the polysilicon layer is too thin, the doping source can easily break through the tunneling oxide layer under the polysilicon layer, causing the tunneling effect to disappear. Moreover, if the polysilicon layer is too thin, higher requirements will be placed on the subsequent screen-printed slurry and sintering temperature during metallization, greatly increasing the cost of battery preparation. Summary of the invention

[0004] The purpose of the present application is to provide a method for preparing a double-sided TOPCon photovoltaic cell and a double-sided TOPCon photovoltaic cell.

[0005] The first aspect of the present application provides a method for preparing a double-sided TOPCon photovoltaic cell, comprising the following steps: Step 101: selecting a silicon wafer, the silicon wafer comprising a front side and a back side opposite to each other, and performing a texturing process on the silicon wafer; then performing boron diffusion on the silicon wafer to form a P+ layer on the front side of the silicon wafer;

[0006] Step 102: removing the BSG layer on the front side of the silicon wafer, and sequentially depositing a first tunneling oxide layer, a first amorphous silicon layer, a first oxide layer, and a second amorphous silicon layer on the front side of the silicon wafer by using LPCVD; then performing boron diffusion and annealing treatment so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer;

[0007] Step 103: removing the BSG layer and the wrapping plating on the back side of the silicon wafer; and using LPCVD to sequentially deposit a second tunneling oxide layer, a third amorphous silicon layer, a second oxide layer, and a fourth amorphous silicon layer on the back side of the silicon wafer; and then performing phosphorus diffusion and annealing treatment so that the third amorphous silicon layer and the fourth amorphous silicon layer form a third doped polysilicon layer and a fourth doped polysilicon layer;

[0008] Step 104: removing the PSG layer, BSG layer and wrap-around plating on the front side of the silicon wafer.

[0009] Step 105: Scanning the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line area on the back side of the silicon wafer using a first laser;

[0010] Step 106: removing the second doped polysilicon layer in the non-gate line region on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line region on the back side of the silicon wafer;

[0011] Step 107: using a second laser to remove the first oxide layer in the non-gate line region on the front side of the silicon wafer, and scanning the first doped polysilicon layer in the non-gate line region on the front side of the silicon wafer.

[0012] Step 108: removing the first doped polysilicon layer in the non-gate line region on the front side of the silicon wafer.

[0013] Step 109: removing the BSG layer and the first tunneling oxide layer in the non-gate line region on the front side of the silicon wafer, and removing the PSG layer and the second oxide layer in the non-gate line region on the back side of the silicon wafer.

[0014] Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer;

[0015] Step 111: depositing a first anti-reflection film layer and a second anti-reflection film layer on the front side of the silicon wafer and the back side of the silicon wafer respectively.

[0016] Step 112: Prepare a front electrode and a back electrode on the gate line region on the front side of the silicon wafer and on the back side of the silicon wafer, respectively.

[0017] In an optional manner, in step 103, before LPCVD, the back side of the silicon wafer is polished to form a tower base of 5-15 μm on the back side of the silicon wafer.

[0018] Preferably, the reflectivity of the tower base is 30%-50%;

[0019] Preferably, the polishing solution is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 2-5%; the mass fraction of the H2O2 is 2-5%;

[0020] Preferably, the polishing solution also includes an additive, the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter, the polishing treatment temperature is 40-80°C, and the treatment time is 150-250 seconds.

[0021] In an optional manner, preferably, the reflectivity of the tower base is 30%-50%;

[0022] Preferably, the polishing solution is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 2-5%; the mass fraction of the H2O2 is 2-5%;

[0023] Preferably, the polishing solution also includes an additive, the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter, the polishing treatment temperature is 40-80°C, and the treatment time is 150-250 seconds.

[0024] In an optional manner, an HF solution is used to remove the BSG layer and / or PSG layer of the silicon wafer, the mass fraction of the HF is 5%-15%, and the processing time is 300-500 seconds.

[0025] In an optional manner, in step 105 and step 107, the first laser and the second laser are picosecond or nanosecond, the spot diameter is 80-120 μm, the wavelength is 193-1064 nm, the repetition frequency is 100-1000 KHz, the output power is 1-20 W, and the laser energy density is 0.5 J / cm 2 -4J / cm 2 .

[0026] In an optional manner, in step 106 and step 108, the solution for removing the doped polysilicon layer is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 5-10%; the mass fraction of the H2O2 is 2-5%.

[0027] Preferably, the mixed solution also includes an additive, the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter; the processing temperature is 40-80°C, and the processing time is 300-450 seconds.

[0028] In an optional manner, in step 109, the solution for removing the oxide layer and the PSG layer or the BSG layer is a mixed solution of HF and HCl, wherein the mass fraction of HF is 30%-50%, the mass fraction of HCl is 40%-60%, the treatment temperature is 20-40°C, and the treatment time is 50-200 seconds.

[0029] In an optional manner, the thickness of the first tunneling oxide layer is greater than the thickness of the first oxide layer; and / or,

[0030] The thickness of the second tunneling oxide layer is greater than the thickness of the second oxide layer; and / or,

[0031] The thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer; and / or,

[0032] The thickness of the third doped polysilicon layer is less than the thickness of the fourth doped polysilicon layer; and / or,

[0033] The first doped polysilicon layer and the second doped polysilicon layer have the same conductivity type, the third doped polysilicon layer and the fourth doped polysilicon layer have the same conductivity type, and the first doped polysilicon layer and the second doped polysilicon layer have opposite conductivity types to the third doped polysilicon layer and the fourth doped polysilicon layer; and / or,

[0034] The doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; and / or,

[0035] The doping concentration of the third doped polysilicon layer is less than the doping concentration of the fourth doped polysilicon layer.

[0036] In an optional manner, the thickness of the first tunneling oxide layer is 1.5-2 nm; and / or,

[0037] The thickness of the second tunneling oxide layer is 1.5-2 nm; and / or,

[0038] The thickness of the first oxide layer is 1-1.5 nm; and / or,

[0039] The thickness of the second oxide layer is 1-1.5 nm; and / or,

[0040] The thickness of the first doped polysilicon layer is 50-80 nm; and / or,

[0041] The thickness of the second doped polysilicon layer is 80-150 nm; and / or,

[0042] The thickness of the third doped polysilicon layer is 50-80 nm; and / or,

[0043] The thickness of the fourth doped polysilicon layer is 80-150 nm; and / or,

[0044] The conductivity types of the first doped polysilicon layer and the second doped polysilicon layer are P-type; the conductivity types of the third doped polysilicon layer and the fourth doped polysilicon layer are N-type; and / or,

[0045] The concentration of the first doped polysilicon layer is 3-5×1019 atom / cm 3 , the concentration of the second doped polysilicon layer is 4-6×10 19 atom / cm 3 ; and / or, the concentration of the third doped polysilicon layer is 2-3×10 20 atom / cm 3 , the concentration of the fourth doped polysilicon layer is 3-5×10 20 atom / cm 3 .

[0046] The second aspect of the present application provides a TOPCon photovoltaic cell, which is prepared using the preparation method of the TOPCon photovoltaic cell of the first aspect of the present application.

[0047] The third aspect of the present application provides a photovoltaic module, comprising the double-sided TOPCon photovoltaic cell of the second aspect of the present application.

[0048] Compared with the prior art, this application:

[0049] (1) The double-sided TOPCon photovoltaic cell prepared in the present application has no polysilicon structure in the non-metallized area on the front side to avoid parasitic absorption of polysilicon; a thinner polysilicon structure is used on the back side to reduce parasitic absorption of polysilicon without damaging the back tower base and affecting the passivation effect, thereby improving the cell performance.

[0050] (2) The present application processes the passivation layer through laser and wet processing. The laser can effectively improve the doping of the non-gate line area on the back side, and the wet processing can repair the damage caused by the laser to the polysilicon layer on the front and back sides, so that the electrical performance of the photovoltaic cell is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0052] Figure 1 A schematic diagram of an embodiment of a double-sided TOPCon photovoltaic cell of the present application is shown.

[0053] Reference numerals:

[0054] 10-silicon wafer; 20-P+ emitter layer; 301-first tunneling oxide layer; 302-first doped polysilicon layer; 303-first oxide layer; 304 second doped polysilicon layer; 40-aluminum oxide layer; 501-first anti-reflection film layer; 502-second anti-reflection film layer; 601-front electrode; 602-back electrode; 701-second tunneling oxide layer; 702-third doped polysilicon layer; 703-second oxide layer; 704 fourth doped polysilicon layer. DETAILED DESCRIPTION

[0055] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0057] The first aspect of the present application provides a method for preparing a photovoltaic cell, comprising the following steps:

[0058] Step 101: Select a silicon wafer, the silicon wafer including a front side and a back side opposite to each other, and perform a texturing process on the silicon wafer; then perform boron diffusion on the silicon wafer to form a P+ layer on the front side of the silicon wafer;

[0059] In this step, the silicon wafer is an N-type single crystal silicon wafer, which refers to a silicon wafer obtained by squaring, chamfering, slicing, cleaning and sorting a crystal rod grown by the Czochralski method.

[0060] In an optional manner, the resistivity of the silicon wafer is 0.5 to 2Ω·cm; for example, it may be 0.5Ω·cm, 0.6Ω·cm, 0.7Ω·cm, 0.8Ω·cm, 0.9Ω·cm, 1.0Ω·cm, 1.1Ω·cm, 1.2Ω·cm, 1.3Ω·cm, 1.4Ω·cm, 1.5Ω·cm, 1.6Ω·cm, 1.7Ω·cm, 1.8Ω·cm, 1.9Ω·cm, 2.0Ω·cm, 2.1Ω·cm, 2.2Ω·cm, 2.3Ω·cm, 2.4Ω·cm or 2.5Ω·cm.

[0061] In an optional embodiment, the size of the silicon wafer is 182×182 mm, 182×210 mm, or 210×210 mm.

[0062] In an optional embodiment, the thickness of the silicon wafer is 130 μm or 110 μm.

[0063] The silicon wafer includes a front side and a back side opposite to each other. Both sides of the silicon wafer, namely the front side and the back side, are subjected to texturing treatment so that a pyramid structure is formed on the surface of the silicon wafer.

[0064] In some specific embodiments, the texturing treatment mainly adopts NAOH solution alkaline texturing.

[0065] Subsequently, boron is diffused into the silicon wafer. Boron diffusion mainly uses a boron source (BBr3 or BCl3) to vaporize in a tube furnace and then is deposited on the surface of the silicon wafer through a series of chemical reactions to obtain the appropriate doping concentration, junction depth and square resistance to form a P+ emitter layer.

[0066] Step 102: removing the BSG layer on the front side of the silicon wafer, and sequentially depositing a first tunneling oxide layer, a first amorphous silicon layer, a first oxide layer, and a second amorphous silicon layer on the front side of the silicon wafer by using LPCVD; then performing boron diffusion and annealing treatment so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer;

[0067] In this step, due to the previous step, boron is diffused on the front and back sides of the silicon wafer to form a BSG layer (borosilicate glass layer). The BSG layer needs to be removed before depositing the passivation layer.

[0068] In a specific embodiment, a chain machine can be used to remove the BSG layer. For example, the mass fraction of HF can be 5%-15%, for example, it can be 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15%; the processing time is 300-500 seconds, for example, it can be 300 seconds, 350 seconds, 400 seconds, 450 seconds or 500 seconds.

[0069] Subsequently, a passivation layer is prepared on the front side of the silicon wafer by using LPCVD (Low Pressure Chemical Vapor Deposition), and a first tunneling oxide layer, a first amorphous silicon layer, a first oxide layer, and a second amorphous silicon layer are sequentially deposited on the front side of the silicon wafer; and boron diffusion and annealing are performed to form the first amorphous silicon layer and the second amorphous silicon layer into a first doped polysilicon layer and a second doped polysilicon layer.

[0070] In some specific embodiments, the process parameters of LPCVD are: oxygen flow rate is 20000-50000 cssm; SiH4 flow rate is 400-1500 sccm; deposition temperature is 550-650° C., and deposition time is 110-200 minutes;

[0071] The boron source gas flow rate for boron diffusion is 300-1800 sccm, and the boron source is BCL3.

[0072] In an optional manner, the thickness of the first tunnel oxide layer is greater than the thickness of the first oxide layer; in a specific embodiment, the thickness of the first tunnel oxide layer is 1.5-2nm; the thickness of the first oxide layer is 1-1.5nm. The thickness of the first oxide layer cannot be too thin, otherwise it cannot block the corrosion at the interface, and the thickness of the first oxide layer cannot be too thick, otherwise it will completely block the boron from entering the front amorphous silicon layer, affecting the barrier effect and doping effect.

[0073] In an optional manner, the thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer. In some specific embodiments, the thickness of the first doped polysilicon layer is 50-80nm; for example, it can be 50nm, 53nm, 55nm, 57nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm or 80nm; the thickness of the second doped polysilicon layer is 80-150nm, for example, it can be 80nm, 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm or 150nm. The thickness of the doped polysilicon layer will affect the diffusion of the doped elements. In order to ensure that the first doped polysilicon can reach a certain doping concentration and not allow too many doped elements to diffuse into the first tunneling oxide layer and affect the tunneling passivation effect of the first tunneling oxide layer, the thickness of the second doped silicon layer is between 80-150nm, and the thickness of the first doped polysilicon layer is set to be smaller than that of the second doped silicon layer, thereby ensuring both the concentration of the first doped polysilicon layer and the passivation effect of the first tunneling oxide layer.

[0074] In an optional manner, the first doped polysilicon layer and the second doped polysilicon layer have the same conductivity type. In a specific embodiment, the first doped polysilicon layer and the second doped polysilicon layer are of P type conductivity.

[0075] In an optional manner, the doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; in a specific embodiment, the concentration of the first doped polysilicon layer is 3-5×10 19 atom / cm 3 , for example, it can be 3×10 19 atom / cm 3 , 3.5×10 19 atom / cm 3 , 4×10 19 atom / cm3 , 4.5×10 19 atom / cm 3 or 5×10 19 atom / cm 3 ; The concentration of the second doped polysilicon layer is 4-6×10 19 atom / cm 3 ; For example, it can be 4×10 19 atom / cm 3 , 4.5×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 5.5×10 19 atom / cm 3 or 6×10 19 atom / cm 3 ; This can make the concentration of the two doped polysilicon layers different, forming high and low potential barriers and improving the carrier transmission effect.

[0076] Step 103: removing the BSG layer and the wrapping plating on the back side of the silicon wafer; and using LPCVD to sequentially deposit a second tunneling oxide layer, a third amorphous silicon layer, a second oxide layer, and a fourth amorphous silicon layer on the back side of the silicon wafer; and then performing phosphorus diffusion and annealing treatment to form the third amorphous silicon layer and the fourth amorphous silicon layer into a third doped polysilicon layer and a fourth doped polysilicon layer;

[0077] In this step, due to the previous steps, two layers of BSG and wrap-around plating are formed on the back of the silicon wafer, that is, the passivation layer structure (first tunneling oxide layer, first doped polysilicon layer, first oxide layer and second doped polysilicon layer) is deposited on the front of the silicon wafer; the BSG and wrap-around plating must be removed before deposition on the back of the silicon wafer.

[0078] In a specific embodiment, the removal process of the BSG layer and the bypass plating is to first remove the BSG layer through a chain machine, then remove the second doped polysilicon layer through an alkaline tank, then remove the first oxide layer through a chain machine, then remove the first doped polysilicon layer through an alkaline tank, and then remove the first tunneling oxide layer and the BSG layer through a chain machine.

[0079] In a more specific embodiment, the solution in the chain machine is a 5%-15% HF solution, and the treatment time is 300-500 seconds.

[0080] In a more specific embodiment, the solution in the alkali tank is a mixed solution of at least one alkali solution containing KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 5-10%; the mass fraction of H2O2 is 2-5%; preferably, the mixed solution also includes an additive, and the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter; the treatment temperature is 40-80°C, and the treatment time is 300-450 seconds.

[0081] Subsequently, a passivation layer is prepared on the back of the silicon wafer by LPCVD, and a second tunneling oxide layer, a third amorphous silicon layer, a second oxide layer, and a fourth amorphous silicon layer are formed on the back of the silicon wafer; and phosphorus is diffused on the third amorphous silicon layer and the fourth amorphous silicon layer, so that the third amorphous silicon layer and the fourth amorphous silicon layer form a third doped polysilicon layer and a fourth doped polysilicon layer;

[0082] In some optional embodiments, the process parameters of LPCVD are: oxygen flow rate is 30000-50000 sccm; SiH4 flow rate is 100-1000 sccm; deposition temperature is 550-650°C, and deposition time is 110-200 minutes.

[0083] In some optional methods, a tubular thermal diffusion device is used to perform high-temperature phosphorus diffusion at high temperature, POCL3 is used as a reaction gas, the flow rate of POCL3 is 1000-2000sccm, the processing temperature is 750-950°C, and the processing time is 70-100 minutes.

[0084] In an optional manner, the thickness of the second tunnel oxide layer is greater than the thickness of the second oxide layer; in a specific embodiment, the thickness of the second tunnel oxide layer is 1.5-2nm; the thickness of the second oxide layer is 1-1.5nm. The thickness of the second oxide layer cannot be too thin, otherwise it cannot block the corrosion at the interface, and the thickness of the second oxide layer cannot be too thick, otherwise it will completely block the boron from entering the front amorphous silicon layer, affecting the barrier effect and doping effect.

[0085] In an optional manner, the thickness of the third doped polysilicon layer is less than the thickness of the fourth doped polysilicon layer. In some specific embodiments, the thickness of the third doped polysilicon layer is 50-80nm; for example, it can be 50nm, 53nm, 55nm, 57nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm or 80nm; the thickness of the fourth doped polysilicon layer is 80-150nm, for example, it can be 80nm, 81nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 140nm, 145nm or 150nm. The third doped polysilicon layer is arranged in the non-gate line area. If the third doped polysilicon layer is too thick, the parasitic absorption will be increased. A thinner third doped polysilicon layer is arranged in the non-gate line area, thereby effectively reducing the parasitic absorption.

[0086] In an optional manner, the third doped polysilicon layer and the fourth doped polysilicon layer have the same conductivity type. In a specific embodiment, the conductivity type of the third doped polysilicon layer and the fourth doped polysilicon layer is N-type.

[0087] In an optional manner, the doping concentration of the third doped polysilicon layer is less than the doping concentration of the fourth doped polysilicon layer; in a specific embodiment, the doping concentration of the third doped polysilicon layer is 2-3×10 20 atom / cm 3 , for example, it can be 2×10 20 atom / cm 3 , 2.5×10 20 atom / cm 3 or 3×10 20 atom / cm 3 ; The concentration of the fourth doped polysilicon layer is 3-5×10 20 atom / cm 3 , for example, it can be 3×10 20 atom / cm 3 , 3.5×10 20 atom / cm 3 , 4×10 20 atom / cm 3 , 4.5×10 20 atom / cm 3 or 5×10 20 atom / cm 3 This can make the concentration of the two doped polysilicon layers different, forming high and low potential barriers and improving the carrier transmission effect.

[0088] In an optional manner, before LPCVD, an alkaline solution is used to polish the back of the silicon wafer so that a 5-15 μm tower base is formed on the back of the silicon wafer; for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm; preferably, the tower base is 5-10 μm; more preferably, the tower base is 5-7 μm. Preferably, the reflectivity of the tower base is 30%-50%, for example, it can be 30%, 35%, 40%, 45% or 50%. The tower base structure can ensure the contact resistivity with the gate line, and the reflectivity can increase the response to the long-wave band of light, thereby improving efficiency. It is worth noting that the size of the tower base in this application refers to the size of the tower base's positive projection on the silicon wafer. Generally, the tower base's positive projection on the silicon wafer is a quadrilateral, and the size of the tower base at this time, that is, the maximum side length of the positive projection, is 5-15 μm.

[0089] The pyramid structure refers to a surface morphology structure similar to a pyramid, and the tower base structure refers to the surface morphology structure after the top of the pyramid structure is cut off. In some specific embodiments, the pyramid structure can be formed by laser etching, mechanical method or plasma etching, and then the tower base structure is formed by alkali polishing.

[0090] In an optional manner, the polishing solution for preparing the tower base is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 2-5%; the mass fraction of H2O2 is 2-5%; preferably, the polishing solution also includes an additive, and the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or an accelerator, the polishing treatment temperature is 40-80°C, and the treatment time is 150-250 seconds.

[0091] Step 104: remove the PSG layer, BSG layer and wrap-around plating on the front side of the silicon wafer.

[0092] In this step, due to the previous steps, a PSG layer (phosphosilicate glass layer), a BSG layer and a wrap-around plating are formed on the front side of the silicon wafer, that is, a passivation layer structure (a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer and a fourth doped polysilicon layer) is deposited on the back side of the silicon wafer.

[0093] In a specific embodiment, the removal process of the PSG layer, the BSG layer and the bypass plating is to first remove the PSG layer through a chain machine, then remove the fourth doped polysilicon layer through an alkaline tank, then remove the second oxide layer through a chain machine, then remove the third doped polysilicon layer through an alkaline tank, and then remove the second tunneling oxide layer and the BSG layer through a chain machine.

[0094] In a more specific embodiment, the solution in the chain machine is a 5%-15% HF solution, and the treatment time is 300-500 seconds.

[0095] In a more specific embodiment, the solution in the alkali tank is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 5-10%; the mass fraction of H2O2 is 2-5%; preferably, the mixed solution also includes an additive, and the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter; the treatment temperature is 40-80°C, and the treatment time is 300-450 seconds.

[0096] Step 105: Scanning the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line area on the back side of the silicon wafer using the first laser;

[0097] In this step, the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon in the non-gate line area on the back side of the silicon wafer are scanned by the first laser, so that the polysilicon layer at the scanned location is amorphized, so as to facilitate the subsequent removal of the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon in the non-gate line area on the back side of the silicon wafer. It is worth noting that the gate line area refers to the placement area of ​​the gate line (that is, the electrode) after the battery cell is prepared. Since the gate line position is fixed, in step 105, although the gate line is not printed, the gate line area is preset in advance, so the second oxide layer can be set according to the preset gate line area. The non-gate line area refers to the area of ​​the non-gate line prepared as the battery cell.

[0098] In an optional manner, the first laser is picosecond or nanosecond, with a spot diameter of 80-120 μm, such as 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 105 μm, 110 μm, 115 μm or 120 μm; a wavelength of 193-1064 nm, such as 193 nm, 532 nm, 785 nm, 850 nm, 980 nm or 1064 nm; a repetition frequency of 100- 1000KHz, for example, it can be 100KHz, 200KHz, 300KHz, 400KHz, 500KHz, 600KHz, 700KHz, 800KHz, 900KHz, or 1000KHz; the output power is 1-20W, for example, it can be 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W or 10W, 15W or 20W; the laser energy density is 0.5J / cm 2 -4J / cm 2 ; For example, it can be 0.5J / cm 2, 0.6J / cm 2 , 0.7J / cm 2 , 0.8J / cm 2 , 0.9J / cm 2 , 1J / cm 2 , 1.5J / cm 2 , 2J / cm 2 , 2.5J / cm 2 , 3J / cm 2 、3.5J / cm 2 or 4J / cm 2 .

[0099] Step 106: removing the second doped polysilicon layer in the non-gate line region on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line region on the back side of the silicon wafer;

[0100] In this step, the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line area on the back side of the silicon wafer are removed by a wet method;

[0101] In a more specific embodiment, the solution for removing the doped polysilicon layer is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 5-10%, for example, 5%, 6%, 7%, 8%, 9% or 10%. The mass fraction of H2O2 is 2-5%, for example, 2%, 3%, 4% or 5%. Preferably, the mixed solution also includes an additive, and the mass fraction of the additive is 1%-3%, for example, 1%, 2% or 3%. The additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter; the treatment temperature is 40-80°C, for example, 40°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C or 80°C. The treatment time is 300-450 seconds, for example, 300 seconds, 350 seconds, 400 seconds or 450 seconds.

[0102] Step 107: using a second laser to remove the first oxide layer in the non-gate line region on the front side of the silicon wafer, and scanning the first doped polysilicon layer in the non-gate line region on the front side of the silicon wafer.

[0103] In this step, the first oxide layer in the non-gate line area on the front side of the silicon wafer is removed by a second laser, and the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer is scanned to amorphize the polysilicon layer at the scanned location, so as to facilitate the subsequent removal of the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer.

[0104] In an optional manner, the second laser is picosecond or nanosecond, with a spot diameter of 80-120 μm, such as 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 105 μm, 110 μm, 115 μm or 120 μm; a wavelength of 193-1064 nm, such as 193 nm, 532 nm, 785 nm, 850 nm, 980 nm or 1064 nm; a repetition frequency of 100- 1000KHz, for example, it can be 100KHz, 200KHz, 300KHz, 400KHz, 500KHz, 600KHz, 700KHz, 800KHz, 900KHz, or 1000KHz; the output power is 1-20W, for example, it can be 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W or 10W, 15W or 20W; the laser energy density is 0.5J / cm 2 -4J / cm 2 ; For example, it can be 0.5J / cm 2 , 0.6J / cm 2 , 0.7J / cm 2 , 0.8J / cm 2 , 0.9J / cm 2 , 1J / cm 2 , 1.5J / cm 2 , 2J / cm 2 , 2.5J / cm 2 , 3J / cm 2 、3.5J / cm 2 or 4J / cm 2 .

[0105] Step 108: removing the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer.

[0106] In this step, the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer is removed by a wet method.

[0107] In a more specific embodiment, the solution for removing the doped polysilicon layer is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 5-10%; the mass fraction of H2O2 is 2-5%. Preferably, the mixed solution also includes an additive, the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter; the treatment temperature is 40-80°C and the treatment time is 300-450 seconds.

[0108] Step 109: remove the BSG layer and the first tunnel oxide layer in the non-gate line area on the front side of the silicon wafer, and remove the PSG layer and the second oxide layer in the non-gate line area on the back side of the silicon wafer.

[0109] In this step, double-sided acid treatment is used to remove the BSG layer and the second tunnel oxide layer in the non-gate line area on the front side of the silicon wafer and the PSG layer and the second oxide layer in the non-gate line area on the back side of the silicon wafer.

[0110] In an optional manner, a mixed solution of HF and HCl, wherein the mass fraction of HF is 30%-50%, for example, 30%, 35%, 40%, 45% or 50%; the mass fraction of HCl is 40%-60%, for example, 40%, 45%, 50%, 55% or 60%; the treatment temperature is 20-40°C, for example, 20°C, 25°C, 30°C, 35°C or 40°C; the treatment time is 50-200 seconds, for example, 50 seconds, 60 seconds, 80 seconds, 100 seconds, 120 seconds, 150 seconds, 180 seconds or 200 seconds.

[0111] Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer;

[0112] In this step, an aluminum oxide layer is prepared on the front side of the silicon wafer to improve the passivation and impurity absorption effects on the surface of the silicon wafer; due to the previous preparation of the selective passivation layer, the thickness of the non-gate line area and the gate line area on the front side of the silicon wafer are different, so the aluminum oxide layer formed in the non-gate line area and the gate line area on the front side of the silicon wafer are not on the same plane.

[0113] In an optional manner, ALD is used to prepare the aluminum oxide layer, with trimethylaluminum (TMA) as the aluminum source and vaporized water (H2O) or gaseous oxygen (O2) as the oxygen (O) source, two or more chemical vapor precursors are alternately introduced into the reaction chamber, and react on the surface of the substrate to form an aluminum oxide layer.

[0114] In an optional embodiment, the thickness of aluminum oxide is 3-7 nm; for example, it can be 3 nm, 4 nm, 5 nm, 6 nm or 7 nm.

[0115] Step 111: depositing a first anti-reflection film layer and a second anti-reflection film layer on the front side and the back side of the silicon wafer respectively.

[0116] In this step, anti-reflection film layers are prepared on the front and back sides of the silicon wafer; due to the previous preparation of the selective passivation layer, the thickness of the non-gate line area and the gate line area on the front side of the silicon wafer are different, so the first anti-reflection film layer on the non-gate line area and the gate line area on the front side of the silicon wafer are not on the same plane; the second anti-reflection film layer on the non-gate line area and the gate line area on the back side of the silicon wafer are not on the same plane.

[0117] In an optional manner, PECVD is used to prepare the anti-reflection film layer.

[0118] In an optional manner, the first anti-reflection film layer and the second anti-reflection film layer contain at least one of SiNx and SiOx.

[0119] In an optional manner, the thickness of the first anti-reflection film layer is less than the thickness of the second anti-reflection film layer.

[0120] In an optional embodiment, the thickness of the first anti-reflection film layer is 50-85nm; for example, it can be 50nm, 55nm, 60nm, 62nm, 64nm, 65nm, 66nm, 68nm, 69nm, 70nm, 72nm, 75nm, 78nm, 80nm, 81nm or 85nm.

[0121] In an optional manner, the thickness of the second anti-reflection film layer is 75-105 nm; for example, it can be 75 nm, 78 nm, 80 nm, 81 nm, 85 nm, 90 nm, 95 nm, 100 nm or 105 nm.

[0122] Step 112: Prepare a front electrode and a back electrode on the gate line regions of the front side and the back side of the silicon wafer respectively.

[0123] In this step, electrodes are prepared on the front and back sides of the silicon wafer. The electrodes are screen-printed, and the main grid and the auxiliary grid are printed on the front and back sides of the silicon wafer. After sintering and light injection, the electrodes are fixed on the surface of the cell to obtain the final product, the double-sided TOPCon photovoltaic cell.

[0124] The second aspect of the present application provides a double-sided TOPCon photovoltaic cell prepared in the first aspect of the present application, such as Figure 1 As shown, the photovoltaic cell comprises:

[0125] Silicon wafer 10, silicon wafer 10 includes a relative front side and a back side, the front side of silicon wafer 10 is divided into a gate line area and a non-gate line area, photovoltaic cells need electrodes to collect and transmit current, electrodes are generally called gate lines, and gate lines are divided into main gate lines and secondary gate lines. Compared with main gate lines, secondary gate lines are more in number and narrower in width. In some cells, main gate lines may not be set. The gate line area of ​​the present application refers to the area where the secondary gate lines printed later are located; the non-gate line area of ​​the present application refers to the area where the secondary gate lines will not be prepared later.

[0126] The front side of the silicon wafer 10 is provided with a P+ emitter layer 20, a first tunneling oxide layer 301, a first doped polysilicon layer 302, a first oxide layer 303, a second doped polysilicon layer 304, an aluminum oxide layer 40, a first anti-reflection film layer 501 and a front electrode 601 in sequence; wherein the first tunneling oxide layer 301, the first doped polysilicon layer 302, the first oxide layer 303, and the second doped polysilicon layer 304 are provided in the gate line region on the front side of the silicon wafer 10;

[0127] A second tunneling oxide layer 701, a third doped polysilicon layer 702, a second oxide layer 703, a fourth doped polysilicon layer 704, a second anti-reflection film layer 502 and a back electrode 602 are sequentially arranged on the back side of the silicon wafer 10; wherein the second oxide layer 703 and the fourth doped polysilicon layer 704 are arranged in the gate line area on the back side of the silicon wafer 10.

[0128] By preparing a passivation contact structure on the front and back sides of the photovoltaic cell, on the one hand, a polysilicon-free structure is used in the non-gridline area on the front side of the photovoltaic cell, and the passivation structure is set in the gridline area, which ensures the passivation effect and avoids the parasitic absorption of polysilicon. On the other hand, a third doped polysilicon layer 702 is set in the non-gridline area on the back side of the photovoltaic cell, and a fourth doped polysilicon layer 704 is set in the gridline area. A thinner polysilicon structure is used on the back side to reduce the parasitic absorption of polysilicon, thereby effectively improving the efficiency of the photovoltaic cell.

[0129] The third aspect of the present application provides a photovoltaic module, comprising the double-sided TOPCon photovoltaic cell of the second aspect of the present application.

[0130] The following describes in detail the preparation method of the double-sided TOPCon photovoltaic cell disclosed in the first aspect and the photovoltaic cell disclosed in the second aspect of the present application with several specific embodiments. It is worth noting that the following description is only an exemplary description and not a specific limitation of the invention.

[0131] Example 1

[0132] Step 101: Select an N-type single crystal silicon wafer, the resistivity of the silicon wafer is 0.5-2.5Ω·cm, the size of the silicon wafer is 182×182mm, and the thickness is 130μm, and use a NaOH aqueous solution to texture both sides of the N-type single crystal silicon wafer; then, use BCl3 to diffuse boron into the silicon wafer in a tube furnace, the temperature of the boron diffusion is 950°C, and a P+ layer is formed on the front side of the silicon wafer;

[0133] Step 102: Use a chain machine to remove the BSG layer on the front side of the silicon wafer, the mass fraction of HF in the chain machine is 7.65%, and the process time is 60 seconds; then use LPCVD to deposit a first tunneling oxide layer, a first amorphous silicon layer, a first oxide layer, and a second amorphous silicon layer on the surface of the silicon wafer in sequence; the deposition thicknesses are 1.5nm, 80nm, 1nm, and 120nm, respectively; and use boron diffusion and annealing treatment to form a P-type first doped polysilicon layer and a P-type second doped polysilicon layer through the first amorphous silicon layer and the second amorphous silicon layer.

[0134] Step 103: Use a chain machine to remove the BSG layer on the back of the silicon wafer, remove the second doped polysilicon layer on the back of the silicon wafer through an alkali bath, remove the first oxide layer on the back of the silicon wafer through a chain machine, remove the first doped polysilicon layer on the back of the silicon wafer through an alkali bath, and remove the first tunnel oxide layer and BSG layer on the back of the silicon wafer through a chain machine. The mass fraction of HF in the chain machine is 7.65%, and the process time is 60 seconds; the mass fraction of KOH in the alkali bath is 7.92%; the mass fraction of H2O2 is 2.5%, the processing temperature is 65°C, and the time is 350 seconds.

[0135] Subsequently, the back of the silicon wafer was polished with an alkaline solution to form a 7μm tower base on the back of the silicon wafer, and the reflectivity of the tower base was 39.2%. The mass fraction of KOH in the polishing solution was 3.43%; the mass fraction of H2O2 was 2.5%, the processing temperature was 65°C, and the time was 200 seconds.

[0136] Subsequently, LPCVD is used to deposit a second tunneling oxide layer, a third amorphous silicon layer, a second oxide layer, and a fourth amorphous silicon layer in sequence on the surface of the silicon wafer; the deposition thicknesses are 1.5nm, 50nm, 1nm, and 100nm, respectively; phosphorus diffusion and annealing are performed to form the first amorphous silicon layer and the second amorphous silicon layer into an N-type first doped polysilicon layer and an N-type second doped polysilicon layer.

[0137] Step 104: Use a chain machine to remove the PSG layer on the back of the silicon wafer, then pass through an alkali bath to remove the fourth doped polysilicon layer on the front of the silicon wafer, then pass through a chain machine to remove the second oxide layer on the front of the silicon wafer, then pass through an alkali bath to remove the third doped polysilicon layer on the front of the silicon wafer, and then pass through a chain machine to remove the second tunnel oxide layer and BSG layer on the back of the silicon wafer. The mass fraction of HF in the chain machine is 7.65%, and the process time is 60 seconds; the mass fraction of KOH in the alkali bath is 7.92%; the mass fraction of H2O2 is 2.5%, the processing temperature is 65°C, and the time is 350 seconds.

[0138] Step 105: Scanning the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and scanning the fourth doped polysilicon layer in the non-gate line area on the back side of the silicon wafer using a picosecond laser with a spot diameter of 90 μm, a wavelength of 355 nm, a repetition frequency of 150 KHz, an output power of 10 W, and a laser energy density of 1.8 J / cm2;

[0139] Step 106: using a solution with a mass fraction of 7.92% KOH and a mass fraction of 2.5% H2O2 to remove the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line area on the back side of the silicon wafer;

[0140] Step 107: Use a picosecond laser with a spot diameter of 90μm, a wavelength of 355nm, a repetition frequency of 150KHz, an output power of 10W, and a laser energy density of 1.8J / cm2 to remove the first oxide layer in the non-gate line area on the front side of the silicon wafer, and scan the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer.

[0141] Step 108: Use a solution containing 7.92% by mass of KOH and 2.5% by mass of H2O2 to remove the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer.

[0142] Step 109: using a mixed solution of 37% HF by mass, 49% HCl by mass and water, at a temperature of 25° C., and a treatment time of 150 seconds; double-sided acid treatment is performed to remove the BSG layer and the second tunneling oxide layer in the non-gate line area on the front side of the silicon wafer and the PSG layer and the second oxide layer in the non-gate line area on the back side of the silicon wafer.

[0143] Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer;

[0144] Step 111: depositing a first anti-reflection film layer and a second anti-reflection film layer on the front side of the silicon wafer and the back side of the silicon wafer respectively;

[0145] Step 112: Prepare a front electrode and a back electrode on the gate line regions of the front side and the back side of the silicon wafer respectively.

[0146] Through the above steps, a finished double-sided TOPCon double-sided cell is prepared, wherein the photovoltaic cell includes a silicon wafer,

[0147] The front side of the silicon wafer is provided with a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first anti-reflection film layer and a front electrode in sequence; wherein the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer and the second doped polysilicon layer are provided in the gate line region on the front side of the silicon wafer; wherein the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer and the second doped polysilicon layer are 1.5 nm, 80 nm, 1 nm and 120 nm respectively; the first doped polysilicon layer and the second doped polysilicon layer are P-type, and the doping concentrations are 3.65×10 1 atom / cm 3 and 4.65×10 19 atom / cm 3 ; The thickness of the aluminum oxide layer is 6nm, and the first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 75nm.

[0148] The back of the silicon wafer is provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second anti-reflection film layer and a back electrode in sequence; wherein the second oxide layer and the fourth doped polysilicon layer are provided in the gate line region on the back of the silicon wafer. The thicknesses of the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer and the fourth doped polysilicon layer are 1.5 nm, 50 nm, 1 nm and 100 nm respectively; the third doped polysilicon layer and the fourth doped polysilicon layer are N-type, and the doping concentrations are 3.65×10 20 atom / cm 3 and 4.65×10 20 atom / cm 3 ; The first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 90nm.

[0149] Use a battery efficiency tester to test the electrical performance of photovoltaic cells.

[0150] Comparative Example 1

[0151] Compared with Example 1, steps 105-109 are omitted. Through the above steps, the finished double-sided TOPCon double-sided battery is prepared as follows:

[0152] The front side of the silicon wafer is provided with a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first anti-reflection film layer and a front electrode in sequence; wherein the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer and the second doped polysilicon layer are 1.5 nm, 80 nm, 1 nm and 120 nm respectively; the first doped polysilicon layer and the second doped polysilicon layer are P-type, and the doping concentrations are 3.65×10 19 atom / cm 3 and 4.65×10 19 atom / cm 3 ; The thickness of the aluminum oxide layer is 6nm, and the first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 75nm.

[0153] The back of the silicon wafer is provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second anti-reflection film layer and a back electrode in sequence; wherein the thicknesses of the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer and the fourth doped polysilicon layer are 1.5 nm, 50 nm, 1 nm and 100 nm respectively; the third doped polysilicon layer and the fourth doped polysilicon layer are N-type, and the doping concentrations are 3.65×10 20 atom / cm 3 and 4.65×10 20 atom / cm 3 ; The first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 90nm.

[0154] Comparative Example 2

[0155] Compared with Example 1,

[0156] Step 107: Use a picosecond laser with a spot diameter of 90μm, a wavelength of 355nm, a repetition frequency of 150KHz, an output power of 10W, and a laser energy density of 1.8J / cm2 to remove the first oxide layer in the non-gate line area on the front side of the silicon wafer and the second oxide layer on the back side of the silicon wafer, and scan the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the third doped polysilicon layer on the back side of the silicon wafer.

[0157] Step 108: Use a solution containing 7.92% KOH and 2.5% H2O2 to remove the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the third doped polysilicon layer on the back side of the silicon wafer.

[0158] Step 109: Use a mixed solution of 37% HF by mass, 49% HCl by mass and water, the temperature is 25°C, and the treatment time is 150 seconds to perform double-sided acid treatment to remove the BSG layer and the second tunneling oxide layer in the non-gate line area on the front side of the silicon wafer and the PSG layer and the first tunneling oxide layer in the non-gate line area on the back side of the silicon wafer.

[0159] Through the above steps, a finished double-sided TOPCon double-sided battery is prepared, wherein Figure 1 As shown, the photovoltaic cell includes a silicon wafer 10,

[0160] Through the above steps, the finished double-sided TOPCon double-sided battery is prepared as follows:

[0161] The front side of the silicon wafer is provided with a P+ emitter layer, a first tunneling oxide layer, a first doped polysilicon layer, a first oxide layer, a second doped polysilicon layer, an aluminum oxide layer, a first anti-reflection film layer and a front electrode in sequence; wherein the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer and the second doped polysilicon layer are provided in the gate line region on the front side of the silicon wafer; wherein the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer, the first oxide layer and the second doped polysilicon layer are 1.5 nm, 80 nm, 1 nm and 120 nm respectively; the first doped polysilicon layer and the second doped polysilicon layer are P-type, and the doping concentrations are 3.65×10 19 atom / cm 3 and 4.65×10 19 atom / cm 3 ; The thickness of the aluminum oxide layer is 6nm, and the first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 75nm.

[0162] The back of the silicon wafer is provided with a second tunneling oxide layer, a third doped polysilicon layer, a second oxide layer, a fourth doped polysilicon layer, a second anti-reflection film layer and a back electrode in sequence; wherein, the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer and the fourth doped polysilicon layer are provided in the gate line region on the back of the silicon wafer; the thicknesses of the second tunneling oxide layer, the third doped polysilicon layer, the second oxide layer and the fourth doped polysilicon layer are 1.5 nm, 50 nm, 1 nm and 100 nm respectively; the third doped polysilicon layer and the fourth doped polysilicon layer are N-type, and the doping concentrations are 3.65×10 20 atom / cm 3 and 4.65×10 20 atom / cm 3 ; The first anti-reflection film layer is a SiNx anti-reflection film with a thickness of 90nm.

[0163] The following table shows the electrical performance data of Example 1 and Comparative Examples 1-2. It can be seen from the table that (1) compared with the fully covered double-sided passivation layer structure of Comparative Example 1, the efficiency value of the battery cell of Example 1 is increased by nearly 0.4%, which is a great improvement in efficiency. (2) Compared with Example 1, the back passivation layer in Comparative Example 2 affects the tower base structure, causing the efficiency value to decrease by 0.2%.

[0164] Table 1 Electrical performance data of Example 1 and Comparative Examples 1-2

[0165] Eta / % Uoc / V Isc / A FF / % Example 1 26.671 0.73509 13.928 86.01 Comparative Example 1 26.266 0.73245 13.787 85.85 Comparative Example 2 26.441 0.73309 13.868 85.81

[0166] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other changes to the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0167] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for preparing a double-sided TOPCon photovoltaic cell, characterized in that: The following steps are involved: Step 101: Select a silicon wafer, the silicon wafer including a front side and a back side opposite to each other, and perform a texturing process on the silicon wafer; then perform boron diffusion on the silicon wafer to form a P+ layer on the front side of the silicon wafer; Step 102: removing the BSG layer on the front side of the silicon wafer, and sequentially depositing a first tunneling oxide layer, a first amorphous silicon layer, a first oxide layer, and a second amorphous silicon layer on the front side of the silicon wafer by using LPCVD; then performing boron diffusion and annealing treatment so that the first amorphous silicon layer and the second amorphous silicon layer form a first doped polysilicon layer and a second doped polysilicon layer; Step 103: removing the BSG layer and the wrap-around plating on the back side of the silicon wafer; and sequentially depositing a second tunneling oxide layer, a third amorphous silicon layer, a second oxide layer, and a fourth amorphous silicon layer on the back side of the silicon wafer by using LPCVD; and then performing phosphorus diffusion and annealing treatment so that the third amorphous silicon layer and the fourth amorphous silicon layer form a third doped polysilicon layer and a fourth doped polysilicon layer; Step 104: removing the PSG layer, the BSG layer and the wrap-around plating on the front side of the silicon wafer; Step 105: Scanning the second doped polysilicon layer in the non-gate line area on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line area on the back side of the silicon wafer using a first laser; Step 106: removing the second doped polysilicon layer in the non-gate line region on the front side of the silicon wafer and the fourth doped polysilicon layer in the non-gate line region on the back side of the silicon wafer; Step 107: using a second laser to remove the first oxide layer in the non-gate line area on the front side of the silicon wafer, and scanning the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer; Step 108: removing the first doped polysilicon layer in the non-gate line area on the front side of the silicon wafer; Step 109: removing the BSG layer and the first tunneling oxide layer in the non-gate line area on the front side of the silicon wafer, and removing the PSG layer and the second oxide layer in the non-gate line area on the back side of the silicon wafer; Step 110: depositing an aluminum oxide layer on the front side of the silicon wafer; Step 111: depositing a first anti-reflection film layer and a second anti-reflection film layer on the front side and the back side of the silicon wafer respectively; Step 112: Prepare a front electrode and a back electrode on the gate line region on the front side of the silicon wafer and on the back side of the silicon wafer, respectively.

2. The method for preparing a photovoltaic cell according to claim 1, characterized in that: In step 103, before LPCVD, the back side of the silicon wafer is polished to form a tower base of 5-15 μm on the back side of the silicon wafer; Preferably, the reflectivity of the tower base is 30%-50%; Preferably, the polishing solution is a mixed solution of at least one alkali solution including KOH, NAOH, NH4OH and H2O2, wherein the mass fraction of the alkali solution is 2-5%; the mass fraction of the H2O2 is 2-5%; Preferably, the polishing solution also includes an additive, the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter, the polishing treatment temperature is 40-80°C, and the treatment time is 150-250 seconds.

3. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The BSG layer and / or PSG layer of the silicon wafer is removed by using an HF solution, the mass fraction of the HF is 5%-15%, and the processing time is 300-500 seconds.

4. The method for preparing a photovoltaic cell according to claim 1, characterized in that: In step 105 and step 107, the first laser and the second laser are picosecond or nanosecond, the spot diameter is 80-120µm, the wavelength is 193-1064nm, the repetition frequency is 100-1000KHz, the output power is 1-20W, and the laser energy density is 0.5J / cm 2 -4J / cm 2 .

5. The method for preparing a photovoltaic cell according to claim 1, characterized in that: In step 106 and step 108, the solution for removing the doped polysilicon layer is a mixed solution of at least one alkali solution including KOH, NAOH, and NH4OH and H2O2, wherein the mass fraction of the alkali solution is 5-10%; the mass fraction of the H2O2 is 2-5%; Preferably, the mixed solution also includes an additive, the mass fraction of the additive is 1%-3%; the additive is at least one of a detergent, an oxidant, a diffusant, a surfactant, a buffer, a defoaming agent or a promoter; the treatment temperature is 40-80°C, and the treatment time is 300-450 seconds.

6. The method for preparing a photovoltaic cell according to claim 1, characterized in that: In step 109, the solution for removing the oxide layer and the PSG layer or the BSG layer is a mixed solution of HF and HCl, wherein the mass fraction of HF is 30%-50%, the mass fraction of HCl is 40%-60%, the treatment temperature is 20-40°C, and the treatment time is 50-200 seconds.

7. The method for preparing a photovoltaic cell according to claim 1, characterized in that: The thickness of the first tunneling oxide layer is greater than the thickness of the first oxide layer; and / or, The thickness of the second tunneling oxide layer is greater than the thickness of the second oxide layer; and / or, The thickness of the first doped polysilicon layer is less than the thickness of the second doped polysilicon layer; and / or, The thickness of the third doped polysilicon layer is less than the thickness of the fourth doped polysilicon layer; and / or, The first doped polysilicon layer and the second doped polysilicon layer have the same conductivity type, the third doped polysilicon layer and the fourth doped polysilicon layer have the same conductivity type, and the first doped polysilicon layer and the second doped polysilicon layer have opposite conductivity types to the third doped polysilicon layer and the fourth doped polysilicon layer; and / or, The doping concentration of the first doped polysilicon layer is less than the doping concentration of the second doped polysilicon layer; and / or, The doping concentration of the third doped polysilicon layer is less than the doping concentration of the fourth doped polysilicon layer.

8. The method for preparing a photovoltaic cell according to claim 7, characterized in that: The thickness of the first tunneling oxide layer is 1.5-2 nm; and / or, The thickness of the second tunneling oxide layer is 1.5-2 nm; and / or, The thickness of the first oxide layer is 1-1.5 nm; and / or, The thickness of the second oxide layer is 1-1.5 nm; and / or, The thickness of the first doped polysilicon layer is 50-80 nm; and / or, The thickness of the second doped polysilicon layer is 80-150 nm; and / or, The thickness of the third doped polysilicon layer is 50-80 nm; and / or, The thickness of the fourth doped polysilicon layer is 80-150 nm; and / or, The conductivity type of the first doped polysilicon layer and the second doped polysilicon layer is P type; the conductivity type of the third doped polysilicon layer and the fourth doped polysilicon layer is N type; and / or, The concentration of the first doped polysilicon layer is 3-5×10 19 atom / cm 3 , the concentration of the second doped polysilicon layer is 4-6×10 19 atom / cm 3 ; and / or, the concentration of the third doped polysilicon layer is 2-3×10 20 atom / cm 3 , the concentration of the fourth doped polysilicon layer is 3-5×10 20 atom / cm 3 .

9. A double-sided TOPCon photovoltaic cell, characterized in that: The preparation method is adopted according to any one of claims 1 to 8.

10. A photovoltaic module, characterized in that: Including the double-sided TOPCon photovoltaic cell as described in claim 9.

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