A GaN-based light-emitting diode epitaxial wafer and a method for preparing the same

Abstract

The present invention provides a GaN-based light-emitting diode epitaxial wafer and a preparation method thereof, which relates to the technical field of semiconductor electronic devices. The preparation method comprises sequentially growing a low-temperature buffer layer, a U-type GaN layer, and an N-type GaN layer on a substrate, growing a stress adjustment layer on the N-type GaN layer, wherein the stress adjustment layer comprises a single or multiple structural layers, each structural layer comprises a stacked first InGaN sublayer and a barrier sublayer, and during the growth of the first InGaN sublayer, H is pulsed into the substrate. 2 , a multi-quantum well layer is grown on the stress adjustment layer, the In concentration of the stress adjustment layer is lower than the In concentration of the multi-quantum well layer, and an electron blocking layer, a low-temperature P-type GaN layer, a hole dispersion layer, a P-type GaN layer, and a P-type GaN layer contact layer are sequentially grown on the multi-quantum well layer. This technical solution significantly alleviates interface stress, reduces defect generation, improves the crystal quality and carrier recombination efficiency of the multi-quantum well layer, and effectively improves the luminous efficiency and reliability of GaN-based light-emitting diodes by optimizing the design and growth process of the stress adjustment layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor electronic devices, and in particular to a GaN-based light-emitting diode epitaxial wafer and a preparation method thereof. Background Art

[0002] With the increasing awareness of environmental protection and the demand for energy saving, light emitting diodes (LEDs) have been widely used in various fields due to their high efficiency and energy saving characteristics. Especially in the case of continuous reduction in size and higher power consumption requirements, how to improve the luminous efficiency of LEDs is particularly important. Improving the quantum efficiency and thus the brightness of semiconductor light emitting diodes is one of the important topics in current LED technology research.

[0003] During the current injection process, the stress generated in the multi-quantum well layer will cause a piezoelectric polarization effect, which will cause the distortion of the band structure, reduce the recombination efficiency of carriers, and seriously affect the luminescence performance of the LED. In order to solve this problem, a stress adjustment layer is usually designed under the multi-quantum well layer to relieve stress. However, since the stress adjustment layer is usually grown at a relatively low temperature, its crystal quality is often poor, which further affects the structure and performance of the multi-quantum well layer. Therefore, how to improve the quality of the stress adjustment layer and enhance the performance of the multi-quantum well layer, thereby increasing the internal quantum efficiency and luminous efficiency of the LED, has become an important direction of technical research. Summary of the invention

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a GaN-based light-emitting diode epitaxial wafer and a preparation method thereof, using the following technical solutions:

[0005] In one aspect, the present invention provides a method for preparing a GaN-based light-emitting diode epitaxial wafer, comprising the following steps:

[0006] S10: providing a substrate, and sequentially growing a low-temperature buffer layer, a U-type GaN layer, and an N-type GaN layer on the substrate;

[0007] S20: growing a stress adjustment layer on the N-type GaN layer, wherein the stress adjustment layer includes a single or multiple structural layers, each structural layer includes a stacked first InGaN sublayer and a barrier sublayer, the barrier sublayer is grown on the first InGaN sublayer, and its composition is Al x In y Ga 1-x-y N sublayers, where 0≤x<1, 0≤y<1, x+y≤1;

[0008] S21: introducing H2 during the growth of the first InGaN sublayer, with a flow rate of H2 of 4 slm to 30 slm;

[0009] S30: growing a multi-quantum well layer on the stress adjustment layer, wherein the In concentration of the stress adjustment layer is lower than the In concentration of the multi-quantum well layer;

[0010] S40: sequentially growing an electron blocking layer, a low-temperature P-type GaN layer, a hole dispersion layer, a P-type GaN layer, and a P-type GaN layer contact layer on the multi-quantum well layer.

[0011] As a further improvement, in step S20, the above Al x In y Ga 1-x-y The N sublayer may also be replaced by a second InGaN sublayer, wherein the In concentration of the second InGaN sublayer is lower than the In concentration of the first InGaN sublayer.

[0012] As a further improvement, the thickness of the first InGaN sublayer is 2nm to 5nm, and the Al x In y Ga 1-x-y The thickness of the N sublayer or the second InGaN sublayer is 5 nm to 60 nm.

[0013] As a further improvement, the In concentration of the first InGaN sublayer is 3% to 10%, and the Al x In y Ga 1-x-y The In concentration of the N sublayer or the second InGaN sublayer is 0% to 5%.

[0014] As a further improvement, in step S20, the introduction of H2 is specifically as follows:

[0015] It includes a H2 introduction stage and an inert gas introduction stage, and the H2 introduction flow rate is 4slm to 30slm;.

[0016] As a further improvement, the above-mentioned inert gas is N2, and the flow rate of N2 is 50slm to 200slm.

[0017] As a further improvement, in step S20, the growth temperature of the first InGaN sublayer is 650°C to 850°C, and the Al x In y Ga 1-x-y The growth temperature of the N sublayer is 700°C to 900°C.

[0018] Another aspect of the present invention provides an epitaxial wafer of a GaN-based light-emitting diode, which is prepared by any one of the preparation methods described above.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] First, the technical solution effectively alleviates the lattice mismatch stress between the N-type GaN layer and the multi-quantum well layer by setting a stress adjustment layer between the two. The stress adjustment layer is composed of a single or multiple structural layers, each of which includes a first InGaN sublayer and an Al x In y Ga 1-x-y By adjusting the first InGaN sublayer and the Al x In y Ga 1-x-y The thickness of the N sublayer and the In concentration can optimize the internal structure of the stress regulation layer, which can effectively alleviate the lattice mismatch between the multi-quantum well layer and the N-type GaN layer, reduce the accumulation of interface stress and the structural defects caused by it, thereby significantly improving the stress matching performance of the multi-quantum well layer and laying the foundation for the improvement of quantum efficiency.

[0021] Secondly, in the process of growing the stress adjustment layer, the present invention adopts the first InGaN sublayer and the Al x In y Ga 1-x-y The structural design of the N sublayer (or the second InGaN sublayer) and the introduction of H2 at a flow rate of 4slm to 30slm during the growth of the first InGaN sublayer can effectively remove the poor quality crystal areas in the InGaN sublayer while retaining high-quality crystals, reducing dislocations and interface defects, and by controlling the H2 introduction time and flow rate ratio, the volatilization of indium components and thinning of the InGaN sublayer caused by excessive H2 can be avoided, ultimately significantly improving the overall crystal quality of the stress adjustment layer and providing a high-quality foundation for the growth of subsequent layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic structural diagram of a GaN-based light-emitting diode epitaxial wafer provided in an embodiment of the present invention;

[0024] Figure 2 A flow chart of a method for preparing a GaN-based light-emitting diode epitaxial wafer provided in an embodiment of the present invention;

[0025] Figure 3 It is a schematic diagram of the longitudinal structure of the GaN barrier sublayer in the stress adjustment layer of the present invention;

[0026] Figure 4 It is a schematic diagram of the longitudinal structure of the barrier sublayer of the stress adjustment layer of the present invention being InGaN;

[0027] Figure 5 It is a schematic diagram of the longitudinal structure of the barrier sublayer of the stress adjustment layer of the present invention being AlInGaN;

[0028] Figure 6 It is a schematic diagram of the longitudinal structure of the stress adjustment layer of the present invention in which the barrier sublayer is AlGaN.

[0029] Reference numerals:

[0030] 1-substrate; 2-low-temperature buffer layer; 3-U-type GaN layer; 4-N-type GaN layer; 5-stress adjustment layer; 51-first InGaN sublayer; 52-barrier sublayer; 6-multiple quantum well layer; 7-electron blocking layer; 8-low-temperature P-type GaN layer; 9-hole dispersion layer; 10-P-type GaN layer; 11-P-type GaN layer contact layer. DETAILED DESCRIPTION

[0031] In order to facilitate understanding by those skilled in the art, the structure of the present invention is further described in detail with reference to the accompanying drawings:

[0032] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. The orientation or positional relationship indicated by the terms "portion", "side", "end", etc. is based on the orientation or positional relationship shown in the drawings and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention.

[0033] like Figure 1 As shown, the present invention provides a GaN-based light-emitting diode epitaxial wafer, whose structure includes, from bottom to top, a substrate 1, a low-temperature buffer layer 2, a U-type GaN layer 3, an N-type GaN layer 4, a stress adjustment layer 5, a multi-quantum well layer 6, an electron blocking layer 7, a low-temperature P-type GaN layer 8, a hole dispersion layer 9, a P-type GaN layer 10 and a P-type GaN layer contact layer 11.

[0034] refer to Figure 1-Figure 2 The method for preparing the GaN-based light-emitting diode epitaxial wafer comprises the following steps:

[0035] S10: providing a substrate 1, and sequentially growing a low-temperature buffer layer 2, a U-type GaN layer 3, and an N-type GaN layer 4 on the substrate 1.

[0036] In this step, the substrate 1 can be selected from sapphire substrate 1, silicon substrate 1, SiC substrate 1 or GaN substrate 1, but is not limited thereto. Sapphire has the advantages of mature technology and low cost; SiC substrate 1 is suitable for high-performance devices due to its excellent thermal conductivity and lattice matching; and GaN template is suitable for high-end applications due to its low dislocation density and high crystal quality. In a specific embodiment, sapphire substrate 1 is selected.

[0037] Furthermore, a low-temperature buffer layer 2 is grown on the substrate 1, wherein the low-temperature buffer layer 2 may be a GaN buffer layer or an AlN buffer layer. The low-temperature buffer layer 2 is used to alleviate the lattice mismatch and thermal mismatch between the substrate 1 and the subsequently grown epitaxial layer, reduce crystal defects, and improve the crystal quality of the subsequent epitaxial layer. In one embodiment, the thickness of the low-temperature buffer layer 2 is 30nm to 100nm, the growth temperature is 500℃ to 600℃, and the growth pressure is 100Torr to 500Torr.

[0038] Furthermore, a U-type GaN layer 3 is grown on the low-temperature buffer layer 2. The U-type GaN layer 3 is mainly used to further relieve lattice mismatch stress and thermal mismatch, and at the same time serves as a transition layer between the buffer layer and the high-temperature N-type GaN layer 4 to improve crystal quality. In one embodiment, the thickness of the U-type GaN layer 3 is 2 μm to 4 μm, the growth temperature is 1000° C. to 1200° C., and the growth pressure is 150 Torr to 250 Torr.

[0039] Furthermore, an N-type GaN layer 4 is grown on the U-type GaN layer 3. The N-type GaN layer 4 is an electron injection layer. The conductivity is improved by Si doping, and the layer has a high electron mobility and a low defect density. Specifically, the thickness of the N-type GaN layer 4 is 1 μm to 4 μm, the growth temperature is 1000° C. to 1150° C., the growth pressure is 100 Torr to 200 Torr, and the doping concentration is 5×10 18 cm -3 ~3×10 19 cm -3 The N-type GaN layer 4 not only provides a high-quality substrate for the stress adjustment layer 5, but also enhances the current expansion capability of the LED device.

[0040] S20: growing a stress adjustment layer 5 on the N-type GaN layer 4, wherein the stress adjustment layer 5 comprises a single or multiple structural layers, each of which comprises a stacked first InGaN sublayer 51 and a barrier sublayer 52, wherein the barrier sublayer 52 is grown on the first InGaN sublayer 51 and comprises Al x In y Ga 1-x-y N sublayers, where 0≤x<1, 0≤y<1, x+y≤1.

[0041] The stress adjustment layer 5 is located between the N-type GaN layer 4 and the multi-quantum well layer 6. Its main function is to relieve the stress caused by lattice mismatch and prevent the stress from being transferred to the multi-quantum well layer 6 and affecting its light-emitting performance.

[0042] In one embodiment, the In concentration in the first InGaN sublayer 51 is 3% to 10%. The lower In content makes the lattice constant between the N-type GaN layer 4 and the multi-quantum well layer 6, forming a gradual transition of stress. Its thickness is 2nm to 5nm, which can effectively relieve stress while ensuring the crystal quality. The growth temperature of the first InGaN sublayer 51 is 650℃ to 850℃, and the appropriate growth temperature helps prevent the growth of poor quality InGaN layers.

[0043] Furthermore, Al x In y Ga 1-x-y The thickness of the N sublayer is 50nm-200nm, which provides support for the first InGaN sublayer 51 and further alleviates the lattice mismatch. The growth temperature is 700°C-900°C, and the crystal quality is better guaranteed in this temperature range.

[0044] In each structural layer, Al x In y Ga 1-x-y The N sublayer is grown on the first InGaN sublayer 51 , which ensures the overall stability of the crystal and provides a flat surface for the subsequent growth of the multi-quantum well layer 6 .

[0045] In some embodiments, each structural layer may be a first InGaN sublayer 51 and a GaN sublayer, a first InGaN sublayer 51 and a second InGaN sublayer, a first InGaN sublayer 51 and an AlInGaN sublayer, or a first InGaN sublayer 51 and an AlGaN sublayer. Figure 3-Figure 6 The barrier sublayer 52 is a schematic diagram of the longitudinal structure of a GaN sublayer, a second InGaN sublayer, an AlInGaN sublayer and an AlGaN sublayer.

[0046] In step S20, A1 x In y Ga 1-x-y The N sublayer can also be replaced by a second InGaN sublayer, wherein the In concentration of the second InGaN sublayer is higher than the In concentration of the first InGaN sublayer 51. The purpose of the lower In concentration of the first InGaN sublayer 51 is to relieve the lattice mismatch stress between the N-type GaN layer 4 and the upper layer and reduce the propagation of defects. The higher In concentration of the second InGaN sublayer further transitions to the high In concentration region of the multi-quantum well layer 6, enhances the lattice matching of the interface, provides better crystal quality, reduces interface stress, and improves carrier recombination efficiency.

[0047] In one embodiment, the In concentration of the first InGaN sublayer 51 is 3% to 10%, and the Al x In y Ga 1-x-y The In concentration of the N sublayer or the second InGaN sublayer is 0% to 5%.

[0048] Step S20 further includes step S21. Step S21 specifically includes: introducing H2 in a pulsed manner during the growth of the first InGaN sub-layer 51, with the H2 flow rate being 4 slm to 30 slm.

[0049] The intermittent introduction of H2 can decompose the poor quality crystal area, remove defects, and retain high-quality crystals, thereby improving the crystal quality of the stress adjustment layer 5. Through pulse control, the problem of In component loss caused by excessive H2 is avoided, ensuring the component stability and structural integrity of the InGaN sublayer.

[0050] Specifically, the introduction of H2 includes an H2 introduction stage and an inert gas introduction stage, and the H2 flow rate is 4slm to 30slm; the inert gas is N2, and the N2 flow rate is 50slm to 200slm.

[0051] In step S20 and step S21, the stress adjustment layer 5 forms a transition zone on the lattice constant, effectively alleviating the lattice mismatch stress between the N-type GaN layer 4 and the multi-quantum well layer 6, significantly reducing the defect generation caused by stress concentration, and preventing the dislocations and defects in the N-type GaN layer 4 from propagating to the multi-quantum well layer 6, thereby improving the overall crystal quality of the epitaxial wafer. In addition, the use of pulsed H2 improves the surface flatness and crystal uniformity of the stress adjustment layer 5, provides a high-quality substrate for the high-quality growth of the multi-quantum well layer 6, achieves a more stable lattice transition, optimizes the interface matching of the multi-quantum well layer 6, and significantly improves the photoelectric performance of the quantum well and the luminous efficiency of the overall epitaxial wafer.

[0052] S30 : growing a multi-quantum well layer 6 on the stress adjustment layer 5 , wherein the In concentration of the stress adjustment layer 5 is lower than the In concentration of the multi-quantum well layer 6 .

[0053] The multi-quantum well layer 6 is the core light-emitting area of ​​the photodiode. The light-emitting wavelength is determined by the In concentration in the InGaN light-emitting layer. The purpose of this step is to form a stable lattice transition between the stress adjustment layer 5 and the multi-quantum well layer 6 by regulating the In concentration gradient, so as to alleviate the stress accumulation and interface mismatch problems, reduce the generation of defects, and provide a high-quality structural foundation for the high-quality growth of the multi-quantum well layer 6.

[0054] S40: sequentially growing an electron blocking layer 7, a low-temperature P-type GaN layer 8, a hole dispersion layer 9, a P-type GaN layer 10, and a P-type GaN layer contact layer 11 on the multi-quantum well layer 6.

[0055] In this step, the electron blocking layer 7 is mainly used to suppress the electrons from overflowing from the multi-quantum well layer 6 to the P-type region, so as to improve the recombination efficiency of electrons and holes in the quantum well. The low-temperature P-type GaN layer 8 reduces the compensation effect of doping (such as Mg) by lowering the growth temperature, thereby improving the hole concentration and conductivity of the P-type region, which can enhance the hole injection ability, and can also serve as the basis of the subsequent hole dispersion layer 9 to provide support for improving the carrier distribution in the P-type region. The hole dispersion layer 9 is used to improve the distribution and expansion efficiency of holes in the P-type region, and further optimize the injection ability of holes. The P-type GaN layer 10 is the main conductive layer in the P-type region, which is responsible for providing a channel for the expansion of carriers and optimizing the current distribution and photoelectric conversion efficiency of the LED. The P-type GaN layer contact layer 11 is located above the P-type GaN layer 10, and its main function is to improve the contact performance with the metal electrode, reduce the ohmic contact resistance, and thus improve the current injection efficiency.

[0056] Table 1 shows the experimental data of the light-emitting diodes of the GaN-based light-emitting diode epitaxial wafers prepared under different conditions, including wavelength, forward voltage and forward current. By comparing different process conditions, the effect of pulsed H2 in optimizing the stress adjustment layer 5 and improving device performance can be verified.

[0057]

[0058] Table 1 - Experimental data table

[0059] Among them, wavelength represents the light output wavelength of the light emitting diode, in nanometers, and the stability and accuracy of the wavelength reflect the crystal quality and stress distribution of the multi-quantum well layer 6. The level of the forward voltage is related to the current expansion capability, interface defects and carrier transport efficiency of the device. The higher the value of the forward current, the higher the current injection efficiency of the LED device.

[0060] The barrier layer 52 is Al x In y Ga 1-x-y N sublayer or second InGaN sublayer.

[0061] In the control group, H2 was not introduced during the growth of the InGaN sublayer of the stress adjustment layer 5, while H2 was introduced into the barrier sublayer 52. Due to the lack of H2 removal optimization, the InGaN sublayer is prone to introduce crystal defects and surface unevenness during the growth process, resulting in poor crystal quality of the stress adjustment layer 5. Finally, the photodiode prepared under this process condition has a wavelength of 453.9nm, a forward voltage of 2.889V, and a forward current of 254.8mA, with weak performance, indicating that the stress adjustment layer 5 failed to effectively relieve the interface stress or improve the defect density.

[0062] In experimental group 1, H2 was pulsed into the InGaN sublayer, while H2 was not passed into the barrier sublayer 52. The pulsed introduction of H2 removed the low-quality area during the growth of the InGaN sublayer, improved the surface flatness and crystal uniformity of the sublayer, and maintained a high structural quality. The barrier sublayer 52 not passing H2 further enhanced its lattice matching with the InGaN sublayer and reduced the interface stress. Compared with the control group, the wavelength of experimental group 1 was slightly shortened to 453.0nm. This is because H2 reduced the defect and dislocation density of the stress adjustment layer 5, made the stress distribution more uniform, reduced the piezoelectric effect in the crystal, and slightly adjusted the optical properties of the multiple quantum wells. Furthermore, the forward voltage was reduced to 2.875V and the forward current was increased to 256.3mA. This shows that the overall performance of the stress adjustment layer 5 has been significantly improved by the pulsed introduction of H2, and the injection efficiency and recombination efficiency of carriers have been improved.

[0063] Experimental group 2 used pulsed H2 during the growth of both the InGaN sublayer and the barrier sublayer 52. The pulsed H2 injection of the InGaN sublayer improved its crystal quality and surface flatness, while the H2 injection of the barrier sublayer 52 could further optimize its own quality, but had an adverse effect on the lattice matching of the InGaN sublayer, resulting in the overall performance of the stress adjustment layer 5 being slightly lower than that of experimental group 1. Experimental data showed that the wavelength was 452.0nm, the forward voltage was 2.870V, and the forward current was 255.8mA under this process, which was better than the control group, but still lower than the performance of experimental group 1.

[0064] The present invention further provides an epitaxial wafer of a GaN-based light-emitting diode, which is prepared by the above-mentioned preparation method.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a GaN-based light-emitting diode epitaxial wafer, characterized in that: The following steps are involved: S10: providing a substrate, and sequentially growing a low-temperature buffer layer, a U-type GaN layer, and an N-type GaN layer on the substrate; S20: growing a stress adjustment layer on the N-type GaN layer, wherein the stress adjustment layer includes a single or multiple structural layers, each of which includes a stacked first InGaN sublayer and a barrier sublayer, wherein the barrier sublayer is grown on the first InGaN sublayer and has a composition of Al x In y Ga 1-x-y N sublayers, where 0≤x<1, 0≤y<1, x+y≤1; S21: During the growth of the first InGaN sublayer, the H2 flow rate is 4 slm to 30 slm; S30: growing a multi-quantum well layer on the stress adjustment layer, wherein the In concentration of the stress adjustment layer is lower than the In concentration of the multi-quantum well layer; S40: sequentially growing an electron blocking layer, a low-temperature P-type GaN layer, a hole dispersion layer, a P-type GaN layer, and a P-type GaN layer contact layer on the multi-quantum well layer.

2. The method for preparing a GaN-based light-emitting diode epitaxial wafer according to claim 1, characterized in that: In step S20, the A1 x In y Ga 1-x-y The N sublayer may also be replaced by a second InGaN sublayer, wherein the In concentration of the second InGaN sublayer is lower than the In concentration of the first InGaN sublayer.

3. The method for preparing a GaN-based light-emitting diode epitaxial wafer according to claim 2, characterized in that: The thickness of the first InGaN sublayer is 2nm to 5nm, and the Al x In y Ga 1-x-y The thickness of the N sublayer or the second InGaN sublayer is 5 nm to 60 nm.

4. The method for preparing a GaN-based light-emitting diode epitaxial wafer according to claim 2, characterized in that: The In concentration of the first InGaN sublayer is 3% to 10%, and the Al x In y Ga 1-x-y The In concentration of the N sublayer or the second InGaN sublayer is 0% to 5%.

5. The method for preparing a GaN-based light-emitting diode epitaxial wafer according to claim 1, characterized in that: In step S20, the introduction of H2 is specifically: It includes a H2 introduction stage and an inert gas introduction stage, and the flow rate is 4slm to 30slm.

6. The method for preparing a GaN-based light-emitting diode epitaxial wafer according to claim 5, characterized in that: The inert gas is N2, and the flow rate of N2 is 50slm to 200slm.

7. The method for preparing a GaN-based light-emitting diode epitaxial wafer according to claim 1, characterized in that: In step S20, the growth temperature of the first InGaN sublayer is 650°C to 850°C, and the Al x In y Ga 1-x-y The growth temperature of the N sublayer is 700°C to 900°C.

8. An epitaxial wafer of a GaN-based light-emitting diode, characterized in that: The method is prepared by any one of claims 1 to 7.

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