Artificial synaptic device based on molybdenum disulfide ink, array of artificial synaptic device and preparation method of artificial synaptic device

Abstract

The invention belongs to the technical field of semiconductor materials, and particularly relates to an artificial synaptic device based on molybdenum disulfide ink, an array of the artificial synaptic device and a preparation method. The device mainly comprises a substrate, a channel, a source / drain electrode, a P (VDF-TrFE) ferroelectric film gate dielectric layer and a gate electrode, wherein the channel material is a MoS2 ink film; the device is of a top gate structure, namely, a P (VDF-TrFE) ferroelectric film gate dielectric layer is located on the upper surface of a channel, a gate electrode is located on the upper surface of the P (VDF-TrFE) ferroelectric film gate dielectric layer, and a source electrode and a drain electrode are located on the two sides of the channel respectively and make contact with the channel. The artificial synaptic device has the characteristics of large storage window, high switch ratio and quick response, has the advantages of nonvolatile storage characteristic, continuous and adjustable weight update, high-density integration, low-power operation, quick response time, strong durability and the like, and can realize simulation of biological synaptic behaviors.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor materials, and particularly relates to an artificial synaptic device based on molybdenum disulfide ink, an array thereof, and a preparation method thereof. Background Art

[0002] Compared with the traditional von Neumann computing architecture, artificial synaptic devices based on neuromorphic computing can achieve the function of in-memory computing, and are expected to significantly reduce the energy and time consumption of data-intensive computing. Among various artificial synaptic devices, two-dimensional material devices are more and more widely used, and the array of devices is becoming more and more important.

[0003] Although various MoS2-based artificial synaptic transistors have been reported in the past few years, due to the low yield and low quality of MoS2 thin films, the controllable fabrication of large-area artificial synaptic transistor arrays for simulating biological synaptic behavior remains a major challenge. In the prior art, mechanical exfoliation, chemical vapor deposition (CVD), and ultrasound-based liquid-phase exfoliation are usually used to prepare MoS2: (1) When preparing MoS2 by mechanical exfoliation, not only is the yield low, but the thickness, size, and shape are difficult to control. (2) Chemical vapor deposition (CVD) growth is considered to be the most promising method for synthesizing large-area MoS2 thin films, but the strict conditions and poor reproducibility of the growth process increase the integration complexity, thus hindering its implementation in large-scale circuit applications. (3) The nanosheets prepared by traditional ultrasound-based liquid-phase exfoliation have a wide thickness distribution and a short transverse length, resulting in unsatisfactory electrical properties of the thin film and cannot be used as a semiconductor channel. Compared with traditional mechanical exfoliation and widely explored chemical vapor deposition techniques, MoS2 electrochemical exfoliation based on electrochemically assisted molecular intercalation has been reported as an emerging solution-processed method.

[0004] Despite the rapid development of solution-processed two-dimensional semiconductor channel devices, research on gate dielectric materials compatible with solution-processable channel materials remains limited. Mechanically exfoliated two-dimensional ferroelectric gate dielectrics cannot be arrayed, and CVD growth of large-area gate dielectric materials requires high temperatures and complex process conditions, making it difficult to meet the needs of large-scale applications. For TMDCs that can also be prepared by liquid-phase exfoliation, such as hafnium disulfide (HfS2), its oxidized phase can be used as a gate dielectric, but it still requires post-oxidation treatment at temperatures above 500°C. MoS2 ink is a stable dispersion composed of a two-dimensional molybdenum disulfide material and a solvent, commonly used in technical fields such as inkjet printing or 3D printing. Currently, research on MoS2 ink has mostly focused on analyzing the basic properties of two-terminal or three-terminal devices. Some studies have used MoS2 ink to fabricate memristors (Chinese patent application CN 118076218 A). This study used MoS2 ink as the intermediate layer of a two-terminal memristor, which holds promise for applications in neural network computing. However, memristors rely on physical changes within the material, which can introduce additional noise sources when integrated at high density. Furthermore, the limited number of ports complicates wiring and interconnection when constructing complex neural networks. A three-terminal structure offers greater flexibility in circuit design and facilitates the integration of logic operations and memory functions within the same device. Using MoS2 ink to construct arrays of artificial synaptic devices that mimic biological synaptic behavior requires finding functional layers compatible with semiconductor processes and capable of arraying. This presents challenges with device fabrication complexity and arraying process compatibility. Currently, substantial progress in constructing three-terminal artificial synaptic devices using MoS2 ink has been limited. According to our research, no research has been reported on arrays of artificial synaptic devices based on MoS2 ink and ferroelectric gate dielectrics. Summary of the Invention

[0005] To address the shortcomings and deficiencies of the prior art, the present invention primarily aims to provide an artificial synaptic device based on molybdenum disulfide ink. This artificial synaptic device exhibits a large memory window, a high on / off ratio, a fast response, excellent stability, and the ability to mimic the behavior of biological synapses.

[0006] Another object of the present invention is to provide a method for fabricating the aforementioned artificial synaptic device based on molybdenum disulfide ink. The present invention proposes a method for fabricating an artificial synaptic device using molybdenum disulfide (MoS2) ink as the semiconductor channel and the ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) as the gate dielectric. Both the semiconductor channel and the ferroelectric gate dielectric are prepared by spin coating. The present invention's low-temperature, fully solution-processed fabrication of high-performance thin-film transistors provides a cost-effective and scalable approach for heterogeneous thin-film electronics.

[0007] Another object of the present invention is to provide applications of the artificial synapse device.

[0008] The present invention also provides an artificial synaptic device array prepared based on the above artificial synaptic device.

[0009] The purpose of the present invention is achieved through the following technical solutions: An artificial synaptic device based on molybdenum disulfide ink, the device mainly includes a substrate, a channel, a source / drain, a P(VDF-TrFE) ferroelectric thin film gate dielectric and a gate; wherein the channel material is a MoS2 ink thin film; The device has a top-gate structure, that is, the P(VDF-TrFE) ferroelectric thin film gate dielectric is located on the upper surface of the MoS2 ink channel, the gate is located on the upper surface of the P(VDF-TrFE) ferroelectric thin film gate dielectric, the source and drain are respectively located on both sides of the MoS2 ink channel and in contact with it, and the lower surface of the channel is in contact with the substrate.

[0010] Preferably, the source / drain electrodes are Cr / Au source / drain electrodes.

[0011] More preferably, in the Cr / Au source-drain electrode, the thickness of Cr is 10-15 nm, and the thickness of Au is 30-35 nm.

[0012] Preferably, the thickness of the P(VDF-TrFE) ferroelectric thin film gate dielectric is 200-300 nm; the thickness of the MoS2 ink channel layer is 10-15 nm.

[0013] Preferably, the gate is a pure Au gate electrode.

[0014] More preferably, the thickness of the gate is 20-30 nm.

[0015] Preferably, the substrate is a SiO2 substrate with a thickness of 285 nm.

[0016] The present invention proposes a method for preparing an artificial synaptic device based on molybdenum disulfide ink, comprising the following steps: (1) Preparation of colloidal solution: MoS2 nanosheet ink was prepared by electrochemical molecular intercalation exfoliation method; polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) was dissolved in solvent to obtain P(VDF-TrFE) gate dielectric solution; (2) Substrate pretreatment: The substrate is cleaned and then treated with oxygen plasma to improve the hydrophilicity of the substrate; (3) Semiconductor channel film deposition and post-processing: MoS2 nanosheet ink is spin-coated on the pre-treated substrate several times to obtain a continuous and uniform nanosheet interconnected film; then, the entire film is acid-washed and thermally annealed; finally, the semiconductor channel is obtained by mask etching to facilitate the subsequent device fabrication; (4) Preparation of source / drain electrodes: Prepare source / drain electrodes at both ends of the channel through processes such as spin coating photoresist, UV lithography, development, vacuum metal evaporation and stripping; (5) Deposition and post-processing of ferroelectric gate dielectric film: On the channel with source / drain electrodes, a gate dielectric layer is prepared by spin coating. The P(VDF-TrFE) gate dielectric solution is spin-coated on the channel as the P(VDF-TrFE) ferroelectric thin film gate dielectric layer, and then dried and vacuum annealed to achieve close contact between the channel and the gate dielectric layer. (6) Preparation of the gate: The gate is prepared using electrode transfer technology to complete the preparation of the artificial synaptic device.

[0017] Preferably, the concentration of the P(VDF-TrFE) gate dielectric solution in step (1) is 4-6 wt%, more preferably 6 wt%, and its solvent is N,N-dimethylformamide (DMF); the peak absorbance of the MoS2 nanosheet ink at 450 nm is 0.70, and its solvent is isopropanol.

[0018] Preferably, the specific preparation steps of the MoS2 nanosheet ink in step (1) include: in an electrolyte solution, using bulk molybdenum disulfide crystals and graphite flakes as cathode and anode, respectively; using an electrochemical workstation to apply a voltage of 8-10V to the anode for 1 hour; ultrasonically dispersing the expanded MoS2 in a PVP / DMF solution, centrifuging the obtained dispersed solution to remove large blocks and unpeeled blocks, further centrifuging the remaining supernatant, washing the obtained sediment with isopropanol, and finally dispersing the sediment in isopropanol to obtain the MoS2 nanosheet ink.

[0019] Preferably, the cleaning in step (2) refers to ultrasonically cleaning the substrate with acetone, isopropanol, and water for 10 to 15 minutes each, and blowing the substrate dry with nitrogen; then using oxygen plasma treatment for 10 to 15 minutes to improve the hydrophilicity of the substrate.

[0020] Preferably, the rotation speed of the spin coating in step (3) is 2000 r / min, and the time for each coating is 60 s; the acid washing refers to immersing the entire membrane in a 10 mg / mL bis(trifluoromethane)sulfonyl imide (TFSI) 1,2-dichloroethane solution and maintaining it at 70-80 °C for 1 h; the thermal annealing is carried out under inert gas protection for 1 hour at a temperature of 250-300 °C.

[0021] Preferably, the number of spin coating in step (3) is about 3 times, and the thickness of the MoS2 ink channel obtained is 10-15 nm.

[0022] Preferably, in step (5), the spin coating is performed at a rotation speed of 500 r / min for 10 seconds and then at a rotation speed of 3000 r / min for 60 seconds; the drying is performed by heating at 70-80°C for 5-10 minutes, and the thermal annealing is performed at 145°C for 1-2 hours.

[0023] Preferably, the specific steps of step (6) are: first, a pure Au electrode is evaporated onto a SiO2 substrate, and then the Au electrode is transferred as a top metal electrode through a polyvinyl butyral (PVB) film.

[0024] The artificial synaptic device described in this invention has broad potential applications, particularly in neuromorphic computing, low-power electronic devices, and intelligent systems. It can be used to construct a hardware platform that mimics the structure of a biological nervous system, enabling efficient and energy-efficient information processing and excelling in image recognition, natural language processing, and other cognitive tasks.

[0025] The present invention also proposes an artificial synaptic device array using molybdenum disulfide (MoS2) ink as a semiconductor channel and a ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) as a gate dielectric, wherein both the semiconductor channel and the ferroelectric gate dielectric are prepared by spin coating.

[0026] In the embodiment of the present invention, a 3×3 artificial synapse array was constructed based on the above-mentioned artificial synapse device, demonstrating the scalability potential of the present invention.

[0027] Compared with the prior art, the present invention has the following advantages and beneficial effects: (1) The artificial synaptic device described in the present invention has the characteristics of a large storage window, a high switching ratio, and a fast response. It has the advantages of non-volatile storage characteristics, continuously adjustable weight update, high-density integration, low-power operation, fast response time, and strong durability, and can realize the simulation of biological synaptic behavior.

[0028] (2) The three-terminal structure of the artificial synaptic device of the present invention provides greater flexibility for circuit design and can be used to construct a hardware platform that simulates the structure of a biological nervous system, achieving efficient and energy-saving information processing. The artificial synaptic device of the present invention can mimic the behavior of biological synapses, including non-volatile weight storage, synaptic plasticity, and excitatory postsynaptic currents (EPSCs), thereby supporting complex neural network operations. The application fields and application prospects of artificial synaptic devices are very broad.

[0029] (3) The channel material of the artificial synaptic device described in the present invention is prepared by a stable phase-pure 2H-MoS2 ink solution based on an electrochemical molecular intercalation exfoliation method, which is low-cost, high-efficiency, simple process, and can be processed on a large scale. The resulting two-dimensional MoS2 nanosheets with high quality and excellent morphology can be successfully used to form thin-film transistor networks on a large area. In this method, due to the action of the electric field, ions or molecules are more likely to enter the interlayer of the host material, which improves the efficiency of the intercalation process and can be carried out at a lower temperature. During the preparation of MoS2 nanosheets, an electrochemical workstation can be used to monitor the intercalation process in real time by online measuring parameters such as current and voltage, facilitating timely adjustment of experimental conditions to optimize the results.

[0030] (4) The ferroelectric gate dielectric used in the artificial synaptic device of the present invention is copolymer P (VDF-TrFE), which has significant advantages such as high spontaneous polarization, good polarization stability, fast polarization reversal time, low leakage current, low-temperature processing, and compatibility with semiconductor technology. As a solution-processable ferroelectric gate dielectric, copolymer P (VDF-TrFE) can be combined with a semiconductor channel made of MoS2 ink to achieve device arraying. In addition, the use of the ferroelectric copolymer P (VDF-TrFE) functional layer introduces logical operation and storage functions to the device, which can be used to construct artificial synaptic devices that simulate biological synaptic behavior and support neuromorphic computing.

[0031] (5) The gate dielectric and semiconductor channel of the artificial synaptic device of the present invention are assembled by layer-by-layer spin coating. The layer-by-layer low-temperature spin coating process is conducive to the formation of a good van der Waals interface between the semiconductor and the ferroelectric copolymer, significantly improving the gate control efficiency of the transistor, and the processing cost is relatively low and the scalability is strong. While ensuring that the overall device can be used as a high-performance artificial synaptic device, large-area, batch-scale thin film preparation can be achieved, which is suitable for industrial-scale production and solves the complexity of the preparation of two-dimensional material device arrays and the compatibility problems of arraying processes. The present invention demonstrates for the first time a high-performance artificial synaptic transistor array based on molybdenum disulfide nanosheet ink, indicating that MoS2 ink prepared by electrochemical stripping has broad application prospects in the manufacture of high-performance artificial synaptic arrays. Our high-performance thin film transistor low-temperature manufacturing process provides an economical, efficient and scalable method for heterogeneous integrated thin film electronic devices.

[0032] (6) After obtaining the channel made of molybdenum disulfide ink, the artificial synaptic device of the present invention is subjected to additional acid washing and thermal annealing processes to passivate the sulfur vacancies in the molybdenum disulfide, thereby obtaining a high-quality 2D n-type semiconductor film. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic structural diagram of the artificial synapse device prepared in Example 1 of the present invention; Among them, 1 is Si; 2 is SiO2 substrate; 3 is the channel prepared by MoS2 ink film; 4 is Cr / Au source and drain electrodes; 5 is P(VDF-TrFE) ferroelectric film gate dielectric layer; ⑥ is Au top gate electrode.

[0034] Figure 2 This is a Raman characterization image of the MoS2 nanosheets prepared in Example 1 of the present invention.

[0035] Figure 3 The electrical properties of the transistor prepared with SiO2 as the gate dielectric before and after acid treatment and thermal annealing of the MoS2 ink film prepared in Example 1 of the present invention are compared.

[0036] Figure 4 The electrical performance of the transistor prepared with the MoS2 ink film prepared in Example 1 of the present invention and SiO2 as the gate dielectric.

[0037] Figure 5 Ferroelectric hysteresis loops obtained in Au-P(VDF-TrFE)-Au capacitors at a test frequency of 10 kHz for P(VDF-TrFE) ferroelectric films prepared according to Example 1 of the present invention and P(VDF-TrFE) gate dielectric solutions with different concentrations.

[0038] Figure 6 This is an optical photograph of a 3×3 artificial synaptic device array constructed by the artificial synaptic device prepared in Example 1 of the present invention.

[0039] Figure 7 The electrical properties of the artificial synapse device prepared in Example 1 of the present invention.

[0040] Figure 8 The current responses of the artificial synaptic device prepared in Example 1 of the present invention when gate voltages of different amplitudes are applied.

[0041] Figure 9 The current response of the artificial synaptic device prepared in Example 1 of the present invention when electric pulses of different widths are applied. DETAILED DESCRIPTION

[0042] The present invention will be described in further detail below with reference to the examples and accompanying drawings, but the embodiments of the present invention are not limited thereto. The raw materials involved in the present invention can be purchased directly from the market. For process parameters not specifically noted, conventional techniques can be used.

[0043] Example 1 A method for preparing an artificial synaptic device based on molybdenum disulfide ink comprises the following steps: (1) Preparation of colloidal solution MoS2 nanosheet ink was prepared by electrochemical exfoliation: in the presence of tetraheptylammonium bromide (THA+ Br − ) and acetonitrile (10 mg / mL) electrolyte solution, with bulk MoS2 crystals and graphite flakes as cathode and anode, respectively. An electrochemical workstation was used to apply a voltage of 8-10 V to the anode for 1 hour. + The interlayer, embedded with bulk molybdenum disulfide, expands its layered structure. The expanded MoS2 was sonicated in a 22 mg / mL PVP / DMF solution (PVP with a molecular weight of 40,000) for 10 minutes. The resulting dispersion was centrifuged at 3,000 rpm for 10 minutes to remove large and unexfoliated pieces. The remaining supernatant was then further centrifuged at 10,000 rpm for 20 minutes. The resulting sediment was washed three times with isopropyl alcohol (IPA) to remove excess PVP. Finally, it was dispersed in IPA to form a uniform and pure 2H-phase MoS2 nanosheet ink. The optical absorbance of the ink solution was measured using a UV-visible spectrophotometer to test the concentration of the MoS2 dispersion. As a standard, the peak absorbance of the ink solution at 450 nm was adjusted to 0.70. Figure 2 The Raman spectrum of the nanosheets proves that the present invention obtains phase-pure, semiconducting, and narrowly distributed 2H-MoS2 nanosheets.

[0044] Preparation of P(VDF-TrFE) gate dielectric solution: The solvent of P(VDF-TrFE) (the molar ratio of PVDF:TrFE is 70%:30%) ferroelectric thin film gate dielectric solution is N,N-dimethylformamide, and the mass concentration of P(VDF-TrFE) in the P(VDF-TrFE) gate dielectric solution is 6%.

[0045] (2) Substrate pretreatment: The selected substrate is a 285 nm thick SiO2 substrate. First, the substrate is ultrasonically cleaned with acetone, isopropanol, and water for 10 min each, and then blown dry with nitrogen. In order to make the substrate surface hydrophilic for better spin coating effect, it is treated with oxygen plasma at 200 W power for 10 minutes.

[0046] (3) Semiconductor channel film deposition and post-treatment: MoS2 nanosheet ink was spin-coated three times on the pretreated substrate to obtain a continuous and uniform nanosheet interconnected film. The spin coating speed was 2000 r / min, and each time lasted 60 s. Then, the entire film was immersed in a 10 mg / mL bis(trifluoromethane)sulfonyl imide (TFSI) 1,2-dichloroethane solution and heated in a water bath at 80 ° C for 1 h. TFSI molecules can passivate the sulfur vacancies in the MoS2 nanosheets. Then, thermal annealing was carried out at 250 ° C for 1 hour in an inert gas tube furnace. Further annealing process further improved the contact between MoS2 nanosheets and removed residual solvent. Finally, the semiconductor channel was obtained by mask etching to facilitate the subsequent device fabrication.

[0047] (4) Preparation of source / drain electrodes: Cr / Au (10 nm / 30 nm) electrodes are prepared at both ends of the channel by spin coating photoresist, UV lithography, development, vacuum metal evaporation and stripping processes; (5) Deposition and post-treatment of ferroelectric gate dielectric film: On the channel with the source / drain electrodes, a P(VDF-TrFE) ferroelectric thin film gate dielectric layer (thickness ≈ 300 nm) was prepared by spin coating using the 6% P(VDF-TrFE) gate dielectric solution prepared in step (1). The detailed parameters of the spin coating were: 500 r / min for 10 seconds, 3000 r / min for 60 seconds. Finally, the entire structure was heated on an 80°C hot plate for 5 minutes and then annealed at 145°C in a vacuum drying oven for 2 hours. The spin coating and drying steps were carried out in a glove box, and the thermal annealing was carried out in a vacuum drying oven.

[0048] (6) Gate fabrication: First, a pure Au electrode was evaporated onto a 285nm SiO2 substrate (electrode thickness 20nm), and then the Au electrode was transferred through a polyvinyl butyral (PVB) film as the top metal electrode. The entire device was then immersed in an ethanol solution at 45℃ for half an hour to dissolve the PVB film. This process did not damage the P(VDF-TrFE) copolymer and the entire device structure.

[0049] (1) Electrical properties and comparison of the artificial synaptic device prepared in Example 1: The electrical performance of the transistor prepared with SiO2 as the gate dielectric before and after the MoS2 ink film prepared in step (3) was tested. The results are as follows: Figure 3 As shown in the figure, the transistors prepared by acid treatment and thermal annealing of MoS2 ink film show typical n-type behavior and over 10 3The on-off ratio of the transistor is 0.05; while the transistor prepared by MoS2 ink film without acid treatment and thermal annealing shows negligible current modulation due to the large presence of sulfur vacancies.

[0050] The artificial synaptic device of the present invention is a typical ferroelectric transistor architecture, which relies on the polarization state of the ferroelectric layer to modulate the conductivity of the channel. Under the action of an external electric field, spontaneous polarization will be generated, and this polarization state can be switched between two directions; even after the external electric field is removed, the polarization state can still be maintained, which is called remanent polarization or coercive force. In a transistor with SiO2 as the gate dielectric, after bidirectional scanning, a small clockwise window is displayed, such as Figure 4 As shown in FIG, this is due to the inevitable interface charge trapping effect and the adsorption of water and oxygen in the air. For the ferroelectric transistor architecture of the present invention, when a gate voltage V higher than the coercive force voltage is applied, gs When the polarization is reversed, the dipoles in the P(VDF-TrFE) layer can be aligned (polarization flipped), thereby producing a typical counterclockwise memory window, indicating the effective regulation of the ferroelectric gate dielectric of the present invention.

[0051] Referring to step (1) of Example 1 above, P(VDF-TrFE) gate dielectric solutions with concentrations of 2wt%, 4wt%, 6wt%, 8wt% and 10wt% were prepared, respectively. Ferroelectric gate dielectric films were prepared from Example 1 and the above P(VDF-TrFE) gate dielectric solutions with different concentrations and their performance was tested. The ferroelectric hysteresis loop obtained in the Au-P(VDF-TrFE)-Au capacitor at a test frequency of 10 kHz was as shown in FIG. Figure 5 As shown, the remanent polarization intensity of the P(VDF-TrFE) ferroelectric gate dielectric layer increases slightly and then decreases with concentration, reaching its highest remanent polarization intensity at a mass concentration of 6% (Example 1). This is because, during device fabrication, the gate dielectric layer is thinner (50-100nm) after spin-coating at a lower concentration of P(VDF-TrFE), making it susceptible to leakage or even breakdown when a high gate voltage is applied. On the other hand, a gate dielectric with a higher concentration, due to its lower remanent polarization intensity and greater thickness, cannot effectively gate the semiconductor layer.

[0052] Based on the artificial synaptic device prepared in Example 1, we constructed a 3×3 artificial synaptic array (such as Figure 6 As shown in Figure 2), the transfer curve of each ferroelectric transistor in the 3×3 artificial synapse array was tested. Figure 7 As shown, the artificial synaptic device prepared in Example 1 has a source-drain voltage V ds = 0.1 V, the typical n-type behavior and a very clear memory hysteresis window exceeding 10 V are displayed in the sweep range above the coercivity voltage of P(VDF-TrFE) ferroelectric polymer (±20 V), with an on-off ratio of >10 3, allowing for low leakage current (~ 10 −10 A) to achieve low power consumption. There is no significant deviation in the electrical performance between the transistors, and they have good uniformity.

[0053] (2) Simulation of biological synaptic behavior of the artificial synaptic device prepared in Example 1: Biological synapses transmit various electrical or chemical signals from the presynaptic terminal to the postsynaptic terminal by regulating neurotransmitter levels. In a three-terminal ferroelectric device, the gate terminal transmits presynaptic signals, while the channel layer transmits postsynaptic signals. When the gate receives a "presynaptic" signal (i.e., an input pulse), it triggers a change in its internal polarization state (polarization reversal), resulting in a transient increase in channel conductance and a transient current similar to an EPSC.

[0054] like Figure 8 and 9 As shown, in the artificial synaptic device prepared in Example 1, excitatory postsynaptic current (EPSC) responses were triggered by gate voltages ranging from 10 V to 25 V under a 10 ms pulse width. Increasing the pulse amplitude resulted in higher EPSCs. Different gate voltages represent different amounts of neurotransmitter release, which indicates synaptic connection strength. After voltage pulse stimulation, EPSCs did not return to their initial values, and higher voltage amplitudes resulted in a significant residual current. This observation suggests that voltage amplitude modulation can shift from short-term potentiation to long-term potentiation. At a gate voltage pulse strength of 15 V, EPSCs gradually increased with increasing pulse width, while longer pulse widths resulted in slower EPSC decay. Pulse amplitude has also been shown to effectively modulate ion channel conductivity. Therefore, larger pulse amplitudes and longer pulse widths favor ferroelectric polarization. This confirms the correlation between the non-volatility of ferroelectric modulation and synaptic weight updating in the artificial synaptic device prepared by this invention, which is consistent with biological synaptic behavior.

[0055] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. An artificial synaptic device based on molybdenum disulfide ink, characterized in that: The device mainly includes a substrate, a channel, a source / drain, a P (VDF-TrFE) ferroelectric film gate dielectric and a gate; wherein the material of the channel is a MoS2 ink film; The device has a top gate structure, that is, the P (VDF-TrFE) ferroelectric thin film gate dielectric is located on the upper surface of the channel, the gate is located on the upper surface of the P (VDF-TrFE) ferroelectric thin film gate dielectric, the source and drain are respectively located on both sides of the channel and in contact with them, and the lower surface of the channel is in contact with the substrate.

2. An artificial synaptic device based on molybdenum disulfide ink according to claim 1, characterized in that: The source / drain are Cr / Au source / drain electrodes, the gate is a pure Au gate electrode, and the substrate is a SiO2 substrate.

3. An artificial synaptic device based on molybdenum disulfide ink according to claim 2, characterized in that: In the Cr / Au source-drain electrode, the thickness of Cr is 10-15 nm, and the thickness of Au is 30-35 nm; The thickness of the P (VDF-TrFE) ferroelectric thin film gate dielectric is 200-300 nm; The thickness of the channel layer is 10-15 nm; The thickness of the gate is 20-30 nm.

4. The method for preparing an artificial synaptic device based on molybdenum disulfide ink according to any one of claims 1 to 3, characterized in that: The following steps are involved: (1) MoS2 nanosheet ink was prepared by electrochemical molecular intercalation stripping method; polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) was dissolved in a solvent to obtain a P(VDF-TrFE) gate dielectric solution; (2) cleaning the substrate and then treating it with oxygen plasma; (3) Spin-coating the MoS2 nanosheet ink on the substrate treated in step (2) for several times to obtain a continuous and uniform nanosheet interconnected film; then, acid-washing and thermally annealing the entire film; and finally, obtaining a semiconductor channel by mask etching; (4) preparing source / drain electrodes to both ends of the channel by spin coating photoresist, UV lithography, development, vacuum metal evaporation and stripping; (5) Spin coating the P(VDF-TrFE) gate dielectric solution on the upper surface of the channel as a P(VDF-TrFE) ferroelectric thin film gate dielectric layer, and performing drying and vacuum thermal annealing; (6) Preparation of gate: The gate is prepared using electrode transfer technology to complete the preparation of the artificial synaptic device.

5. The preparation method according to claim 4, characterized in that: The concentration of the P(VDF-TrFE) gate dielectric solution in step (1) is 4-6 wt%, and its solvent is N,N-dimethylformamide; the peak absorbance of the MoS2 nanosheet ink at 450nm is 0.70, and its solvent is isopropanol; The MoS2 nanosheet ink of step (1) is prepared by the following steps: in an electrolyte solution, blocky molybdenum disulfide crystals and graphite flakes are used as cathode and anode, respectively; an electrochemical workstation is used to apply a voltage of 8-10V to the anode for 1 hour; the expanded MoS2 is ultrasonically dispersed in a PVP / DMF solution, the obtained dispersed solution is centrifuged to remove large blocks and unpeeled blocks, the remaining supernatant is further centrifuged, the obtained sediment is washed with isopropanol, and finally the sediment is dispersed in isopropanol to obtain the MoS2 nanosheet ink.

6. The preparation method according to claim 4, characterized in that: The cleaning in step (2) refers to ultrasonically cleaning the substrate with acetone, isopropanol, and water for 10 to 15 minutes respectively, and blowing the substrate dry with nitrogen; then using oxygen plasma treatment for 10 to 15 minutes to improve the hydrophilicity of the substrate; The specific steps of step (6) are: firstly, a pure Au electrode is evaporated onto a SiO2 substrate, and then the Au electrode is transferred through a polyvinyl butyral film as a top metal electrode.

7. The preparation method according to claim 4, characterized in that: The rotation speed of the spin coating in step (3) is 2000 r / min, and the coating time for each time is 60 s; the acid washing refers to immersing the entire membrane in a 10 mg / mL bis(trifluoromethane)sulfonyl imide 1,2-dichloroethane solution and maintaining it at 80 °C for 1 h; the thermal annealing is carried out under inert gas protection for 1 hour at a temperature of 250~300 °C.

8. The preparation method according to claim 4, characterized in that: In step (5), the spin coating is carried out at a speed of 500 r / min for 10 seconds and then at a speed of 3000 r / min for 60 seconds; The drying step is performed by heating at 80°C for 5-10 min, and the thermal annealing step is performed by annealing at 145°C for 2 h.

9. Use of the artificial synapse device according to any one of claims 1 to 3, characterized in that: The device is used in the fields of neuromorphic computing, low-power electronics and intelligent systems.

10. An artificial synaptic device array, characterized in that: It is made using the artificial synapse device described in any one of claims 1 to 3.

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