Display substrate and display device

Abstract

A display substrate comprises a substrate, a first shielding structure, a frame connecting structure, a plurality of pixel circuits, a plurality of data lines and a plurality of multiplexing circuits. The plurality of pixel circuits and the plurality of data lines are located in a display area, and the plurality of data lines are connected with the plurality of pixel circuits. The plurality of multiplexing circuits are located in a peripheral area and connected with the plurality of data lines. The first shielding structure is located in the display area and on a side of the plurality of pixel circuits close to the substrate. A normal projection of the first shielding structure on the substrate at least partially overlaps with a normal projection of the plurality of pixel circuits on the substrate. The frame connecting structure is located in the peripheral area and is an integral structure with the first shielding structure. The frame connecting structure comprises a first connecting structure located in a frame corner region, and the first connecting structure is located on a side of the plurality of multiplexing circuits in the frame corner region close to the display area and extends in a stepped manner along an edge of the display area.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This application provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a substrate, a first shielding structure disposed on the substrate, a bezel connection structure, multiple pixel circuits, multiple data lines, and multiple multiplexing circuits. The substrate includes a display area and a peripheral area located on at least one side of the display area. The peripheral area includes: at least one first peripheral area extending along a first direction, at least one second peripheral area extending along a second direction, and at least one bezel corner area. The at least one bezel corner area connects between adjacent first and second peripheral areas. The first direction intersects the second direction; for example, the first direction may be perpendicular to the second direction. The multiple pixel circuits and multiple data lines are located in the display area, and the multiple data lines extend along the second direction and are connected to the multiple pixel circuits. The multiple multiplexing circuits are located in the peripheral area and are connected to the multiple data lines. The first shielding structure is located in the display area and on the side of the multiple pixel circuits closest to the substrate. The orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the multiple pixel circuits on the substrate. The bezel connection structure is located in the peripheral area and is integral with the first shielding structure. The bezel connection structure includes: a first connection structure located in the corner area of ​​the bezel, the first connection structure extending in a stepped manner along the edge of the display area, and the first connection structure located on the side of the multiple multiplexed circuits in the corner area of ​​the bezel close to the display area.

[0006] In some exemplary embodiments, the display substrate further includes: a plurality of first signal lines, a plurality of first adapter holes, and a plurality of adapter electrodes. The plurality of first signal lines are located in the display area, extend along the first direction, and are connected to the plurality of pixel circuits. The plurality of first adapter holes and the plurality of adapter electrodes are located in the peripheral area; the plurality of adapter electrodes are connected to the first ends of the plurality of first signal lines extending into the peripheral area through the plurality of first adapter holes. The orthographic projection of the first connection structure onto the substrate does not overlap with the orthographic projection of the plurality of first adapter holes in the bezel corner area onto the substrate.

[0007] In some exemplary embodiments, the first connection structure includes: a plurality of first connecting strips extending along the first direction and a plurality of second connecting strips extending along the second direction, wherein the plurality of first connecting strips and the plurality of second connecting strips are connected at intervals to form a stepped shape.

[0008] In some exemplary embodiments, the first connection structure is located on the side of the multiple first adapter holes in the corner area of ​​the bezel that is away from the display area.

[0009] In some exemplary embodiments, at least one of the plurality of first connecting strips is a straight strip extending along the first direction, and at least one of the plurality of second connecting strips is a straight strip extending along the second direction.

[0010] In some exemplary embodiments, the frame connection structure further includes: a plurality of first auxiliary connecting strips located in the corner area of ​​the frame and extending along the first direction and a plurality of second auxiliary connecting strips extending along the second direction, wherein the plurality of first auxiliary connecting strips and the plurality of second auxiliary connecting strips are located on the side of the first connection structure and the plurality of first transition holes in the corner area of ​​the frame near the display area, and the plurality of first auxiliary connecting strips, the plurality of second auxiliary connecting strips and the first connection structure are connected to form a plurality of first closed areas, each first closed area surrounding at least one of the plurality of first transition holes.

[0011] In some exemplary embodiments, the second connecting strip of the first connecting structure is located on the side of the plurality of first adapter holes in the corner area of ​​the bezel, near the display area. The first connecting strip of the first connecting structure includes a straight segment and a broken line segment extending along the first direction. The broken line segment is located on the side of the plurality of first adapter holes near the display area in the second direction, and the broken line segment bends toward the display area.

[0012] In some exemplary embodiments, the display substrate further includes: a plurality of data leads located in the peripheral region and a plurality of second adapter holes. The plurality of data leads are connected to the plurality of data lines through the plurality of second adapter holes; the orthographic projection of the first connection structure on the substrate and the orthographic projection of the plurality of second adapter holes in the corner area of ​​the bezel on the substrate do not overlap.

[0013] In some exemplary embodiments, the first connection structure is located on the side of the plurality of first adapter holes and the plurality of second adapter holes in the corner area of ​​the frame, near the display area.

[0014] In some exemplary embodiments, the multiplexing circuit includes a plurality of multiplexing control transistors. The display substrate further includes a second shielding structure located in the corner region of the bezel, wherein the orthographic projection of the second shielding structure onto the substrate covers the orthographic projection of the active layer of the plurality of multiplexing control transistors of the multiplexing circuit onto the substrate, and the second shielding structure is integral with the first connection structure.

[0015] In some exemplary embodiments, the bezel connection structure further includes: a second connection structure located in the corner area of ​​the bezel, the second connection structure extending in a stepped manner along the edge of the display area, and the multiple multiplexed circuits located in the corner area of ​​the bezel on the side away from the first connection structure; the second connection structure and the second shielding structure are an integral structure.

[0016] In some exemplary embodiments, the bezel connection structure further includes a third connection structure located in the corner area of ​​the bezel and in a mesh-like form. The third connection structure is located on the side of the multiple multiplexed circuits in the corner area of ​​the bezel that is away from the display area, and is an integral structure with the second blocking structure.

[0017] In some exemplary embodiments, the bezel connection structure further includes a third connection structure located in the corner area of ​​the bezel and in a mesh-like form. The third connection structure is located on the side of the multiple multiplexed circuits in the corner area of ​​the bezel that is away from the display area, and is an integral structure with the first connection structure.

[0018] In some exemplary embodiments, the third connection structure includes: a plurality of third connecting strips extending along the first direction, a plurality of fourth connecting strips extending along the second direction, and a fifth connecting strip, wherein the plurality of third connecting strips and the plurality of fourth connecting strips are connected, and the fifth connecting strip is connected to the end of the plurality of third connecting strips away from the display area, and the fifth connecting strip is located on the side of the plurality of third connecting strips and the plurality of fourth connecting strips away from the display area.

[0019] In some exemplary embodiments, the fifth connecting strip is an arc segment extending along the edge of the display area.

[0020] In some exemplary embodiments, the surrounding area includes: two first surrounding areas, two second surrounding areas, and four corner border areas. The two first surrounding areas include a first border area and a second border area; the two second surrounding areas include a third border area and a fourth border area; the four corner border areas include a first corner border area, a second corner border area, a third corner border area, and a fourth corner border area. The first corner border area is connected between the first border area and the third border area; the second corner border area is connected between the first border area and the fourth border area; the third corner border area is connected between the second border area and the third border area; and the fourth corner border area is connected between the second border area and the fourth border area. The plurality of multiplexing circuits are disposed in the first border area, the first corner border area, and the second corner border area; the first connection structure is located in the first corner border area and the second corner border area.

[0021] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0022] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0026] Figure 3 This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0027] Figure 4 An equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of this disclosure;

[0028] Figure 5 for Figure 1 A magnified view of a portion of the central region S1;

[0029] Figure 6A for Figure 5 A schematic diagram of the bottom shielding metal layer;

[0030] Figure 6B for Figure 5 A schematic diagram of the semiconductor layer in the diagram;

[0031] Figure 6C for Figure 5 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0032] Figure 6D for Figure 5 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0033] Figure 6E for Figure 5 A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer;

[0034] Figure 6F for Figure 5 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0035] Figure 6G for Figure 6F A schematic diagram of the third conductive layer in the diagram;

[0036] Figure 6H for Figure 5 A schematic diagram of the fourth conductive layer in the diagram;

[0037] Figure 7 for Figure 1 Another enlarged view of a portion of the central region S1;

[0038] Figure 8A for Figure 7 A schematic diagram of the bottom shielding metal layer;

[0039] Figure 8B for Figure 7 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0040] Figure 8C for Figure 7 A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer;

[0041] Figure 8D for Figure 7 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0042] Figure 9A for Figure 1 Another enlarged view of a portion of the central region S1;

[0043] Figure 9B for Figure 9A A schematic diagram of the bottom shielding metal layer;

[0044] Figure 9C for Figure 9A A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer;

[0045] Figure 10 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0046] Figure 11A for Figure 10 A magnified view of a portion of the central region S2;

[0047] Figure 11B for Figure 11A A schematic diagram of the bottom shielding metal layer;

[0048] Figure 11C for Figure 11A A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer;

[0049] Figure 12A for Figure 10 Another enlarged view of a portion of the central region S2;

[0050] Figure 12B for Figure 12A A schematic diagram of the bottom shielding metal layer;

[0051] Figure 12C for Figure 12A A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer;

[0052] Figure 13 This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0053] Figure 14A for Figure 1 Another enlarged view of a portion of the central region S1;

[0054] Figure 14B for Figure 14A A schematic diagram of the bottom shielding metal layer, the first semiconductor layer, the second conductive layer, the third conductive layer, and the fifth conductive layer;

[0055] Figure 14C for Figure 14A A schematic diagram of multiple vias formed by the bottom shielding metal layer and the fourth insulating layer;

[0056] Figure 14D for Figure 14A A schematic diagram of the display substrate after the third conductive layer has been formed;

[0057] Figure 15 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0058] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0059] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0060] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0061] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0062] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0063] In this specification, "connection" can include "electrical connection." "Electrical connection" includes situations where components are connected together by elements that have some electrical function. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0064] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0065] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0066] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0067] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0068] In this disclosure, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "same" can include cases where index values ​​differ by no more than 10%.

[0069] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0070] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The phrase "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The phrase "the shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0071] In some implementations, bottom shielding metal (BSM) can be placed in the display area of ​​the display substrate to improve image retention. To maintain voltage uniformity of the bottom shielding metal, a ring-shaped winding is usually placed in the peripheral area, connecting the extension ends of the bottom shielding metal in the display area as a single unit. However, this method requires a lot of peripheral space, which is not conducive to narrow bezel designs. Moreover, to effectively prevent static electricity, the bottom shielding metal is usually connected to the first power signal VDD. The ring-shaped winding located in the peripheral area and transmitting the first power signal VDD is prone to overlapping with other circuits (such as multiplexing circuits) or traces (such as gate drive signal traces), causing problems such as display defects.

[0072] This embodiment provides a display substrate, including: a substrate, a first shielding structure disposed on the substrate, a bezel connection structure, multiple pixel circuits, multiple data lines, and multiple multiplexing circuits. The substrate includes a display area and a peripheral area located on at least one side of the display area. The peripheral area includes: at least one first peripheral area extending along a first direction, at least one second peripheral area extending along a second direction, and at least one bezel corner area. The bezel corner area connects adjacent first and second peripheral areas. The first direction intersects the second direction; for example, the first direction may be perpendicular to the second direction. The multiple pixel circuits and multiple data lines are located in the display area, and the multiple data lines extend along the second direction and are connected to the multiple pixel circuits. The multiple multiplexing circuits are located in the peripheral area and are connected to the multiple data lines. The first shielding structure is located in the display area and on the side of the multiple pixel circuits closest to the substrate. The orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the multiple pixel circuits on the substrate. The bezel connection structure is located in the peripheral area and is integral with the first shielding structure. The bezel connection structure includes: a first connection structure located in the corner area of ​​the bezel, the first connection structure extending in a stepped manner along the edge of the display area, and the first connection structure located on the side of the multiple multiplexed circuits in the corner area of ​​the bezel close to the display area.

[0073] This embodiment optimizes the design of the frame connection structure of the bottom shielding metal layer, so that the first connection structure in the corner area of ​​the frame extends in a stepped manner on the side of the multiplexing circuit near the display area. This can effectively reduce the impact of the frame connection structure on the multiplexing circuit and facilitate the realization of a narrow frame design.

[0074] In some exemplary embodiments, the display substrate may further include: a plurality of first signal lines located in the display area, a plurality of first adapter holes located in the peripheral area, and a plurality of adapter electrodes. The plurality of first signal lines may extend along a first direction and connect to a plurality of pixel circuits. The plurality of adapter electrodes may connect to the first ends of the plurality of first signal lines extending into the peripheral area via the plurality of first adapter holes. The orthographic projection of the first connection structure onto the substrate and the orthographic projection of the plurality of first adapter holes in the bezel corner area onto the substrate may not overlap. In some examples, the first connection structure may be located on the side of the plurality of first adapter holes in the bezel corner area away from the display area. In other examples, the first connection structure may include a plurality of first connecting strips extending along the first direction and a plurality of second connecting strips extending along a second direction, the second connecting strips of the first connection structure being located on the side of the plurality of first adapter holes in the bezel corner area closer to the display area. This example, by designing the first connection structure to avoid the first adapter holes, can reduce the risk of electrostatic discharge (ESD) and avoid defects.

[0075] In some exemplary embodiments, the display substrate may further include a second shielding structure located in the corner region of the bezel. The orthographic projection of the second shielding structure onto the substrate can cover the orthographic projection of the active layer of the multiplexed control transistors of the multiplexed circuit in the corner region onto the substrate. The second shielding structure and the first connection structure can be an integral structure. This example increases the stability of the multiplexed control transistors of the multiplexed circuit by providing a second shielding structure below the multiplexed circuit.

[0076] The following examples illustrate the solution of this embodiment.

[0077] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate of this embodiment may include: a display area AA and a border area BB surrounding the display area AA. The border area BB may include: two first peripheral areas extending along a first direction X (e.g., including a first border area B1 and a second border area B2), two second peripheral areas extending along a second direction Y (e.g., including a third border area B3 and a fourth border area B4), and a plurality of border corner areas connecting adjacent first and second peripheral areas (e.g., including a first border corner area C1, a second border corner area C2, a third border corner area C3, and a fourth border corner area C4). For example, the first border area B1 may be the lower border area of ​​the display substrate, the second border area B2 may be the upper border area of ​​the display substrate, the third border area B3 may be the left border area of ​​the display substrate, and the fourth border area B4 may be the right border area of ​​the display substrate.

[0078] In some examples, the first border corner area C1 connects between the first border area B1 and the third border area B3; the second border corner area C2 connects between the first border area B1 and the fourth border area B4; the third border corner area C3 connects between the third border area B3 and the second border area B2; and the fourth border corner area C4 connects between the second border area B2 and the fourth border area B4. The first border corner area C1, the second border corner area C2, the third border corner area C3, and the fourth border corner area C4 can each correspond to the curved edge of the display area AA. The edges of the first border corner area C1, the second border corner area C2, the third border corner area C3, and the fourth border corner area C4 away from the display area AA can all be curved edges (e.g., arc edges). The first border corner area C1 and the second border corner area C2 can be referred to as the lower corner area, and the third border corner area C3 and the fourth border corner area C4 can be referred to as the upper corner area.

[0079] In some examples, the display area AA can be provided with multiple sub-pixels. At least one sub-pixel can include a pixel circuit and a light-emitting element. The pixel circuit can be configured to drive the connected light-emitting element. The pixel circuit can include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0080] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and a light-emitting functional layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0081] In some examples, a pixel unit of the display area AA may include three light-emitting elements, which may include a light-emitting element emitting a first color light (e.g., red light), a light-emitting element emitting a second color light (e.g., green light), and a light-emitting element emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In other examples, a pixel unit may include four light-emitting elements, which may include a light-emitting element emitting red light, a light-emitting element emitting green light, a light-emitting element emitting blue light, and a light-emitting element emitting white light. For example, a pixel unit may include four light-emitting elements, which may include one light-emitting element emitting red light, one light-emitting element emitting blue light, and two light-emitting elements emitting green light.

[0082] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three light-emitting elements, the three light-emitting elements can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; when a pixel unit includes four light-emitting elements, the four light-emitting elements can be arranged horizontally side by side, vertically side by side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0083] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described using a 7T1C structure as an example. Figure 2 As shown, the pixel circuit in this example includes seven transistors (i.e., transistors T1 to T7) and a storage capacitor Cst. Transistor T1 is also called the first reset transistor, transistor T2 is also called the compensation transistor, transistor T3 is also called the driving transistor, transistor T4 is also called the data writing transistor, transistor T5 is also called the first light-emitting control transistor, transistor T6 is also called the second light-emitting control transistor, and transistor T7 is also called the second reset transistor. The light-emitting element EL may include a first electrode, a second electrode, and a light-emitting functional layer disposed between the first and second electrodes. The first electrode of the light-emitting element EL can be an anode, and the second electrode of the light-emitting element EL can be a cathode.

[0084] In some examples, the seven transistors in the pixel circuit can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide (Oxide). LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0085] In some examples, such as Figure 2As shown, the pixel circuit can be connected to the scan line GL, data line DL, first power line PL1, light emission control line EML, first initial signal line INIT1, second initial signal line INIT2, first reset control line RST1, and second reset control line RST2. The light-emitting element EL can be connected to the pixel circuit and the second power line PL2. The first power line PL1 can be configured to provide a constant first power signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second power signal VSS, where the first power signal VDD is greater than the second power signal VSS. The scan line GL can be configured to provide a scan signal to the pixel circuit, the data line DL can be configured to provide a data signal to the pixel circuit, the light emission control line EML can be configured to provide a light emission control signal to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit. In some examples, the second reset control line RST2 electrically connected to the nth row pixel circuit and the first reset control line RST1 electrically connected to the (n+1)th row pixel circuit can be a single integrated structure. This reduces the number of signal lines on the display substrate, which is beneficial for achieving a narrow bezel design. However, this embodiment is not limited to this.

[0086] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between the first power supply signal VDD and the second power supply signal VSS, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0087] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The gate of the compensation transistor T2 is electrically connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor T5 is electrically connected to the first power line PL1, and the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T3. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3, and the second terminal of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first terminal of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first terminal of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL. The first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0088] In this example, the first node N1 can be the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the compensation transistor T2; the second node N2 can be the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3; the third node N3 can be the connection point of the driving transistor T3, the compensation transistor T2 and the second light-emitting control transistor T6; and the fourth node N4 can be the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0089] Figure 3 This is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 3 The structure of a sub-pixel in the display area is illustrated as an example. Figure 3 The illustration takes an example where each sub-pixel's pixel circuit includes a first-type transistor 16 and a capacitor 17. The first-type transistor 16 can be a low-temperature polycrystalline silicon thin-film transistor. For example, the first-type transistor 16 can be... Figure 2 The sixth transistor T6 or the seventh transistor T7 in the pixel circuit shown, and capacitor 17 can be... Figure 2 The storage capacitor Cst of the pixel circuit shown.

[0090] In some examples, such as Figure 3 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 100, and a circuit structure layer 120, a light-emitting structure layer 130, and an encapsulation structure layer 140 sequentially disposed on the substrate 100. The circuit structure layer 120 of the display area may include pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 130 of the display area may include light-emitting elements for multiple sub-pixels. In some other examples, a touch structure layer may be disposed on the side of the encapsulation structure layer away from the substrate 100 to integrate touch functionality.

[0091] In some examples, the circuit structure layer 120 of the display substrate may include: a bottom shielding metal layer 200, a first semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source / drain metal layer) and a fourth conductive layer (also referred to as a second source / drain metal layer) disposed on the substrate 100. A first insulating layer (also called a buffer layer) 101 may be disposed between the bottom shielding metal layer 200 and the first semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be disposed between the first semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be disposed between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, wherein the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; and a seventh insulating layer (also called a second planarization layer) 107 may be disposed on the side of the fourth conductive layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be inorganic insulating layers, while the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, the fifth insulating layer may be omitted between the third and fourth conductive layers, and only the sixth insulating layer may be provided between the third and fourth conductive layers.

[0092] In some examples, the substrate 100 can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0093] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The material of the first semiconductor layer may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0094] In some examples, such as Figure 3 As shown, the first semiconductor layer of the display area may include an active layer 160 of a first type transistor 16 of the pixel circuit. The active layer 160 of the first type transistor 16 may include a first region 1601, a second region 1602, and a channel region 1600 located between the first region 1601 and the second region 1602. The first conductive layer may include a first gate 163 of the first type transistor 16 and a first electrode 171 of the capacitor 17. The orthographic projection of the first gate 163 of the first type transistor 16 onto the substrate 100 may cover the orthographic projection of the channel region 1600 of the active layer 160 onto the substrate 100. The second conductive layer may include a second electrode 172 of the capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of the capacitor 17 onto the substrate 100 may at least partially overlap, for example, they may coincide.

[0095] In some examples, such as Figure 3 As shown, the third conductive layer of the display area may include a first source 161 and a first drain 162 of a first type transistor 16. The first source 161 of the first type transistor 16 may be electrically connected to the first region 1601 of the active layer 160, and the first drain 162 may be electrically connected to the second region 1602 of the first active layer 160. The fourth conductive layer may include an anode transition electrode 181. The anode transition electrode 181 may be electrically connected to the first drain 162 of the transistor 16 of the pixel circuit through vias formed in the fifth insulating layer 105 and the sixth insulating layer 106. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the anode transition electrode 181.

[0096] In some examples, such as Figure 3As shown, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, a light-emitting functional layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on a seventh insulating layer 107 and electrically connected to an anode transfer electrode 181 through a via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the light-emitting functional layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the light-emitting functional layer 132 and connected to the light-emitting functional layer 132. The light-emitting functional layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0097] In some examples, the light-emitting functional layer 132 of the light-emitting element may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0098] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side of the light-emitting layer. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the light-emitting functional layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0099] In some examples, such as Figure 3 As shown, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0100] Figure 4 This is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 4 The example shown is a multiplexing circuit with a 1:4 design. In some examples, such as... Figure 4As shown, a multiplexing circuit MUX can be electrically connected to four multiplexing control lines (e.g., including first multiplexing control lines ML1 to fourth multiplexing control lines ML4), one multiplexing data line SL, and multiple data lines (e.g., including first data lines DL1 to fourth data lines DL4). The multiplexing circuit MUX can include four multiplexing control transistors (i.e., first multiplexing control transistor M1 to fourth multiplexing control transistor M4). The gates of the four multiplexing control transistors can be connected to different multiplexing control lines respectively; that is, the gate of the first multiplexing control transistor M1 is connected to the first multiplexing control line ML1, the gate of the second multiplexing control transistor M2 is connected to the second multiplexing control line ML2, the gate of the third multiplexing control transistor M3 is connected to the third multiplexing control line ML3, and the gate of the fourth multiplexing control transistor M4 is connected to the fourth multiplexing control line ML4.

[0101] In some examples, the first terminals of the four multiplexing control transistors of a multiplexing circuit can all be connected to the same multiplexed data line SL. The second terminals of the four multiplexing control transistors are respectively connected to different data lines in the display area. For example, the second terminal of the first multiplexing control transistor M1 is connected to the first data line DL1, the second terminal of the second multiplexing control transistor M2 is connected to the second data line DL2, the second terminal of the third multiplexing control transistor M3 is connected to the third data line DL3, and the second terminal of the fourth multiplexing control transistor M4 is connected to the fourth data line DL4. Each data line can be connected to at least one column of pixel circuits in the display area. A column of pixel circuits can include multiple pixel circuits arranged along a second direction. The four multiplexing control lines can control multiple multiplexing circuits MUX to provide data signals to the corresponding column of pixel circuits in the display area.

[0102] In some examples, such as Figure 1 As shown, the bottom shielding metal layer may include: a first shielding structure located in the display area AA, and a frame connection structure 21 located in the peripheral area BB. The frame connection structure 21 may be connected to the portion of the first shielding structure extending into the peripheral area BB, thereby improving the static electricity problem present in the first shielding structure. The frame connection structure 21 may include: a first connection structure 211 located in the first frame corner area C1 and the second frame corner area C2, a first frame trace 221 located in the first frame area B1, a second frame trace 222 located in the second frame area B2, a third frame trace 223 located in the third frame area B3, a fourth frame trace 224 located in the fourth frame area B4, a fifth frame trace 225 located in the third frame corner area C3, and a sixth frame trace 226 located in the fourth frame corner area C4.

[0103] In some examples, the first connection structure 211 located in the first bezel corner area C1 can connect the first bezel trace 221 and the third bezel trace 223, and the first connection structure 211 located in the first bezel corner area C2 can connect the first bezel trace 221 and the fourth bezel trace 224. The third bezel trace 223, the fifth bezel trace 225, the second bezel trace 222, the sixth bezel trace 226, and the fourth bezel trace 224 can be connected sequentially. The first bezel trace 221 and the second bezel trace 222 can be strips extending along the first direction X, and the third bezel trace 223 and the fourth bezel trace 224 can be strips extending along the second direction Y. The fifth bezel trace 225 and the sixth bezel trace 226 can be arc-shaped traces extending along the edge of the display area AA.

[0104] In some examples, the first connecting structure 211 located in the first bezel corner area C1 and the second bezel corner area C2 can extend in a stepped shape along the edge of the display area AA. In this example, by using a stepped design for the first connecting structure 211 in the lower corner area, it is beneficial to compress the wiring space in the surrounding area BB, thereby facilitating the implementation of a narrow bezel design.

[0105] Figure 5 for Figure 1 A magnified view of a portion of the central region S1. Figure 5 The main schematic diagram shows the circuit structure layer of region S1. Figure 6A for Figure 5 A schematic diagram of the bottom shielding metal layer. In some examples, such as... Figure 5 and Figure 6AAs shown, the bottom shielding metal layer of the display substrate may include a first shielding structure 31 located in the display area AA. The first shielding structure 31 may include a plurality of first shielding blocks 310, a plurality of first extension strips 311, and a plurality of second extension strips 312. The plurality of first extension strips 311 may extend along a first direction X, and the plurality of second extension strips 312 may extend along a second direction Y. Adjacent first shielding blocks 310 along the first direction X may be connected by the first extension strips 311, and adjacent first shielding blocks 310 along the second direction Y may be connected by the second extension strips 312. The first extension strips 311 may extend to connect with the third frame trace 223 of the third frame area B3, or may extend to connect with the fourth frame trace 224 of the fourth frame area B4, or may extend to connect with the fifth frame trace 225 of the third frame corner area C3, or may extend to connect with the sixth frame trace 226 of the fourth frame corner area C4. The second extension strip 312 can extend to connect with the first border trace 221 of the first border area B1, or it can extend to connect with the second border trace 222 of the second border area B2, or it can extend to connect with the first connection structure 211 at the first border corner area C1 or the second border corner area C2. The orthographic projection of a first blocking block 310 on the substrate can overlap with the orthographic projection of the active layer of at least one transistor of a pixel circuit on the substrate. For example, as... Figure 6C As shown, the orthographic projection of the first blocking block 310 onto the substrate can cover the orthographic projection of the channel region of the active layer T30 of the third transistor T3 of the pixel circuit onto the substrate.

[0106] In some examples, such as Figure 6A As shown, the first connection structure 211 of the first border corner area C1 may include: a plurality of first connecting strips 2111 and a plurality of second connecting strips 2112. The plurality of first connecting strips 2111 may extend along a first direction X, and the plurality of second connecting strips 2112 may extend along a second direction Y. The plurality of first connecting strips 2111 and the plurality of second connecting strips 2112 may be connected at intervals to form a stepped shape. A step formed by connecting one first connecting strip 2111 and one second connecting strip 2112 of the first connection structure 211 may be aligned with a row of pixel circuits in the display area AA.

[0107] In some examples, such as Figure 6A As shown, the frame connection structure 21 may further include: a plurality of first auxiliary connecting strips 231 and a plurality of second auxiliary connecting strips 232 located in the first frame corner area C1. The plurality of first auxiliary connecting strips 231 may extend along a first direction X, and the plurality of second auxiliary connecting strips 232 may extend along a second direction Y. The plurality of first auxiliary connecting strips 231 and the plurality of second auxiliary connecting strips 232 may be located on the side of the first connection structure 211 closer to the display area AA.

[0108] In some examples, such as Figure 6A As shown, the first auxiliary connecting strip 231 can be located along the first direction X on the side of a first connecting strip 2111 near the display area AA, and is connected to the first connecting strip 2111. The second auxiliary connecting strip 232 can be located along the first direction X on the side of a second connecting strip 2112 near the display area AA. One end of the second auxiliary connecting strip 232 can be connected to the first auxiliary connecting strip 231, and the other end can be connected to another first connecting strip 2111. A second connecting strip 2112, a first auxiliary connecting strip 231, a second auxiliary connecting strip 232, and a first connecting strip 2111 can be connected to form a first closed area K1, which can be approximately rectangular.

[0109] In some examples, such as Figure 6A As shown, the line width L3 of the first auxiliary connecting strip 231 can be smaller than the line width L1 of the first connecting strip 2111, and the line width L4 of the second auxiliary connecting strip 232 can be smaller than the line width L2 of the second connecting strip 2112. The line width L3 of the first auxiliary connecting strip 231 and the line width L4 of the second auxiliary connecting strip 232 can be approximately the same; the line width L1 of the first connecting strip 2111 and the line width L2 of the second connecting strip 2112 can be approximately the same.

[0110] Figure 6B for Figure 5 A schematic diagram of the first semiconductor layer. In some examples, such as... Figure 6B As shown, the first semiconductor layer of the display substrate may include: an active layer of multiple transistors of multiple pixel circuits located in the display area AA (e.g., an active layer T10 including the first transistor T1 to the seventh transistor T7 active layer T70), and an active layer of multiple multiplexing control transistors of multiple multiplexing circuits located in the first frame corner area C1 (e.g., an active layer M10a and M10b including the first multiplexing control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, and the fourth multiplexing control transistor M4).

[0111] In some examples, such as Figure 6BAs shown, the active layers T10 of the first transistor, T20 of the second transistor, T30 of the third transistor, T40 of the fourth transistor, T50 of the fifth transistor, T60 of the sixth transistor, and T70 of the seventh transistor in a single pixel circuit can be an integral structure. The second region of the active layer T10 of the first transistor is connected to the second region of the active layer T20 of the second transistor. The first regions of the active layers T20, T30, and T60 of the sixth transistor are connected. The first regions of the active layers T30, T40, and T50 of the fifth transistor are connected. The second region of the active layer T60 of the sixth transistor is connected to the second region of the active layer T70 of the seventh transistor. The first region of the active layer T10 of the first transistor, the first region of the active layer T70 of the seventh transistor, the first region of the active layer T50 of the fifth transistor, and the first region of the active layer T40 of the fourth transistor can be set independently.

[0112] In some examples, such as Figure 6B As shown, the orthographic projections of the active layers T10 and T30 of the first and third transistors onto the substrate can be approximately n-shaped, the orthographic projections of the active layers T20 and T60 of the second and sixth transistors onto the substrate can be approximately L-shaped, and the orthographic projections of the active layers T40, T50, and T70 of the fourth, fifth, and seventh transistors onto the substrate can be approximately I-shaped. This embodiment is not limited in this respect.

[0113] In some examples, such as Figure 6B As shown, the active layer M10a of the first multiplexing control transistor and the active layer M20a of the second reset control transistor in a single multiplexing circuit can be an integral structure; the active layer M10b of the first multiplexing control transistor and the active layer M20b of the second reset control transistor can be an integral structure; the active layer M30a of the third multiplexing control transistor and the active layer M40a of the fourth reset control transistor can be an integral structure; and the active layer M30b of the third multiplexing control transistor and the active layer M40b of the fourth reset control transistor can be an integral structure. The integrated structure of the active layer M10a of the first multiplexing control transistor and the active layer M20a of the second reset control transistor, the integrated structure of the active layer M10b of the first multiplexing control transistor and the active layer M20b of the second reset control transistor, the integrated structure of the active layer M30a of the third multiplexing control transistor and the active layer M40a of the fourth reset control transistor, and the integrated structure of the active layer M30b of the third multiplexing control transistor and the active layer M40b of the fourth reset control transistor can be a rectangle when projected onto the substrate, and arranged in two rows and two columns.

[0114] Figure 6C for Figure 5 A schematic diagram of a display substrate after the first conductive layer has been formed. In some examples, such as... Figure 6C As shown, the first conductive layer of the display substrate may include: multiple gate signal lines (e.g., including first reset control lines RST1(n), RST1(n+1), RST1(n+2), scan lines GL(n), GL(n+1), light emission control lines EML(n), EML(n+1)) located in the display area AA and extending along the first direction X, gates of multiple transistors of multiple pixel circuits (e.g., including the first gate T21 of the second transistor T2) and the first plate of the storage capacitor (e.g., the first plate Cst-1); gates of multiple multiplexing control transistors of multiple multiplexing circuits located in the first frame corner area C1 (e.g., the gate M11 of the first multiplexing control transistor M1, the gate M21 of the second multiplexing control transistor M2, the gate M31 of the third multiplexing control transistor M3, and the gate M41 of the fourth multiplexing control transistor M4), and a first power supply adapter line 511.

[0115] In some examples, such as Figure 6C As shown, the scan line GL(n) can be located in the second direction Y between the first reset control line RST1(n) and the light emission control line EML(n). The overlapping portion of the scan line GL(n) with the active layer T20 of the second transistor of the same row pixel circuit can serve as the second gate of the second transistor T2. The scan line GL(n) and the first gate T21 of the second transistor T2 of the same row pixel circuit can be an integral structure. The overlapping portion of the scan line GL(n) with the active layer T40 of the fourth transistor T4 of the same row pixel circuit can serve as the gate of the fourth transistor T4.

[0116] In some examples, such as Figure 6C As shown, the orthographic projection of the first plate Cst-1 of the storage capacitor onto the substrate can be approximately rectangular. The first plate Cst-1 of the storage capacitor can also serve as the gate of the third transistor T3. The orthographic projection of the first plate Cst-1 of the storage capacitor onto the substrate can be located within the orthographic projection range of the first blocking block 310 of the first blocking structure 31 onto the substrate.

[0117] In some examples, such as Figure 6C As shown, the overlapping portion of the light emission control line EML(n) with the active layer of the fifth transistor of the same row pixel circuit can serve as the gate of the fifth transistor T5, and the overlapping portion of the light emission control line EML(n) with the active layer of the sixth transistor of the same row pixel circuit can serve as the gate of the sixth transistor T6.

[0118] In some examples, such as Figure 6CAs shown, the first reset control line RST1(n) can also serve as the second reset control line connected to the previous row of pixel circuits. The overlapping portion of the first reset control line RST1(n) with the active layer T10 of the first transistor in the current row of pixel circuits can serve as the gate of the first transistor T1, and the overlapping portion of the first reset control line RST1(n) with the active layer T70 of the seventh transistor in the previous row of pixel circuits can serve as the gate of the seventh transistor.

[0119] In some examples, such as Figure 6C As shown, the scan line GL(n) may have a first end 401 extending to the first border corner region C1; the light emission control line EML(n) may have a first end 402 extending to the first border corner region C1; and the first reset control line RST1(n+1) may have a first end 403 extending to the first border corner region C1. The orthographic projection of the plurality of first ends 401, 402, and 403 onto the substrate may be located within the first closed region K1 formed by the connection of the first connecting structure 211, the first auxiliary connecting strip 231, and the second auxiliary connecting strip 232.

[0120] In some examples, such as Figure 6C As shown, the gates M11 of the first multiplexing control transistor M1, M21 of the second multiplexing control transistor M2, M31 of the third multiplexing control transistor M3, and M41 of the fourth multiplexing control transistor M4 can be arranged sequentially along the first direction X, and all extend along the second direction Y. The first reset control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, and the fourth multiplexing control transistor M4 can be arranged along the first direction and located on the side of the first connection structure 211 away from the display area AA. The first connecting strip 2111 of the first connection structure 211 can be adjacent to a multiplexing circuit in the second direction Y, and the second connecting strip 2112 can be adjacent to a multiplexing circuit in the first direction X. The first reset control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, and the fourth multiplexing control transistor M4 can be arranged sequentially in the first direction X towards the second connecting strip 2112.

[0121] In some examples, such as Figure 6C As shown, the first power adapter cable 511 can extend along the second direction Y and is located between two adjacent multiplexed circuits along the first direction X. One end of the first power adapter cable 511 can extend into the first enclosed area K1. The first power adapter cable 511 can be configured to transmit a first power signal.

[0122] Figure 6D for Figure 5 A schematic diagram of a display substrate after the second conductive layer has been formed. In some examples, such as... Figure 6DAs shown, the second conductive layer of the display substrate may include: multiple initial signal lines located in the display area AA (e.g., including first initial signal lines INIT1(n), INIT1(n+1), second initial signal lines INIT2(n-1), INIT2(n), INIT2(n+1)), second plates Cst-2 of storage capacitors of multiple pixel circuits, and multiple auxiliary blocking blocks 191; and multiplexed data lines SL located in the first frame corner area C1.

[0123] In some examples, the orthographic projection of the auxiliary blocking block 191 onto the substrate may partially overlap with the orthographic projection of the active layer T20 of the second transistor T2 of the pixel circuit onto the substrate. For example, the active layer T20 of the second transistor T2 may include a first channel region, a second channel region, and a channel connection region connecting the first channel region and the second channel region. The first channel region overlaps with the first gate T21 of the second transistor T2, and the second channel region overlaps with the second gate of the second transistor T2. The orthographic projection of the auxiliary blocking block 191 onto the substrate and the orthographic projection of the channel connection region of the active layer T20 of the second transistor T2 onto the substrate may at least partially overlap. For example, the orthographic projection of the auxiliary blocking block 191 onto the substrate may cover the orthographic projection of the channel connection region of the active layer T20 of the second transistor T2 onto the substrate.

[0124] In some examples, the orthographic projection of the second plate Cst-2 of the storage capacitor onto the substrate may overlap with the orthographic projection of the first plate Cst-1 onto the substrate. The second plate Cst-2 may have a cutout portion, the orthographic projection of which may fall within the orthographic projection range of the first plate Cst-1 onto the substrate. The second plate Cst-2 of the storage capacitor in the same row of pixel circuits may be a single, integrated structure, enabling the transmission of the first power signal along the first direction X.

[0125] In some examples, the first initial signal line INIT1(n) and the second initial signal line INIT2(n) can be approximately straight lines extending along the first direction X. The orthographic projection of the first initial signal line INIT1(n) onto the substrate can be located on the side of the orthographic projection of the second initial signal line INIT2(n) onto the substrate closer to the third transistor T3.

[0126] In some examples, the first initial signal line INIT1(n) may have a first end 404 extending to the first border corner region C1, and the second initial signal line INIT2(n) may have a first end 405 extending to the first border corner region C1. The orthographic projections of the first ends 404 and 405 onto the substrate may lie within a first enclosed region K1 formed by the connection of the first connecting structure 211, the first auxiliary connecting strip 231, and the second auxiliary connecting strip 232. The first ends 401, 402, 404, 405, and 403 may be arranged sequentially along the second direction Y.

[0127] In some examples, the multiplexed data line SL can be located along the second direction Y on the side of the multiplexing circuit away from the display area AA. The multiplexed data line SL can extend along the second direction Y, for example, it can extend to the first border area B1.

[0128] Figure 6E for Figure 5 A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer. In some examples, such as... Figure 6E As shown, the fourth insulating layer may have multiple vias, such as multiple vias located in the display area AA and multiple vias located in the first bezel corner area C1 (e.g., vias V1 to V21). The orthographic projections of the multiple vias in the first bezel corner area C1 onto the substrate may not overlap with the orthographic projections of the first connecting structure 211, the first auxiliary connecting strip 231, and the second auxiliary connecting strip 232 onto the substrate. The first vias V1 to V6 may be located within the first closed area K1. In this example, the multiple first signal lines may include multiple gate signal lines and multiple initial signal lines, and the multiple first adapter holes may include the first vias V1 to V6.

[0129] Figure 6F for Figure 5 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 6G for Figure 6F A schematic diagram of the third conductive layer. In some examples, such as... Figure 6F and Figure 6G As shown, the third conductive layer of the display substrate may include: multiple pixel connection electrodes (e.g., first pixel connection electrode 441 to fourth pixel connection electrode 444) located in the display area AA, multiple first DC signal lines 451, and multiple first power lines PL1; a second power connection line 512 located in the first bezel corner area C1, multiple adapter electrodes (e.g., first adapter electrode 411 to fifth adapter electrode 415), multiple multiplexed connection electrodes (e.g., first multiplexed connection electrode 461 to sixth multiplexed connection electrode 466), and a bezel DC transmission line 452.

[0130] In some examples, the first pixel connection electrode 441 can be connected to the first region of the active layer T10 of the first transistor T1 in the pixel circuit, and also to the first initial signal line (e.g., the first initial signal line INIT1(n-1)). The second pixel connection electrode 442 can be connected to the second region of the active layer T20 of the second transistor T2 in the pixel circuit and the gate of the third transistor T3. The third pixel connection electrode 443 can be connected to the second region of the active layer T60 of the sixth transistor T6. The fourth pixel connection electrode 444 can be connected to the first region of the active layer T70 of the seventh transistor T7 and the second initial signal line INIT2(n).

[0131] In some examples, the first power line PL1 can be a straight line extending along the second direction Y. The first power line PL1 can be connected to the first region of the active layer T50 of the fifth transistor T5 of the pixel circuit, and also to the second plate Cst-2 of the storage capacitor. The first power line PL1 can extend to the first bezel corner region C1 and connect to the second power connection line 512. The first power line PL1 and the connected second power connection line 512 can be an integral structure. The second power connection line 512 can be a straight line extending along the first direction X. The end of the second power connection line 512 away from the display area AA can be connected to the first power connection line 511 through the sixth via V6. The first power connection line 511 can extend to the first bezel region B1 and connect to the bezel power line within the first bezel region B1, thereby realizing the transmission of the first power signal VDD.

[0132] In some examples, the first DC signal line 451 can be a zigzag line extending along the second direction Y. A first DC signal line 451 can be provided between adjacent first power lines PL1. The frame DC transmission line 452 of the first frame corner area C1 can extend in a stepped manner along the edge of the display area AA. The orthographic projection of the frame DC transmission line 452 on the substrate can at least partially overlap with the orthographic projection of the first connection structure 211 on the substrate. For example, the orthographic projection of the frame DC transmission line 452 on the substrate can cover the orthographic projection of the first connection structure 211 on the substrate. The frame DC transmission line 452 and the first DC signal line 451 can be connected by a DC signal adapter 453 located on the fourth conductive layer, thereby realizing the transmission of DC signals (e.g., the first initial signal or the second initial signal) along the second direction Y within the display area AA.

[0133] In some examples, the first multiplexing connection electrode 461 may extend along the second direction Y. The first multiplexing connection electrode 461 may be connected to the second region of the active layer M10a of the first multiplexing control transistor M1 via a plurality of seventh vias V7 arranged along the second direction Y, and may also be connected to the second region of the active layer M10b of the first multiplexing control transistor M1 via a plurality of eighth vias V8 arranged along the second direction Y. The first multiplexing connection electrode 461 may serve as the second electrode of the first multiplexing control transistor M1.

[0134] In some examples, the second multiplexing connection electrode 462 and the fifth multiplexing connection electrode 465 can be an integral structure. The second multiplexing connection electrode 462 can be connected to the first region of the active layer M10a of the first multiplexing control transistor M1 through multiple ninth vias V9 arranged along the second direction Y, and can also be connected to the first region of the active layer M10b of the first multiplexing control transistor M1 through multiple tenth vias V10 arranged along the second direction Y; the fifth multiplexing connection electrode 465 can be connected to the first region of the active layer M30a of the third multiplexing control transistor M3 through multiple fifteenth vias V15 arranged along the second direction Y, and can also be connected to the first region of the active layer M30b of the third multiplexing control transistor M3 through multiple sixteenth vias V16 arranged along the second direction Y; the integral structure of the second multiplexing connection electrode 462 and the fifth multiplexing connection electrode 465 can also be connected to the multiplexed data line SL through the nineteenth via V19. The second multiplexing connection electrode 462 can serve as the first electrode of the first multiplexing control transistor M1 and the first electrode of the second multiplexing control transistor M2, and the fifth multiplexing connection electrode 465 can serve as the first electrode of the third multiplexing control transistor M3 and the first electrode of the fourth multiplexing control transistor M4.

[0135] In some examples, the third multiplexing connection electrode 463 can extend along the second direction Y. The third multiplexing connection electrode 463 can be connected to the second region of the active layer M20a of the second multiplexing control transistor M2 through multiple eleventh vias V11 arranged along the second direction Y, and can also be connected to the second region of the active layer M20b of the second multiplexing control transistor M2 through multiple twelfth vias V12 arranged along the second direction Y. The third multiplexing connection electrode 463 can serve as the second electrode of the second multiplexing control transistor M2.

[0136] In some examples, the fourth multiplexed connection electrode 464 can extend along the second direction Y. The fourth multiplexed connection electrode 464 can be connected to the second region of the active layer M30a of the third multiplexed control transistor M3 through multiple thirteenth vias V13 arranged along the second direction Y, and can also be connected to the second region of the active layer M30b of the third multiplexed control transistor M3 through multiple fourteenth vias V14 arranged along the second direction Y. The fourth multiplexed connection electrode 464 can serve as the second electrode of the third multiplexed control transistor M3.

[0137] In some examples, the sixth multiplexed connection electrode 466 can extend along the second direction Y. The sixth multiplexed connection electrode 466 can be connected to the second region of the active layer M40a of the fourth multiplexed control transistor M4 through multiple seventeenth vias V17 arranged along the second direction Y, and can also be connected to the second region of the active layer M40b of the fourth multiplexed control transistor M4 through multiple eighteenth vias V18 arranged along the second direction Y. The sixth multiplexed connection electrode 466 can serve as the second electrode of the fourth multiplexed control transistor.

[0138] In some examples, the first multiplexed control line ML1 can be connected to the gate M11 of the first multiplexed control transistor M1 through the twentieth via V20. The third multiplexed control line ML3 can be connected to the gate M31 of the third multiplexed control transistor M3 through the twenty-first via V21.

[0139] In some examples, the orthographic projection of the first to fifth adapter electrodes 411 onto the substrate can be approximately a strip extending along the first direction X. The orthographic projection of the first to fifth adapter electrodes 411 onto the substrate can be located within a first enclosed region K1. The first adapter electrode 411 can be connected to the first end 401 of the scan line GL(n) via a first via V1. The second adapter electrode 412 can be connected to the first end 402 of the light emission control line EML(n) via a second via V2. The third adapter electrode 413 can be connected to the first initial signal line INIT1(n) via a third via V3. The fourth connecting electrode 414 can be connected to the second initial signal line INIT2(n) via a fourth via V4. The fifth connecting electrode 415 can be connected to the first reset control line RST1(n+1) via a fifth via V5.

[0140] Figure 6H for Figure 5 A schematic diagram of the fourth conductive layer. In some examples, such as... Figure 5 and Figure 6H As shown, the fourth conductive layer of the display substrate may include: multiple data lines (e.g., data lines DL1, DL2, DL3 and DL4) and multiple first power auxiliary lines 513 located in the display area AA, and multiple anode connection electrodes 181; multiple signal conversion lines (e.g., first signal conversion line 421 to fifth signal conversion line 425) located in the first frame corner area C1, and DC signal conversion line 453.

[0141] In some examples, one end of the DC signal adapter cable 453 can be connected to the frame DC transmission line 452, and the other end can be connected to the first DC signal line 451, so as to realize the transmission of DC signals (such as the first initial signal or the second initial signal line) in the display area AA along the second direction Y.

[0142] In some examples, the first power auxiliary line 513 can be connected to the first power line PL1, so that the first power signal VDD can be transmitted through double-layer traces in the display area AA, which helps to reduce transmission impedance.

[0143] In some examples, data line DL1 can be connected to the second terminal of the first multiplexed control transistor M1. Data line DL2 can be connected to the second terminal of the second multiplexed control transistor M2. Data line DL3 can be connected to the second terminal of the third multiplexed control transistor M3, and data line DL4 can be connected to the second terminal of the fourth multiplexed control transistor M4.

[0144] In some examples, the first signal adapter 421 can be connected to the first adapter electrode 411, the second signal adapter 422 can be connected to the second adapter electrode 412, the third signal adapter 423 can be connected to the third adapter electrode 413, the fourth signal adapter 424 can be connected to the fourth adapter electrode 414, and the fifth signal adapter 425 can be connected to the fifth adapter electrode 415. The first signal adapter 421, the second signal adapter 422, and the fifth signal adapter 425 can be connected to the corresponding gate drive circuits within the third frame region B3 to enable the first signal adapter 421 to transmit a scan signal, the second signal adapter 422 to transmit a light emission control signal, and the fifth signal adapter 425 to transmit a first reset control signal. The third signal adapter 423 and the fourth signal adapter 424 can be connected to the initial frame line within the third frame region B3 to enable the third signal adapter 423 to transmit a first initial signal and the fourth signal adapter 424 to transmit a second initial signal.

[0145] In this example, in the first bezel corner area C1 and the second bezel corner area C2 of the display substrate, the first connection structure 211 can adopt a stepped design, and the wiring is on the side of the multiplexer circuit MUX near the display area AA, avoiding multiple first transition vias and vias in the fourth insulating layer of the multiplexer circuit MUX. In this way, the surrounding space can be compressed without compressing the device size, thereby achieving the purpose of a narrow bezel. Moreover, by avoiding the vias in the fourth insulating layer, the risk of electrostatic discharge caused by the overlap between the bottom shielding metal layer and the vias in the fourth insulating layer can be reduced, thus avoiding defects.

[0146] Figure 7 for Figure 1 Another enlarged schematic diagram of a portion of the central region S1. Figure 8A for Figure 7 A schematic diagram of the bottom shielding metal layer. Figure 8B for Figure 7 A schematic diagram of the display substrate after the second conductive layer has been formed. Figure 8C for Figure 7A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer. Figure 8D for Figure 7 A schematic diagram of the display substrate after the third conductive layer has been formed.

[0147] In some examples, such as Figures 7 to 8D As shown, the frame connection structure 21 of the bottom shielding metal layer may include a first connection structure 211 located in the first frame corner area C1. The first connection structure 211 may include: a plurality of first connecting strips 2111 extending along a first direction X, and a plurality of second connecting strips 2112 extending along a second direction Y. The plurality of first connecting strips 2111 and the plurality of second connecting strips 2112 may be connected at intervals to form a stepped shape. The first connecting strip 2111 may include: a straight line segment 2111-1 and a broken line segment 2111-2 extending along the first direction X. The broken line segment 2111-2 may be located on the side of the straight line segment 2111-1 near the display area AA in the first direction X. The broken line segment 2111-2 may be located on the side of the plurality of first transition vias (e.g., including the first via V1 to the sixth via V6) near the display area AA in the second direction Y. The broken line segment 2111-2 may be bent towards the side near the display area AA in the second direction Y to avoid the plurality of first transition vias.

[0148] In some examples, the second connecting strip 2112 may be located on the side of the plurality of first transition vias (e.g., including first vias V1 to sixth vias V6) near the display area AA. The second connecting strip 2112 may be directly connected to the first extension 311 of the first shielding structure 31.

[0149] Compared to Figure 5 In the illustrated embodiment, by designing the first connecting strip 2111 of the first connecting structure 211 to be bent along the second direction Y, the first auxiliary connecting strip and the second auxiliary connecting strip can be omitted, thereby saving more border space. Further descriptions of this embodiment can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0150] Figure 9A for Figure 1 Another enlarged schematic diagram of a portion of the central region S1. Figure 9A The diagram mainly illustrates the bottom shielding metal layer, the first semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer. Figure 9B for Figure 9A A schematic diagram of the bottom shielding metal layer. Figure 9C for Figure 9A A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer.

[0151] In some examples, such as Figures 9A to 9CAs shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA, a second shielding structure 32 located in the first bezel corner area C1, a first connecting structure 211, a second connecting structure 212, a plurality of first auxiliary connecting strips 231, and a plurality of second auxiliary connecting strips 232. The first connecting structure 211 may include: a first connecting strip 2111 extending along a first direction X and a second connecting strip 2112 extending along a second direction Y. A step formed by connecting one first connecting strip 2111 and one second connecting strip 2112 can be aligned with the three rows of pixel circuits. In other words, the length of the second connecting strip 2112 along the second direction Y can be approximately the same as the length of the three rows of pixel circuits along the second direction Y.

[0152] In some examples, the first connecting structure 211, multiple first auxiliary connecting strips 231, and second auxiliary connecting strips 232 can be connected to form multiple first closed regions K1. Each first closed region K1 can correspond to a row of pixel circuits.

[0153] In some examples, the second blocking structure 32 may include multiple second blocking blocks 320. The orthographic projection of a single second blocking block 320 onto the substrate may be rectangular. The orthographic projection of a single second blocking block 320 onto the substrate may cover the orthographic projection of the active layer of the four multiplexed control transistors of a single multiplexed circuit MUX onto the substrate. The second blocking block 320 may be located on the side of the second connecting strip 2112 of the first connecting structure 211 away from the display area AA. The second blocking block 320 may be directly connected to the second connecting strip 2112.

[0154] In some examples, the second connecting structure 212 may extend in a stepped manner along the edge of the display area AA. The second connecting structure 212 may include: a plurality of sixth connecting strips 2121 extending along a first direction X and a plurality of seventh connecting strips 2122 extending along a second direction Y. The sixth connecting strips 2121 may be located on the side of the second blocking block 320 away from the display area AA in the second direction Y. The sixth connecting strips 2121 may be aligned with a first auxiliary connecting strip 231 along the first direction X. The seventh connecting strips 2122 may be located on the side of the second blocking block 320 away from the display area AA in the first direction X. The seventh connecting strips 2122, the second blocking block 320, and the second connecting strips 2122 may be directly connected as a single unit.

[0155] In some examples, the first connecting structure 211 and the second connecting structure 212 can be connected to form multiple second enclosed regions K2. A second blocking block 320 can be located within a second enclosed region K2 and directly connected to the second connecting strip 2112 of the first connecting structure 211 and the seventh connecting strip 2122 of the second connecting structure 212.

[0156] In some examples, such as Figure 9A As shown, the first frame corner area C1 may also be provided with a third power connection line 521 located on the first conductive layer and a fourth power connection line 522 located on the third conductive layer. The third power connection line 521 can be connected to the fourth power connection line 522. The third power connection line 521 and the fourth power connection line 522 can be located on the side of the multiplexing circuit MUX away from the display area AA. The third power connection line 521 and the fourth power connection line 522 can be configured to transmit a second power signal. The first multiplexing control line ML1, the second multiplexing control line ML2, the third multiplexing control line ML3, and the fourth multiplexing control line ML4 connected to the multiplexing circuit MUX can be located on the third conductive layer. The first multiplexing control line ML1, the third multiplexing control line ML3, the second multiplexing control line ML2, and the fourth multiplexing control line ML4 can be arranged along the direction away from the display area AA, and extend in a stepped manner on the side of the multiplexing circuit MUX away from the display area AA.

[0157] This example increases the stability of the multiplexing control transistor of the multiplexing circuit MUX by providing a second shielding structure in the lower corner region (e.g., the first frame corner region C1) covering the active layer of the multiplexing control transistor. The remaining structure of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0158] Figure 10 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 11A for Figure 10 A magnified view of a portion of the central region S2. Figure 11B for Figure 11A A schematic diagram of the bottom shielding metal layer. Figure 11C for Figure 11A A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer.

[0159] In some examples, such as Figures 10 to 11C As shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA, a second shielding structure 32 located in the first bezel corner area C1, a first connecting structure 211, a third connecting structure 213, a plurality of first auxiliary connecting strips 231, and a plurality of second auxiliary connecting strips 232. The first connecting structure 211 may include: a plurality of first connecting strips 2111 extending along a first direction X and a plurality of second connecting strips 2112 extending along a second direction Y. A step formed by connecting one first connecting strip 2111 and one second connecting strip 2112 can be aligned with the three rows of pixel circuits. In other words, the length of the second connecting strip 2112 along the second direction Y can be approximately the same as the length of the three rows of pixel circuits along the second direction Y.

[0160] In some examples, the second shielding structure 32 may include multiple third shielding blocks 321 and multiple shielding connection electrodes 322. The orthographic projection of a single third shielding block 321 onto the substrate may be rectangular. The orthographic projection of the third shielding block 321 onto the substrate may cover an integral structure of the active layers of two multiplexed control transistors (e.g., the active layer M10a of the first multiplexed control transistor M1 and the active layer M20a of the second multiplexed control transistor M2). Each multiplexed circuit MUX may correspond to four third shielding blocks 321. The four third shielding blocks 321 may be arranged in a two-row, two-column array, and adjacent third shielding blocks 321 may be connected via shielding connection electrodes 322. The four third shielding blocks 321 and four shielding connection electrodes 322 corresponding to a single multiplexed circuit MUX may be an integral structure.

[0161] In some examples, the third connecting structure 213 can be a mesh. The third connecting structure 213 can be located on the side of the second shielding structure 32 away from the first connecting structure 211. The third connecting structure 213 may include: a plurality of third connecting strips 2131 extending along a first direction X, a plurality of fourth connecting strips 2132 extending along a second direction Y, and a fifth connecting strip 2133. The fifth connecting strip 2133 can be located on the side of the plurality of third connecting strips 2131 and the plurality of fourth connecting strips 2132 away from the display area AA. The fifth connecting strip 2133 can be integrally connected to the ends of the plurality of third connecting strips 2131 away from the display area AA. The third connecting strips 2131 can be straight strips extending along the first direction X, the fourth connecting strips 2132 can be straight strips extending along the second direction Y, and the fifth connecting strip 2133 can be curved or zigzag. For example, the line width of the fifth connecting strip 2133 can be 10 micrometers (μm).

[0162] In some examples, the third blocking block 321 may be located in the first direction X between the second connecting strip 2112 of the first connecting structure 211 and the fourth connecting strip 2132 of the third connecting structure 213. The third blocking block 321 may not be directly connected to the second connecting strip 2112 and the fourth connecting strip 2132, but may be connected to the second connecting strip 2112 through the first auxiliary connecting strip 231 and to the fourth connecting strip 2132 through the third connecting strip 2131.

[0163] This example increases the stability of the multiplexing control transistors of the multiplexing circuit MUX by providing a second shielding structure 32 covering the active layer of the multiplexing control transistor in the lower corner region (e.g., the first bezel corner region C1 and the second bezel corner region C2). Furthermore, this example provides a mesh-like third connection structure 213 in the first bezel corner region C1 and the second bezel corner region C2, which improves the voltage uniformity of the bottom shielding metal layer in the surrounding area and helps avoid vias formed in the fourth insulating layer. The remaining structures of the display substrate in this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0164] Figure 12A for Figure 10 Another enlarged schematic diagram of a portion of the central region S2. Figure 12B for Figure 12A A schematic diagram of the bottom shielding metal layer. Figure 12C for Figure 12A A schematic diagram of the via formed by the bottom shielding metal layer and the fourth insulating layer.

[0165] In some examples, such as Figures 12A to 12C As shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA, a first connecting structure 211, a third connecting structure 213, a plurality of first auxiliary connecting strips 231, and a plurality of second auxiliary connecting strips 232 located in the first bezel corner area C1. The first connecting structure 211 may include: a plurality of first connecting strips 2111 extending along a first direction X and a plurality of second connecting strips 2112 extending along a second direction Y. The third connecting structure 213 may be mesh-like. The third connecting structure 213 may be located on the side of the first connecting structure 211 away from the display area AA. The third connecting structure 213 may include: a plurality of third connecting strips 2131 extending along the first direction X, a plurality of fourth connecting strips 2132 extending along the second direction Y, and a fifth connecting strip 2133. The first connecting structure 211 and the third connecting structure 213 may be connected to form a plurality of third closed areas K3. For example, the third closed area K3 may be formed by connecting the first connecting strips 2111, the second connecting strips 2112, the third connecting strips 2131, and the fourth connecting strips 2132. A multiplexing circuit MUX can be located within a third enclosed region K3. The orthographic projection of the active layer of the multiple multiplexing control transistors of the multiplexing circuit MUX onto the substrate can be located within the orthographic projection range of the third enclosed region K3 onto the substrate.

[0166] In this example, a mesh-like third connection structure 213 is provided in the lower corner area (e.g., the first frame corner area C1 and the second frame corner area C2). This can improve the voltage uniformity of the bottom shielding metal layer in the surrounding area and help avoid vias in the fourth insulating layer. The remaining structure of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0167] Figure 13 This is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 13 The diagram illustrates the structure of a sub-pixel within the display area. In this example, the pixel circuitry includes both low-temperature polysilicon thin-film transistors (LTPTs) and oxide thin-film transistors (OTFTs). Figure 13 The illustration uses an example where each sub-pixel includes a first-type transistor 16, a second-type transistor 15, and a capacitor 17. The first-type transistor 16 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 15 can be an oxide thin-film transistor.

[0168] In some examples, such as Figure 13 As shown, the circuit structure layer 120 may include: a bottom shielding metal layer 200, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a fifth conductive layer (which may also be referred to as a third gate metal layer), a third conductive layer, and a fourth conductive layer disposed on the substrate 100. A first insulating layer (also called a buffer layer) 101 may be disposed between the bottom shielding metal layer 200 and the first semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be disposed between the first semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be disposed between the first conductive layer and the second conductive layer; an eighth insulating layer (also called a third gate insulating layer) 108 may be disposed between the second conductive layer and the second semiconductor layer; a ninth insulating layer (also called a fourth gate insulating layer) 109 may be disposed between the second semiconductor layer and the fifth conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be disposed between the fifth conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first planarization layer) 106 may be disposed between the third conductive layer and the fourth conductive layer, wherein the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; and a seventh insulating layer (also called a second planarization layer) 107 may be disposed on the side of the fourth conductive layer away from the substrate 100. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, the eighth insulating layer 108 and the ninth insulating layer 109 can be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers.

[0169] In some examples, such as Figure 13 As shown, the first semiconductor layer of the display area may include: an active layer 160 of a first type transistor 16. The first conductive layer may include: a first gate 163 of the first type transistor 16 and a first electrode 171 of the capacitor 17. The second conductive layer may include: a second electrode 172 of the capacitor 17 and a bottom gate 154 of the second type transistor 15. The second semiconductor layer may include: an active layer 150 of the second type transistor 15. The fifth conductive layer may include: a top gate 153 of the second type transistor 15. The orthographic projection of the top gate 153 of the second type transistor 15 onto the substrate 100 may partially overlap with the orthographic projection of the active layer 150 onto the substrate 100. The orthographic projection of the bottom gate 154 of the second type transistor 15 onto the substrate 100 may partially overlap with the orthographic projection of the active layer 150 onto the substrate 100.

[0170] In some examples, such as Figure 13 As shown, the third conductive layer of the display area may include: a first source 161 and a first drain 162 of a first type transistor 16, and a second source 151 and a second drain 152 of a second type transistor 15. The second source 151 of the second type transistor 15 may be electrically connected to one end of the active layer 150 of the second type transistor 15, and the second drain 152 of the second type transistor 15 may be electrically connected to the other end of the active layer 150. The fourth conductive layer may include: an anode transition electrode 181. Further descriptions of the display substrate of this example can be found in [reference needed]. Figure 3 The description of the illustrated embodiment is omitted here.

[0171] Figure 14A for Figure 1 Another enlarged schematic diagram of a portion of the central region S1. Figure 14A The partial structure of the first border corner area C1 is illustrated. Figure 14B for Figure 14A A schematic diagram of the bottom shielding metal layer, the first semiconductor layer, the second conductive layer, the third conductive layer, and the fifth conductive layer; Figure 14C for Figure 14A A schematic diagram of multiple vias formed by the bottom shielding metal layer and the fourth insulating layer; Figure 14D for Figure 14A A schematic diagram of the display substrate after the third conductive layer has been formed.

[0172] In some examples, such as Figures 14A to 14DAs shown, the bottom shielding metal layer may include: a first shielding structure located in the display area AA (e.g., including a first extension strip 311 and a second extension strip 312), and a first connecting structure 211 located in the first bezel corner area C1. The first connecting structure 211 may include: a plurality of first connecting strips 2111 extending along a first direction X, and a plurality of second connecting strips 2112 extending along a second direction Y. The first connecting strips 2111 may be straight strips extending along the first direction X, and the second connecting strips 2112 may be zigzag lines extending along the second direction Y.

[0173] In some examples, the first border corner area C1 may not have a multiplexing circuit; instead, the multiplexing circuit can be located in the first border area B1. Multiple data leads are provided in the first border corner area B1 to achieve electrical connection between the data lines and the multiplexing circuit in the first border area C1. For example... Figure 14B As shown, multiple data leads in the first bezel corner area can be arranged at intervals in the first conductive layer and the second conductive layer. For example, data lead 55a can be located in the first conductive layer, and data lead 55b can be located in the second conductive layer. The first ends of the multiple first signal lines can extend to the side of the second connecting strip 2112 away from the display area AA. For example, first signal lines XL1 and XL2 can be located in the first conductive layer, first signal lines XL3 and XL6 can be located in the second conductive layer, and first signal lines XL4 and XL5 can be located in the fifth conductive layer.

[0174] In some examples, such as Figures 14A to 14D As shown, the data line DL can be located in the fourth conductive layer. One data line DL can be connected to the data transfer electrode 56b located in the third conductive layer. The data transfer electrode 56b can be connected to the data lead 55b located in the second conductive layer through the thirty-first via V31 opened in the fourth insulating layer. Another data line DL can be connected to the data transfer electrode 56a located in the third conductive layer. The data transfer electrode 56a can be connected to the data lead 55a located in the first conductive layer through the thirty-second via V32 opened in the fourth insulating layer. The second transfer hole in this example can include the thirty-first via V31 and the thirty-second via V32. The first connecting strip 2111 can be located in the second direction Y on the side of the second transfer hole closer to the display area AA.

[0175] In some examples, such as Figures 14A to 14DAs shown, the second signal lines YL1 and YL2 can be located in the third conductive layer. The second signal line YL1 can extend to the display area AA. The second connecting strip 2112 can avoid the vias corresponding to the second signal lines YL1 and YL2. The seventh adapter electrode 417 and the eighth adapter electrode 418 can be located in the third conductive layer. Signal adapter lines ZL1, ZL2, and ZL3 can be located in the third conductive layer, and signal adapter lines ZL4 and ZL5 can be located in the fourth conductive layer. Signal adapter line ZL1 can be connected to the first signal line XL1, signal adapter line ZL4 can be connected to the first signal line XL2 through the seventh adapter electrode 417, signal adapter line ZL2 can be connected to the first signal lines XL3 and XL4, signal adapter line ZL5 can be connected to the first signal line XL5 through the eighth adapter electrode 418, and signal adapter line ZL3 can be connected to the first signal line XL6. The first adapter hole in this example may include: a via connecting signal adapter cable ZL1 to the first signal line XL1, a via connecting signal adapter cable ZL4 to the seventh adapter electrode 417, a via connecting signal adapter cable ZL2 to the first signal line XL3, a via connecting signal adapter cable ZL2 to the first signal line XL4, a via connecting signal adapter cable ZL5 to the eighth connecting electrode 418, and a via connecting signal adapter cable ZL3 to the first signal line XL6. The second connecting strip 2112 may be located on the side of the first adapter hole closer to the display area AA.

[0176] In this example, in the first bezel corner area C1, the orthographic projection of the first connecting structure 211 onto the substrate does not overlap with the orthographic projection of the via in the fourth insulating layer onto the substrate, thus avoiding the risk of electrostatic discharge. The first connecting structure 211 can be located on the side of the first and second transition vias closer to the display area AA, which is beneficial for narrow bezel design. Further descriptions of the display substrate in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0177] Figure 15 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 15As shown, this embodiment provides a display device 91, which may include a display substrate 910. The display substrate 910 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be a product with image (including static images or dynamic images, where dynamic images may be video) display capabilities. For example, the display device may be any of the following products: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device may also be a microdisplay, a VR device or AR device containing a microdisplay, etc.

[0178] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0179] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a peripheral area located on at least one side of the display area. The peripheral area includes at least one first peripheral area extending along a first direction, at least one second peripheral area extending along a second direction, and at least one bezel corner area. The at least one bezel corner area connects adjacent first and second peripheral areas, and the first direction intersects the second direction. Multiple pixel circuits and multiple data lines are located in the display area, and the multiple data lines extend along the second direction and are connected to the multiple pixel circuits; Multiple multiplexed circuits are located in the surrounding area and connected to the multiple data lines; A first blocking structure is located in the display area and on the side of the plurality of pixel circuits close to the substrate, wherein the orthographic projection of the first blocking structure on the substrate at least partially overlaps with the orthographic projection of the plurality of pixel circuits on the substrate. A border connection structure is located in the surrounding area, and the border connection structure is an integral structure with the first occlusion structure; The frame connection structure includes: a first connection structure located in the corner area of ​​the frame, the first connection structure extending in a stepped manner along the edge of the display area, and the first connection structure located on the side of the multiple multiplexed circuits in the corner area of ​​the frame that are close to the display area. The display substrate further includes: Multiple first signal lines are located in the display area, extend along the first direction and are connected to the multiple pixel circuits; Multiple first adapter holes and multiple adapter electrodes are located in the peripheral area; the multiple adapter electrodes are connected to the first ends of the multiple first signal lines extending into the peripheral area through the multiple first adapter holes; The orthographic projection of the first connecting structure on the substrate does not overlap with the orthographic projection of the plurality of first adapter holes in the corner area of ​​the frame on the substrate.

2. The display substrate according to claim 1, characterized in that, The first connection structure includes: a plurality of first connecting strips extending along the first direction and a plurality of second connecting strips extending along the second direction, wherein the plurality of first connecting strips and the plurality of second connecting strips are connected at intervals to form a stepped shape.

3. The display substrate according to claim 2, characterized in that, The first connection structure is located on the side of the multiple first adapter holes in the corner area of ​​the frame that are away from the display area.

4. The display substrate according to claim 3, characterized in that, At least one of the plurality of first connecting strips is a straight strip extending along the first direction, and at least one of the plurality of second connecting strips is a straight strip extending along the second direction.

5. The display substrate according to claim 3 or 4, characterized in that, The frame connection structure further includes: a plurality of first auxiliary connecting strips located in the corner area of ​​the frame and extending along the first direction and a plurality of second auxiliary connecting strips extending along the second direction. The plurality of first auxiliary connecting strips and the plurality of second auxiliary connecting strips are located on the side of the first connection structure and the plurality of first transition holes in the corner area of ​​the frame that are close to the display area. The plurality of first auxiliary connecting strips, the plurality of second auxiliary connecting strips and the first connection structure are connected to form a plurality of first closed areas. Each first closed area surrounds at least one of the plurality of first transition holes.

6. The display substrate according to claim 2, characterized in that, The second connecting strip of the first connecting structure is located on the side of the multiple first adapter holes in the corner area of ​​the frame, near the display area; The first connecting strip of the first connecting structure includes a straight segment and a broken line segment extending along the first direction. The broken line segment is located on the side of the plurality of first adapter holes near the display area in the second direction, and the broken line segment bends toward the display area.

7. The display substrate according to claim 1, characterized in that, The display substrate further includes: Multiple data leads and multiple second adapter holes are located in the surrounding area; the multiple data leads are connected to the multiple data lines through the multiple second adapter holes; The orthographic projection of the first connecting structure on the substrate does not overlap with the orthographic projection of the plurality of second adapter holes in the corner area of ​​the frame on the substrate.

8. The display substrate according to claim 7, characterized in that, The first connection structure is located on the side of the plurality of first adapter holes and the plurality of second adapter holes in the corner area of ​​the frame, near the display area.

9. The display substrate according to claim 1, characterized in that, The multiplexing circuit includes multiple multiplexing control transistors; The display substrate further includes: a second shielding structure located in the corner area of ​​the bezel, wherein the orthographic projection of the second shielding structure on the substrate covers the orthographic projection of the active layer of the multiplexed control transistors of the multiplexed circuit on the substrate, and the second shielding structure and the first connection structure are integral structures.

10. The display substrate according to claim 9, characterized in that, The frame connection structure further includes: a second connection structure located in the corner area of ​​the frame, the second connection structure extending in a stepped manner along the edge of the display area, and the multiple multiplexed circuits located in the corner area of ​​the frame on the side away from the first connection structure; the second connection structure and the second shielding structure are an integral structure.

11. The display substrate according to claim 9, characterized in that, The frame connection structure further includes a third connection structure located in the corner area of ​​the frame and in a mesh-like form. The third connection structure is located on the side of the multiple multiplexed circuits in the corner area of ​​the frame that is away from the display area, and is an integral structure with the second blocking structure.

12. The display substrate according to claim 1, characterized in that, The frame connection structure further includes a third connection structure located in the corner area of ​​the frame and in a mesh-like form. The third connection structure is located on the side of the multiple multiplexed circuits in the corner area of ​​the frame that is away from the display area, and is an integral structure with the first connection structure.

13. The display substrate according to claim 11 or 12, characterized in that, The third connection structure includes: a plurality of third connecting strips extending along the first direction, a plurality of fourth connecting strips extending along the second direction, and a fifth connecting strip. The plurality of third connecting strips and the plurality of fourth connecting strips are connected. The fifth connecting strip is connected to the ends of the plurality of third connecting strips that are away from the display area. The fifth connecting strip is located on the side of the plurality of third connecting strips and the plurality of fourth connecting strips that are away from the display area.

14. The display substrate according to claim 13, characterized in that, The fifth connecting strip is an arc segment extending along the edge of the display area.

15. The display substrate according to claim 1, characterized in that, The surrounding area includes: two first surrounding areas, two second surrounding areas, and four border corner areas. The two first surrounding areas include: a first border area and a second border area. The two second surrounding areas include: a third border area and a fourth border area. The four border corner areas include: a first border corner area, a second border corner area, a third border corner area, and a fourth border corner area. The first border corner area is connected between the first border area and the third border area. The second border corner area is connected between the first border area and the fourth border area. The third border corner area is connected between the second border area and the third border area. The fourth border corner area is connected between the second border area and the fourth border area. The plurality of multiplexing circuits are disposed in the first frame area, the first frame corner area and the second frame corner area; The first connection structure is located in the first border corner area and the second border corner area.

16. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 15.

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