Chip testing equipment and testing methods

Abstract

This application provides a chip testing device and method. The testing device includes a processor for acquiring pin connection control information of a target chip, the pin connection control information indicating the connection sequence of at least some pins of the target chip with a power supply module; the processor is also configured to control the connection of the at least some pins with the power supply module according to the connection sequence. The testing device and method of this application can improve the efficiency of chip testing.

Description

Technical Field

[0001] This application relates to the field of chip testing, and in particular to a chip testing device and testing method. Background Technology

[0002] As chips become increasingly complex, the number of corresponding failure modes increases, making chip testing technology particularly important. Current chip testing solutions still primarily rely on manual testing, resulting in low levels of automation and inefficient testing. Summary of the Invention

[0003] This application provides a chip testing device and testing method, which can improve chip testing efficiency.

[0004] In a first aspect, a chip testing device is provided, comprising: a processor configured to acquire pin connection control information of a target chip, the pin connection control information being used to indicate the connection sequence of at least some pins of the target chip with a power supply module; the processor is further configured to control the connection of the at least some pins with the power supply module according to the connection sequence.

[0005] In this embodiment, the processor obtains the pin connection control information of the target chip to control the connection order of at least some pins of the target chip with the power supply module, thereby enabling intelligent testing of the chip and improving the testing efficiency of the chip.

[0006] In one possible implementation, the power supply module includes multiple power supply units, and the processor is specifically configured to: control the at least some pins to be connected to the positive and negative terminals of at least some of the multiple power supply units, respectively, according to the connection order.

[0007] In one possible implementation, the at least part of the power supply unit includes a first power supply unit and a second power supply unit. The processor is specifically configured to: control two pins of the at least part of the pins to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively, according to the connection sequence, so that the voltage between the two pins is U, where U is the sum of the voltages of the plurality of power supply units.

[0008] In this embodiment, according to the connection sequence, at least two pins of some pins are controlled to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively, so that the voltage between these two pins is the sum of the voltages of the multiple power supply units corresponding to the target chip. This allows the target chip to be tested under the most likely damage conditions, which helps to prevent the outflow of abnormal chips.

[0009] In one possible implementation, the positive terminal of the first power supply unit is the positive terminal of the power supply module, and the negative terminal of the second power supply unit is the negative terminal of the power supply module.

[0010] In one possible implementation, the two pins include the power supply pin and the ground pin of the target chip.

[0011] In one possible implementation, the connection sequence includes: the two pins are first connected to the power supply module.

[0012] In this embodiment, by controlling at least two pins of the target chip to be connected to the power supply module first, the voltage between the two pins can be made to be the sum of the voltages of the multiple power supply units corresponding to the target chip. This allows the target chip to be tested under the most likely damage conditions, which helps to prevent the outflow of abnormal chips.

[0013] In one possible implementation, the connection sequence further includes: after the two pins are connected to the power supply module, the pins other than the two pins in at least a portion of the pins are connected to the power supply module in a random order.

[0014] In one possible implementation, the connection sequence includes: at least some of the pins are connected to the power supply module in a random order.

[0015] In one possible implementation, the pin connection control information is further used to indicate the connection delay between two pins that are sequentially connected to the power supply module among the at least some pins; the processor is specifically used to: control the connection of the at least some pins to the power supply module according to the connection sequence and the connection delay.

[0016] In one possible implementation, the connection delay is a random value.

[0017] In one possible implementation, the test device further includes a switch matrix, through which the pins of the target chip are connected to the power supply module, and the pin connection control information is used to indicate the switching sequence of the switch matrix.

[0018] In this embodiment, since the pins of the target chip are connected to the power supply module through a switch matrix, by obtaining the switch closing sequence of the switch matrix and closing the switches in the switch matrix in sequence according to the switch closing sequence, at least some pins of the target chip can be connected to the power supply module, thereby improving the testing flexibility of the target chip.

[0019] In one possible implementation, the target chip includes a first target chip and a second target chip, the power supply module includes a first power supply module and a second power supply module, and the switch matrix includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector. The first connector is connected to the first power supply module, the second connector is connected to the second power supply module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip. The first connector and the third connector are connected through the plurality of first switches, and the second connector and the fourth connector are connected through the plurality of second switches. The power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative terminals of the first power supply module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative terminals of the second power supply module.

[0020] In one possible implementation, the switch closing sequence includes: two of the plurality of first switches connected to the power supply pin and the ground pin of the first target chip are closed first, and then the other first switches of the plurality of first switches are closed randomly; and / or, two of the second switches connected to the power supply pin and the ground pin of the second target chip are closed first, and then the other second switches of the plurality of second switches are closed randomly.

[0021] In one possible implementation, the switch closing sequence includes: the plurality of first switches closing randomly, and / or the plurality of second switches closing randomly.

[0022] In one possible implementation, the target chip includes a first target chip or a second target chip, the power supply module includes a first power supply module and a second power supply module connected in series, the switch matrix includes a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply module, the second connector is connected to the second power supply module, and the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector through the plurality of third switches.

[0023] In one possible implementation, the switch closing sequence includes: a portion of the third switches connected to the first connector closing first, and another portion of the third switches connected to the second connector closing later; or a portion of the third switches connected to the second connector closing first, and another portion of the third switches connected to the first connector closing later.

[0024] In one possible implementation, the power supply pin and ground pin of the first target chip or the second target chip are respectively connected to the positive and negative terminals of the power supply module; the portion of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip, and the other portion of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip. The switch closing sequence includes: after the portion of the third switches is closed, the third switch connected to the ground pin of the first target chip or the second target chip in the other portion of the third switches closes first, and then the other third switches in the other portion of the third switches close randomly; or, the portion of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip, and the other portion of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip. The switch closing sequence includes: after the portion of the third switches is closed, the third switch connected to the power supply pin of the first target chip or the second target chip in the other portion of the third switches closes first, and then the other third switches in the other portion of the third switches close randomly.

[0025] In one possible implementation, the target chip includes a first target chip and a second target chip. The switch matrix includes multiple fourth switches, multiple fifth switches, a first connector, and a second connector. The first connector is connected to the power supply module. Both the first target chip and the second target chip are connected to the second connector. The first connector and the second connector are connected through the multiple fourth switches and the multiple fifth switches. The power supply pin and ground pin of the first target chip are respectively connected to the positive and negative terminals of a portion of the power supply units in the power supply module. The power supply pin and ground pin of the second target chip are respectively connected to the positive and negative terminals of another portion of the power supply units in the power supply module.

[0026] In one possible implementation, the switch closing sequence includes: the fourth switch among the plurality of fourth switches connected to the power supply pin of the first target chip and the fifth switch among the plurality of fifth switches connected to the ground pin of the second target chip are closed first; then the fourth switch among the plurality of fourth switches connected to the ground pin of the first target chip and the fifth switch among the plurality of fifth switches connected to the power supply pin of the second target chip are closed again; finally, the other fourth switches among the plurality of fourth switches and the other fifth switches among the plurality of fifth switches are closed randomly.

[0027] In one possible implementation, the switch closing sequence includes: the plurality of fourth switches and the plurality of fifth switches closing randomly.

[0028] In one possible implementation, the power supply pin of the first target chip is connected to the ground pin of the second target chip.

[0029] In one possible implementation, the switch closing sequence includes: the plurality of fourth switches closing first, then the fifth switch among the plurality of fifth switches connected to the power supply pin of the second target chip closing next, and finally the other fifth switches among the plurality of fifth switches closing randomly; or, the plurality of fifth switches closing first, then the fourth switch among the plurality of fourth switches connected to the ground pin of the first target chip closing next, and finally the other fourth switches among the plurality of fourth switches closing randomly.

[0030] In one possible implementation, the switch matrix includes multiple discharge units, each of which is disposed between two pins in the target chip. The processor is further configured to control the multiple discharge units to discharge the peripheral circuits of the target chip before acquiring pin connection control information of the target chip.

[0031] In one possible implementation, one of these discharge units is provided between every two adjacent pins of the target chip.

[0032] In one possible implementation, each of the target chip's pins, except for the ground pin, has a discharge unit positioned between it and the ground pin.

[0033] In one possible implementation, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch. The processor is specifically configured to: control the closing of the discharge switch in each of the plurality of discharge units to discharge the peripheral circuitry of the target chip.

[0034] Optionally, the testing equipment can be used to perform hot-plug tests on the target chip.

[0035] In this embodiment, multiple discharge units are set in the switch matrix to discharge the peripheral circuits of the target chip after each hot-plug test, ensuring that the initial state of each hot-plug test is consistent. This avoids the problem that the target chip is partially charged after the first hot-plug test, resulting in increasingly weaker hot-plug stress and rendering the test meaningless. Furthermore, adding discharge units can make each test of the target chip closer to the real situation, improving the accuracy of the test.

[0036] In one possible implementation, the processor is specifically used to: control the connection of at least some pins to the power supply module multiple times according to the connection sequence and a preset number of times.

[0037] In this embodiment, repeated testing under the same working conditions can increase the reliability of the test.

[0038] Optionally, the preset number of times is greater than or equal to 30.

[0039] In one possible implementation, the processor is further configured to: perform functional verification on the target chip after controlling at least some pins to connect to the power supply module multiple times according to the connection sequence and the preset number of times.

[0040] Optionally, the processor can also be used to: during the process of controlling the connection of at least some pins to the power supply module according to the connection sequence, confirm whether the circuit function of the target chip is normal based on the reported information of the target chip.

[0041] In one possible implementation, the target chip is an analog front-end (AFE) chip.

[0042] In this embodiment, hot-plugging testing of the AFE chip at the AFE chip design stage helps to prevent the leakage of abnormal AFE chips, thereby reducing losses in terminal applications, accelerating the design and application of terminals, and promoting the healthy development of the new energy industry.

[0043] In a second aspect, a chip testing method is provided, comprising: acquiring pin connection control information of a target chip, the pin connection control information being used to indicate the connection sequence of at least some pins of the target chip with a power supply module; and controlling the connection of the at least some pins with the power supply module according to the connection sequence.

[0044] In one possible implementation, the power supply module includes multiple power supply units, and controlling the connection of at least some pins to the power supply module according to the connection order includes: controlling the connection of at least some pins to the positive and negative terminals of at least some of the power supply units respectively according to the connection order.

[0045] In one possible implementation, the at least partial power supply unit includes a first power supply unit and a second power supply unit. The step of controlling the at least partial pins to be connected to the positive and negative terminals of at least partial power supply units among the plurality of power supply units according to the connection sequence includes: controlling two pins among the at least partial pins to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively, so that the voltage between the two pins is U, where U is the sum of the voltages of the plurality of power supply units.

[0046] In one possible implementation, the positive terminal of the first power supply unit is the positive terminal of the power supply module, and the negative terminal of the second power supply unit is the negative terminal of the power supply module.

[0047] In one possible implementation, the two pins include the power supply pin and the ground pin of the target chip.

[0048] In one possible implementation, the connection sequence includes: the two pins are first connected to the power supply module.

[0049] In one possible implementation, the connection sequence further includes: after the two pins are connected to the power supply module, the pins other than the two pins in at least a portion of the pins are connected to the power supply module in a random order.

[0050] In one possible implementation, the connection sequence includes: at least some of the pins are connected to the power supply module in a random order.

[0051] In one possible implementation, the pin connection control information is further used to indicate the connection delay between two pins that are sequentially connected to the power supply module among the at least some pins; the control of connecting the at least some pins to the power supply module according to the connection order includes: controlling the connection of the at least some pins to the power supply module according to the connection order and the connection delay.

[0052] In one possible implementation, the pins of the target chip are connected to the power supply module via the switch matrix, and the pin connection control information is used to indicate the switching sequence of the switch matrix.

[0053] In one possible implementation, the switch matrix includes multiple discharge units, each of which is disposed between two pins in the target chip. The test method further includes controlling the multiple discharge units to discharge the peripheral circuits of the target chip before acquiring the pin connection control information of the target chip.

[0054] In one possible implementation, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch. Controlling the plurality of discharge units to discharge the peripheral circuits of the target chip includes: controlling the discharge switch in each of the plurality of discharge units to close, so as to discharge the peripheral circuits of the target chip.

[0055] In one possible implementation, controlling the connection of at least some pins to the power supply module according to the connection sequence includes: controlling the connection of at least some pins to the power supply module multiple times according to the connection sequence and a preset number of times.

[0056] In one possible implementation, the preset number of times is greater than or equal to 30.

[0057] In one possible implementation, the testing method further includes: performing functional verification on the target chip after controlling at least some pins to connect to the power supply module multiple times according to the connection sequence and the preset number of times.

[0058] In one possible implementation, the test method further includes: during the process of controlling the connection of at least some pins to the power supply module according to the connection sequence, confirming whether the circuit function of the target chip is normal based on the reported information of the target chip.

[0059] In one possible implementation, the target chip is an analog front-end (AFE) chip.

[0060] Thirdly, a chip is provided, including a processor for calling and running a computer program from memory, such that a device having the chip mounted performs the method of the second aspect and any possible implementation thereof.

[0061] Fourthly, a computer program is provided that causes a computer to perform the methods of the second aspect and any possible implementation thereof.

[0062] Fifthly, a computer-readable storage medium is provided for storing a computer program that causes a computer to perform the methods of the second aspect and any possible implementation thereof.

[0063] In a sixth aspect, a computer program product is provided, including computer program instructions that cause a computer to perform the methods of the second aspect and any possible implementation thereof. Attached Figure Description

[0064] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0065] Figure 1 A schematic block diagram illustrating a method for testing a chip according to an embodiment of this application is shown.

[0066] Figure 2 A schematic diagram showing the connection relationship between the target chip and the power supply module in an embodiment of this application is shown.

[0067] Figure 3 A schematic connection diagram of a chip testing system according to an embodiment of this application is shown.

[0068] Figure 4 Another schematic connection diagram of a chip testing system according to an embodiment of this application is shown.

[0069] Figure 5 Another schematic connection diagram of a chip testing system according to an embodiment of this application is shown.

[0070] Figure 6 This illustration shows another schematic connection diagram of a chip testing system according to an embodiment of this application.

[0071] Figure 7 A schematic block diagram of a test apparatus for a chip according to an embodiment of this application is shown.

[0072] Figure 8 Another schematic block diagram of a test apparatus for a chip according to an embodiment of this application is shown. Detailed Implementation

[0073] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application, that is, this application is not limited to the described embodiments.

[0074] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0075] As chips become increasingly complex, with more and more internal modules and more advanced manufacturing processes, the number of failure modes also increases. Therefore, the importance of effectively and completely testing the entire chip during the design process is growing. Current chip testing solutions still primarily rely on manual testing. Taking hot-plug testing as an example, it requires manually controlling the connection and disconnection of the chip's pins from the power supply module and simulating various operating conditions of the chip. This is extremely time-consuming and labor-intensive, resulting in very low testing efficiency.

[0076] In view of this, embodiments of this application provide a method for testing chips. By acquiring the pin connection control information of the target chip, the connection order of at least some pins of the target chip with the power supply module can be controlled, thereby enabling intelligent testing of the chip and improving the efficiency of chip testing.

[0077] Figure 1 A schematic block diagram of a chip testing method 100 according to an embodiment of this application is shown. Optionally, the method 100 can be executed by a testing device, which may include a host computer. Figure 1 As shown, the method 100 includes some or all of the following contents.

[0078] Step 110: Obtain the pin connection control information of the target chip, which is used to indicate the connection sequence of at least some pins of the target chip with the power supply module.

[0079] Step 120: According to the connection sequence, control the connection of at least some pins of the target chip to the power supply module.

[0080] Optionally, method 100 can be a hot-swap testing method for the chip. Hot-swap, or hot-plugging, refers to inserting or removing a chip into or from the system without turning off the system power. Because hot-swap has a significant impact on the system, chips are usually tested for hot-swap before leaving the factory to prevent chips that do not meet the hot-swap requirements from entering the market.

[0081] Optionally, the hot-swap testing method of this application embodiment can be applied to the field of battery management system (BMS). For example, the hot-swap testing method of this application embodiment can realize hot-swap testing of analog front end (AFE) chips in BMS. An AFE chip is a multi-channel sampling monitoring chip that can monitor the battery voltage and temperature of series-connected batteries. Since the pin order of the AFE chip is not fixed when connecting to a battery, there may be a voltage difference between two pins, which may damage the AFE chip. Therefore, hot-swap testing of the AFE chip is necessary. After passing the hot-swap test and verification, AFE chips that meet the requirements can be released to the market.

[0082] Optionally, in this embodiment, the test equipment can acquire pin connection control information of the target chip (also referred to as the chip under test). This pin connection control information can be used to indicate the connection sequence of at least some pins of the target chip with the power supply module. For example, the pin connection control information can be used to indicate the connection sequence of all pins of the target chip with the power supply module. As another example, the pin connection control information can be used to indicate the connection sequence of some pins, including the power supply pins and ground pins of the target chip, with the power supply module. When the pin connection control information is used to indicate the connection sequence of some pins of the target chip with the power supply module, it can also be used to indicate that the connection sequence of another portion of the pins of the target chip with the power supply module is random. Optionally, the connection sequence indicated by the pin connection control information can be one of several connection sequences preset within the test equipment. For example, if the target chip includes pins 1 to 3, various connection sequences can be preset according to different arrangements of pins 1 to 3, as shown in Table 1. The pin connection control information can be used to indicate one of the 15 connection sequences in Table 1. Once the testing equipment obtains the pin connection control information, it can control at least some pins of the target chip to connect to the power supply module according to the connection sequence indicated by the pin connection control information. For example, if the pin connection control information is used to indicate connection sequence 10 in Table 1, then the testing equipment will control the pins of the target chip to be connected to the power supply module in the order of pin 1-pin 2-pin 3.

[0083] Table 1

[0084]

[0085]

[0086] Optionally, in this embodiment, the power supply module can be a real battery or a cell simulator. Optionally, the power supply module can include multiple power supply units connected in series, wherein one power supply unit can correspond to one battery cell. There is a correspondence between the number of power supply units in the power supply module and the number of pins of the target chip.

[0087] In this embodiment, by acquiring the pin connection control information of the target chip, the connection order of at least some pins of the target chip with the power supply module can be controlled, thereby enabling intelligent testing of the chip and improving the efficiency of chip testing.

[0088] Optionally, in this embodiment of the application, the power supply module may include multiple power supply units. Step 120, namely, according to the connection order, controls at least some pins of the target chip to be connected to the power supply module, includes: according to the connection order, controlling the at least some pins to be connected to the positive and negative terminals of at least some power supply units among the multiple power supply units respectively.

[0089] As mentioned above, the power supply module can include multiple power supply units, which can be connected in series. Each power supply unit has a lead extending from its positive and negative terminals, and these leads can correspond to the pins of the target chip. The testing equipment controls the connection between at least some pins of the target chip and the power supply module; in effect, it controls the connection between at least some pins of the target chip and at least some of the leads extending from the multiple power supply units. For example, as... Figure 2 As shown, the power supply module includes three power supply units connected in series, labeled 1, 2, and 3. The power supply module can produce six leads, labeled 11, 12, 13, 14, 15, and 16. The leads 11 and 16, which are the positive and negative terminals of the power supply module, correspond to the power supply pin 101 and ground pin 106 of the target chip 7, respectively. The other leads 12 to 15 of the power supply module correspond to the other pins 102 to 105 of the target chip 7. If the connection sequence indicated by the pin connection control information is power pin 101-ground pin 106-pin 102-pin 103-pin 104-pin 105, then the test equipment can control the connection of power pin 101 to lead 11, ground pin 106 to lead 16, pin 102 to lead 12, pin 103 to lead 13, pin 104 to lead 14, and pin 105 to lead 15 in sequence according to this connection sequence.

[0090] Optionally, in an embodiment of this application, the at least part of the power supply unit includes a first power supply unit and a second power supply unit. The step of controlling at least part of the pins to be connected to the positive and negative terminals of at least part of the power supply units according to the connection order includes: controlling two pins of the at least part of the pins to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively according to the connection order, so that the voltage between the two pins is U, where U is the sum of the voltages of the multiple power supply units.

[0091] Specifically, such as Figure 2As shown, the power supply module includes power supply unit 1, power supply unit 2, and power supply unit 3, which are connected in series. Leads 11 and 12 are connected to the positive terminal of power supply unit 1, while leads 15 and 16 are connected to the negative terminal of power supply unit 3. The testing equipment can control the power supply pin 101 and ground pin 106 of the target chip 7 to first connect to the positive terminal of power supply unit 1 and the negative terminal of power supply unit 3, respectively. This means controlling the connection of power supply pin 101 to lead 11 and ground pin 106 to lead 16, so that the voltage between power supply pin 101 and ground pin 106 is the sum of the voltages of power supply units 1, 2, and 3. In other words, the voltage between power supply pin 101 and ground pin 106 is the sum of the voltages of the multiple power supply units corresponding to the target chip 7, thus making the voltage between power supply pin 101 and ground pin 106 the maximum voltage among any two pins of the target chip 7.

[0092] Optionally, two of the at least some pins can be any two pins of the target chip 7. That is, regardless of which two pins of the target chip 7 have the highest voltage between any two pins, as long as the test equipment controls these two pins of the target chip 7 to be connected to the power supply module according to the connection sequence, it is not limited whether other pins are connected to the power supply module.

[0093] In this embodiment, according to the connection sequence, at least two pins of some pins are controlled to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively, so that the voltage between these two pins is the sum of the voltages of the multiple power supply units corresponding to the target chip. This allows the target chip to be tested under the most likely damage conditions, which helps to prevent the outflow of abnormal chips.

[0094] Optionally, in this embodiment, the positive terminal of the first power supply unit is the positive terminal of the power supply module, and the negative terminal of the second power supply unit is the negative terminal of the power supply module. For example, as... Figure 2 As shown, the power supply module includes power supply unit 1, power supply unit 2, and power supply unit 3, which are connected in series. The positive terminal of power supply unit 1 is the positive terminal of the power supply module, and the negative terminal of power supply unit 3 is the negative terminal of the power supply module. The testing equipment can control at least two pins of the target chip 7 to be connected to the positive terminal of power supply unit 1 and the negative terminal of power supply unit 3, respectively, according to the connection sequence. This ensures that the voltage between these two pins is the voltage of the power supply module, i.e., the sum of the voltages of power supply units 1, 2, and 3.

[0095] Optionally, in other embodiments of this application, the power supply module may include power supply modules 1 to N, each power supply module including multiple power supply units connected in series, each power supply module corresponding to a target chip, that is, the power supply modules 1 to N correspond to target chips 1 to N. The test equipment can control at least two pins of any target chip i (i is any value among 1 to N) to be connected to the positive and negative terminals of the power supply module i respectively, according to the connection sequence, so that the voltage between the two pins of the target chip i is the voltage of the power supply module i.

[0096] Optionally, in this embodiment, the two pins include a power supply pin and a ground pin of the target chip. That is, the test equipment can control the power supply pin and ground pin of the target chip to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively according to the connection sequence, so that the voltage between the power supply pin and the ground pin of the target chip is the sum of the voltages of the multiple power supply units corresponding to the target chip.

[0097] Optionally, in one embodiment of this application, the connection sequence includes: the two pins are first connected to the power supply module. In other words, the test equipment can first control at least two pins of the target chip to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit, so that the voltage between the two pins is the sum of the voltages of the multiple power supply units corresponding to the target chip.

[0098] For example, at least some pins of the target chip may include only these two pins. After the test equipment controls these two pins to be connected to the power supply module, the test equipment can control the other pins of the target chip not to be connected to the power supply module. As another example, at least some pins of the target chip may include pins other than these two pins. After the test equipment controls these two pins to be connected to the power supply module first, the test equipment then controls the other pins in this at least some pin group to be connected to the power supply module.

[0099] It should be understood that the embodiments of this application do not limit the order in which the two pins connected to the power supply module are connected.

[0100] In this embodiment, by controlling at least two pins of the target chip to be connected to the power supply module first, so that the voltage between the two pins is the sum of the voltages of the multiple power supply units corresponding to the target chip, the target chip can be tested under the most likely damage conditions, which helps to avoid the outflow of abnormal chips.

[0101] Optionally, the connection sequence may further include: after the two pins are connected to the power supply module, the pins of at least a portion of the target chip, excluding the two pins, are connected to the power supply module in a random order. That is, when at least a portion of the target chip's pins include pins other than the two pins, after the test equipment controls the two pins to be connected to the power supply module first, the test equipment can control the other pins of the at least a portion of the pins to be connected to the power supply module in a random order. For example, as... Figure 2 As shown, at least some of the pins include pins 101-103 and 106. The test equipment can control the power supply pin 101 and the ground pin 106 to be connected to the power supply module first, and then control the pins 102 and 103 to be connected to the power supply module in a random order. For example, the random order could be to connect pin 102 to the power supply module first, and then connect pin 103 to the power supply module. Another example is that the random order could be to connect pin 103 to the power supply module first, and then connect pin 102 to the power supply module. In this embodiment, the random order means that the connection order of any two consecutive tests may be different.

[0102] Optionally, in another embodiment of this application, the connection sequence includes: at least some pins of the target chip are connected to the power supply module in a random order. For example, such as Figure 2 As shown, at least some of the pins include pins 101-103 and 106. The test equipment can control the pins 101-103 and 106 to be connected to the power supply module in a random order. For example, the random order could be pin 101-pin 102-pin 103-pin 106. Another example is pin 101-pin 106-pin 102-pin 103. Yet another example is pin 106-pin 102-pin 101-pin 103. In this embodiment, the random order means that the connection order of any two consecutive tests may be different.

[0103] Optionally, in this embodiment of the application, the pin connection control information is also used to indicate the connection delay between two pins that are sequentially connected to the power supply module among the at least some pins. Step 120, that is, according to the connection order, controls the connection of at least some pins to the power supply module, includes: according to the connection order and the connection delay, controlling the connection of at least some pins to the power supply module.

[0104] Optionally, the connection delay can be preset within the test equipment, just like the connection sequence. For example, multiple connection delays can be preset within the test equipment, and the pin connection control information can indicate at least one of these multiple connection delays. For example, the test equipment can preset six connection delays: 500ms, 600ms, 700ms, 800ms, 900ms, and 1s. Optionally, the pin connection control information can indicate only one of these six connection delays. That is, the delay between any two consecutively connected pins of the target chip to the power supply module is the same. For example, if the pin connection control information indicates a connection delay of 500ms, then the delay between any two consecutively connected pins of the target chip to the power supply module is 500ms, meaning the test equipment controls one pin of the target chip to connect to the power supply module every 500ms. Optionally, the pin connection control information can indicate multiple of the six connection delays. For example, as... Figure 2 As shown, the test equipment controls pins 101-103 and 106 to connect to the power supply module in the order of pin 101-pin 106-pin 102-pin 103. The pin connection control information is used to indicate three connection delays: 500ms, 800ms, and 1s. This pin connection control information can also indicate a connection delay of 500ms between pin 102 and pin 106, 800ms between pin 106 and pin 102, and 1s between pin 102 and pin 103. That is, after controlling pin 101 to connect to the power supply module, the test equipment controls pin 106 to connect to the power supply module after a 500ms interval, then controls pin 102 to connect after an 800ms interval, and finally controls pin 103 to connect after a 1s interval.

[0105] Optionally, in this embodiment, the connection delay can be a random value. For example, the connection delay can be a random value between 500ms and 1s. A random connection delay means that the connection delay between any two consecutively connected power supply modules of the target chip is randomly selected by the test equipment and is not preset.

[0106] Optionally, in this embodiment, the pins of the target chip are connected to the power supply module via a switch matrix, and the pin connection control information is used to indicate the switching sequence of the switch matrix.

[0107] In this embodiment, since the pins of the target chip are connected to the power supply module through a switch matrix, by obtaining the switch closing sequence of the switch matrix and closing the switches in the switch matrix in sequence according to the switch closing sequence, at least some pins of the target chip can be connected to the power supply module, thereby improving the testing flexibility of the target chip.

[0108] Optionally, the switch matrix can be a relay or a semiconductor switch, etc.

[0109] The following will combine Figures 3 to 6 This application describes in detail a method for testing a chip according to an embodiment. Specifically, in Figures 3 to 6 In this method, the target chip is an AFE chip, and two AFE chips form a cell monitor unit (CMU). The test object is a CMU, meaning this method can be used to perform hot-plug testing on the CMU. Besides the test equipment and the test object, the test system may also include a power supply module. The test equipment includes a switch matrix, which can include switches and connectors. The on / off state of the switches in the switch matrix is ​​equivalent to the connector being connected or disconnected. Optionally, in... Figures 3 to 6 In this test device, the control functions can be implemented by a host computer. The power supply module can use a real battery or a cell simulator. Optionally, the number of AFE chips included in a CMU can be varied, and the number of battery cells included in the power supply module can also vary in actual application.

[0110] Optionally, in the first embodiment, the target chip includes a first target chip and a second target chip, the power supply module includes a first power supply module and a second power supply module, and the switch matrix includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector. The first connector is connected to the first power supply module, the second connector is connected to the second power supply module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip. The first connector and the third connector are connected through the plurality of first switches, and the second connector and the fourth connector are connected through the plurality of second switches. The power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative terminals of the first power supply module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative terminals of the second power supply module.

[0111] Optionally, in one implementation, the switch closing sequence may include: two of the plurality of first switches connected to the power supply pin and the ground pin of the first target chip are closed first, and then the other first switches in the plurality of first switches are closed randomly; and / or, two of the second switches connected to the power supply pin and the ground pin of the second target chip are closed first, and then the other second switches in the plurality of second switches are closed randomly.

[0112] Alternatively, in another implementation, the plurality of first switches are closed randomly, and / or the plurality of second switches are closed randomly.

[0113] For example, such as Figure 3As shown, the target chip includes a first AFE chip 210 and a second AFE chip 220, wherein the first AFE chip 210 and the second AFE chip 220 form a CMU 200. The power supply module 300 includes a first power supply module 310 and a second power supply module 320. The switch matrix 400 includes a first switch group 410 and a second switch group 420. The first switch group 410 includes K1 to Km, and the second switch group 420 includes Km+1 to K2m. The switch matrix 400 also includes a first connector 411 for connecting the first power supply module 310, a second connector 412 for connecting the second power supply module 320, a third connector 413 for connecting the first AFE chip 210, and a fourth connector 414 for connecting the second AFE chip 220. The first connector 411 and the third connector 413 are connected through the first switch group 410, and the second connector 412 and the fourth connector 414 are connected through the second switch group.

[0114] like Figure 3 As shown, the number of battery cells in the first power supply module 310 is the same as the number of sampling channels in the first AFE chip 210, and all sampling leads of the first power supply module 310 are concentrated in the first connector 411, while all sampling channel lines of the first AFE chip 210 are concentrated in the third connector 413. Similarly, the number of battery cells in the second power supply module 320 is the same as the number of sampling channels in the second AFE chip 220, and all sampling leads of the second power supply module 320 are concentrated in the second connector 412, while all sampling channel lines of the second AFE chip 220 are concentrated in the fourth connector 414. The positive terminal of the first power supply module 310 is connected to the power pin of the first AFE chip 210 via Km, the negative terminal of the first power supply module 320 is connected to the ground pin (GND) of the first AFE chip 210 via K1, the positive terminal of the second power supply module 320 is connected to the power pin of the second AFE chip 220 via K2m, and the negative terminal of the second power supply module 320 is connected to the ground pin (GND) of the second AFE chip 220 via Km+1.

[0115] Condition 1 (the worst-case scenario for the first AFE chip 210 and / or the second AFE chip 220): K1 and Km close first (either K1 closes first, then Km; or Km closes first, then K1), followed by the random closure of other switches K2 to Km-1 in the first switch group 410; and / or, Km+1 and K2m close first (either Km+1 closes first, then K2m; or K2m closes first, then Km+1), followed by the random closure of other switches Km+2 to K2m-1 in the second switch group 420. The random closure includes both random closure order and random time delay.

[0116] Operating condition 2 (the closest to the real situation for the first AFE chip 210 and / or the second AFE chip 220): K1 to Km are randomly closed; and / or, Km+1 to K2m are randomly closed. Among them, random closure includes randomness in the closure sequence and randomness in the time delay.

[0117] Optionally, in the second embodiment, the target chip includes a first target chip or a second target chip, the power supply module includes a first power supply module and a second power supply module connected in series, the switch matrix includes a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply module, the second connector is connected to the second power supply module, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector through the plurality of third switches.

[0118] Optionally, the switch closing sequence includes: a portion of the third switches connected to the first connector closing first, and another portion of the third switches connected to the second connector closing later; or, a portion of the third switches connected to the second connector closing first, and another portion of the third switches connected to the first connector closing later.

[0119] Optionally, the power supply pin and ground pin of the first target chip or the second target chip are respectively connected to the positive and negative terminals of the power supply module; the portion of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip, and the other portion of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip. The closing sequence of the switches includes: after the portion of the third switches is closed, the third switch connected to the ground pin of the first target chip or the second target chip in the other portion of the third switches is closed first, and then the other third switches in the other portion of the third switches are closed randomly; or, the portion of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip, and the other portion of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip. The closing sequence of the switches includes: after the portion of the third switches is closed, the third switch connected to the power supply pin of the first target chip or the second target chip in the other portion of the third switches is closed first, and then the other third switches in the other portion of the third switches are closed randomly.

[0120] For example, such as Figure 4As shown, the target chip includes a first AFE chip 210 and a second AFE chip 220, wherein the first AFE chip 210 and the second AFE chip 220 form a CMU 200. The power supply module 300 includes a first power supply module 310 and a second power supply module 320, and the switch matrix 400 includes a third switch group 430, which includes K1 to K2m. The switch matrix 400 also includes a first connector 411 for connecting the first power supply module 310, a second connector 412 for connecting the second power supply module 320, and a third connector 413 for connecting either the first AFE chip 210 or the second AFE chip 220. The power supply pin of the first AFE chip 210 is connected to the positive terminal of the power supply module 300 via K2m, and the ground pin of the first AFE chip 210 is connected to the negative terminal of the power supply module 300 via K1. Alternatively, the power supply pin of the second AFE chip 220 is connected to the positive terminal of the power supply module 300 through K2m, and the ground pin of the second AFE chip 220 is connected to the negative terminal of the power supply module 300 through K1.

[0121] like Figure 4 As shown, the sum of the number of battery cells in the first power supply module 310 and the second power supply module 320 is consistent with the number of sampling channels in the first AFE chip 210 or the second AFE chip. Furthermore, all sampling leads of the first power supply module 310 are concentrated in the first connector 411, all sampling leads of the second power supply module 320 are concentrated in the second connector 412, and all sampling channel lines of the first AFE chip 210 or the second AFE chip 220 are concentrated in the third connector 413.

[0122] Operating Condition 3: K1 to Km are closed first, and after a certain delay, Km+1 to K2m are closed. During the closure of Km+1 to K2m, K2m is closed first, and then Km+1 to K2m-1 are closed randomly. The random closure includes randomness in the closure order and randomness in the time delay.

[0123] Condition 4: Km+1 to K2m are closed first, and K1 to Km are closed after a certain delay. During the closure of K1 to Km, K1 is closed first, and then K2 to Km are closed randomly. The random closure includes random closure order and random time delay.

[0124] Optionally, in a third embodiment, the target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected through the plurality of fourth switches and the plurality of fifth switches, the power supply pin and ground pin of the first target chip are respectively connected to the positive and negative terminals of a portion of the power supply units in the power supply module, and the power supply pin and ground pin of the second target chip are respectively connected to the positive and negative terminals of another portion of the power supply units in the power supply module.

[0125] Optionally, in one implementation, the switch closing sequence includes: the fourth switch among the plurality of fourth switches connected to the power supply pin of the first target chip and the fifth switch among the plurality of fifth switches connected to the ground pin of the second target chip are closed first; then the fourth switch among the plurality of fourth switches connected to the ground pin of the first target chip and the fifth switch among the plurality of fifth switches connected to the power supply pin of the second target chip are closed again; finally, the other fourth switches among the plurality of fourth switches and the other fifth switches among the plurality of fifth switches are closed randomly.

[0126] Alternatively, in another implementation, the switch closing sequence includes: the plurality of fourth switches and the plurality of fifth switches closing randomly.

[0127] For example, such as Figure 5As shown, the target chip includes a first AFE chip 210 and a second AFE chip 220, wherein the first AFE chip 210 and the second AFE chip 220 form a CMU 200. The power supply module 300 includes a first power supply module 310, and the switch matrix 400 includes a fourth switch group 440 and a fifth switch group 450. The fourth switch group 440 includes K1 to Km, and the fifth switch group 450 includes Km+1 to K2m. The switch matrix 400 also includes a first connector 411 for connecting the first power supply module 310 and a second connector 412 for connecting the first AFE chip 210 and the second AFE chip 220. In this configuration, the power supply pin of the first AFE chip 210 is connected to the positive terminal of the battery cell in the first part of the first power supply module 310 connected in series via Km; the ground pin of the first AFE chip 210 is connected to the negative terminal of the battery cell in the first part of the first power supply module 310 connected in series via K1; the power supply pin of the second AFE chip 210 is connected to the positive terminal of the battery cell in the second part of the first power supply module 310 connected in series via K2m; and the ground pin of the second AFE chip 220 is connected to the negative terminal of the battery cell in the second part of the first power supply module 310 connected in series via Km+1. The positive terminals of the battery cells in the first part of the series connection are connected to the negative terminals of the battery cells in the second part of the series connection.

[0128] like Figure 5 As shown, the number of battery cells in the first part of the series-connected battery cells is the same as the number of sampling channels of the first AFE chip 210, and all the sampling leads of the first power supply module 310 are concentrated in the first connector 411, and all the sampling channel lines of the first AFE chip 210 and the second AFE chip 220 are concentrated in the second connector 412.

[0129] Condition 5: Km and Km+1 are closed first, followed by K1 and K2m after a delay, and the remaining switches are closed randomly. This random closure includes both random closure order and random time delay.

[0130] Condition 6: All switches K1 to K2m are closed randomly. Random closure includes randomness in both the closing sequence and the time delay.

[0131] Optionally, in the fourth embodiment, the target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected through the plurality of fourth switches and the plurality of fifth switches, the power supply pin and ground pin of the first target chip are respectively connected to the positive and negative terminals of a portion of the power supply units in the power supply module, the power supply pin and ground pin of the second target chip are respectively connected to the positive and negative terminals of another portion of the power supply units in the power supply module, and the power supply pin of the first target chip is connected to the ground pin of the second target chip.

[0132] In this embodiment, optionally, the switch closing sequence includes: the plurality of fourth switches closing first, then the fifth switch among the plurality of fifth switches connected to the power supply pin of the second target chip closing next, and finally the other fifth switches among the plurality of fifth switches closing randomly; or, the plurality of fifth switches closing first, then the fourth switch among the plurality of fourth switches connected to the ground pin of the first target chip closing next, and finally the other fourth switches among the plurality of fourth switches closing randomly.

[0133] For example, such as Figure 6 As shown, the target chip includes a first AFE chip 210 and a second AFE chip 220, wherein the first AFE chip 210 and the second AFE chip 220 form a CMU 200. The power supply module 300 includes a first power supply module 310, and the switch matrix 400 includes a fourth switch group 440 and a fifth switch group 450. The fourth switch group 440 includes K1 to Km, and the fifth switch group 450 includes Km+1 to K2m. The switch matrix 400 also includes a first connector 411 for connecting the first power supply module 310 and a second connector 412 for connecting the first AFE chip 210 and the second AFE chip 220. In this configuration, the power supply pin of the first AFE chip 210 is connected to the positive terminal of the battery cell in the first part of the first power supply module 310 connected in series via Km; the ground pin of the first AFE chip 210 is connected to the negative terminal of the first part of the first power supply module 310 connected in series via K1; the power supply pin of the second AFE chip 210 is connected to the positive terminal of the battery cell in the second part of the first power supply module 310 connected in series via K2m; and the ground pin of the second AFE chip 220 is connected to the negative terminal of the battery cell in the second part of the first power supply module 310 connected in series via Km+1. The positive terminals of the first part of the series-connected battery cells are connected to the negative terminals of the second part of the series-connected battery cells. The power supply pin of the first AFE chip 210 is connected to the ground pin of the second AFE chip 220.

[0134] like Figure 6As shown, the number of battery cells in the first part of the series-connected battery cells is the same as the number of sampling channels of the first AFE chip 210, and all the sampling leads of the first power supply module 310 are concentrated in the first connector 411, and all the sampling channel lines of the first AFE chip 210 and the second AFE chip 220 are concentrated in the second connector 412.

[0135] Condition 7: Km+1 to K2m are closed first, then K1 is closed after a delay, and finally K2 to Km are closed randomly.

[0136] Condition 8: K1 to Km are closed first, then K2m is closed after a delay, and finally Km+1 to K2m-1 are closed randomly.

[0137] Optionally, in this embodiment of the application, the switch matrix includes multiple discharge units, each of which is disposed between two pins in the target chip. The processor is further configured to: control the multiple discharge units to discharge the peripheral circuits of the target chip before acquiring the pin connection control information of the target chip.

[0138] In one embodiment, a discharge unit is provided between every two adjacent pins of the target chip.

[0139] In another embodiment, each of the target chip's pins, except for the ground pin, is provided with a discharge unit between itself and the ground pin.

[0140] Further optionally, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch. Controlling the plurality of discharge units to discharge the peripheral circuit of the target chip includes: controlling the discharge switch in each of the plurality of discharge units to close, so as to discharge the peripheral circuit of the target chip.

[0141] For example, such as Figures 3 to 6 As shown, the switch matrix 400 also includes multiple discharge units 460, which are respectively disposed between every two pins of the AFE chip. Each discharge unit 460 includes a discharge switch 461 and a discharge resistor 462, which are connected in series. After each hot-plug simulation power-down, the discharge switches 461 in all discharge units 460 are closed to discharge the peripheral circuits of the first AFE chip 210 and / or the second AFE chip 220, so that the first AFE chip 210 and / or the second AFE chip 220 return to their initial state.

[0142] In this embodiment, multiple discharge units are set in the switch matrix to discharge the peripheral circuits of the target chip after each hot-plug test, ensuring that the initial state of each hot-plug test is consistent. This avoids the problem that the target chip is partially charged after the first hot-plug test, resulting in increasingly weaker hot-plug stress and rendering the test meaningless. Furthermore, adding discharge units can make each test of the target chip closer to the real situation, improving the accuracy of the test.

[0143] Alternatively, in other embodiments, it is also possible to... Figures 3 to 6 Each pin of the AFE chip has a discharge unit between it and the ground pin.

[0144] Optionally, in the embodiments of this application, as described above, the target chip is an AFE chip.

[0145] In this embodiment, hot-plugging testing of the AFE chip at the AFE chip design stage helps to prevent the leakage of abnormal AFE chips, thereby reducing losses in terminal applications, accelerating the design and application of terminals, and promoting the healthy development of the new energy industry.

[0146] Optionally, in this embodiment, step 220, i.e., controlling the connection of at least some pins to the power supply module according to the connection sequence, includes: controlling the connection of at least some pins to the power supply module multiple times according to the connection sequence and a preset number of times.

[0147] Specifically, the process of connecting the pins of the target chip to the power supply module in the correct connection sequence, and then disconnecting all pins of the target chip from the power supply module, can be considered as one test of the target chip. The test equipment can perform multiple tests on the target chip using the same or different connection sequences. For example, the preset number of tests can be greater than or equal to 30.

[0148] by Figure 3 For example, under operating condition 1, the switch matrix can be controlled 30 times in the order of first closing K1 and Km, and then randomly closing other switches. Optionally, within these 30 times, the closing order is always K1 and Km first, but the closing order of other switches can be the same or different. Optionally, the switch matrix can also be controlled 30 times in the same closing order each time the closing order is changed, until all closing orders have been obtained once.

[0149] In this embodiment, repeated testing under the same working conditions can increase the reliability of the test.

[0150] Optionally, in this embodiment of the application, the method further includes: after controlling at least some pins to connect to the power supply module multiple times according to the connection sequence and the preset number of times, performing functional verification on the target chip.

[0151] For example, in adopting Figures 3 to 6 After the testing system completes the CMU test, it can verify the CMU's power supply voltage range. This verification can include the following steps: placing the CMU in a temperature chamber and adjusting the chamber temperature to a specified value; powering on the CMU, adjusting the individual cell voltage to a specified value, and checking whether the CMU's function meets the specified requirements; once the CMU's temperature stabilizes, maintaining it under these conditions for a specified operating time; and during operation, monitoring the CMU's operating status in real time to ensure it meets the specified requirements. The CMU uses six chips, operates for 24 hours, and the ambient temperature and power supply voltage combinations are shown in Table 2.

[0152] Table 2

[0153]

[0154] Where N is the number of configurable sampling channels of the AFE chip, and N_min is the minimum number of configurable sampling channels of the AFE chip.

[0155] In this embodiment, after testing the target chip, the target chip is further functionally verified to ensure that it is only released to the market when the functional status level meets certain requirements, thereby reducing losses at the application end.

[0156] Optionally, in this embodiment of the application, the method further includes: during the process of controlling the connection of at least some pins to the power supply module according to the connection sequence, confirming whether the circuit function of the target chip is normal according to the reported information of the target chip.

[0157] In other words, the testing equipment has two functions: one is to control the pin connection of the target chip to the power supply module based on the acquired pin connection control information; the other is to receive the reporting information from the target chip, so that the testing equipment can confirm whether the circuit function of the target chip is normal based on the reported information. For example, the host computer reads the CMU information to confirm whether the circuit function of the CMU is normal after hot-swapping.

[0158] The following describes in detail the hot-plug test scheme for the CMU including the AFE chip in the embodiments of this application. Specifically, the CMU is hot-plugged according to the following test method. Test requirements: The number of CMUs is 6; the sampling channels (i.e., the number of configuration strings) of the AFE chip is N; (a) the CMU status is that after the power supply voltage range verification, all functions and parameters of the DUT meet the design specifications; the battery cell voltage value is 4.25V, which can be determined by negotiation between the manufacturer and the application party, and the differences should be explained in the test report; the number of hot-plugging cycles is not less than 30 times; the hot-plugging condition can be any of the above conditions 1 to 8 according to the connection relationship between the power supply module and the CMU. The test steps are as follows: (a) Set up the simulated test bench according to the hot-swap test bench requirements for the CMU; (b) Power on the CMU, adjust the voltage of the individual cell to the specified value, and check whether the CMU function meets the specified requirements; (c) Power off the CMU and discharge the residual charge; (d) Simulate the hot-swap scenario and corresponding operating conditions, and connect the corresponding battery channels in sequence. After all channels are connected, check whether the CMU function is normal; (e) Repeat steps c to d to complete the required number of hot-swap tests under this operating condition; (f) Repeat steps c to e to complete the test requirements for the remaining hot-swap operating conditions.

[0159] The testing method for the chip according to the embodiments of this application has been described in detail above. The following will be combined with... Figures 7 to 8 The technical features described in the chip testing equipment and method embodiments of this application are applicable to the following apparatus embodiments.

[0160] Figure 7 A schematic block diagram of a chip testing apparatus 500 according to an embodiment of this application is shown. Figure 7 As shown, the test equipment 500 includes some or all of the following components.

[0161] The processor 510 is configured to acquire pin connection control information of the target chip, the pin connection control information being used to indicate the connection sequence of at least some pins of the target chip with the power supply module; the processor 510 is also configured to control the connection of the at least some pins with the power supply module according to the connection sequence.

[0162] Optionally, in this embodiment of the application, the power supply module includes multiple power supply units, and the processor 510 is specifically used to: control the at least some pins to be connected to the positive and negative terminals of at least some of the multiple power supply units respectively, according to the connection order.

[0163] Optionally, in this embodiment of the application, the at least part of the power supply unit includes a first power supply unit and a second power supply unit. The processor 510 is specifically used to: control two pins of the at least part of the pins to be connected to the positive terminal of the first power supply unit and the negative terminal of the second power supply unit respectively according to the connection sequence, so that the voltage between the two pins is U, where U is the sum of the voltages of the plurality of power supply units.

[0164] Optionally, in this embodiment, the positive terminal of the first power supply unit is the positive terminal of the power supply module, and the negative terminal of the second power supply unit is the negative terminal of the power supply module.

[0165] Optionally, in this embodiment, the two pins include the power supply pin and the ground pin of the target chip.

[0166] Optionally, in this embodiment of the application, the connection sequence includes: the two pins are first connected to the power supply module.

[0167] Optionally, in this embodiment of the application, the connection sequence further includes: after the two pins are connected to the power supply module, the pins other than the two pins among the at least some pins are connected to the power supply module in a random order.

[0168] Optionally, in this embodiment of the application, the connection sequence includes: the at least some pins are connected to the power supply module in a random order.

[0169] Optionally, in this embodiment, the pin connection control information is further used to indicate the connection delay between two pins that are sequentially connected to the power supply module among the at least some pins; the processor 510 is specifically used to: control the connection of the at least some pins to the power supply module according to the connection order and the connection delay.

[0170] Optionally, in this embodiment, the connection delay is a random value.

[0171] Optionally, such as Figure 8 As shown, the test device 500 also includes a switch matrix 520. The pins of the target chip are connected to the power supply module through the switch matrix 520. The pin connection control information is used to indicate the switching sequence of the switch matrix 520.

[0172] Optionally, in this embodiment, the power supply module includes a first power supply module and a second power supply module, the target chip includes a first target chip and a second target chip, and the switch matrix 520 includes a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector, and a fourth connector. The first connector is connected to the first power supply module, the second connector is connected to the second power supply module, the third connector is connected to the first target chip, and the fourth connector is connected to the second target chip. The first connector and the third connector are connected through the plurality of first switches, and the second connector and the fourth connector are connected through the plurality of second switches. The power supply pin and the ground pin of the first target chip are respectively connected to the positive and negative terminals of the first power supply module, and the power supply pin and the ground pin of the second target chip are respectively connected to the positive and negative terminals of the second power supply module.

[0173] Optionally, in this embodiment, the switch closing sequence includes: two first switches connected to the power supply pin and ground pin of the first target chip are closed first, and then the other first switches are closed randomly; and / or, two second switches connected to the power supply pin and ground pin of the second target chip are closed first, and then the other second switches are closed randomly.

[0174] Optionally, in this embodiment of the application, the switch closing sequence includes: the plurality of first switches closing randomly, and / or the plurality of second switches closing randomly.

[0175] Optionally, in this embodiment of the application, the power supply module includes a first power supply module and a second power supply module connected in series, the target chip includes a first target chip or a second target chip, the switch matrix 520 includes a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply module, the second connector is connected to the second power supply module, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector through the plurality of third switches.

[0176] Optionally, in this embodiment, the switch closing sequence includes: a portion of the third switches connected to the first power supply module are closed first, and another portion of the third switches connected to the second power supply module are closed later; or a portion of the third switches connected to the second power supply module are closed first, and another portion of the third switches connected to the first power supply module are closed later.

[0177] Optionally, in this embodiment, the power supply pin and ground pin of the first target chip or the second target chip are respectively connected to the positive and negative terminals of the power supply module; the portion of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip, and the other portion of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip. The closing sequence of the switches includes: after the portion of the third switches is closed, the third switch connected to the ground pin of the first target chip or the second target chip in the other portion of the third switches is closed first, and then the other third switches in the other portion of the third switches are closed randomly; or the portion of the third switches includes a third switch connected to the ground pin of the first target chip or the second target chip, and the other portion of the third switches includes a third switch connected to the power supply pin of the first target chip or the second target chip. The closing sequence of the switches includes: after the portion of the third switches is closed, the third switch connected to the power supply pin of the first target chip or the second target chip in the other portion of the third switches is closed first, and then the other third switches in the other portion of the third switches are closed randomly.

[0178] Optionally, in this embodiment, the target chip includes a first target chip and a second target chip. The switch matrix 520 includes a plurality of fourth switches, a plurality of fifth switches, a first connector, and a second connector. The first connector is connected to the power supply module. Both the first target chip and the second target chip are connected to the second connector. The first connector and the second connector are connected through the plurality of fourth switches and the plurality of fifth switches. The power supply pin and ground pin of the first target chip are respectively connected to the positive and negative terminals of a portion of the power supply units in the power supply module. The power supply pin and ground pin of the second target chip are respectively connected to the positive and negative terminals of another portion of the power supply units in the power supply module.

[0179] Optionally, in this embodiment, the switch closing sequence includes: the fourth switch connected to the power supply pin of the first target chip and the fifth switch connected to the ground pin of the second target chip are closed first; then the fourth switch connected to the ground pin of the first target chip and the fifth switch connected to the power supply pin of the second target chip are closed again; finally, the other fourth switches and the other fifth switches are closed randomly.

[0180] Optionally, in this embodiment, the switch closing sequence includes: the plurality of fourth switches and the plurality of fifth switches closing randomly.

[0181] Optionally, in this embodiment of the application, the power supply pin of the first target chip is connected to the ground pin of the second target chip.

[0182] Optionally, in this embodiment, the switch closing sequence includes: the plurality of fourth switches closing first, then the fifth switch among the plurality of fifth switches connected to the power supply pin of the second target chip closing next, and finally the other fifth switches among the plurality of fifth switches closing randomly; or the plurality of fifth switches closing first, then the fourth switch among the plurality of fourth switches connected to the ground pin of the first target chip closing next, and finally the other fourth switches among the plurality of fourth switches closing randomly.

[0183] Optionally, in this embodiment of the application, the switch matrix 520 includes a plurality of discharge units, each of which is disposed between two pins in the target chip. Before acquiring the pin connection control information of the target chip, the processor 510 is further configured to: control the plurality of discharge units to discharge the peripheral circuits of the target chip.

[0184] Optionally, in this embodiment of the application, a discharge unit is provided between every two adjacent pins of the target chip.

[0185] Optionally, in this embodiment of the application, each of the pins of the target chip other than the ground pin is provided with a discharge unit between the ground pin and the ground pin.

[0186] Optionally, in this embodiment of the application, the discharge unit includes a discharge switch and a resistor connected in series with the discharge switch. The processor 510 is specifically used to: control the discharge switch in each of the plurality of discharge units to close, so as to discharge the peripheral circuit of the target chip.

[0187] Optionally, in this embodiment of the application, the processor 510 is specifically used to: control the connection of at least some pins to the power supply module multiple times according to the connection sequence and a preset number of times.

[0188] Optionally, in this embodiment, the preset number of times is greater than or equal to 30.

[0189] Optionally, in this embodiment of the application, the processor 510 is further configured to: perform functional verification on the target chip after controlling at least some pins to connect to the power supply module multiple times according to the connection sequence and the preset number of times.

[0190] Optionally, in this embodiment of the application, the processor 510 is further configured to: during the process of controlling the connection of at least some pins to the power supply module according to the connection sequence, confirm whether the circuit function of the target chip is normal according to the reported information of the target chip.

[0191] Optionally, in this embodiment of the application, the target chip is an analog front-end (AFE) chip.

[0192] Optionally, the test device further includes a memory for storing instructions, wherein the processor 510 is used to read the instructions and execute the methods of the various embodiments of the present application based on the instructions.

[0193] The memory can be a separate device independent of the processor 510, or it can be integrated into the processor 510.

[0194] Optionally, the test device may also include a transceiver, which the processor 510 can control to communicate with other devices. Specifically, it can send information or data to other devices, or receive information or data sent by other devices.

[0195] It should be understood that each module or unit in the test equipment 500 can implement the corresponding process in the chip test method provided in the embodiments of this application, and for the sake of brevity, it will not be described in detail here.

[0196] This application also provides a chip, including a processor, for calling and running a computer program from a memory, causing a device equipped with the chip to perform the methods described in the various embodiments of this application.

[0197] It should be understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0198] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0199] This application also provides a computer storage medium for storing a computer program for executing the methods of the various embodiments of this application described above.

[0200] Optionally, the computer-readable storage medium can be applied to the test device in the embodiments of this application, and the computer program causes the computer to execute the corresponding processes implemented by the test device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0201] This application also provides a computer program product, including computer program instructions.

[0202] Optionally, the computer program product can be applied to the test equipment in the embodiments of this application, and the computer program instructions cause the computer to execute the corresponding processes implemented by the test equipment in the various methods of the embodiments of this application. For the sake of brevity, they will not be described in detail here.

[0203] This application also provides a computer program.

[0204] Optionally, the computer program can be applied to the test device in the embodiments of this application. When the computer program is run on the computer, it causes the computer to execute the corresponding processes implemented by the test device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0205] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip testing apparatus characterized by comprising: The device comprises a processor and a switch matrix, the switch matrix comprises a plurality of discharge units, each of the plurality of discharge units is arranged between two pins of a target chip, and the pins of the target chip are connected with a power supply module through the switch matrix; The processor is configured to control the plurality of discharge units to discharge a peripheral circuit of the target chip before obtaining pin connection control information of the target chip; The processor is further configured to obtain pin connection control information of the target chip, the pin connection control information is used to indicate a connection sequence of at least part of pins of the target chip and the power supply module, and is used to indicate a switch closing sequence of the switch matrix; The processor is further configured to control the connection of the at least part of pins and the power supply module according to the connection sequence.

2. The test apparatus of claim 1, wherein, The power supply module comprises a plurality of power supply units, and the processor is specifically configured to: According to the connection sequence, control the connection of the at least part of pins and at least part of power supply units in the plurality of power supply units.

3. The test apparatus of claim 2, wherein, The at least part of power supply units comprises a first power supply unit and a second power supply unit, and the processor is specifically configured to: According to the connection sequence, control the connection of two pins in the at least part of pins and the positive electrode of the first power supply unit and the negative electrode of the second power supply unit, so that the voltage between the two pins is U, wherein U is the sum of the voltages of the plurality of power supply units.

4. The test apparatus of claim 3, wherein, The positive electrode of the first power supply unit is the positive electrode of the power supply module, and the negative electrode of the second power supply unit is the negative electrode of the power supply module.

5. The test apparatus of claim 3, wherein, The two pins comprise a power pin and a ground pin of the target chip.

6. The test apparatus of claim 3, wherein, The connection sequence comprises that the two pins are connected with the power supply module first.

7. The test apparatus of claim 6, wherein, The connection sequence further comprises that after the connection of the two pins and the power supply module, the pins other than the two pins in the at least part of pins are connected with the power supply module in a random sequence.

8. The test apparatus of claim 1, wherein, The connection sequence comprises that the at least part of pins are connected with the power supply module in a random sequence.

9. The test apparatus according to any one of claims 1 to 8, characterized in that, The power supply module comprises a first power supply module and a second power supply module, the target chip comprises a first target chip and a second target chip, the switch matrix comprises a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector and a fourth connector, the first connector is connected with the first power supply module, the second connector is connected with the second power supply module, the third connector is connected with the first target chip, the fourth connector is connected with the second target chip, the first connector and the third connector are connected through the plurality of first switches, the second connector and the fourth connector are connected through the plurality of second switches, the power pin and the ground pin of the first target chip are connected with the positive electrode and the negative electrode of the first power supply module respectively, and the power pin and the ground pin of the second target chip are connected with the positive electrode and the negative electrode of the second power supply module respectively.

10. The test apparatus of claim 9, wherein, The switch closing sequence comprises: two first switches connected with the power pin and the ground pin of the first target chip in the plurality of first switches are closed first, and then other first switches in the plurality of first switches are closed randomly; and / or, The switch closing sequence comprises: two second switches connected with the power pin and the ground pin of the second target chip in the plurality of second switches are closed first, and then other second switches in the plurality of second switches are closed randomly.

11. The test apparatus of claim 9, wherein, The switch closing sequence comprises: the plurality of first switches are closed randomly, and / or, the plurality of second switches are closed randomly.

12. The test apparatus of any one of claims 1 to 8, wherein, The power supply module comprises a first power supply sub-module and a second power supply sub-module connected in series, the target chip comprises a first target chip or a second target chip, the switch matrix comprises a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected with the first power supply sub-module, the second connector is connected with the second power supply sub-module, the third connector is connected with the first target chip or the second target chip, and the first connector and the second connector are connected with the third connector through the plurality of third switches.

13. The test apparatus of claim 12, wherein, The switch closing sequence comprises: a part of the third switches connected with the first connector are closed first, and another part of the third switches connected with the second connector are closed later; or The switch closing sequence comprises: a part of the third switches connected with the second connector are closed first, and another part of the third switches connected with the first connector are closed later.

14. The test apparatus of claim 13, wherein, The power pin and the ground pin of the first target chip or the second target chip are connected with the positive electrode and the negative electrode of the power supply module respectively; The part of the third switches comprises third switches connected with the power pin of the first target chip or the second target chip, the other part of the third switches comprises third switches connected with the ground pin of the first target chip or the second target chip, and the switch closing sequence comprises: after the part of the third switches are closed, the third switches connected with the ground pin of the first target chip or the second target chip in the other part of the third switches are closed first, and then other third switches in the other part of the third switches are closed randomly; or The part of the third switches comprises third switches connected with the ground pin of the first target chip or the second target chip, the other part of the third switches comprises third switches connected with the power pin of the first target chip or the second target chip, and the switch closing sequence comprises: after the part of the third switches are closed, the third switches connected with the power pin of the first target chip or the second target chip in the other part of the third switches are closed first, and then other third switches in the other part of the third switches are closed randomly.

15. The test apparatus of any one of claims 1 to 8, wherein, The target chip includes a first target chip and a second target chip, the switch matrix includes a plurality of fourth switches, a plurality of fifth switches, a first connector and a second connector, the first connector is connected with the power supply module, the first target chip and the second target chip are both connected with the second connector, the first connector and the second connector are connected through the plurality of fourth switches and the plurality of fifth switches, the power supply pin and the ground pin of the first target chip are connected with the positive pole and the negative pole of a part of power supply units in the power supply module respectively, and the power supply pin and the ground pin of the second target chip are connected with the positive pole and the negative pole of another part of power supply units in the power supply module respectively.

16. The test apparatus of claim 15, wherein, The closing sequence of the switches includes that the fourth switch connected with the power supply pin of the first target chip in the plurality of fourth switches and the fifth switch connected with the ground pin of the second target chip in the plurality of fifth switches are closed first, then the fourth switch connected with the ground pin of the first target chip in the plurality of fourth switches and the fifth switch connected with the power supply pin of the second target chip in the plurality of fifth switches are closed again, and finally the other fourth switches in the plurality of fourth switches and the other fifth switches in the plurality of fifth switches are closed randomly.

17. The test apparatus of claim 15, wherein, The closing sequence of the switches includes that the plurality of fourth switches and the plurality of fifth switches are closed randomly.

18. The test apparatus of claim 15, wherein, The power supply pin of the first target chip is connected with the ground pin of the second target chip.

19. The test apparatus of claim 18, wherein, The closing sequence of the switches includes that the plurality of fourth switches are closed first, then the fifth switch connected with the power supply pin of the second target chip in the plurality of fifth switches is closed again, and finally the other fifth switches in the plurality of fifth switches are closed randomly, or The plurality of fifth switches are closed first, then the fourth switch connected with the ground pin of the first target chip in the plurality of fourth switches is closed again, and finally the other fourth switches in the plurality of fourth switches are closed randomly.

20. The test apparatus of any one of claims 1 to 8, wherein, One of the discharge units is arranged between every two adjacent pins of the target chip.

21. The test apparatus of any one of claims 1 to 8, wherein, One of the discharge units is arranged between every pin of the target chip and the ground pin except the ground pin.

22. The test apparatus of any one of claims 1 to 8, wherein, The discharge unit includes a discharge switch and a resistance connected with the discharge switch in series, and the processor is specifically configured to: Control the discharge switch in each discharge unit to discharge the peripheral circuit of the target chip.

23. The test apparatus of any one of claims 1 to 8, wherein, The processor is specifically configured to: According to the connection sequence, control the at least part of pins to be connected with the power supply module for a preset number of times.

24. The test apparatus of claim 23, wherein, The processor is further configured to: After the at least part of pins is controlled to be connected with the power supply module for the preset number of times according to the connection sequence, perform function verification on the target chip.

25. A method of testing a chip, characterized by, It includes: Control a plurality of discharge units in a switch matrix to discharge the peripheral circuit of a target chip, wherein the pins of the target chip are connected with a power supply module through the switch matrix, and each discharge unit in the plurality of discharge units is arranged between two pins in the target chip. obtain pin connection control information of the target chip, the pin connection control information being used to indicate a connection sequence of at least part of pins of the target chip and the power supply module, and being used to indicate a switch closing sequence of the switch matrix; control the at least part of pins to be connected to the power supply module according to the connection sequence.

26. The test method of claim 25, wherein, The power supply module includes a plurality of power supply units, and the control of the at least part of pins to be connected to the power supply module according to the connection sequence includes: control the at least part of pins to be connected to the positive and negative poles of at least part of the plurality of power supply units according to the connection sequence.

27. The test method of claim 26, wherein, The at least part of the power supply units includes a first power supply unit and a second power supply unit, and the control of the at least part of pins to be connected to the positive and negative poles of at least part of the plurality of power supply units according to the connection sequence includes: control two pins of the at least part of pins to be connected to the positive pole of the first power supply unit and the negative pole of the second power supply unit according to the connection sequence, so that the voltage between the two pins is U, wherein U is the sum of the voltages of the plurality of power supply units.

28. The test method of claim 27, wherein, The connection sequence includes that the two pins are connected to the power supply module first.

29. The test method of claim 28, wherein, The connection sequence further includes that after the two pins are connected to the power supply module, pins other than the two pins in the at least part of pins are connected to the power supply module in a random sequence.

30. The test method of claim 25, wherein, The connection sequence includes that the at least part of pins are connected to the power supply module in a random sequence.

31. The test method according to any one of claims 25 to 30, wherein, The pin connection control information is further used to indicate a connection delay between two pins of the at least part of pins connected to the power supply module in sequence; The control of the at least part of pins to be connected to the power supply module according to the connection sequence includes: control the at least part of pins to be connected to the power supply module according to the connection sequence and the connection delay.

32. The test method according to any one of claims 25 to 30, characterized in that, The discharge unit includes a discharge switch and a resistor connected in series with the discharge switch, and the control of the plurality of discharge units to discharge the peripheral circuit of the target chip includes: control the discharge switch in each discharge unit of the plurality of discharge units to discharge the peripheral circuit of the target chip.

33. The test method according to any one of claims 25 to 30, wherein, The control of the at least part of pins to be connected to the power supply module according to the connection sequence includes: control the at least part of pins to be connected to the power supply module according to the connection sequence for a preset number of times.

34. The test method of claim 33, wherein, The test method further includes: after the at least part of pins is controlled to be connected to the power supply module according to the connection sequence for the preset number of times, perform function verification on the target chip.

35. The test method according to any one of claims 25 to 30, wherein, The test method further includes: in the process of controlling the at least part of pins to be connected to the power supply module according to the connection sequence, confirm whether the circuit function of the target chip is normal according to the report information of the target chip.

36. A chip, comprising: include: a processor configured to invoke and run a computer program from a memory, so that a device installed with the chip performs the test method according to any one of claims 25 to 35.

37. A computer-readable storage medium, comprising: A computer program for storing a computer program causing a computer to perform the test method of any one of claims 25 to 35.

38. A computer program product, characterised in that, Computer program instructions comprising a computer program causing a computer to perform the test method of any one of claims 25 to 35.

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