Data processing apparatus and biosensor

Abstract

The data processing apparatus includes a memory, a controller, and a processor. The memory includes a first buffer and a memory array, and writes data held in the first buffer to the memory array based on receiving a write command. The controller transmits data received from the outside to the first buffer, and outputs a trigger signal on the basis of a prescribed amount of data transmitted to the first buffer. The processor sends a write command to the memory based on receiving the trigger signal. As a result, even if any of the memories having various command specifications is installed in the data processing device, it is possible to write data to the memory while suppressing an increase in power consumption of the processor.

Description

Technical Field

[0001] The invention relates to a data processing device and a biosensor. Background Art

[0002] For example, a biosensor that acquires biological information from a living body includes an integrated circuit that acquires the biological information as a voltage and converts the acquired voltage into digital data, and an MPU (microprocessing unit) that controls the overall operation of the biosensor. The MPU writes the digital data (biological information) received from the integrated circuit into a memory (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-163128 Summary of the invention

[0004] <Problems to be Solved by the Invention>

[0005] When the biometric information is written to the memory using the MPU that controls the overall operation of the biosensor, the memory with various command specifications can be installed on the biosensor by changing the program executed by the MPU. However, when the biometric information is written to the memory under the control of the MPU, the operating rate of the MPU increases and the power consumption increases.

[0006] On the other hand, when the integrated circuit acquiring biological information writes biological information into a memory without via an MPU, an increase in power consumption of the MPU is suppressed, but when a memory having a different command specification is mounted on the biosensor, redesign of the integrated circuit is required.

[0007] The present invention has been made in view of the above circumstances, and aims to provide a data processing device and a biosensor capable of writing data into a memory while suppressing an increase in power consumption of a processor even when any of memories with various command specifications is installed.

[0008] <Methods used to solve the problem>

[0009] A data processing device according to an embodiment of the present invention includes: a memory including a first buffer for holding data and a memory array, and writing the data held in the first buffer into the memory array based on receiving a write command; a controller, transmitting data received from the outside to the first buffer, and outputting a trigger signal based on transmitting a specified amount of data to the first buffer; and a processor, sending the write command to the memory based on receiving the trigger signal.

[0010] <Effects of the Invention>

[0011] According to the technology disclosed in the present invention, it is possible to provide a data processing device and a biosensor capable of writing data into a memory while suppressing an increase in power consumption of a processor even when any of memories of various command specifications are loaded. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is an overall block diagram showing an example of a data processing device according to one embodiment.

[0013] Figure 2 Yes means Figure 1 A sequence diagram of an example of the operation of a data processing device.

[0014] Figure 3 Yes means Figure 2 An explanatory diagram of an example of the signal status of each step of the action sequence.

[0015] Figure 4 This is an overall block diagram showing an example of a biosensor according to one embodiment.

[0016] Figure 5 Yes means Figure 4 A flowchart of an example of the operation of the biosensor.

[0017] Figure 6 Yes means Figure 5 Flowchart of the continuation of . DETAILED DESCRIPTION

[0018] Hereinafter, the mode for implementing the present invention will be described with reference to the accompanying drawings. Hereinafter, the same reference numerals as the signal names are used for signal lines for transmitting information such as signals. In addition, the same reference numerals as the voltage names are used for voltage lines for transmitting voltages. In addition, in each of the accompanying drawings, the same reference numerals are sometimes given to the same components, and repeated descriptions are omitted.

[0019] Figure 1 This is an overall block diagram showing an example of a data processing device according to one embodiment. Figure 1 The data processing device 100 shown includes a controller 10 (including a buffer 12), a processor 20, and a memory 30 (including a page register PGR, a cache 32, and a memory array 34). The memory array 34 has a plurality of pages PG as data writing units. For example, the controller 10, the processor 20, and the memory 30 are mounted on a substrate of the data processing device 100. The cache 32 is an example of a first buffer, and the buffer 12 is an example of a second buffer.

[0020] For example, the controller 10 may be mounted on an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). In addition, the controller 10 and the processor 20 may be mounted in one FPGA. For example, the memory 30 is a non-volatile memory having an electrically rewritable serial interface, such as a flash memory. Note that the memory may have a multi-bit data terminal or may be a volatile memory.

[0021] For example, the controller 10, the processor 20, and the memory 30 are connected to each other through SPI (Serial Peripheral Interface). Note that the controller 10, the processor 20, and the memory 30 may be connected to each other through a serial interface other than SPI.

[0022] The clock signal line CLK and the serial signal line MOSI (Master Output Slave Input) of the SPI interconnect the controller 10, the processor 20, and the memory 30. The serial signal line MOSI is an example of a common data line and a common serial data line. The slave selection line SS1 (slave selection) and the serial signal line MISO (Master Input Slave Output) 1 interconnect the controller 10 and the processor 20.

[0023] The slave selection line SS2 and the serial signal line MISO2 connect the processor 20 and the memory 30 to each other. In addition, between the controller 10 and the processor 20, a master-slave signal line M / S and a trigger signal line TRG are arranged.

[0024] Hereinafter, the signals transmitted to the clock signal line CLK and the serial signal lines MOSI, MISO1, and MISO2 are also referred to as the CLK signal, the MOSI signal, the MISO1 signal, and the MISO2 signal, respectively. The signals transmitted to the slave selection lines SS1 and SS2 are also referred to as the SS1 signal and the SS2 signal, respectively. The master-slave signal M / S transmitted to the master-slave signal line M / S and the trigger signal TRG transmitted to the trigger signal line TRG are also referred to as the M / S signal and the TRG signal, respectively.

[0025] For example, the clock signal line CLK, the serial signal lines MOSI, MISO1, MISO2, and the slave selection lines SS1, SS2 are pulled up. The CLK signal, the MOSI signal, the MISO1 signal, the MISO2 signal, the SS1 signal, and the SS2 signal are bidirectional signals. The SS2 signal is an example of a chip selection signal for selecting the memory 30, and the processor 20 has a function of outputting the SS2 signal to the SS2 terminal of the memory 30. The slave signal terminal SS2 of the memory 30 is an example of a chip selection terminal.

[0026] The M / S signal is output from the processor 20 to the controller 10. The M / S signal is set to a low level (= logical value 0) during the period when the controller 10 is set as a slave device, and the processor 20 becomes a master device. The M / S signal is set to a high level (= logical value 1) during the period when the controller 10 is set as a master device, and the processor 20 becomes a slave device.

[0027] The TRG signal is output from the controller 10 to the processor 20. The TRG signal indicates completion of the transfer of a specified amount of data from the controller 10 to the cache 32 of the memory 30. For example, the specified amount is an amount of data corresponding to the storage capacity of each page PG. Based on the reception of the TRG signal, the processor 20 instructs the memory 30 to write (program) the data held in the cache 32 into the memory array 34.

[0028] Note that the processor 20 may also use the SS1 signal to detect the completion of the data transfer from the controller 10 to the cache 32. In this case, the trigger signal line TRG may not be configured between the controller 10 and the processor 20. When starting to transfer data to the cache 32, the controller 10 sets the SS1 signal from a logic value of 1 to a logic value of 0, and maintains the logic value of 0 of the SS1 signal during the data transfer. When the data transfer to the cache 32 is completed, the controller 10 sets the SS1 signal from a logic value of 0 to a logic value of 1. And, the processor 20 detects the start of data transfer to the cache 32 based on the change from the logic value 1 to the logic value 0 of the SS1 signal, and detects the completion of transferring one page of data to the cache 32 based on the change from the logic value 0 to the logic value 1 of the SS1 signal.

[0029] The controller 10 receives the input data signal IN via the external terminal ET of the data processing device 100, and stores the received input data signal IN as data in the buffer 12. For example, the buffer 12 has a storage capacity greater than the storage capacity of 1 page PG of the memory 30. By providing the buffer 12 in the controller 10, the difference between the rate of receiving the input data signal IN (receiving rate) and the rate of sending data to the memory 30 (sending rate) can be absorbed.

[0030] Note that the controller 10 may include a signal processing unit for performing digital signal processing such as averaging the input data signal IN held in the buffer 12. In this case, the buffer 12 may hold the input data signal IN before signal processing and the input data signal IN after signal processing.

[0031] The memory array 34 of the memory 30 has a plurality of page PGs, and the cache memory 32 has a storage capacity equal to the storage capacity of the page PG. Although not particularly limited, the storage capacity of one page PG is, for example, 256 bytes. Furthermore, the data held in the cache memory 32 is written to any page PG of the memory array 34.

[0032] Page PG is a unit for writing data. Therefore, for example, when the written data is 128 bytes, half of the page PG of the written data will be wasted. In order to efficiently write data to the memory array 34, it is preferred that the capacity of the data written to each page PG is equal to the storage capacity of the page PG.

[0033] Note that the data processing device 100 may also be mounted on a sensor that detects any one of voltage, current, temperature, light, pressure, geomagnetism, etc. In this case, the controller 10 receives an input data signal IN representing voltage, current, temperature, etc. through the external terminal ET. In addition, for example, the data processing device 100 may process a differential input data signal instead of a single-phase input data signal. Also, when detecting multiple of voltage, current, temperature, light, pressure, geomagnetism, etc., the data processing device 100 may include multiple external terminals ET or multiple pairs of differential external terminals ET.

[0034] Figure 2 Yes means Figure 1 The sequence diagram is an example of the operation of the data processing device 100. For example, the operation of the controller 10 is realized by hardware, and the operation of the processor 20 is realized by a program (ie, software) executed by the processor 20. Figure 2 The actions shown are performed in synchronization with the CLK signal output from the processor 20 or the controller 10 .

[0035] exist Figure 2 In the operation shown, data of one page PG is transferred from the controller 10 to the cache 32 of the memory 30 , and data of a predetermined page PG is written from the cache 32 to the memory array 34 based on instructions from the processor 20 .

[0036] Before step (1), the processor 20 switches the controller 10 to a slave device by setting the M / S signal to a logic value of 0, and then switches itself to a master device. The processor 20 stops the output of the SS2 signal, thereby setting the SS2 signal line to a logic value of 1 by pulling it up. Figure 2 “1 (Hi-Z)” in the SS1 signal or the SS2 signal indicates that the SS1 signal line or the SS2 signal line in a floating state is set to a logic value of 1 by being pulled up.

[0037] In step (1), the processor 20 performs initial settings on registers and the like of the controller 10 by transmitting data to the controller 10 via the MOSI line. Note that the processor 20 sets the SS1 signal to a logical value of 0 in accordance with the period during which the data is output to the MOSI line. For example, the initial settings include the frequency of the CLK signal or the output period of the TRG signal when the controller 10 is a master device. The controller 10 that receives the initial setting data of the registers and the like sends the received data to the processor 20 via the MISO1 line as feedback data.

[0038] After the initial setting of the controller 10, the processor 20 stops outputting the SS1 signal, thereby setting the SS1 signal line to a logic value of 1. Furthermore, in step (2), the processor 20 performs initial setting on the memory 30 via the MOSI line while maintaining the M / S signal at a logic value of 0. The processor 20 sets the SS2 signal to a logic value of 0 in accordance with the period during which the data is output to the MOSI line. For example, the initial setting includes the number of the page PG to which the data is first written.

[0039] The memory 30 holds the page number (page information) indicating the initially set page PG in the page register PGR. The memory 30 sends the received data as feedback data to the processor 20 via the MISO2 line. Note that the operations of step (1) and step (2) may also be performed in reverse order.

[0040] The processor 20 that performs the initial setting of the memory 30 sets the controller 10 as the master device by setting the M / S signal to a logical value of 1. The processor 20 maintains the state of stopping the output of the SS1 signal and the state of setting the SS2 signal to a logical value of 0 (the selection state of the memory 30), and enters the sleep state. That is, the processor 20 shifts from the normal mode to the low power consumption mode. For example, during the sleep state, the processor 20 stops executing the control program and does not accept any interrupts other than hardware interrupts. Figure 2 In FIG. 1 , the period of the low power consumption mode of the processor 20 is indicated by a dotted line.

[0041] Note that the logic of the SS1 signal and the SS2 signal is set using, for example, the I / O (input / output) ports of the controller 10 and the processor 20. Therefore, even during the sleep period of the processor 20, the SS1 signal line or the SS2 signal line can be maintained at a predetermined logic value.

[0042] In step (3), the controller 10, which receives the M / S signal with a logic value of 1 and becomes the master device, sequentially sends the data A stored in the buffer 12 to the memory 30. The controller 10 sends the data corresponding to one page PG of the memory array 34 to the memory 30. The controller 10 sets the SS1 signal to a logic value of 0 in accordance with the period of outputting data to the MOSI line.

[0043] Since the SS1 signal line connects the controller 10 and the processor 20, the SS1 signal is not output to the memory 30 but is output to the processor 20 in sleep mode. However, the memory 30 can continue to be selected as the slave device by the SS2 signal whose logic value is 0 set by the processor 20. Whenever the memory 30 receives data A from the controller 10, the memory 30 stores the received data A in the cache 32.

[0044] The memory 30 transmits the received data A as feedback data to the processor 20 via the MISO2 line. However, the processor 20 does not receive the feedback data because it is in sleep mode. Note that when the data A equivalent to 1 page PG is held in the buffer 12, the controller 10 can transmit the data A equivalent to 1 page PG to the memory 30 through 1 serial transfer.

[0045] During step (3) of transferring data from the controller 10 to the memory 30, the processor 20 stops the execution of the program by hibernation. The power consumption of the processor 20 during the hibernation period is almost entirely caused by power leakage. Thus, compared with the case where data is transferred to the memory 30 via the processor 20 through the program executed by the processor 20, the power consumption of the processor 20 can be greatly reduced.

[0046] After sending the data A of one page PG to the memory 30, the controller 10 stops the output of the SS1 signal and sets the SS1 signal to a logic value of 1. Then, in step (4), the controller 10 controls the I / O port to set the TRG signal line to an effective level (e.g., a logic value of 1). The processor 20 receives the TRG signal of the effective level as an interrupt signal and returns from the low power consumption mode to the normal mode. That is, the processor 20 resumes from the sleep mode.

[0047] The processor 20 that has recovered from hibernation becomes a master by setting the M / S signal to a logical value of 0. The processor 20 generates status information to be sent to the memory 30. For example, the status information includes information such as the temperature of the substrate of the data processing device 100 or the voltage used in the data processing device 100.

[0048] Processor 20 stops outputting SS1 signal and sets SS1 signal to logic value 1. In step (5), processor 20 sends data B including status information to memory 30 via MOSI line. Processor 20 sets SS2 signal to logic value 0 in accordance with the period of outputting data on MOSI line.

[0049] The memory 30 sends the received data B as feedback data to the processor 20 via the MISO2 line. Note that the processor 20 may not generate the status information, in which case step (5) is omitted.

[0050] Next, in step (6), processor 20 sends a write command to memory 30 via MOSI line. Processor 20 sets SS2 signal to logic value 0 in accordance with the period of outputting data to MOSI line. Memory 30 sends the received write command as feedback data to processor 20 via MISO2 line.

[0051] In response to the write command, the memory 30 writes data corresponding to one page PG stored in the cache 32 to the page PG indicated by the page number held in the page register PGR (programs the data into the page PG).

[0052] When the memory 30 is replaced with another memory having a different command specification by sending a write command from the processor 20 to the memory 30, it can be handled by changing the program executed by the processor 20. Therefore, for example, the memory 30 can be replaced with another memory having a larger storage capacity without changing the substrate on which the controller 10, the processor 20, and the memory 30 are mounted.

[0053] Furthermore, since the processor 20 stops executing the program and sleeps during step (3), the power consumption of the processor 20 related to data transfer can be reduced to almost zero. Therefore, even when the memory 30 with various command specifications is installed, data can be written to the memory 30 while suppressing an increase in the power consumption of the processor 20.

[0054] Next, in step (7), the processor 20 sends a page switch command to the memory 30 via the MOSI line. The processor 20 sets the SS2 signal to a logic value of 0 in accordance with the period of outputting data to the MOSI line. The memory 30 sends the received page switch command as feedback data to the processor 20 via the MISO2 line.

[0055] In response to the page switch command, the memory 30 updates (e.g., increments) the page number stored in the page register PGR. Note that the actions of step (6) and step (7) may also be performed in reverse order. In addition, the processor 20 may also update the page register PGR to an arbitrary page number. If step (7) is performed earlier than step (6), the data held in the cache 32 is written to the page PG updated in step (7).

[0056] After sending the page switch command to the memory 30, the processor 20 sets the controller 10 as the master device by setting the M / S signal to a logical value of 1. Similar to the operation after the above step (2), the processor 20 maintains the state of stopping the output of the SS1 signal and setting the SS2 signal to a logical value of 0, and enters sleep. Thereafter, the operations of the above steps (3) to (7) are repeated, and the data processing device 100 writes the data received via the external terminal ET into the memory 30 in units of pages PG.

[0057] Note that the actions of step (5) to step (7) can also be performed while the M / S signal is kept at a logic value of 1. In this case, the controller 10 controls the I / O port so that the TRG signal line is at an effective level and stops the output of the CLK signal and the MOSI signal (set to Hi-Z). The effective state of the TRG signal and the stop state of the output of the CLK signal and the MOSI signal continue until the next data is sent to the memory 30.

[0058] When the M / S signal is kept at a logic value of 1, the processor 20 also receives the active level TRG signal as an interrupt signal and recovers from the low power consumption mode to the normal mode. That is, the processor 20 recovers from the sleep state. The processor 20 after recovering from the sleep state generates state information to be sent to the memory 30 during the period when the TRG signal is in the active state. Then, the processor 20 sends the data B containing the state information, the write command, and the page switch command to the memory 30 via the MOSI line.

[0059] The processor 20 that sends the page switch command to the memory 30 stops the output of the CLK signal and the MOSI signal, maintains the state of stopping the output of the SS1 signal and setting the SS2 signal to a logical value of 0, and enters sleep. After that, the controller 10 restarts the output of the CLK signal and the MOSI signal in accordance with the output of the next transmission data, and executes step (3). That is, the actions of steps (3) to (7) are repeatedly executed in the state of setting the M / S signal to a logical value of 1. As a result, it is possible to simplify the data transmission control by eliminating the need to switch the M / S signal after starting to send data from the controller 10 to the memory 30.

[0060] In addition, the operations of step (5) to step (7) can be performed in the intervals between the multiple consecutive data transfers from the controller 10 to the memory 30 while the M / S signal is kept at a logical value of 1. In this case, the controller 10 continuously performs the data transfer to the memory 30 in step (3) at a predetermined cycle. In addition, the controller 10 stops the output of the CLK signal and the MOSI signal (sets them to Hi-Z) after the TRG signal is set to the effective level until the next data is transferred to the memory 30.

[0061] For example, the prescribed period is a period during which the controller 10 receives the input data signal IN through the external terminal ET. For example, if the controller 10 has an analog-to-digital converter that converts the analog input data signal IN into a digital value, the prescribed period is a sampling period of the analog-to-digital converter.

[0062] The processor 20 predetermines the data transfer cycle from the controller 10 to the memory 30. Then, after receiving the active level TRG signal, the processor 20 generates status information and executes the actions of steps (5) to (7) until the next data is transferred from the controller 10 to the memory 30.

[0063] Note that when the status information generation process takes time, the processor 20 may also generate status information and sleep after sending the page switch command to the memory 30. In this case, the processor 20 sends the generated status information to the memory 30 based on reception of the next active level TRG signal.

[0064] By setting the cycle of transmitting data to the memory 30 to the cycle of receiving the input data signal IN via the external terminal ET, the input data signal IN can be received without interruption at a predetermined cycle. In addition, the controller 10 does not need to retain the data of one page PG in the buffer 12. Therefore, the capacity of the buffer 12 can be the minimum capacity for processing the digital signal of the input data signal IN.

[0065] Note that if the controller 10 is switched to a slave device using the M / S signal during the execution of steps (5) to (7), the sampling period of the controller 10 may be offset. Therefore, if the data transfer timing to the memory 30 is offset relative to the sampling timing of the input data signal IN, the data transfer to the memory 30 may not be performed normally.

[0066] Figure 3 Yes means Figure 2 1 is an explanatory diagram of an example of the signal state of each step of the action sequence. Since the CLK signal, MOSI signal, MISO1 signal, MISO2 signal, SS1 signal, and SS2 signal are bidirectional signals, when these signals are not used, they are set to the high impedance state Hi-Z as described above, and are set to the logic value 1 by being pulled up. Note that in each step, the SS1 signal is set to the logic value 0 only during the period when the master device transmits data. Except for step (3), the SS2 signal is set to the logic value 0 only during the period when the master device transmits data. The SS2 signal is fixed to the logic value 0 in step (3).

[0067] As described above, in this embodiment, the processor 20 does not control the transfer of data to the memory 30, but controls the sending of a write command to the memory 30. Thus, for example, when the memory 30 is replaced with another memory having a different command specification, it can be processed by changing the program executed by the processor 20. As a result, it is possible to provide a data processing device that can write data to the memory while suppressing an increase in the power consumption of the processor 20 even in the case where any of the memories having various command specifications is installed.

[0068] During step (3) of transferring data from the controller 10 to the memory 30, the processor 20 stops the execution of the program by entering sleep mode. The processor 20 is released from sleep mode based on a TRG signal output from the controller 10 after a predetermined amount of data is transferred to the memory 30. During sleep mode, the power consumption of the processor 20 is almost zero. Thus, the power consumption of the processor 20 can be greatly reduced compared to the case where data is transferred to the memory 30 by a program executed by the processor 20.

[0069] Furthermore, since the processor 20 is put into sleep mode by stopping the execution of the program during step (3), the power consumption of the processor 20 related to data transfer can be reduced to almost zero. Therefore, even when the memory 30 of various command specifications is installed, data can be written to the memory 30 while suppressing an increase in the power consumption of the processor 20.

[0070] Using the MOSI signal line as a common serial data line, data A is transmitted from the controller 10 to the memory 30, and register data is transmitted from the processor 20 to the controller 10. In addition, by using the common MOSI signal line, initial setting data, data B, a write command, and a page switch command are transmitted from the processor 20 to the memory 30. Thus, a minimum number of wirings can be formed on a substrate on which the controller 10, the processor 20, and the memory 30 are mounted to perform Figure 2 and Figure 3 As a result, the size of the substrate can be reduced, and the cost of the data processing device 100 can be reduced.

[0071] Whenever data A corresponding to the storage capacity of page PG is transferred to memory 30, controller 10 outputs TRG signal to processor 20 to make processor 20 send a write command. Thus, data A can be written into memory array 34 in units of page PG, so that data A can be written into memory array 34 efficiently.

[0072] The processor 20 updates the page register PGR in synchronization with writing of the data A to the memory array 34. Thus, the data A can be sequentially written to a plurality of pages PG of the memory array 34 without causing the controller 10 to identify the page PG to which the data A is to be written.

[0073] By providing the buffer 12 in the controller 10 to store the data A, the timing of receiving the input data signal IN from the external terminal ET can be asynchronous with the timing of transmitting the data A from the controller 10. For example, the controller 10 can store the data A in the buffer 12 in such a manner that the timing of receiving the final data A of one page PG (receiving timing) is consistent with the timing of transmitting the final data A to the memory 30 (transmitting timing). As a result, regardless of the rate at which the input data signal IN is received from the external terminal ET, the data A can be sent to the memory 30 in units of page PG, so that the data A can be efficiently written to the memory array 34.

[0074] Figure 4 1 is an overall block diagram showing an example of a biosensor according to one embodiment. Figure 1 Detailed description of the same or similar elements. Figure 4 The biosensor 200 shown in FIG. 1 includes a controller 10A, which replaces Figure 1 10. In addition to Figure 1 In addition to the structure of the data processing device 100, the biosensor 200 further includes a battery 40, a DC / DC converter 50, a wireless communication unit 60, and an antenna 70. The processor 20 and the memory 30 are respectively connected to Figure 1 The processor 20 and the memory 30 in the embodiment are the same or similar. For example, the biosensor 200 is a wearable device capable of acquiring biological information from a living body. The biosensor 200 also functions as a data processing device that receives the biological information as data.

[0075] The controller 10A includes an amplifier AMP, an analog-to-digital converter ADC, and a buffer 12. The controller 10A receives a biological signal from a living body as a differential input voltage signal VINp / VINn via a pair of external terminals ET of the data processing device 100. The biological signal is biological information such as an electrocardiogram waveform, a brain wave, a pulse, blood pressure, oxygen saturation, body temperature, heart sound, or respiratory sound. The biosensor 200 can receive a plurality of biological signals of the same type in a plurality of terminal pairs, or can receive different types of biological information in a plurality of terminal pairs.

[0076] The amplifier AMP differentially amplifies the input voltage signal VINp / VINn received by a pair of external terminals ET, and outputs the amplified differential signal to the analog-to-digital converter ADC. The analog-to-digital conversion circuit ADC converts the differential signal received from the amplifier AMP into digital data. The controller 10A sequentially stores the digital data generated by the analog-to-digital conversion circuit ADC in the buffer 12.

[0077] The battery 40 outputs the power supply voltage VCC1 to the DC / DC converter 50. The DC / DC converter 50 uses the power supply voltage VCC1 to generate power supply voltages VCC2 and VCC3. For example, the power supply voltage VCC2 is used as an operating power supply for the processor 20 and the memory 30, and as an operating power supply for the digital circuit installed in the controller 10A. For example, the power supply voltage VCC3 is used as an operating power supply for analog circuits such as the amplifier AMP and the analog-to-digital conversion circuit ADC installed in the controller 10. Note that the memory 30 can also be provided with a power supply voltage for programming data. In this case, the DC / DC converter 50 can generate a power supply voltage for programming.

[0078] Under the control of the processor 20, the wireless communication unit 60 communicates with an external device located outside the biosensor 200 via the antenna 70. For example, the processor 20 transmits the biological information stored in the memory 30 to the external device via the wireless communication unit 60.

[0079] The operations of the controller 10A, the processor 20 and the memory 30 are similar to Figure 2 and Figure 3 The actions shown are the same. Note that the controller 10A may be implemented in an ASIC or an FPGA.

[0080] Figure 5 and Figure 6 Yes means Figure 4 A flowchart of an example of the operation of the biosensor 200. First, in step S10, Figure 2 and Figure 3 Similarly to step (1), the processor 20 sets the register of the controller 10A. Then, in step S12, Figure 2 and Figure 3 In step (2), the processor 20 performs initial settings on the memory 30.

[0081] Next, in step S14, the processor 20 waits for an instruction (start instruction) to start acquiring biological information from outside the biosensor 200. When the processor 20 receives the start instruction, step S16 is executed. For example, the processor 20 receives the start instruction via the wireless communication unit 60. In step S16, the processor 20 sets the controller 10A as the master device and changes from the normal mode to the low power consumption mode (sleep).

[0082] Next, in step S18, the controller 10A acquires biological information and stores the acquired biological information in the buffer 12. Next, in step S20, Figure 2 and Figure 3 In step (3), the controller 10A similarly sends the biological information stored in the buffer 12 to the memory 30.

[0083] Next, in step S22, the controller 10A determines whether or not one PG page of biological information has been transferred to the memory 30. When the controller 10A has transferred one PG page of biological information to the memory 30, the execution Figure 6 When the controller 10A has not transferred the biological information of one PG page to the memory 30, step S18 is executed.

[0084] exist Figure 6 In step S24, Figure 2 and Figure 3 Similarly, in step (4), the controller 10A outputs the trigger signal TRG of the active level to the trigger signal line TRG. Next, in step S26, the processor 20 returns to the normal mode (sleep release) from the low power consumption mode based on the TRG signal.

[0085] Next, in step S28, Figure 2 and Figure 3 Similarly, in step (5), the processor 20 generates status information and sends the generated status information to the memory 30. Then, in step S30, Figure 2 and Figure 3 Similarly, in step (6), the processor 20 sends a write command to the memory 30. Then, in step S32, the memory 30 that receives the write command writes the biometric information held in the cache 32 into a page PG indicated by a page number held in the page register PGR among a plurality of page PGs of the memory array 34.

[0086] Next, in step S34, Figure 2 and Figure 3 Similarly, in step (7), the processor 20 sends a page switching command to the memory 30. Next, in step S36, the memory 30 that has received the page switching command updates the page number held in the page register PGR to set the next page PG to which the biometric information is to be written.

[0087] Next, in step S38, the processor 20 determines whether an instruction (end instruction) for ending the acquisition of biological information has been received from outside the biosensor 200. For example, the processor 20 receives the end instruction via the wireless communication unit 60. If the end instruction is received, the processor 20 ends the acquisition of biological information. Figure 5 and Figure 6If the processor 20 does not receive the end instruction, step S16 of FIG. 15 is executed. Note that although the biosensor 200 receives an instruction for ending the acquisition of bio-information at any timing, the biosensor 200 performs the operation until step S38 regardless of the timing of receiving the end instruction, and then ends the acquisition of bio-information. Thus, the bio-information can be written to the memory array 34 in units of page PG.

[0088] As described above, this embodiment can also obtain Figures 1 to 3 The same effect as the data processing device 100 shown in FIG. 1 can be achieved. For example, the processor 20 does not control the transfer of biological information to the memory 30, but controls the sending of a write command to the memory 30. Thus, for example, when the memory 30 is replaced with another memory having a different command specification, it can be handled by changing the program executed by the processor 20. As a result, it is possible to provide a biosensor 200 that can write biological information to the memory while suppressing an increase in power consumption of the processor 20 even when any of the memories having various command specifications is installed.

[0089] The processor 20 is in sleep mode while the biological information is being transferred from the controller 10 to the memory 30, and is released from sleep mode based on a TRG signal output from the controller 10 after a predetermined amount of biological information has been transferred to the memory 30. Thus, compared with a case where data is transferred to the memory 30 by a program executed by the processor 20, the power consumption of the processor 20 can be significantly reduced.

[0090] Using the MOSI signal line as a common serial data line, biological information, data, a write command, or a page switch command is transmitted from the controller 10 to the memory 30, from the processor 20 to the controller 10, and from the processor 20 to the memory 30. Thus, the number of wirings formed on the substrate on which the controller 10, the processor 20, and the memory 30 are mounted can be minimized to perform Figure 5 and Figure 6 As a result, the size of the substrate can be reduced, and thus the cost of the biosensor 200 can be reduced.

[0091] Whenever biometric information corresponding to the storage capacity of page PG is transferred to memory 30, controller 10 outputs TRG signal to processor 20 to cause processor 20 to send a write command. Thus, biometric information can be written into memory array 34 in units of page PG, thereby efficiently writing biometric information into memory array 34.

[0092] The processor 20 updates the page register PGR in synchronization with writing of the biological information to the memory array 34. Therefore, the biological information can be sequentially written to a plurality of pages PG of the memory array 34 without causing the controller 10 to recognize the page PG to which the biological information is written.

[0093] By providing the buffer 12 for storing the biometric information in the controller 10, the timing of receiving the input voltage signal VINp / VINn from the input voltage signal terminal VINp / VINn can be desynchronized with the timing of transmitting the biometric information from the controller 10. As a result, regardless of the rate at which the input voltage signal VINp / VINn is received from the input voltage signal terminal VINp / VINn, the biometric information can be sent to the memory 30 in units of page PG, so that the biometric information can be efficiently written in the memory array 34.

[0094] As mentioned above, although this invention was demonstrated based on each embodiment, this invention is not limited to the embodiment specifically disclosed, and these points can be changed within the range which does not impair the meaning of this invention.

[0095] The embodiments of the present invention are as follows, for example.

[0096] <1>

[0097] A data processing device, comprising:

[0098] A memory, comprising a first buffer for holding data and a memory array, wherein upon receiving a write command, the data held in the first buffer is written into the memory array;

[0099] a controller that transfers data received from the outside to the first buffer and outputs a trigger signal based on the transfer of a prescribed amount of data to the first buffer; and

[0100] The processor sends the write command to the memory based on receiving the trigger signal.

[0101] <2>

[0102] The data processing device according to <1>, wherein:

[0103] The controller, the processor and the memory are connected to each other via a common data line.

[0104] The processor has a function of outputting a chip select signal for selecting the memory to a chip select terminal of the memory,

[0105] The processor that has sent the write command to the memory goes into sleep mode after setting the chip select signal to a selected state of the memory, and recovers from the sleep mode upon receiving the trigger signal.

[0106] <3>

[0107] The data processing device according to <2>, wherein:

[0108] The common data line is a serial data line,

[0109] The controller sends the data to the memory via the serial data line,

[0110] The processor sends the write command to the memory via the serial data line.

[0111] <4>

[0112] The data processing device according to any one of <1> to <3>, wherein:

[0113] The memory array has a plurality of pages as data writing units,

[0114] The prescribed amount transferred by the controller to the first buffer is an amount of data corresponding to a storage capacity of each of the plurality of pages.

[0115] <5>

[0116] The data processing device according to <2> or <3>, wherein:

[0117] The memory array has a plurality of pages for data writing,

[0118] The memory has a page register for holding page information, the page information indicating a page of the memory array to which data is to be written,

[0119] The processor updates the page information held by the page register before performing the hibernation.

[0120] <6>

[0121] The data processing device according to any one of <1> to <4>, wherein:

[0122] The controller includes a second buffer for holding data received from an external terminal before transferring the data to the first buffer, and transfers data held in the second buffer to the first buffer.

[0123] <7>

[0124] A biosensor comprising:

[0125] A memory, comprising a first buffer for holding data and a memory array, wherein upon receiving a write command, the biometric information held in the first buffer is written into the memory array;

[0126] a controller that transfers biological information received from the outside to the first buffer, and outputs a trigger signal based on the transfer of a prescribed amount of biological information to the first buffer; and

[0127] The processor sends the write command to the memory based on receiving the trigger signal.

[0128] This application claims priority based on patent application No. 2022-133919 filed with the Japan Patent Office on August 25, 2022, and cites all the contents described in the above application.

[0129] Description of Reference Numerals

[0130] 10, 10A controller

[0131] 12 Buffer

[0132] 20 Processors

[0133] 30 Memory

[0134] 32 Cache

[0135] 34 Memory Array

[0136] 40 Batteries

[0137] 50 DC / DC Converter

[0138] 60 Wireless Communications Department

[0139] 70 Antenna

[0140] 100 Data processing device

[0141] 200 Biosensors

[0142] AMP

[0143] ADC Analog-to-Digital Converter

[0144] ET External terminal

[0145] IN Input data signal

[0146] PG Page

[0147] PGR Page Register

[0148] VINp / VINn input voltage signal.

Claims

1. A data processing device, comprising: A memory, comprising a first buffer for holding data and a memory array, wherein upon receiving a write command, the data held in the first buffer is written into the memory array; a controller that transfers data received from the outside to the first buffer and outputs a trigger signal based on the transfer of a specified amount of data to the first buffer; as well as The processor sends the write command to the memory based on receiving the trigger signal.

2. The data processing device according to claim 1, wherein: The controller, the processor and the memory are connected to each other via a common data line. The processor has a function of outputting a chip select signal for selecting the memory to a chip select terminal of the memory, The processor that has sent the write command to the memory goes into sleep mode after setting the chip select signal to a selected state of the memory, and recovers from the sleep mode upon receiving the trigger signal.

3. The data processing device according to claim 2, wherein: The common data line is a serial data line, The controller sends the data to the memory via the serial data line, The processor sends the write command to the memory via the serial data line.

4. The data processing device according to any one of claims 1 to 3, wherein: The memory array has a plurality of pages as data writing units, The prescribed amount transferred by the controller to the first buffer is an amount of data corresponding to a storage capacity of each of the plurality of pages.

5. The data processing device according to claim 2 or 3, wherein: The memory array has a plurality of pages for data writing, The memory has a page register for holding page information, the page information indicating a page of the memory array to which data is to be written, The processor updates the page information held by the page register before performing the hibernation.

6. The data processing device according to any one of claims 1 to 3, wherein: The controller includes a second buffer for holding data received from an external terminal before transferring the data to the first buffer, and transfers data held in the second buffer to the first buffer.

7. A biosensor comprising: A memory, comprising a first buffer for holding data and a memory array, wherein upon receiving a write command, the biometric information held in the first buffer is written into the memory array; a controller that transmits biological information received from the outside to the first buffer, and outputs a trigger signal based on the transmission of a prescribed amount of biological information to the first buffer; as well as The processor sends the write command to the memory based on receiving the trigger signal.

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