Data acquisition circuit and biosensor

Abstract

The data acquisition circuit includes a plurality of signal processing sections each having a first analog chopper circuit, an amplifier, a second analog chopper circuit, and an analog filter connected in series. The data acquisition circuit serially converts an analog signal from an analog filter into a digital signal in a first mode, and filters the digital signal after parallel conversion. And the data acquisition circuit serially converts the analog signal from the amplifier into a digital signal in the second mode, outputs the digital signal to the digital chopper circuit, and filters the digital signal from the digital chopper circuit after parallel conversion. This makes it possible to appropriately acquire biological information of a plurality of frequency bands.

Description

Technical Field

[0001] The invention relates to a data acquisition circuit and a biosensor. Background Art

[0002] For example, a biosensor for acquiring biological information from a living body has an analog front end that amplifies a weak analog signal acquired as biological information and converts the amplified analog signal into a digital signal (for example, see Patent Document 1). A chopper amplifier for removing flicker noise (1 / f noise) generated when amplifying an analog signal is known (for example, see Patent Document 2). An oversampling data conversion circuit is known in which an analog chopper circuit is connected to the input of a Σ-Δ modulator, and a digital filter and a digital chopper circuit are connected in sequence to the output of the Σ-Δ modulator (for example, see Patent Document 3).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-163128

[0004] Patent Document 2: Japanese Patent Application Publication No. 2011-19156

[0005] Patent Document 3: U.S. Patent No. 8633843 Summary of the invention

[0006] <Problems to be Solved by the Invention>

[0007] Recently, in order to acquire a variety of biological information using one biosensor, there is a demand for multi-channel and broadband biosensors. However, no proposal has been made for a biosensor that meets such a demand and a data acquisition circuit installed in the biosensor.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data acquisition circuit and a biosensor capable of appropriately acquiring biological information in a plurality of frequency bands.

[0009] <Methods used to solve the problem>

[0010] The data acquisition circuit of an embodiment of the present invention is characterized in that it includes: a plurality of signal processing units, each having a first analog chopper circuit, an amplifier, a second analog chopper circuit and an analog filter connected in series, and receiving analog signals through the first analog chopper circuit respectively; a first conversion unit, which serially converts the analog signals output from the plurality of analog filters in a first mode, and serially converts the analog signals output from the plurality of amplifiers in a second mode; an analog-to-digital converter, which converts the analog signals serially converted by the first conversion unit into digital signals; a digital chopper circuit, which is connected to the output of the analog-to-digital converter; a second conversion unit, which converts the digital signals output from the analog-to-digital converter into parallel digital signals in the first mode, and converts the digital signals output from the digital chopper circuit into parallel digital signals in the second mode; and a plurality of digital filters, which respectively filter the parallel digital signals converted by the second conversion unit.

[0011] <Effects of the Invention>

[0012] According to the technology of the present disclosure, it is possible to provide a data acquisition circuit and a biosensor capable of appropriately acquiring biological information in a plurality of frequency bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram showing an overall configuration of an example of a biosensor including a data acquisition circuit according to one embodiment.

[0014] Figure 2 Yes means Figure 1 A circuit block diagram of an example of a circuit state of a data acquisition circuit.

[0015] Figure 3 Yes means Figure 1 A circuit block diagram of another example of the circuit state of the data acquisition circuit.

[0016] Figure 4 Yes means Figure 2 and Figure 3 Circuit diagram of an example of a chopper circuit.

[0017] Figure 5 Yes means Figure 2 FIG. 4 is a timing diagram showing an example of the operation of the data acquisition circuit in the digital chopping mode.

[0018] Figure 6 Yes means Figure 5 A timing diagram of the continuation of the action.

[0019] Figure 7 Yes means Figure 2 and Figure 3An explanatory diagram of an overview of the operations in the digital chopping mode and the analog chopping mode in the data acquisition circuit.

[0020] Figure 8 It means that in digital chopping mode Figure 2 An explanatory diagram of an example of frequency spectra of a digital signal before demodulation by the chopper circuit DCP and a digital signal output from the low-pass filter LPF (D).

[0021] Fig. 9 It is an explanatory diagram showing an example of the frequency band of the input signal that can be acquired in the normal mode and the wideband mode. DETAILED DESCRIPTION

[0022] Hereinafter, the mode for implementing the invention will be described with reference to the accompanying drawings. Hereinafter, the same reference numerals as the signal names are used for signal lines that transmit information such as signals. In addition, the same reference numerals as the voltage names are used for voltage lines that transmit voltages. It should be noted that in each of the accompanying drawings, the same reference numerals are given to the same components, and repeated descriptions are sometimes omitted.

[0023] Figure 1 1 is a general configuration diagram showing an example of a biosensor including a data acquisition circuit according to an embodiment. For example, the biosensor 100 is a wearable device capable of acquiring various biological information from a living body.

[0024] Figure 1 The biosensor 100 shown includes a data acquisition circuit 10, a control circuit 20, a memory 30, a battery 40, a DC / DC converter 50, and an antenna 60. Although not particularly limited, the data acquisition circuit 10, the control circuit 20, the memory 30, the battery 40, the DC / DC converter 50, and the antenna 60 are mounted on a circuit board installed in the biosensor 100.

[0025] For example, the data acquisition circuit 10 may be installed in an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). For example, the control circuit 20 may be installed in an SoC (System on Chip) or an FPGA. In addition, the data acquisition circuit 10 and the control circuit 20 may be installed in one FPGA.

[0026] For example, the memory 30 is an electrically rewritable nonvolatile memory such as a flash memory or a magnetoresistive random access memory (MRAM). When receiving power from the outside, the biosensor 100 may not include the battery 40. When receiving the power supply voltages VCC2 and VCC3 from the outside, the biosensor 100 may not include the battery 40 and the DC / DC converter 50.

[0027] The data acquisition circuit 10 receives differential input voltage signals VINp0 / VINn0, VINp1 / VINn1, VINp2 / VINn2, and VINp3 / VINn3 between four channels CH0-CH3 through eight input terminals IN, respectively. Hereinafter, when channels CH0-CH3 are described without distinction, they are also referred to as channels CH. When input voltage signals VINp0-VINp3 are described without distinction, they are also referred to as input voltage signals VINp, and when input voltage signals VINn0-VINn3 are described without distinction, they are also referred to as input voltage signals VINn. It should be noted that the number of channels of the data acquisition circuit 10 is not limited to four channels, as long as there are multiple channels.

[0028] For example, the input voltage signal VINp / VINn is a biological signal obtained from a biological body via electrodes or various sensors, and represents biological information. The biological information is at least one of an electrocardiogram waveform, an electroencephalogram, a pulse, blood pressure, oxygen saturation, body temperature, heart sounds, or breathing sounds. The biosensor 100 can obtain a plurality of biological information of the same type on a plurality of channels CH, or can obtain different types of biological information on a plurality of channels.

[0029] The data acquisition circuit 10 amplifies the received input voltage signal VINp / VINn, removes noise, and outputs it as a digital output signal DOUT (DOUT0-DOUT3) to, for example, the control circuit 20. The digital output signal DOUT is a signal obtained by processing the input voltage signal VINp / VINn in the channel CH having the same value at the end. Figure 2 and Figure 3 An example of the data acquisition circuit 10 is shown in FIG.

[0030] The control circuit 20 includes, for example, an MCU (microcontroller unit) 22 and a wireless communication unit 24. The MCU 22 controls the overall operation of the biosensor 100 by executing a control program. For example, the MCU 22 can output an acquisition start instruction to start acquiring biological information to the data acquisition circuit 10 through the signal line SIG, and can also output an acquisition stop instruction to stop acquiring biological information to the data acquisition circuit 10. It should be noted that the information exchange between the control circuit 20 and the data acquisition circuit 10 can be performed through a serial interface such as SPI (Serial Peripheral Interface: registered trademark).

[0031] MCU22 receives the digital output signal DOUT (biological information) output from the data acquisition circuit 10, and writes the received biological information into the memory 30. MCU22 reads out the biological information stored in the memory 30, and outputs it to the wireless communication unit 24. Although not particularly limited, the control circuit 20 and the memory 30 can be connected via a serial interface such as SPI. It should be noted that the data acquisition circuit 10 can also write the digital output signals DOUT0-DOUT3 directly into the memory 30. In addition, MCU22 can receive a biological information acquisition start instruction or an acquisition stop instruction from the outside via the wireless communication unit 24, and control the operation of the data acquisition circuit 10.

[0032] Under the control of the MCU 22, the wireless communication unit 24 communicates with an external device located outside the biosensor 100 via the antenna 60. For example, the biological information sent by the wireless communication unit 24 to the external device may be the biological information retained in the memory 30, or may be the biological information output from the data acquisition circuit 10 before being written into the memory 30.

[0033] The battery 40 outputs the power supply voltage VCC1 to the DC / DC converter 50. The DC / DC converter 50 uses the power supply voltage VCC1 to generate power supply voltages VCC2 and VCC3. For example, the power supply voltage VCC2 is used as an operating power supply for the control circuit 20 and the memory 30, and as an operating power supply for the digital circuit installed in the data acquisition circuit 10. For example, the power supply voltage VCC3 is used as an operating power supply for the analog circuit mounted in the data acquisition circuit 10. It should be noted that the memory 30 can also be provided with a power supply voltage for programming data. In this case, the DC / DC converter 50 can generate the power supply voltage for programming.

[0034] Figure 2 Yes means Figure 1 1 is a circuit block diagram of an example of a circuit state of the data acquisition circuit 10 shown in FIG. The data acquisition circuit 10 includes a chopper circuit ACP1, an amplifier AMP, a switch SW1, a chopper circuit ACP2, an analog low-pass filter LPF (A), a switch SW2, and a digital low-pass filter LPF (D) corresponding to each channel CH0-CH3. For channels CH0-CH3, the data acquisition circuit 10 includes a multiplexer MUX, an analog-to-digital converter ADC, a chopper circuit DCP, a switch SW3, and a demultiplexer DEMUX. In addition, the data acquisition circuit 10 includes a control circuit CNTL and a clock generation circuit CLKGEN for controlling the operation of the switches SW1-SW3.

[0035] The chopper circuit ACP1, the amplifier AMP, the switch SW1, the chopper circuit ACP2 and the analog low-pass filter LPF(A) are an example of a signal processing unit. The switch SW1 is an example of a third selection unit. The switch SW2 and the analog-to-digital converter ADC are an example of a first conversion unit. The switch SW3 and the demultiplexer DEMUX are an example of a second conversion unit. The switch SW2 is an example of a first selection unit, and the switch SW3 is an example of a second selection unit.

[0036] Each chopper circuit ACP1 operates as a modulator that modulates the input voltage signal VINp / VINn (analog signal) in synchronization with the chopper clock CCLK, and outputs a differential voltage signal obtained by modulation to the amplifier AMP. The chopper circuit ACP1 is an example of a first analog chopper circuit that modulates a voltage signal. The chopper clock CCLK is an example of a first clock.

[0037] Each amplifier AMP amplifies the differential voltage signal received from the chopper circuit ACP1 and outputs the amplified differential voltage signal to the switch SW1. For example, the amplifier AMP of the channel CH0 outputs the differential voltage signal VINp0CP / VINn0CP. The switch SW1 connects the output of the amplifier AMP to the switch SW2 or the chopper circuit ACP2 based on the control signal from the control circuit CNTL.

[0038] Each chopper circuit ACP2 operates as a demodulator that demodulates a voltage signal (difference) output from the amplifier AMP in synchronization with the chopper clock CCLK, and outputs a differential voltage signal obtained by demodulation to the low-pass filter LPF (A). The chopper circuit ACP2 is an example of a second analog chopper circuit that demodulates a voltage signal.

[0039] Each low-pass filter LPF (A) removes the high-frequency component of the voltage signal received from the chopper circuit ACP2, and outputs the voltage signal with the high-frequency component removed to the switch SW2. The switch SW2 connects the output of the amplifier AMP or the output of the low-pass filter LPF (A) to the multiplexer MUX based on the control signal from the control circuit CNTL.

[0040] The multiplexer MUX sequentially selects the differential voltage signals of the channels CH0-CH3 provided via the switch circuit SW2 according to the selection signal SEL[0:3] output from the analog-to-digital converter ADC. The multiplexer MUX outputs the selected differential voltage signals to the analog-to-digital converter ADC. The multiplexer MUX functions as a parallel-to-serial conversion circuit for serially converting voltage signals output in parallel from a plurality of low-pass filters LPF(A) or voltage signals output in parallel from a plurality of amplifiers AMP. An example of the operation of the multiplexer MUX is shown in FIG. Figure 5 Shown in.

[0041] By serially converting the plurality of voltage signals provided in parallel via the switch SW2 by the multiplexer MUX, one analog-to-digital converter ADC can convert the input voltage signals VINp / VINn of four channels into digital values. Since a plurality of analog-to-digital converters ADC are not required, an increase in the chip size of the data acquisition circuit 10 can be suppressed even when processing a plurality of input voltage signals VINp / VINn.

[0042] The analog-to-digital converter ADC converts the differential voltage signal received from the multiplexer MUX into a digital value in synchronization with the sampling clock SCLK, and outputs it as a digital signal ADCOUT. The sampling clock SCLK is an example of a second clock. In addition, the analog-to-digital converter ADC generates a 4-bit selection signal SEL[0:3] using the sampling clock SCLK, and outputs the generated selection signal SEL[0:3] to the multiplexer MUX. For example, the frequency of the sampling clock SCLK is twice the frequency of the chopping clock CCLK.

[0043] Based on the sampling clock SCLK, the analog-to-digital converter ADC sequentially generates the selection signal SEL[0:3], which is set to a high level during one cycle of the chopping clock CCLK. That is, each bit of the selection signal SEL[0:3] is set to a high level during one cycle of the chopping clock CCLK in accordance with every four cycles of the chopping clock CCLK. By using the sampling clock SCLK to generate the selection signal SEL[0:3] by the analog-to-digital converter ADC, it is not necessary to provide a circuit for generating the selection signal SEL[0:3]. As a result, the circuit scale of the data acquisition circuit 10 can be reduced.

[0044] The chopper circuit DCP operates as a demodulator that demodulates the digital signal ADCOUT received from the analog-to-digital converter ADC in synchronization with the chopper clock CCLK, and outputs a digital signal DCPOUT obtained by demodulation to the switch SW3. The chopper circuit DCP is a digital chopper circuit that demodulates a digital signal.

[0045] The switch SW3 connects the output of the analog-to-digital converter ADC or the output of the chopper circuit DCP to the demultiplexer DEMUX based on a control signal from the control circuit CNTL.

[0046] The demultiplexer DEMUX outputs the digital signals of the channels CH0-CH3 provided via the switch circuit SW3 as one of the digital signals DMXOUT0-DMXOUT3 based on the control signal received from the control circuit CNTL. Hereinafter, when the digital signals DMXOUT0-DMXOUT3 are described without distinction, they are referred to as the digital signal DMXOUT. The digital signal DMXOUT is a signal corresponding to the channel CH having the same numerical value at the end.

[0047] The demultiplexer DEMUX functions as a serial-parallel conversion circuit for converting a serial digital signal ADCOUT output from the analog-to-digital converter ADC or a serial digital signal DCPOUT output from the chopper circuit DCP into a parallel digital signal DMXOUT. Figure 6 Shown in.

[0048] Each low pass filter LPF (D) performs filtering for removing high frequency components of the digital signal DMXOUT output from the demultiplexer DEMUX and outputs it as a digital output signal DOUT (DOUT0-DOUT3). Thus, the data acquisition circuit 10 can output four digital output signals DOUT corresponding to the input voltage signals VINp / VINn of the four channels, respectively.

[0049] The data acquisition circuit 10 operates four low-pass filters LPF (D) in parallel to generate digital output signals DOUT corresponding to input signals VINp / VINn of four channels CH0-CH3. Thus, even if the low-pass filter LPF (D) performs complex filtering processing, the four digital output signals DOUT0-DOUT3 can be output in real time.

[0050] The clock generation circuit CLKGEN generates a chopping clock CCLK and a sampling clock SCLK.

[0051] Figure 2 The state of the switches SW1, SW2, and SW3 indicates the state of the digital chopping mode in which the chopping circuit ACP2 and the low-pass filter LPF(A) are bypassed and the digital chopping circuit DCP is used as a demodulator. In the digital chopping mode, the switches SW1 and SW2 separate the chopping circuit ACP2 and the low-pass filter LPF(A) from the action path by outputting the output of the amplifier AMP to the multiplexer MUX. The digital chopping mode is an example of the second mode.

[0052] In the digital chopping mode, the switch SW1 disconnects the output of the amplifier AMP from the chopping circuit ACP2, thereby reducing the charge and discharge current caused by the operation of the chopping circuit ACP2. As a result, for example, the propagation delay time of the voltage signal VINp0CP / VINn0CP output from the amplifier AMP to the multiplexer MUX can be reduced, thereby enabling the data acquisition circuit 10 to operate at high speed. In addition, the power consumption of the data acquisition circuit 10 can be reduced.

[0053] In the digital chopping mode, the switch SW3 connects the output of the chopping circuit DCP to the demultiplexer DEMUX. That is, in the digital chopping mode, the chopping circuit ACP1, the amplifier AMP, and the chopping circuit DCP function as a so-called chopping amplifier, and the 1 / f noise generated in the amplifier AMP is modulated by the chopping circuit DCP and removed by the low-pass filter LPF (D).

[0054] For example, in the digital chopping mode, the data acquisition circuit 10 can acquire biological information processed at a relatively high sampling rate, such as heart sounds or breathing sounds. Hereinafter, the digital chopping mode is also referred to as a broadband mode.

[0055] It should be noted that the data acquisition circuit 10 may not include the switch SW1. In this case, the output of the amplifier AMP is always connected to the chopping circuit ACP2 and the switch SW2. In the absence of the switch SW1, in the digital chopping mode, the supply of the chopping clock CCLK to the chopping circuit ACP2 may be stopped, and the chopping clock terminal CCLK of the chopping circuit ACP2 may be fixed at a low level. In addition, the data acquisition circuit 10 may have a switch between the analog-to-digital converter ADC and the chopping circuit DCP. In this case, the switch connects the analog-to-digital converter ADC to the chopping circuit DCP in the digital chopping mode, and cuts off the connection between the analog-to-digital converter ADC and the chopping circuit DCP in the analog chopping mode.

[0056] In addition, the demultiplexer DEMUX and the low-pass filter LPF (D) may also be configured outside the data acquisition circuit 10 (for example, Figure 1 In this case, the chip size of the data acquisition circuit 10 can be reduced. In addition, the output of the switch SW3 (the amount of four channels) can be output as a 1-bit digital output signal DOUT. Therefore, the number of digital output signal lines between the data acquisition circuit 10 and the control circuit 20 can be reduced. As a result, the size of the substrate on which the data acquisition circuit 10, the control circuit 20, etc. are mounted can be reduced.

[0057] Figure 3 Yes means Figure 1 FIG. 1 is a circuit block diagram of another example of the circuit state of the data acquisition circuit 10. In addition to the different states of the switches SW1-SW3, Figure 3 and Figure 2 same. Figure 3 The states of the switches SW1 to SW3 represent the state of the analog chopping mode in which the chopping circuit DCP is bypassed using the chopping circuit ACP2 and the low-pass filter LPF(A). The analog chopping mode is an example of the first mode.

[0058] In the analog chopping mode, the switch SW1 connects the output of the amplifier AMP to the chopping circuit ACP2, and the switch SW2 connects the output of the low-pass filter LPF(A) to the multiplexer MUX. In addition, in the analog chopping mode, the chopping circuit DCP is separated from the operation path.

[0059] That is, in the analog chopping mode, a chopper amplifier based on the chopper circuit ACP1, the amplifier AMP, and the chopper circuit ACP2 operates, and 1 / f noise generated in the amplifier AMP is modulated by the chopper circuit ACP2 and removed by the low-pass filter LPF(A).

[0060] For example, in the analog chopping mode, the data acquisition circuit 10 can acquire biological information processed at a relatively low sampling rate, such as electrocardiogram waveforms, brain waves, pulse, blood pressure, oxygen saturation or body temperature, etc. Hereinafter, the analog chopping mode is also referred to as the normal mode.

[0061] Figure 4 Yes means Figure 2 and Figure 3 A circuit diagram of an example of chopping circuits ACP1, ACP2, and DCP. Each chopping circuit ACP1 and ACP2 is a circuit identical to each other. Each chopping circuit ACP1 and ACP2 includes a pair of switches SWa and a pair of switches SWb. It should be noted that, as described above, if the data acquisition circuit 10 does not have the switch SW1, the supply of the chopping clocks CCLK and CCLKB to the chopping circuit ACP2 can be stopped during the digital chopping mode. In this case, the chopping clocks CCLK and CCLKB are fixed to a low level and a high level, respectively.

[0062] The switch SWa is turned on during the high level period of the chopping clock CCLK, and outputs the input voltage signal VINp as the output voltage VOUTn, and outputs the input voltage signal VINn as the output voltage VOUTp. The switch SWb is turned on during the high level period of the chopping clock CCLKB, and outputs the input voltage signal VINp as the output voltage VOUTp, and outputs the input voltage signal VINn as the output voltage VOUTn. The phase of the chopping clock CCLKB is opposite to the phase of the chopping clock CCLK, and the high level period of the chopping clock CCLKB does not overlap with the high level period of the chopping clock CCLK.

[0063] Each chopper circuit ACP1, ACP2 switches the switch SWa, SWb on / off once in one cycle of the chopper clock CCLK, and inverts the polarity of the output signals VOUTP, VOUTN. The operation of each chopper circuit ACP1, ACP2 is mathematically equivalent to multiplying the waveform of the input voltage signal VINp, VINn by a rectangular wave.

[0064] The chopping circuit DCP includes an exclusive OR circuit EOR and a selector SEL. The exclusive OR circuit EOR receives a digital input signal DIN and a logic value "1", and outputs a signal in which the logic of the digital input signal DIN has been inverted to the selector SEL. During the low level period of the chopping clock CCLK, the selector SEL outputs the digital input signal DIN as a digital output signal DOUT.

[0065] During the high level period of the chopping clock CCLK, the selector SEL outputs a signal obtained by inverting the logic of the digital input signal DIN as the digital output signal DOUT. Thus, the chopping circuit DCP outputs the digital output signal DOUT obtained by inverting the sign of the digital input signal DIN during the period of the chopping clock CCLK.

[0066] Figure 5 and Figure 6 Yes means Figure 2 The timing diagram of an example of the operation of the data acquisition circuit 10 in the digital chopping mode is shown in FIG. Figure 5 The waveform of the input voltage signal VINp0 of the channel CH0 is illustrated, but the data acquisition circuit 10 receives differential input voltage signals VINp and VINn on all channels CH0 - CH3 .

[0067] First, the chopper circuit ACP1 inverts the polarity of the differential input voltage signal VINp0 / VINn0 during the high level period of the chopper clock CCLK. The amplifier AMP amplifies the differential voltage whose polarity is inverted during the high level period of the chopper clock CCLK, and outputs the differential voltage signal VINp0CP / VINn0CP. Figure 5 , the waveform of the voltage VINn0CP is omitted. The symbol “-” marked below the waveform of the voltage signal VINp0CP indicates that the polarity is inverted. The symbol “+” marked below the waveform of the voltage signal VINp0CP indicates that the polarity is not inverted.

[0068] The multiplexer MUX receives a voltage signal (eg, VINp0CP) output from the amplifier AMP via switches SW1 and SW2. The multiplexer MUX sequentially selects a voltage output from the amplifier AMP of the channel CH corresponding to one of the 4-bit selection signals SEL[0:3] set to a high level in each cycle of the chopping clock CCLK.

[0069] The multiplexer MUX outputs the selected voltage signal to the analog-to-digital converter ADC. The input voltage signal VINp0 corresponding to the channel CH0 is selected during the high level period of the selection signal SEL[0], and is not selected during the high level period of other selection signals SEL[1:3]. It should be noted that the multiplexer MUX can also generate the selection signal SEL[0:3] internally by receiving a 2-bit selection signal that is repeatedly updated from 0 to 3 and decoding the received selection signal.

[0070] The analog-to-digital converter ADC sequentially converts the voltage signal received from the multiplexer MUX into a digital value ADCOUT in synchronization with the sampling clock SCLK. For example, the frequency of the sampling clock SCLK is twice or more than twice the frequency of the chopping clock CCLK. Therefore, the analog-to-digital converter ADC samples the voltage signal with a polarity of "-" and the voltage signal with a polarity of "+" in one cycle of the chopping clock CCLK.

[0071] Thus, the analog-to-digital converter ADC can sequentially obtain the voltage signals VINp0CP / VINn0CP with polarities of "-" and "+" as digital values ​​ADCOUT (data D0, D1, D2, D3). In addition, since the bits of the selection signal SEL[0:3] are sequentially set to high levels, the analog-to-digital converter ADC can sequentially obtain digital values ​​ADCOUT (data D0, D1, D2, D3) for each channel CH0-CH3.

[0072] Figure 6 In the embodiment, during the high level period of the chopping clock CCLK, the chopping circuit DCP inverts the sign of the digital value ADCOUT received from the analog-to-digital converter ADC and outputs it as a digital value DCPOUT. During the low level period of the chopping clock CCLK, the chopping circuit DCP outputs the digital value ADCOUT received from the analog-to-digital converter ADC as a digital value DCPOUT without inverting its sign. The data D0b and D2b represented in the digital signal DCPOUT indicate that the polarity is inverted.

[0073] During the high level period of the chopping clock CCLK, the digital value ADCOUT received by the chopping circuit DCP corresponds to the voltage signal VINp0CP / VINn0CP whose polarity is inverted and amplified in the chopping circuit ACP1. Thus, the digital value DCPOUT output from the chopping circuit DCP is returned to the polarity of the input voltage signal VINp / VINn provided to the data acquisition circuit 10 (demodulation).

[0074] The demultiplexer DEMUX outputs the digital value DCPOUT received from the chopping circuit DCP as a digital value DMXOUT (DMXOUT0-DMXOUT3) to any one of the four low-pass filters LPF (D). For example, each low-pass filter LPF (D) receives the digital value DMXOUT every four cycles of the chopping clock CCLK. In addition, the digital values ​​DMXOUT received by the four low-pass filters LPF (D) are offset one cycle of the chopping clock CCLK one by one.

[0075] Thus, the digital value ADCOUT serially output from the analog-to-digital converter ADC can be provided to the four low-pass filters LPF (D) as parallel digital values ​​DMXOUT corresponding to the channels CH0 to CH3, respectively.

[0076] After that, Figure 2 Each low-pass filter LPF (D) shown removes the high-frequency components of the received digital value DMXOUT and uses it as Figure 2 The digital output signal DOUT (DOUT0-DOUT3) is output as shown. For example, the digital output signal DOUT (DOUT0-DOUT3) is output to Figure 1 The control circuit 20.

[0077] It should be noted that, in addition to Figure 5 The output of the low-pass filter LPF(A) and Figure 6 In addition to the demultiplexer DEMUX outputting the digital signal ADCOUT as the digital signal DMXOUT, the action in the analog chopping mode is the same as Figure 5 and Figure 6 same.

[0078] Figure 7 Yes means Figure 2 and Figure 3 FIG. 1 is an explanatory diagram of the operation of the digital chopping mode and the analog chopping mode in the data acquisition circuit 10. In the digital chopping mode, the digital chopper amplifier is composed of the analog chopping circuit ACP1 and the amplifier AMP for modulation, and the digital chopping circuit DCP for demodulation connected to the output of the analog-to-digital converter ADC.

[0079] In the digital chopper amplifier, the modulated analog signal amplified by the amplifier AMP is converted into a digital signal and then demodulated by the digital chopper circuit DCP. Then, the 1 / f noise generated by the amplification of the amplifier AMP is moved to the high frequency side by the demodulated digital chopper circuit DCP and removed by the digital low-pass filter LPF (D). The passband of the digital low-pass filter LPF (D) is wider than that of the analog low-pass filter LPF (A), and the boundary of the frequency band that cuts off the signal is steep. Therefore, a wideband input voltage signal VINp / VINn with noise removed can be obtained as bio-information.

[0080] On the other hand, in the analog chopper mode, the analog chopper circuit ACP1 for modulation, the amplifier AMP, and the analog chopper circuit ACP2 for demodulation constitute an analog chopper amplifier (LNA: low noise amplifier). The 1 / f noise generated by the amplification of the amplifier AMP is moved to the high frequency region by the analog chopper circuit ACP2 and removed by the analog low-pass filter LPF (A). However, the analog low-pass filter LPF (A) has a narrower passband than the digital low-pass filter LPF (D), and the boundary of the frequency band of the cut-off signal is gentle, so the passband of the input voltage signal VINp / VINn is limited.

[0081] Figure 8 It means that in digital chopping mode Figure 2 An explanatory diagram of an example of a frequency spectrum between a digital signal before demodulation by the chopper circuit DCP and a digital signal output from the low-pass filter LPF (D).

[0082] Figure 8 The upper part indicates that Figure 2 The spectrum of the digital signal ADCOUT which is output by the analog-to-digital converter ADC and provided to the chopping circuit DCP. Figure 8 The lower part of the figure shows the spectrum of the digital signal DOUT output from the digital low-pass filter LPF(D). Although not particularly limited, Figure 8 In the embodiment, the frequency of the input voltage signal VINp / VINn is 11 Hz.

[0083] In the spectrum of the digital signal ADCOUT, the input voltage signal VINp / VINn represented by the digital signal ADCOUT is shifted to 16.384 kHz, which is the same frequency as the chopping clock CCLK, by modulation of the chopping circuit ACP1. The spectrum of the digital signal ADCOUT includes 1 / f noise and white noise.

[0084] On the other hand, in the spectrum of the digital signal DOUT, the input voltage signal VINp / VINn represented by the digital signal DOUT is returned to the original frequency 11Hz by demodulation of the chopper circuit DCP. In addition, the 1 / f noise moved to the high frequency band by demodulation of the chopper circuit DCP is removed by the low-pass filter LPF (D). For example, the SNDR (Signal to Noise and Distortion Ratio) of the digital signal DOUT is 60.1dB, which is good.

[0085] Fig. 9 This is an explanatory diagram showing an example of the frequency band of the input voltage signal VINp / VINn that can be obtained in the normal mode (analog chopping mode) and the wideband mode (digital chopping mode). The cutoff frequency of the input voltage signal VINp / VINn on the high-frequency band side is 350 Hz in the normal mode and 3.1 kHz in the wideband mode.

[0086] Therefore, the data acquisition circuit 10 can be operated in any appropriate mode of the analog chopping mode or the digital chopping mode according to the frequency band of the input voltage signal VINp / VINn. For example, the normal mode can sometimes reduce the white noise or external noise of the amplifier AMP compared to the broadband mode. In this case, in an application where only a narrow-band signal such as an electrocardiogram signal is acquired, it is best to acquire the signal in the normal mode. It should be noted that the cutoff frequency on the low-band side of the input voltage signal VINp / VINn is independent of the mode, for example, below 0.1 Hz.

[0087] As described above, in this embodiment, in the data acquisition circuit 10 and the biosensor 100 that can acquire a plurality of input voltage signals VINp / VINn by time division multiplexing, the frequency band in which the input voltage signals VINp / VINn can be acquired can be switched according to the operation mode. Therefore, for example, biological information (electrocardiographic waveform, brain wave, pulse, blood pressure, oxygen saturation, or body temperature, etc.) that can be processed at a relatively low sampling rate and biological information (heart sound or respiratory sound, etc.) that can be processed at a relatively high sampling rate can be processed by one biosensor 100.

[0088] That is, a data acquisition circuit 10 and a biosensor 100 capable of appropriately acquiring biological information of a plurality of frequency bands can be provided. In other words, for example, a multifunctional biosensor 100 having both an electrocardiograph function and a phonocardiograph function can be provided. In this case, the biosensor 100 does not need to include a data acquisition circuit for an electrocardiograph and a data acquisition circuit for a phonocardiograph. As a result, the cost of the multifunctional biosensor 100 can be reduced, and the size of the multi-type biosensor 100 can be reduced.

[0089] Furthermore, for example, by alternately switching the analog chopping mode and the digital chopping mode, biological information having a low frequency band and biological information having a high frequency band can be acquired in a time-division manner.

[0090] By using the multiplexer MUX and the demultiplexer DEMUX, the analog-to-digital converter ADC and the chopping circuit DCP can be used in common for a plurality of differential input voltage signals VINp / VINn. Thus, the circuit scale of the data acquisition circuit 10 can be reduced compared to the case where the analog-to-digital converter ADC and the chopping circuit DCP are provided for each of the plurality of differential input voltage signals VINp / VINn.

[0091] In the digital chopping mode, the output of the amplifier AMP is disconnected from the input of the chopping circuit ACP2 by the switch SW1 , and the supply of the chopping clock CCLK to the chopping circuit ACP2 is stopped, so that the power consumption of the data acquisition circuit 10 can be reduced.

[0092] Since the selection signal SEL[0:3] is generated by the analog-to-digital converter ADC using the sampling clock SCLK, it is not necessary to separately provide a circuit for generating the selection signal SEL[0:3]. Therefore, the circuit scale of the data acquisition circuit 10 can be reduced.

[0093] By operating the four low-pass filters LPF (D) in parallel, even when a complicated filtering process is performed using each low-pass filter LPF (D), the four digital output signals DOUT0 to DOUT3 can be output in real time.

[0094] In the digital chopping mode, the switch SW1 cuts off the connection between the output of the amplifier AMP and the chopping circuit ACP2, and the charging and discharging current caused by the operation of the chopping circuit ACP2 can be reduced. As a result, for example, the propagation delay time of the voltage signal VINp0CP / VINn0CP output from the amplifier AMP to the multiplexer MUX can be reduced, so that the data acquisition circuit 10 can be operated at a high speed. In addition, the power consumption of the data acquisition circuit 10 can be reduced.

[0095] As mentioned above, although this invention was demonstrated based on each embodiment, this invention is not limited to the embodiment specifically disclosed, and these points can be changed within the range which does not hinder the meaning of this invention.

[0096] For example, the data acquisition circuit is not limited to being applied to the biosensor 100. The data acquisition circuit 10 can be installed on a sensor for detecting signals such as temperature, light, pressure, and geomagnetism in addition to biological signals. In addition, for example, the data acquisition circuit 10 can also process a single-phase input signal instead of the differential input voltage signal VINp / VINn.

[0097] The embodiments of the present invention are as follows, for example.

[0098] <1>

[0099] A data acquisition circuit, comprising:

[0100] A plurality of signal processing units, each having a first analog chopper circuit, an amplifier, a second analog chopper circuit and an analog filter connected in series, and each receiving an analog signal through the first analog chopper circuit;

[0101] a first conversion section that serially converts analog signals output from the plurality of analog filters in a first mode and serially converts analog signals output from the plurality of amplifiers in a second mode;

[0102] an analog-to-digital converter, converting the analog signal serially converted by the first conversion unit into a digital signal;

[0103] A digital chopper circuit connected to the output of the analog-to-digital converter;

[0104] a second conversion section that converts the digital signal output from the analog-to-digital converter into a parallel digital signal in the first mode and converts the digital signal output from the digital chopper circuit into a parallel digital signal in the second mode; and

[0105] A plurality of digital filters respectively filter the parallel digital signals converted by the second conversion unit.

[0106] <2>

[0107] The data acquisition circuit according to <1>, wherein:

[0108] A plurality of said amplifiers operate in parallel,

[0109] The first analog chopper circuit, the second analog chopper circuit, and the digital chopper circuit operate in synchronization with a common first clock.

[0110] The first conversion unit has:

[0111] a first selection unit that selects analog signals outputted from the plurality of analog filters in a first mode and selects analog signals outputted from the plurality of amplifiers in a second mode; and

[0112] The multiplexer sequentially selects the plurality of analog signals selected by the first selection unit in each cycle of the first clock.

[0113] <3>

[0114] The data acquisition circuit according to <2>, wherein:

[0115] The analog-to-digital converter

[0116] sampling the analog signal in synchronization with a second clock having a frequency more than twice the frequency of the first clock,

[0117] A selection signal for causing the multiplexer to sequentially select any one of the plurality of analog signals is generated using the second clock.

[0118] <4>

[0119] The data acquisition circuit according to <2> or <3>, wherein:

[0120] The second conversion unit has:

[0121] a second selection unit that selects the digital signal output from the analog-to-digital converter in the first mode and selects the digital signal output from the digital chopper circuit in the second mode; and

[0122] a demultiplexer that sequentially outputs the digital signal selected by the second selection unit from a plurality of outputs in each cycle of the first clock,

[0123] A plurality of digital filters are respectively connected to the outputs of the demultiplexer.

[0124] <5>

[0125] The data acquisition circuit according to any one of <1> to <4>, comprising:

[0126] The third selection unit connects the output of the amplifier to the second analog chopper circuit in the first mode, and connects the output of the amplifier to the first conversion unit in the second mode.

[0127] <6>

[0128] The data acquisition circuit according to any one of <1> to <5>, wherein:

[0129] The analog filter and the digital filter are low pass filters.

[0130] <7>

[0131] A biosensor comprises a data acquisition circuit for acquiring biological information and a control circuit for controlling the operation of the data acquisition circuit, wherein:

[0132] The data acquisition circuit comprises:

[0133] A plurality of signal processing units, each having a first analog chopper circuit, an amplifier, a second analog chopper circuit, and an analog filter connected in series, and receiving an analog signal as the biological information through the first analog chopper circuit;

[0134] a first conversion section that serially converts analog signals output from the plurality of analog filters in a first mode and serially converts analog signals output from the plurality of amplifiers in a second mode;

[0135] an analog-to-digital converter, converting the analog signal serially converted by the first conversion unit into a digital signal;

[0136] A digital chopper circuit connected to the output of the analog-to-digital converter;

[0137] a second conversion section that converts the digital signal output from the analog-to-digital converter into a parallel digital signal in the first mode and converts the digital signal output from the digital chopper circuit into a parallel digital signal in the second mode; and

[0138] A plurality of digital filters respectively filter the parallel digital signals converted by the second conversion unit.

[0139] This application claims the priority based on patent application No. 2022-133918 filed with the Japan Patent Office on August 25, 2022, and cites all the contents described in the above application.

[0140] Description of Reference Numerals

[0141] 10 Data acquisition circuit

[0142] 20 Control Circuit

[0143] 22 MCU

[0144] 24 Wireless Communications Department

[0145] 30 Memory

[0146] 40 Batteries

[0147] 50 DC / DC Converter

[0148] 60 Antenna

[0149] 100 Biosensors

[0150] ACP1, ACP2 chopper circuit

[0151] ADC Analog-to-Digital Converter

[0152] ADCOUT digital signal

[0153] AMP

[0154] CCLK Chopping Clock

[0155] CH0-CH3 Channels

[0156] CLKGEN Clock generation circuit

[0157] DCP Chopper Circuit

[0158] DCPOUT digital signal

[0159] DEMUX Demultiplexer

[0160] DMXOUT0-DMXOUT3 digital signal

[0161] DOUT0-DOUT3 digital output signal

[0162] IN Input terminal

[0163] LPF(A), LPF(D) Low pass filter

[0164] MUX Multiplexer

[0165] SCLK Sampling Clock

[0166] SW1-SW3 switches

[0167] VINn0-VINn3 input voltage signal

[0168] VINn0CP voltage signal

[0169] VINp0-VINp3 input voltage signal

[0170] VINp0CP voltage signal.

Claims

1. A data acquisition circuit, comprising: A plurality of signal processing units, each having a first analog chopper circuit, an amplifier, a second analog chopper circuit and an analog filter connected in series, and each receiving an analog signal through the first analog chopper circuit; a first conversion section that serially converts analog signals output from the plurality of analog filters in a first mode and serially converts analog signals output from the plurality of amplifiers in a second mode; an analog-to-digital converter, converting the analog signal serially converted by the first conversion unit into a digital signal; A digital chopper circuit connected to the output of the analog-to-digital converter; a second conversion section that converts the digital signal output from the analog-to-digital converter into a parallel digital signal in the first mode and converts the digital signal output from the digital chopper circuit into a parallel digital signal in the second mode; and A plurality of digital filters respectively filter the parallel digital signals converted by the second conversion unit.

2. The data acquisition circuit according to claim 1, wherein: A plurality of said amplifiers operate in parallel, The first analog chopper circuit, the second analog chopper circuit, and the digital chopper circuit operate in synchronization with a common first clock. The first conversion unit has: a first selection unit that selects analog signals outputted from the plurality of analog filters in a first mode and selects analog signals outputted from the plurality of amplifiers in a second mode; as well as The multiplexer sequentially selects the plurality of analog signals selected by the first selection unit in each cycle of the first clock.

3. The data acquisition circuit according to claim 2, wherein: The analog-to-digital converter sampling the analog signal in synchronization with a second clock having a frequency more than twice the frequency of the first clock, A selection signal for causing the multiplexer to sequentially select any one of the plurality of analog signals is generated using the second clock.

4. The data acquisition circuit according to claim 2 or 3, wherein: The second conversion unit has: a second selection unit that selects the digital signal output from the analog-to-digital converter in the first mode and selects the digital signal output from the digital chopper circuit in the second mode; as well as a demultiplexer that sequentially outputs the digital signal selected by the second selection unit from a plurality of outputs in each cycle of the first clock, A plurality of digital filters are respectively connected to the outputs of the demultiplexer.

5. The data acquisition circuit according to any one of claims 1 to 3, comprising: The third selection unit connects the output of the amplifier to the second analog chopper circuit in the first mode, and connects the output of the amplifier to the first conversion unit in the second mode.

6. The data acquisition circuit according to any one of claims 1 to 3, wherein: The analog filter and the digital filter are low pass filters.

7. A biosensor comprising a data acquisition circuit for acquiring biological information and a control circuit for controlling the operation of the data acquisition circuit, wherein: The data acquisition circuit comprises: A plurality of signal processing units, each having a first analog chopper circuit, an amplifier, a second analog chopper circuit, and an analog filter connected in series, and receiving an analog signal as the biological information through the first analog chopper circuit; a first conversion section that serially converts analog signals output from the plurality of analog filters in a first mode and serially converts analog signals output from the plurality of amplifiers in a second mode; an analog-to-digital converter, converting the analog signal serially converted by the first conversion unit into a digital signal; A digital chopper circuit connected to the output of the analog-to-digital converter; a second conversion section that converts the digital signal output from the analog-to-digital converter into a parallel digital signal in the first mode and converts the digital signal output from the digital chopper circuit into a parallel digital signal in the second mode; and A plurality of digital filters respectively filter the parallel digital signals converted by the second conversion unit.

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