Overhead-free data coding

Abstract

A method of encoding data for transmission includes aligning and marking a start of a data stream; receiving, at a communication interface comprising a scrambler (111C1), a digitized signal comprising formatted digital data; scrambling the formatted digital data into scrambled digital data to reduce spectral bandwidth and enhance a balance between the number of digital values of the digital data without adding coding bits to the formatted digital data; and outputting the scrambled digital data.

Description

Background Art

[0001] In digital communication circuits, DC balance refers to the balance between the number of digital bits in a signal. In digital communication circuits, ensuring that the same number of 1s and 0s are transmitted can reduce the low-frequency content of the transmission, thereby improving signal fidelity, which in turn makes systems with digital communication circuits more robust against low-frequency noise. Clock recovery circuits require a certain number of transitions in each bit string (run length) to ensure a stable clock. The 8b / 10b encoding scheme guarantees DC balance and short run length by mapping an 8-bit input word into a 10-bit code, thereby running an additional 25% data overhead and data processing. Other encoding schemes (for example, 64b / 66b or 128b / 132b encoding) provide less overhead and also rely on scrambling methods to "statistically" guarantee DC balance, where the overhead required bits guarantee the run length. Summary of the invention

[0002] According to one aspect of the present disclosure, a method of encoding data for transmission includes: aligning and marking the beginning of a data stream; receiving a digitized signal including formatted digital data at a communication interface including a scrambler; scrambling the formatted digital data into scrambled digital data to reduce spectral bandwidth and enhance the balance between the number of digital values ​​of the digital data without adding coded bits to the formatted digital data; and outputting the scrambled digital data.

[0003] According to another aspect of the present disclosure, a digital interface includes a receiver, a scrambler, and an output unit. The receiver receives a digitized signal including formatted digital data, and the receiver includes a receiving logic device, which is suitable for detecting an alignment code and aligning with respect to the code. The scrambler scrambles the formatted digital data into scrambled digital data to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data, and does not add coded bits to the formatted digital data. The output unit outputs the scrambled digital data. In the data flow between the ultrasonic transducer and the processing system, the reduction of overhead coded bits reduces the data rate and processing load and improves the overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The exemplary embodiments may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that the various features are not necessarily drawn to scale. In fact, the dimensions may be increased or decreased arbitrarily for clarity of discussion. Where applicable and feasible, the same reference numerals refer to the same elements.

[0005] Figure 1A A system for overhead-free data encoding according to a representative embodiment is illustrated.

[0006] Figure 1B Another system for overhead-free data encoding according to a representative embodiment is illustrated.

[0007] Figure 1C Another system for overhead-free data encoding according to a representative embodiment is illustrated.

[0008] Figure 1D Another system for overhead-free data encoding according to a representative embodiment is illustrated.

[0009] Figure 2A A digital interface for overhead-free data encoding is illustrated according to a representative embodiment.

[0010] Figure 2B Timing relationships for overhead-free data encoding are illustrated according to a representative embodiment.

[0011] Figure 3A A method for overhead-free data encoding according to a representative embodiment is illustrated.

[0012] Figure 3B Another method for overhead-free data encoding according to a representative embodiment is illustrated.

[0013] Figure 4 An example circuit of a scrambler for overhead-free data encoding according to a representative embodiment is illustrated.

[0014] Figure 5 A computer system on which a method for overhead-free data encoding is implemented is illustrated according to another representative embodiment. DETAILED DESCRIPTION

[0015] In the following detailed description, for the purpose of explanation rather than limitation, representative embodiments of the disclosure details are set forth to provide a thorough understanding of the embodiments according to the present teachings. However, other embodiments that are consistent with the present disclosure that are different from the specific details disclosed herein are still within the scope of the appended claims. The description of known systems, equipment, materials, operating methods, and manufacturing methods may be omitted to avoid blurring the description of representative embodiments. Nevertheless, systems, equipment, materials, and methods within the knowledge of those of ordinary skill in the art are also within the scope of the present teachings and may be used according to representative embodiments. It should be understood that the terms used herein are only for the purpose of describing specific embodiments, not for limitation. The definitions and explanations of the terms herein are supplements to the scientific and technological meanings of the terms that are generally understood and accepted in the technical field of the present teachings.

[0016] It should be understood that although the terms first, second, third, etc. can be used to describe various elements or components herein, these elements or components should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, without departing from the teaching of the present invention, the first element or component discussed below can be referred to as the second element or component.

[0017] As used in the specification and the appended claims, the singular forms of the terms "a", "an", and "the" are intended to include both the singular and the plural, unless the context clearly dictates otherwise. In addition, when the terms "include" and / or "comprises" and / or similar terms are used in this specification, these terms specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] Unless otherwise specified, when an element or component is referred to as being "connected to," "coupled to," another element or component, it should be understood that the element or component can be directly connected or coupled to another element or component, or there may be intermediate elements or components. That is, these terms and similar terms include situations where one or more intermediate elements or components can be used to connect two elements or components. However, when an element or component is referred to as being "directly connected" to another element or component, this only includes situations where two elements or components are connected to each other without any intermediate or intervening elements or components.

[0019] Thus, the present disclosure, through one or more of its various aspects, embodiments and / or specific features or subcomponents, is intended to provide one or more advantages as specifically pointed out below.

[0020] As described herein, a scrambler is used to modulate a digitized signal before transmitting data to reduce its low frequency spectrum bandwidth and improve the signal-to-noise ratio. A digital interface including a scrambler can eliminate the use of coded bits to improve power efficiency in transmission, and can rely on statistical properties to meet run length requirements and DC balance requirements. The digital interface can reduce the necessary power in a digital transducer probe, such as an ultrasound system, by using a reconfigurable parallel scrambler topology. The digital interface can be used in any digital transducer probe to ensure robust signal integrity, but the teachings herein are not limited to digital transducer probes.

[0021] Figure 1A A system for overhead-free data encoding according to a representative embodiment is illustrated.

[0022] Figure 1AThe system 100A in includes a data source 110A, a digital interface 111A, and a signal processor 120A. The data source 110A can be any of a variety of data sources, for example, a medical imaging device or a network security camera. The digital interface 111A can include circuits including a scrambler, as described below. The signal processor 120A can receive and process signals from the digital interface 111A. The data source 110A, the digital interface 111A, and the signal processor 120A can be connected by wired signals and / or wireless signals, and each device can include circuit elements, such as a transmitter, a receiver, a memory, a processor, and an interface for inputting and outputting data and instructions.

[0023] The digital interface 111A is configured to implement a method for encoding data for transmission. The method may include aligning and marking the beginning of a data stream generated based on data from the data source 110A. The method may also include receiving a digitized signal comprising formatted digital data in a data stream generated based on data from the data source 110A. The method performed by the digital interface 111A may also include scrambling the formatted digital data into scrambled digital data to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data, and not adding coded bits to the formatted digital data. The method performed by the digital interface 111A also includes outputting the scrambled digital data directly or indirectly to the signal processor 120A via, for example, a wire or via, for example, a wireless network.

[0024] Figure 1B Another system for overhead-free data encoding according to a representative embodiment is illustrated.

[0025] Figure 1B The ultrasound imaging system 100B in the embodiment includes an imaging device 110B and a computer system 115, the computer system 115 being used to control the imaging of a region of interest (e.g., in a patient 105 on an examination table 106). The imaging device 110B is illustratively an ultrasound imaging system capable of providing ultrasound (US) image scanning of a region of interest in the patient 105. Illustratively, the imaging device 110B may be of a type commonly used in ultrasound imaging procedures. The imaging device 110B may be suitable for providing color Doppler imaging or three-dimensional flow volume imaging or continuous wave (CW) Doppler measurement. The imaging device 110B may illustratively include a transducer array, which may include a capacitive micromachined ultrasound transducer (CMUT) or a piezoelectric transducer formed of a material such as PZT or PVDF. The transducer array may be coupled to a microwave beam former (not shown) in the imaging device and control the transducer's reception of signals. Figure 1B The imaging device 110B in Figure 1A An example of data source 110A in FIG.

[0026] In some embodiments, the imaging device 110B may include features consistent with the description in the commonly owned international patent application publication WO2022069264 (international filing date is April 7, 2022) and the U.S. provisional application US63 / 084728 (filing date is September 29, 2020). The entire disclosure of the international patent application publication WO2022069264 and the U.S. provisional application US63 / 084728 is incorporated herein by reference (copies of these documents are attached to this application).

[0027] Computer system 115 receives image data from imaging device 110B and stores and processes the imaging data according to representative embodiments described herein. Computer system 115 includes controller 120B, memory 130, display 140 (which optionally includes a graphical user interface 145 (GUI)), and user interface 150. Display 140 may also include a speaker (not shown) to provide auditory feedback.

[0028] The controller 120B interfaces with the imaging device 110B via the imaging interface 111B. The imaging interface 111B may include a digital transducer interface (DTI) (in Figure 1B The DTI may include a plurality of ports and may enable operation of a selected one of a plurality of imaging devices 110B operating at a relatively high data rate in the ultrasound imaging system 100B. The DTI of the imaging interface 111B may enable high data speed switching between a plurality of imaging devices 110B and receiving high data rate echo imaging data for further digital signal processing. In one aspect, the imaging interface 111B enables implementation of a plurality of imaging devices 110B employing a plurality of digital technologies requiring different voltages. In addition, the DTI of the imaging interface 111B may also enable compensation for voltage drops in a cable connecting the imaging device 110B between the computer system 115 and the imaging device 110B. In addition, in addition to the imaging device 110B, the DTI of the imaging interface 111B may also enable operation of an imaging device 110B adapted to perform CW Doppler imaging.

[0029] The imaging interface 111B is configured to implement a method for encoding data for transmission. The method may include aligning and marking the beginning of a data stream generated based on data from the imaging device 110B. The method may also include receiving a digitized signal, the digitized signal including formatted digital data in a data stream generated based on data from the imaging device 110B. The method performed by the imaging interface 111B may also include scrambling the formatted digital data into scrambled digital data to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data, and not adding coded bits to the formatted digital data. The method performed by the imaging interface 111B also includes directly or indirectly outputting the scrambled digital data to the controller 120B via, for example, a wire or via, for example, a wireless network. The formatted digital data received by the imaging interface 111B may include an ultrasonic signal. The scrambling at the imaging interface 111B may meet the run length requirement based on statistical properties. Figure 1B The imaging interface 111B in Figure 1A An example of the digital interface 111A in FIG.

[0030] The memory 130 stores instructions that can be executed by the controller 120B. As described more fully below, the instructions, when executed, enable the controller 120B to allow a user to use the graphical user interface 145 or the user interface 150 or both to perform different steps to initialize an ultrasound imaging device including a transducer, etc. In addition, the controller 120B can perform additional operations based on executing the instructions (e.g., issuing instructions to or communicating with another element of the computer system 115 (including the memory 130 and the display 140) to perform one or more of the above-mentioned processes).

[0031] Controller 120B represents one or more processing devices and is configured to execute software instructions stored in memory 130 to perform functions as described in various embodiments herein. Controller 120B can be implemented using any combination of hardware, software, firmware, hard-wired logic circuits, or a combination thereof, by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a general-purpose computer, a central processing unit, a computer processor, a microprocessor, a graphics processing unit (GPU), a microcontroller, a state machine, a programmable logic device, or a combination thereof. In addition, any processing unit or processor herein may include multiple processors, parallel processors, or both. Multiple processors may be included in or coupled to a single device or multiple devices.

[0032] The term "processor" as used herein includes an electronic component that is configured and capable of executing a program or machine-executable instructions. References to a computing device that includes a "processor" should be interpreted as including more than one processor or processing core (as in a multi-core processor). A processor may also refer to a collection of processors within a single computer system, or a collection of processors distributed across multiple computer systems (for example, in a cloud-based application or other multi-site application). The term computing device should also be interpreted to include a collection or network of computing devices, each of which includes one or more processors. A program has software instructions executed by one or more processors, which may be within the same computing device or distributed across multiple computing devices.

[0033] The memory 130 may include a main memory and / or a static memory, wherein these memories may communicate with each other and with the controller 120B via one or more buses. The memory 130 stores instructions for implementing some or all aspects of the methods and processes described herein. For example, the memory 130 may be implemented by any number, type, and combination of random access memory (RAM) and read-only memory (ROM), and may store various types of information (e.g., software algorithms used as instructions that, when executed by a processor, cause the processor to perform various steps and methods according to the present teachings). In addition, updates to the methods and processes described herein may also be provided to the computer system 115 and stored in the memory 130.

[0034] The various types of ROM and RAM may include any number, type, and combination of computer-readable storage media, such as disk drives, flash memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, tapes, compact disk read-only memory (CD-ROM), digital versatile disks (DVD), floppy disks, Blu-ray disks, universal serial bus (USB) drives, or any other form of storage media known in the art. Memory 130 is a tangible storage medium for storing data and executable software instructions, and is non-transient during the time the software instructions are stored therein. The term "non-transient" as used herein should not be interpreted as a permanent state characteristic, but rather a state characteristic that will last for a period of time. The term "non-transient" specifically denies transient characteristics (e.g., carrier waves or signals or other forms of characteristics that only exist temporarily at any time and any place). Memory 130 may store software instructions and / or computer-readable code that enable the execution of various functions. Memory 130 may be secure and / or encrypted, or may be unsecured and / or unencrypted.

[0035] "Memory" is an example of a computer-readable storage medium and should be interpreted as possibly being multiple memories or databases. A memory or database may be, for example, local to a computer and / or distributed across multiple computer systems or computing devices. A computer-readable storage medium is defined as any medium that constitutes patentable subject matter under 35 U.S.C. 101, and excludes any medium that does not constitute patentable subject matter under 35 U.S.C. 101. Examples of such media include non-transient media (e.g., computer storage devices that store information in a format readable by a computer or data processing system). More specific examples of non-transient media include computer disks and non-volatile memory.

[0036] The user interface 150 may include a user interface and / or a network interface, which is used to provide information and data output by the controller 120B and / or the memory 130 to the user, and / or for receiving information and data input by the user. That is, the user interface 150 enables the user to operate the imaging device as described herein, and schedules, controls or manipulates the various aspects of the ultrasonic imaging system 100B of this teaching. It is worth noting that the user interface 150 enables the controller 120B to indicate the effect of the control or manipulation of the user. The user interface 150 may include one or more of the following: a port, a disk drive, a wireless antenna or other types of receiver circuits. The user interface 150 can also connect one or more interface devices (e.g., a mouse, a keyboard, a mouse, a trackball, a joystick, a microphone, a video camera, a touch pad, a touch screen, a voice or gesture recognition captured by a microphone or a video camera).

[0037] The display 140 may be a monitor (e.g., a computer monitor), a television, a liquid crystal display (LCD), a light emitting diode (LED) display, a flat panel display, a solid state display, or a cathode ray tube (CRT) display, or an electronic whiteboard. The display 140 may also provide a graphical user interface 145 (GUI) for displaying information to a user and receiving information from a user.

[0038] Figure 1C Another system for overhead-free data encoding according to a representative embodiment is illustrated.

[0039] Figure 1CThe system 100C in the embodiment includes a digital interface 111C and a processing system 120C. The digital interface 111C includes a scrambler 111C1, an output driver 111C2, a signal multiplexer 111C3, and a gating logic device 111C4. The scrambler 111C1 scrambles the digital transducer signal received at the digital interface 111C. The signal multiplexer 111C3 is configured to multiplex the scrambled digital transducer signal using or based on one or more other received signals (e.g., a selected idle code or a selected alignment code). The output driver 111C2 outputs the multiplexed signal to the processing system 120C through a transmission path. The gating logic device 111C4 receives a trigger signal from the processing system 120C and outputs a gating selection signal I and an alignment selection signal A to gating the idle signal or the alignment signal input to the signal multiplexer 111C3. The descrambler 120C1 descrambles the received multiplexed signal and generates / reproduces a digital transducer signal.

[0040] The system 100C can be viewed as a block diagram of any system configured to perform the teachings herein. The system 100C can be configured to scramble formatted data without headers and to reduce transmission spectrum and save power. Figure 1C In the embodiment of the present invention, the system 100C can use the data of the digital transducer signal as a seed to perform self-synchronous scrambling, so that the descrambler 120C1 only needs a polynomial to descramble the received multiplexed signal. In other words, the system 100C is able to scramble and descramble the signal without, for example, frame synchronization. The alignment code is used to select the time when valid data appears.

[0041] The digital interface 111C is configured to implement a method for encoding data for transmission. The method may include aligning and marking the beginning of a data stream generated based on a digital transducer signal. The method may also include receiving a digitized signal, the digitized signal including a digital transducer signal as formatted digital data. The method performed by the digital interface 111C may also include a scrambler 111C1 scrambling the formatted digital data into scrambled digital data to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data, and not adding coded bits to the formatted digital data. The method performed by the digital interface 111C also includes an output driver 111C2 outputting the scrambled digital data directly or indirectly to the processing system 120C via, for example, a limited network (as a transmission path) or via, for example, a wireless network (as a transmission path).

[0042] Figure 1D Another system for overhead-free data encoding according to a representative embodiment is illustrated.

[0043] Figure 1DThe system 100D in includes a digital interface 111D and a processing system 120D. The digital interface 111D includes a scrambler 111D1, an output driver 111D2, a signal multiplexer 111D3, and a gating logic device 111D4. The scrambler 111D1 scrambles the digital transducer signal received at the digital interface 111D. 111D1 and in the processing system 120D. The signal multiplexer 111D3 is configured to multiplex the scrambled digital transducer signal using or based on one or more other signals received (e.g., a selected idle code or a selected alignment code). The output driver 111D2 outputs the multiplexed signal to the processing system 120D through a transmission path. The gating logic device 111D4 receives a trigger signal from the processing system 120D, and outputs a gating selection signal I and an alignment selection signal A to gating the idle signal or alignment signal input to the signal multiplexer 111D3. exist Figure 4 In the embodiment, the trigger signal from the processing system 120D also triggers the seed reset input to the scrambler 111D1 to reset the scrambler 111D1 to the starting seed value. The alignment code can be used to synchronize the descrambler 120D1 and the gate timing, and the seed reset is used to synchronize the scrambler 111D1. The multiplexed signal received by the descrambler 120D1 is descrambled and a digital transducer signal is generated / reproduced.

[0044] The system 100D can be viewed as a block diagram of any system configured to perform the teachings herein. The system 100D can be configured to scramble formatted data without headers and to reduce transmission spectrum and save power. Figure 1D In the embodiment of the present invention, the system 100D can use the seed reset to synchronize the seed code in the scrambler and use the alignment code to synchronize the descrambler and the gate timing, thereby performing synchronous scrambling.

[0045] The digital interface 111D is configured to implement a method for encoding data for transmission. The method may include aligning and marking the beginning of a data stream generated based on a digital transducer signal. The method may also include receiving a digitized signal, the digitized signal including a digital transducer signal as formatted digital data. The method performed by the digital interface 111D may also include a scrambler 111D1 scrambling the formatted digital data into scrambled digital data to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data, and not adding coded bits to the formatted digital data. The method performed by the digital interface 111D also includes an output driver 111D2 outputting the scrambled digital data directly or indirectly to the processing system 120D via, for example, a wire (as a transmission path) or via, for example, a wireless network (as a transmission path).

[0046] Figure 2AA digital interface for overhead-free data encoding is illustrated according to a representative embodiment.

[0047] The digital interface 211 includes a frame synchronization circuit 212, a receiver 211A, a scrambler 211B having a LFSR 211B1 (linear feedback shift register), and an output section 211C. The receiver 211A is configured to receive a digitized signal including formatted digital data. Figure 2A In a modified embodiment, the receiver 211A is configured to enable alignment detection, thereby searching for alignment codes at specific time intervals. The frame synchronization circuit 212 synchronizes the seed code in the scrambler 211B and the corresponding descrambler. The frame synchronization circuit 212 can perform one or more functions (including transmitting a frame synchronization signal at defined intervals to synchronize the seed code and achieve bit alignment).

[0048] The digital interface 211 is configured to implement a method for encoding data for transmission. The method may include aligning and marking the beginning of a data stream generated based on a digital transducer signal. The method may also include receiving a digitized signal, the digitized signal including a digital transducer signal as formatted digital data. The method performed by the digital interface 211 may also include a scrambler 211B scrambling the formatted digital data into scrambled digital data to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data, and not adding coded bits to the formatted digital data. The method performed by the digital interface 211 also includes an output unit 211C outputting the scrambled digital data directly or indirectly via, for example, a wire or via, for example, a wireless network.

[0049] Digital interface 211 can be implemented in a digital transducer ultrasound system to eliminate bit overhead, save power, reduce data rate and simplify system architecture. For example, digital interface 211 can eliminate 25% (2 bits) of the coding scheme overhead of, for example, 8b / 10b coding scheme, and smaller but still significant coding scheme overhead of, for example, 64b / 66b coding scheme or 128b / 132b coding scheme. 64b / 66b coding scheme and 128b / 132b coding scheme rely on pseudo-random number generator to meet DC balance tolerance, and use additional bit overhead to ensure run length and classified data type. Digital interface 211 and other digital interfaces described herein can be simplified to eliminate bit overhead, save power, reduce data rate and simplify system architecture. Figure 2AThe scrambler 211B in and other scramblers described herein may be implemented in a LFSR 211B1, wherein the coding scheme specifies which polynomial is used in the LFSR 211B1. However, the scrambler 211B may be reconfigurable to allow a user to specify a scrambling polynomial. Thus, scrambling may be performed using the LFSR 211B1 that determines the sequence of the output. The LFSR 211B1 may include a reconfigurable and tunable polynomial. The polynomial can then be tuned to determine its characteristics (e.g., the number of samples before a repeated LFSR code appears). Since the characteristic has a repetitive, periodic nature, the characteristic may be useful in ultrasound imaging. That is, a fixed LFSR polynomial period may overlap with an ultrasound period, resulting in excessive spectral content and potentially increasing the bit error rate of the system, so that providing a reconfigurable configuration provides the user with the ability to reconfigure the scrambler 211B to change the polynomial period of the LFSR 211B1.

[0050] Figure 2B The timing relationships for overhead-free data encoding according to a representative embodiment are illustrated.

[0051] exist Figure 2B , the top row shows the trigger signal from the FPGA to the transducer. For example, the trigger signal can be provided from the processing system 120C to Figure 1C or provided from the processing system 120D to the transducer Figure 1D The second row shows the search for the alignment code 00111100. The second row starts with the idle code 01010101 and ends with the alignment code 00111100. After the alignment code, the second row represents data transmission. The third row shows the flow of a DC balanced idle code (i.e., 01010101), an alignment code (i.e., 00111100), then the substantial formatted digital data starting with byte 0, byte 1, etc. The fourth row shows the transmission from the gating logic device 111C4 to the Figure 1C The signal multiplexer 111C3 and from the gating logic device 111D4 to Figure 1D The fifth row shows the idle selection signal from the signal multiplexer 111D3 in the gate logic device 111C4 to Figure 1C The signal multiplexer 111C3 and from the gating logic device 111D4 to Figure 1D The alignment selection signal A of the signal multiplexer 111D3 in.

[0052] like Figure 2B As shown, the trigger signal indicates the start of the sound wave line. The trigger signal can be Figure 1C Processing system 120C or Figure 1DThe FPGA of the processing system 120D in the processing system 120D passes through the transducer cable to the transducer without encountering processing delays, thereby allowing the acoustic energy to be transmitted into the body and allowing the first echo to be reflected back. The trigger signal can set the SR trigger, which enables the multiplexer to select an idle code (e.g., a byte including 01010101) to send the high-speed link back to the FPGA. The idle code can be any code that is different from the alignment code and is DC balanced. The multiplexer can select an alignment code (e.g., a byte including 00111100) to mark the beginning of the data stream. Other alignment codes can be used. The serializer can form a serial data stream, which is sent back to the FPGA along the transducer cable using a current mode logic buffer. As described herein, the data is scrambled using an LSFR scrambler to maintain DC balance. The output of the scrambler can be used to selectively invert the data bit using an XOR gate.

[0053] The current mode logic receiver in the FPGA can feed the alignment detector group to look for alignment codes and feed the deserializer to produce an 8-bit parallel data stream. The alignment detection can be gated using the enable input so that the FPGA only looks for alignment codes before the first data byte of the payload, so that valid data values ​​00111100 will not cause an alignment code detection event. This gated alignment detection allows encoding without the need for additional bits. The SR flip-flop can enable alignment detection when the row is triggered, and can disable alignment detection when the first alignment code is detected just before the first valid data in the payload. In the interval before alignment detection, the transducer can send idle codes that cannot trigger alignment detection. The LFSR scrambler and supporting XOR gates, which are exactly the same design as in the transducer, can descramble the data to produce a valid data output stream.

[0054] The timing diagram of Figure 2 shows the overall shorter sequence due to 8-bit encoding relative to 10-bit encoding, resulting in a 20% reduction in power for transmitting the same amount of data. The "Alignment Detect Gate Interval" is the output of the SR flip-flop. The data stream shows the idle code, alignment code, and 8-bit data serial / scrambled data.

[0055] Figure 3A A method for overhead-free data encoding according to a representative embodiment is illustrated.

[0056] Figure 3AThe method starts at S310: providing a unique alignment code. The unique alignment code can be a default alignment code set when the digital interface is provided from a manufacturer or intermediary, or can be set by a user. As an arbitrary example, the default byte can be set to a value of 99 (i.e., 01100011) and used to mark the beginning of a data stream. The alignment code can be a code in the formatted digital data in the digitized signal from the data stream that is not used as any value. The alignment code can also be recognized by a scrambler at the encoding end and a descrambler at the decoding end.

[0057] At S320, a unique alignment code is used to align and mark the beginning of the data stream. For example, the unique alignment code may be used to fill the first byte or the first two bytes of the data stream.

[0058] At S330, Figure 3A The method includes gating alignment detection on a receiver so as to search for an alignment code at a specified time interval. That is, a receiver having a descrambler is gated so as to perform alignment detection by searching for an alignment code at a specified time interval.

[0059] At S340, the start of a data stream is detected at the digital interface. The start of a data stream is detected when a unique alignment code is identified in a digitized signal including formatted digital data.

[0060] At S350 , a digitized signal is received. The digitized signal may include a unique alignment code, payload data including formatted digital data, and an end code marking the end of the data.

[0061] At S360, the digitized signal is scrambled without adding coded bits. Scrambling can be performed using a linear feedback shift register that includes a defined polynomial that is fixed when reset. Scrambling is performed to reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data. That is, scrambling is performed to randomize the bits, which can cause a relatively uniform distribution of 0s and 1s in the scrambled digital signal.

[0062] At S370, the scrambled digital data is outputted so that Figure 3A The method ends by outputting the scrambled digital data.

[0063] Figure 3B Another method for overhead-free data encoding according to a representative embodiment is illustrated.

[0064] Figure 3B The method starts at S311: a frame synchronization signal is output at a defined interval. The frame synchronization signal is used to synchronize the transmitter and the receiver, and is similar to Figure 3A The alignment code used in .

[0065] At S331, Figure 3B The method includes enabling alignment detection at the receiver to search for a frame synchronization signal at specific time intervals.

[0066] At S340 , the start of a data stream is detected at the digital interface.

[0067] At S350, a digitized signal is received. The digitized signal includes formatted digital data.

[0068] At S360, the digitized signal is scrambled without adding coded bits to the formatted digital data. Figure 3B The digitized signal is scrambled in order to again reduce the spectrum bandwidth and enhance the balance between the number of digital values ​​of the digital data.

[0069] At S370, the scrambled digital data is outputted so that Figure 3B The method ends by outputting the scrambled digital data.

[0070] Figure 4 An example circuit of a scrambler for overhead-free data encoding in a reconfigurable manner is illustrated according to a representative embodiment.

[0071] exist Figure 4 In the embodiment, the LFSR includes a first multiplexer 511 , a first XOR element 512 , a first logic element 513 a , a second logic element 513 b , a second XOR element 514 , and a second multiplexer 516 . Figure 4 The circuit in also includes a frame synchronization memory 515.

[0072] The LFSR feeds back its 32-bit parallel output (labeled as "LFSR<31:0>"), and uses the polynomial address to multiplex the 32 bits into two outputs through the first multiplexer 511. The first multiplexer 511 outputs the two outputs to the first XOR element 512. The first XOR element 512 provides a data output D to the first logic element 513a. The first logic element 513a also receives a clock signal, a reset signal R, and 24-bit seed data (labeled as "Seed<31:8>"). The first logic element 513 a outputs 24 bits (labeled as “LFSR<31:8>”) to the second XOR element 514. The second XOR element 514 provides 24 bits of scrambled output data (labeled as “Scrambled<23:0>”) from the second XOR element 514. The second multiplexer 516 then multiplexes the scrambled output data with a frame synchronization signal from the frame synchronization memory 515 to generate an output signal (labeled as “Out”).

[0073] The first multiplexer 511 determines the feedback polynomial of the LFSR. The first XOR element 512 provides mathematical addition in the LFSR. The first logic element 513a stores the digital value at the input "D" and outputs the digital value to "Q" at the rising edge of the input clock marked as "CLK". When the input marked as "RESET" rises to a digital logic high, the first logic element 513a will output 0. When the input marked as "S" rises to a digital logic high, the first logic element 513a will output 1. The input bus marked as "Seed<31:8>" will cause the output of the first logic element 513a to output the seed value. The second logic element 513b stores the eight highest bits, so that a larger number of polynomials can be used. The first logic element 513a and the second logic element 513b output the LFSR data stream and feed it back to the input of the LFSR to calculate the polynomial. The second XOR element 514 scrambles the data by performing an XOR operation on the incoming parallel 24-bit data stream with the 24-bit output of the LFSR. The output "Scrambled<23:0>" of the second XOR element 514 represents the scrambled data. The frame synchronization memory 515 stores the frame synchronization word or the gate alignment word. The second multiplexer 516 selects between the two inputs "Scrambled<23:0>" and the 24-bit output of the frame synchronization memory 515. During frame synchronization, the second multiplexer 516 selects the input from the frame synchronization memory 515 to output to "Out". In addition to frame synchronization, the second multiplexer 516 also selects the input "Scrambled<23:0>".

[0074] exist Figure 4 In , LFSR is used to scramble digital ultrasound data to reduce the bandwidth of the signal before transmitting it elsewhere. No coding bits are added, which saves power. The need for coding bits is avoided by relying on the periodicity of data such as digital ultrasound data, thereby guaranteeing the run length. Figure 4 The scrambling LFSR in can be implemented as a module in the digital transducer probe. The descrambling LFSR can be added in the receiving hardware.

[0075] exist Figure 4 In , the scramblers are parallel and synchronous and use reconfigurable and tunable polynomials. Figure 4 The seed of the scrambler in can be fixed, or can be reconfigurable. According to the teachings of this article, all four of these characteristics are variable. The following paragraphs will further explain these four characteristics.

[0076] The LFSR can be a fixed polynomial LFSR, or it can be a reconfigurable polynomial LFSR. The LFSR polynomial determines the sequence of the output. On reset, a fixed polynomial LFSR will follow the defined polynomial. A reconfigurable polynomial LFSR allows the user to specify the polynomial used, and can be reconfigured when needed. Figure 4 The LFSR in is a reconfigurable polynomial LFSR.

[0077] The LFSR can use a fixed seed code, or it can use a reconfigurable seed code. The LFSR seed code determines the first output pattern used by the LFSR. The fixed seed code resets the LFSR to a specific starting code. The reconfigurable seed allows the user to specify a specific starting code and can be reconfigured when needed. Figure 4 The seed code in is reconfigurable.

[0078] The LFSR can provide either serial or parallel outputs. The output mode of the LFSR determines how many bits are scrambled at a time. A serial output will scramble one bit at a time at a rate equal to the data rate of the system. A parallel output will scramble N bits at a time at 1 / N the system data rate. Serial scramblers are smaller than parallel scramblers, and parallel scramblers use less power than serial scramblers. Figure 4 The LFSR in provides parallel outputs.

[0079] LFSR can perform synchronous scrambling, or can perform self-synchronous scrambling. Synchronous scramblers require a frame synchronization header to synchronize the seed code in the scrambler and descrambler. Self-synchronous scramblers use the data itself as the seed and only require a polynomial to descramble, without frame synchronization. Figure 4 The system in is a synchronous scrambler.

[0080] Figure 2 shows an implementation of a scrambler that can use any 24-bit polynomial for the LFSR. To synchronize the LFSR with the receiving hardware, the frame sync header word is multiplexed into the data stream immediately after the sound line is triggered. The receiving hardware (e.g., FPGA) is programmed to align the decoding scrambler with the repeated frame sync word.

[0081] Figure 5 A computer system on which a method for overhead-free data encoding is implemented is illustrated according to another representative embodiment.

[0082] refer to Figure 5, the computer system 500 includes a set of software instructions that can be executed to cause the computer system 500 to perform any of the methods or computer-based functions disclosed herein. The computer system 500 can operate as a standalone device, or can be connected to other computer systems or peripheral devices, for example using a network 501. In an embodiment, the computer system 500 performs logic processing based on digital signals received via an analog-to-digital converter.

[0083] In a networked deployment, the computer system 500 operates as a server, or as a client user computer in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The computer system 500 can also be implemented as a variety of devices or incorporated into a variety of devices, for example, a workstation, a fixed computer, a mobile computer, a personal computer (PC), a laptop computer, a tablet computer, or other machines that can (sequentially or otherwise) execute a set of software instructions including a controller, which specifies the actions to be performed by the machine. The computer system 500 can be combined as a device or combined in a device, which in turn is included in an integrated system including additional devices. In an embodiment, the computer system 500 can be implemented using an electronic device that provides voice, video or data communication. In addition, although the computer system 500 is illustrated as a single system, the term "system" should also be considered to include any collection of systems or subsystems that execute one or more sets of software instructions to perform one or more computer functions individually or jointly.

[0084] like Figure 5As shown, computer system 500 includes processor 510. Processor 510 can be considered as a representative example of a processor of a controller, and executes instructions to implement some or all aspects of the methods and processes described herein. Processor 510 is tangible and non-transient. The term "non-transient" as used herein should not be interpreted as a permanent state characteristic, but should be interpreted as a characteristic of a state that will last for a period of time. The term "non-transient" specifically denies transient characteristics, such as carriers or signals or other forms of characteristics that only exist instantaneously at any time and any place. Processor 510 is an article of manufacture and / or a machine component. Processor 510 is configured to execute software instructions to perform functions as described in various embodiments herein. Processor 510 can be a general-purpose processor or part of an application-specific integrated circuit (ASIC). Processor 510 can also be a microprocessor, a microcomputer, a processor chip, a controller, a microcontroller, a digital signal processor (DSP), a state machine or a programmable logic device. Processor 510 can also be a logic circuit (including a programmable gate array (PGA) such as a field programmable gate array (FPGA)) or another type of circuit including discrete gates and / or transistor logic units. Processor 510 may be a central processing unit (CPU), a graphics processing unit (GPU), or both. In addition, any processor described herein may include multiple processors, parallel processors, or both. Multiple processors may be included in a single device or multiple devices or coupled to a single device or multiple devices.

[0085] The term "processor" as used herein encompasses an electronic component capable of executing a program or machine-executable instructions. References to a computing device that includes a "processor" should be interpreted as including more than one processor or processing core, such as in a multi-core processor. A processor may also refer to a collection of processors within a single computer system or distributed across multiple computer systems. The term computing device should also be interpreted to include a collection or network of computing devices, each of which includes one or more processors. A program has software instructions that are executed by one or more processors, which may be within the same computing device or distributed across multiple computing devices.

[0086] The computer system 500 also includes a main memory 520 and a static memory 530, wherein the memories in the computer system 500 communicate with each other and with the processor 510 via a bus 508. One or both of the main memory 520 and the static memory 530 can be considered as representative examples of the memory of the controller, and store instructions for implementing some or all aspects of the methods and processes described herein. The memory described herein is a tangible storage medium for storing data and executable software instructions, and is non-transient during the time when the software instructions are stored therein. The term "non-transient" as used herein should not be interpreted as a permanent state characteristic, but should be interpreted as a characteristic of a state that will last for a period of time. The term "non-transient" specifically denies transient characteristics, such as carrier waves or signals or other forms of characteristics that only exist momentarily at any time and anywhere. The main memory 520 and the static memory 530 are articles of manufacture and / or machine components. The main memory 520 and the static memory 530 are computer-readable media from which a computer (e.g., processor 510) can read data and executable software instructions. Each of the main memory 520 and the static memory 530 may be implemented as one or more of the following: random access memory (RAM), read-only memory (ROM), flash memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, removable disk, tape, compact disk read-only memory (CD-ROM), digital versatile disk (DVD), floppy disk, Blu-ray disk, or any other form of storage medium known in the art. The memory may be volatile or non-volatile, secure and / or encrypted, unsecure and / or unencrypted.

[0087] "Memory" is an example of a computer-readable storage medium. Computer memory is any memory that a processor can directly access. Examples of computer memory include, but are not limited to, RAM memory, registers, and register files. References to "computer memory" or "memory" should be interpreted as potentially being multiple memories. The memory may be, for example, multiple memories within the same computer system. The memory may also be multiple memories distributed among multiple computer systems or computing devices.

[0088] As shown, the computer system 500 also includes, for example, a video display unit 550 (e.g., a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, or a cathode ray tube (CRT)). In addition, the computer system 500 includes an input device 560 (e.g., a keyboard / virtual keyboard or a touch-sensitive input screen or a voice input unit with voice recognition) and a cursor control device 570 (e.g., a mouse or a touch-sensitive input screen or pad). The computer system 500 also optionally includes a disk drive unit 580, a signal generating device 590 (e.g., a speaker or a remote controller), and / or a digital interface 540 that connects the computer system 500 to a network interface.

[0089] In an embodiment, Figure 5 As shown, the disk drive unit 580 includes a computer readable medium 582 in which one or more sets of software instructions 584 (software) are embedded. The set of software instructions 584 to be executed by the processor 510 is read from the computer readable medium 582. In addition, the software instructions 584 perform one or more steps of the methods and processes described herein when executed by the processor 510. In an embodiment, the software instructions 584 reside in whole or in part in the main memory 520, the static memory 530, and / or reside in whole or in part in the processor 510 during operation by the computer system 500. In addition, the computer readable medium 582 may include the software instructions 584 or receive and execute the software instructions 584 in response to a propagated signal, so that the device connected to the network 501 transmits voice, video or data on the network 501. The software instructions 584 may be sent or received on the network 501 via the digital interface 540.

[0090] In an embodiment, a dedicated hardware implementation (e.g., an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array, and other hardware components) is constructed to implement one or more of the methods described herein. One or more embodiments described herein may use two or more specific interconnected hardware modules or devices to implement functions, and these two or more specific interconnected hardware modules or devices have related control and data signals that can communicate between and through these modules. Therefore, the present disclosure covers software, firmware, and hardware implementations. Nothing in this application should be interpreted as being (able to) be implemented using only software rather than hardware such as tangible non-transient processors and / or memories.

[0091] According to various embodiments of the present disclosure, a hardware computer system executing a software program can be used to implement the methods described herein. In addition, in an exemplary non-limiting embodiment, the implementation can include distributed processing, component / object distributed processing, and parallel processing. Virtual computer system processing can implement one or more of the methods or functions described herein, and the processor described herein can be used to support a virtual processing environment.

[0092] Thus, overhead-free data encoding enables low-power digital communications.

[0093] Although no overhead data encoding has been described with reference to several exemplary embodiments, it is to be understood that the words that have been used are words of description and illustration, rather than words of limitation. Changes may be made within the scope of the appended claims (as presently stated and as amended) without departing from the scope and spirit of no overhead data encoding in its various aspects. Although no overhead data encoding has been described with reference to specific means, materials, and embodiments, no overhead data encoding is not intended to be limited to the details disclosed; rather, no overhead data encoding extends to all functionally equivalent structures, methods, and uses (e.g., those within the scope of the appended claims).

[0094] The description of the embodiments described herein is intended to provide an overall understanding of the structure of various embodiments. These descriptions are not intended to serve as a complete description of all elements and features of the disclosure described herein. After reviewing the present disclosure, many other embodiments will be apparent to those skilled in the art. Other embodiments may be utilized and derived from the present disclosure so that structural and logical replacements and changes may be made without departing from the scope of the present disclosure. In addition, these illustrations are only representative and may not be drawn to scale. Certain ratios in the illustrations may be amplified, while other ratios may be minimized. Therefore, the present disclosure and the accompanying drawings should be considered to be illustrative and not restrictive.

[0095] In this article, for the purpose of convenience only, the term "invention" may be used to refer to one or more embodiments in the present disclosure individually and / or collectively, without intending to limit the scope of the present application to any specific invention or inventive concept. In addition, although specific embodiments have been illustrated and described herein, it should be understood that any subsequent arrangement designed to implement the same or similar purpose for the specific embodiments shown can be replaced. The present disclosure is intended to cover any and all subsequent adjustments or changes of the various embodiments. After reading the specification, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art.

[0096] The Abstract of the Disclosure is provided to comply with 35 CFR §1.52(b) and, when submitted, should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, various features may be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. The disclosure should not be interpreted as reflecting the intention that the claimed embodiments require more features than those expressly recited in each claim. On the contrary, as reflected in the claims, the inventive subject matter may be directed to less than all features of any of the disclosed embodiments. Therefore, the claims are incorporated into the Detailed Description, with each claim independently defining a separately claimed subject matter.

[0097] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to practice the concepts described in the present disclosure. As such, the subject matter disclosed above should be considered illustrative rather than restrictive, and the claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the present disclosure. Therefore, to the maximum extent permitted by law, the scope of the present disclosure will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be limited by the foregoing specific embodiments.

Claims

1. A method for encoding data for transmission, the method comprising: Aligning and marking (S320) the beginning of the data stream; receiving (S350) a digitized signal including formatted digital data at a communication interface including a scrambler (111C1); scrambling (S360) the formatted digital data into scrambled digital data to reduce spectrum bandwidth and enhance balance between the number of digital values ​​of the digital data without adding coded bits to the formatted digital data; and The scrambled digital data is output (S370).

2. The method of claim 1, further comprising gating alignment detection (S330) at the receiver (211A) to search for alignment codes at specific time intervals.

3. The method according to claim 1, further comprising providing (S310) a unique alignment code at the beginning of the data stream to align the formatted digital data.

4. The method according to claim 1, wherein: The formatted digital data includes an ultrasound signal.

5. The method according to claim 1, wherein: The scrambling is based on statistical properties to meet the run length requirements.

6. The method according to claim 1, wherein: The scrambling is performed using a linear feedback shift register (LFSR(211B1)) which determines the sequence of the output and includes a defined polynomial which is fixed at reset.

7. The method according to claim 1, wherein: The scrambling is performed using a linear feedback shift register (LFSR(211B1)) which determines the sequence of the output and includes a reconfigurable and tunable polynomial.

8. The method according to claim 7, wherein: The method is performed by a module (211B) in a digital transducer probe, and the module includes the linear feedback shift register (LFSR (211B1)).

9. The method according to claim 1, wherein: The scrambling is performed using a linear feedback shift register (LFSR (211B1)) that uses a fixed seed code to determine a first output (211C) pattern used by the linear feedback shift register.

10. The method according to claim 1, wherein: The scrambling is performed using a linear feedback shift register (LFSR (211B1)) that uses a reconfigurable seed code to determine a first output (211C) pattern used by the linear feedback shift register.

11. The method according to claim 1, wherein: The scrambling is performed using a linear feedback shift register (LFSR(211B1)) which linearly scrambles one bit at a time.

12. The method according to claim 1, wherein: The scrambling is performed using a linear feedback shift register (LFSR(211B1)) which scrambles multiple bits in parallel.

13. The method according to claim 1, further comprising: A frame synchronization signal is output (S311) at defined intervals to synchronize the seed code and achieve bit alignment.

14. The method according to claim 1, wherein: The scrambling and the outputting are performed without transmitting a frame synchronization signal, so that descrambling is performed using the scrambled digital data as a seed code.

15. A digital interface (111A), comprising: a receiver (211A) receiving (S350) a digitized signal including formatted digital data, the receiver (211A) including a receiving logic device adapted to detect an alignment code and align with respect to the code; a scrambler (211B) that scrambles (S360) the formatted digital data into scrambled digital data to reduce spectrum bandwidth and enhance balance between numbers of digital values ​​of the digital data without adding coded bits to the formatted digital data; as well as An output unit (211C) outputs (S370) the scrambled digital data.

16. The digital interface (111A) according to claim 15, wherein: The receiver (211A) is configured to gate alignment detection to search for alignment codes at specific time intervals.

17. The digital interface (111A) of claim 15, wherein: A unique alignment code is provided at the beginning of the data stream to align the formatted digital data.

18. The digital interface (111A) of claim 15, wherein: The digital interface (111A) is included in a digital transducer probe in an ultrasound system (100B), and the formatted digital data includes an ultrasound signal.

19. The digital interface (111A) of claim 15, wherein: The scrambler (111C1) comprises: A linear feedback shift register (LFSR(211B1)) which determines the sequence of the output and includes a reconfigurable and tunable polynomial.

20. The digital interface (111A) of claim 15, wherein: The scrambler (111C1) comprises: A linear feedback shift register (LFSR (211B1)) that uses a reconfigurable seed code to determine a first output (211C) pattern used by the linear feedback shift register.

21. The digital interface (111A) of claim 15, wherein: The scrambler (111C1) comprises: Linear Feedback Shift Register (LFSR(211B1)) which scrambles multiple bits in parallel.

22. The digital interface (111A) of claim 15, further comprising: A frame synchronization circuit (212) provides a frame synchronization signal at defined intervals to synchronize the seed code and achieve bit alignment.

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