Method for generating thick film layer of ion trap chip

Abstract

The invention provides a method for generating a thick film layer of an ion trap chip. The method specifically comprises the following steps: S1, growing a first bonding layer on a substrate of the ion trap chip; s2, growing a second bonding layer on the material required by the thick film layer; s3, bonding the first bonding layer and the second bonding layer through a bonding process; and S4, reducing the thickness of a material required by the thick film layer to a preset thickness through a thinning process. According to the invention, the speed limitation caused by the fact that the whole ion trap chip adopts a growth mode is avoided, and the problem that the thicker the grown film is, the more difficult the quality is to guarantee is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of ion trap manufacturing, and in particular relates to a method for generating a thick film layer of an ion trap chip. Background Art

[0002] The ion trap system has become an important platform for quantum computing, quantum simulation and precision measurement due to its advantages such as long coherence time and high fidelity of logical operations. Thanks to mature semiconductor technology, chip-type ion traps are considered to be one of the effective ways to achieve multi-ion quantum bit information processing. Compared with the traditional manual or semi-manual ion trap production method, the chip-type ion trap is made using mature micro-nano technology, which not only speeds up the production speed of ion traps and improves the quality of ion traps, but also has high integration and expansion capabilities, which lays the foundation for the standardization and industrialization of future ion trap quantum computing.

[0003] In order to realize a variety of different functions, the ion trap chip used in the ion trap system needs to have a multilayer structure. Some of the layers need to be relatively thick (more than 10 microns). For example, in order to meet the precision requirements required for quantum information processing, the radio frequency loss of the ion trap chip cannot be too large, otherwise the coherence time of the ions and the fidelity of the operation will not meet the actual needs. However, in order to make the processing of the ion trap chip compatible with the existing technology, silicon-based ion trap chips are usually used, but the radio frequency loss of silicon is very large, so a very thick silicon dioxide dielectric layer (at least 10 microns) is needed as a barrier between the radio frequency signal on the ion trap chip and the silicon substrate, thereby reducing the loss of the radio frequency signal and improving the performance of the ion trap chip. For another example, in order to reduce the breakdown voltage and reduce the influence of the stray charge of the dielectric layer on the performance of the ion trap, the ion trap chip also needs a thick metal electrode layer (more than 10 microns). However, the commonly used growth methods, such as CVD (Chemical Vapor Deposition), sputtering, evaporation, etc. to grow thick films have great defects, such as the limitation of growth rate. The thicker the film is, the longer it takes to grow. Generally, it takes several hours or even days to grow a thin film layer of more than 10 microns. Moreover, the thicker the grown film is, the more difficult it is to guarantee its quality, such as internal pores, cracks caused by stress, poor surface roughness, etc.

[0004] Therefore, it is necessary to design a method for generating a thick film layer of an ion trap chip to solve the above technical problems. Summary of the invention

[0005] In view of the above problems, the present invention provides a method for generating a thick film layer of an ion trap chip, which specifically comprises:

[0006] A method for generating a thick film layer of an ion trap chip, the method comprising:

[0007] S1: growing a first bonding layer on the substrate of the ion trap chip;

[0008] S2: growing a second bonding layer on the material required for the thick film layer;

[0009] S3: bonding the first bonding layer to the second bonding layer through a bonding process;

[0010] S4: Through the thinning process, the thickness of the material required for the thick film layer is reduced to a preset thickness.

[0011] Furthermore, the thickness of the first bonding layer and the second bonding layer are both in the range of 10-100 nanometers.

[0012] Furthermore, in step S1, a first bonding layer is grown on the substrate of the ion trap chip, and the following steps are also included:

[0013] S11, preparing a preliminary sheet having a first conductive material on a substrate of the ion trap chip;

[0014] A first bonding layer having a second conductive material is grown on the prepared wafer, and the second conductive material is grown on the surface of the first conductive material.

[0015] Furthermore, step S11 specifically includes:

[0016] S111, growing n layers of thin film on a substrate of the ion trap chip to form a preparatory sheet, where n is an integer greater than or equal to 0; wherein the preparatory sheet comprises a plurality of first through holes that vertically penetrate the preparatory sheet, and the first through holes are filled with a first conductive material by metallization to achieve electrical interconnection between the upper and lower surfaces of the preparatory sheet;

[0017] S112. A graphic first bonding layer is grown on the surface of the prepared sheet, wherein the first bonding layer has a plurality of second through holes, and a second conductive material is contained in the second through holes. The second conductive material is grown on the surface of the first conductive material, and the second conductive material is insulated from the first bonding layer.

[0018] Furthermore, in step S2, a second bonding layer is grown on the material required for the thick film layer, and the following steps are also included:

[0019] S21. Growing a second bonding layer having a fourth conductive material on the thick film layer having the third conductive material.

[0020] Furthermore, step S21 specifically includes:

[0021] S211, preparing a plurality of blind holes or a plurality of third through holes on the thick film layer, wherein the blind holes or the third through holes are filled with a third conductive material by metallization;

[0022] S212. A graphic second bonding layer is grown on the surface of the thick film layer, wherein the second bonding layer has a plurality of fourth through holes, and a fourth conductive material is contained in the fourth through holes. The fourth conductive material is grown on the surface of the third conductive material, and the fourth conductive material is insulated from the second bonding layer.

[0023] Furthermore, the number of the blind holes or the third through holes is the same as the number of the first through holes, and the arrangement positions correspond one to one.

[0024] Further, S3: bonding the first bonding layer to the second bonding layer through a bonding process, further comprising:

[0025] Before bonding, the fourth conductive material and the second conductive material are aligned by infrared alignment, sheet-to-sheet alignment or surface-to-surface alignment, and then a bonding process is performed.

[0026] Furthermore, step S4 further includes:

[0027] The thickness of the material required for the thick film layer is reduced to a preset thickness by chemical mechanical polishing, and at the same time, the roughness is polished to a preset roughness, wherein the preset thickness is: less than 200um, and the preset roughness is: less than 50nm.

[0028] Furthermore, the method further comprises:

[0029] S5: annealing the ion trap chip with a thick film layer obtained after bonding and thinning at a preset temperature for a preset time under vacuum so that the first bonding layer and the second bonding layer meet the preset requirements after bonding, wherein the preset temperature is: 250~900℃, and the preset time is: 0.5~6h.

[0030] The present invention provides a method for generating a thick film layer of an ion trap chip, which solves the problem of preparing a dielectric layer below 200 microns in the ion trap chip, that is, it avoids the speed limitation caused by the growth method adopted for the entire ion trap chip, and also solves the problem that the thicker the grown film, the more difficult it is to ensure the quality, thereby laying a foundation for quantum information processing based on ion trap chips.

[0031] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings to be used in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A flow chart of a method for generating a thick film layer of an ion trap chip according to an embodiment of the present invention is shown;

[0034] Figure 2 A structural diagram showing the formation of a preliminary sheet according to an embodiment of the present invention is shown;

[0035] Figure 3 A structural diagram of growing a first bonding layer according to an embodiment of the present invention is shown;

[0036] Figure 4 It shows a thick film layer structure diagram after preparing a plurality of blind holes or a plurality of third through holes according to an embodiment of the present invention;

[0037] Figure 5 A structural diagram of growing a second bonding layer according to an embodiment of the present invention is shown;

[0038] Figure 6 It shows the overall structure formed after BD bonding according to an embodiment of the present invention;

[0039] Figure 7 The embodiment of the present invention is shown Figure 6 The overall structure diagram shown is the structure diagram after thinning. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] like Figure 1 As shown, the present invention provides a method for generating a thick film layer of an ion trap chip, the method comprising:

[0042] S1: growing a first bonding layer 1 on a substrate of the ion trap chip;

[0043] S2: growing a second bonding layer 3 on the material required for the thick film layer 4;

[0044] S3: bonding the first bonding layer 1 and the second bonding layer 3 through a bonding process;

[0045] S4: Through a thinning process, the thickness of the material required for the thick film layer 4 is reduced to a preset thickness.

[0046] The method of the present invention is described in detail below.

[0047] In some embodiments of the present invention, the substrate material of the ion trap chip and the material required for the thick film layer 4 include but are not limited to silicon wafer, sapphire, glass, metal, semiconductor, alloy, photoresist, etc. For example, in the form of "material of the ion trap chip substrate - material required for the thick film layer", it can be any of the following combinations:

[0048] Silicon wafer-glass, metal and glass, semiconductor-alloy, semiconductor-glass, photoresist-photoresist, etc.

[0049] In addition, in some embodiments of the present invention, the first bonding layer 1 and the second bonding layer 3 include but are not limited to materials such as lead tin, gold tin, copper tin, gold silicon, gold, etc. In addition, in this embodiment, the thickness level of the first bonding layer 1 and the second bonding layer 3 is 10-100 nanometers.

[0050] In some embodiments of the present invention, in step S1, a first bonding layer 1 is grown on a substrate of an ion trap chip, and the step further includes: S11, on the substrate of the ion trap chip, a preparatory sheet (5) having a first conductive material is prepared; on the preparatory sheet (5), a first bonding layer (1) having a second conductive material (7) is grown, and the second conductive material (7) is grown on the surface of the first conductive material (6). Specifically, the step includes:

[0051] S111. On the substrate of the ion trap chip, n layers of thin film are grown to form a preparatory sheet 5 (how to grow them is not described in detail in the present invention), where n is an integer greater than or equal to 0; wherein the preparatory sheet 5 includes a plurality of first through holes longitudinally penetrating the preparatory sheet 5, and the first through holes are filled with a first conductive material 6 by metallization (including grouting solidification, side sputtering, electroplating, etc.) to achieve electrical interconnection between the upper and lower surfaces of the preparatory sheet 5; S112. A graphic first bonding layer 1 is grown on the surface of the preparatory sheet 5, wherein the first bonding layer 1 has a plurality of second through holes (9), and a second conductive material 7 is contained in the second through holes (9), and the second conductive material 7 is grown on the surface of the first conductive material 6, and the second conductive material 7 is insulated from the first bonding layer 1, and belongs to the same material as the first bonding layer 1.

[0052] In some embodiments of the present invention, before growing the second bonding layer 3 on the material required for the thick film layer 4, if the thickness of the material is greater than 500 microns, the following steps are further included: polishing the material required for the thick film layer with a thickness level of greater than 500 microns to a thickness of 200-500 microns by mechanical polishing to form a thick film layer 4. After the thick film layer 4 is formed, in step S2, growing the second bonding layer 3 on the material required for the thick film layer 4 also includes: growing the second bonding layer 3 having the fourth conductive material 2 on the thick film layer 4 having the third conductive material (8), specifically including:

[0053] S211, preparing a plurality of blind holes or a plurality of third through holes on the thick film layer 4, wherein the blind holes or the third through holes are filled with a third conductive material 8 by metallization (including grouting curing, side sputtering, electroplating, etc.);

[0054] S212. A graphic second bonding layer 3 is grown on the surface of the thick film layer 4, wherein the second bonding layer 3 has a plurality of fourth through holes 10, and a fourth conductive material 2 is contained in the fourth through holes 10. The fourth conductive material 2 is grown on the surface of the third conductive material 8, and the fourth conductive material 2 is insulated from the second bonding layer 3 and belongs to the same material as the second bonding layer 3.

[0055] Wherein, in the above-mentioned step S1 and step S2, the number of the blind holes or the third through holes is the same as the number of the first through holes, and the arrangement positions correspond one to one.

[0056] In some embodiments of the present invention, S3: bonding the first bonding layer 1 to the second bonding layer 3 through a bonding process, also includes: before bonding, aligning the fourth conductive material 2 to the second conductive material 7 through infrared alignment, sheet-to-sheet alignment, and face-to-face alignment, and then performing a bonding process.

[0057] In some embodiments of the present invention, the material required for the thick film layer 4 is silicon dioxide material, but it should be understood that the material required for the thick film layer 4 may not only be silicon dioxide material. The material required for obtaining a thick film layer 4 with a thickness of more than 10um (for example, more than 10um) according to the method of this embodiment may also be other materials, such as gold, silicon nitride, sapphire material, etc.

[0058] In some embodiments of the present invention, step S4 is further included, namely: thinning the bonded thick film layer material to a preset thickness by chemical mechanical polishing, and the preset thickness can expose the third conductive material 8 in the blind hole. In addition, step S4 also includes: while thinning the thickness of the material required for the thick film layer 4 to a preset thickness, polishing the roughness to a preset roughness. The preset thickness is: less than 200um, and the preset roughness is: less than 50nm.

[0059] In some embodiments of the present invention, after step S4, the method further comprises the following steps:

[0060] S5: annealing the ion trap chip with a thick film layer obtained after bonding and thinning under vacuum at a preset temperature and a preset time, so that the first bonding layer 1 and the second bonding layer 3 meet the preset requirements after bonding. The preset temperature is: 250-900°C, and can be 300°C for example, and the preset time is: 0.5-6h, and can be 1h for example.

[0061] The above is a description of the method of the present invention. Figure 2-Figure 7 The present invention is described with a specific example as follows:

[0062] S1: growing a first bonding layer 1 on a substrate of an ion trap chip, wherein the substrate material of the ion trap chip and the material required for the thick film layer are both silicon wafers, specifically comprising: S111, such as Figure 1 As shown, on the substrate of the ion trap chip, n layers of thin film are grown to form a preliminary sheet 5 (i.e. Figure 1 A) in Figure 2 As shown, the preparatory sheet 5 includes a plurality of first through holes that vertically penetrate the preparatory sheet 5, and the first through holes are filled with a first conductive material 6. At this time, the upper and lower surfaces of the preparatory sheet 5 are electrically interconnected; S112, as Figure 3 As described above, a patterned first bonding layer 1 (i.e. Figure 1 In B), the first bonding layer 1 has a plurality of second through holes 9. The second through holes 9 contain a second conductive material 7, which grows on the surface of the first conductive material 6, and the second conductive material 7 is insulated from the first bonding layer 1.

[0063] The material of the main body of the first bonding layer 1 is the same as that of the second conductive material 7, which is made of lead-tin material with a thickness of 50 nanometers.

[0064] S2: In the thick film layer 4 (i.e. Figure 1 C) The second bonding layer 3 (i.e. Figure 1 D), wherein, since the thickness of the material required for the thick film layer 4 is less than 200 microns and is made of silicon dioxide material, before the growth, the material required for the thick film layer of 500 microns is polished to a thickness of 200 microns to form the thick film layer 4. After the thick film layer 4 is formed, the following steps are performed: S211, as Figure 4 As shown, a plurality of blind holes are prepared on the polished thick film layer 4, wherein the blind holes are filled with a third conductive material 8; S212, as shown Figure 5As shown, a graphic second bonding layer 3 is grown on the surface of the thick film layer 4, wherein the second bonding layer 3 has a plurality of fourth through holes 10, and a fourth conductive material 2 is contained in the fourth through holes 10. The fourth conductive material 2 grows on the surface of the third conductive material 8, and the fourth conductive material 2 is insulated from the second bonding layer 3.

[0065] The material of the second bonding layer 3 body is the same as that of the fourth conductive material 2, which is made of lead-tin material with a thickness of 50 nanometers.

[0066] S3: Before bonding, the fourth conductive material 2 and the second conductive material 7 are aligned by infrared alignment and then a bonding process is performed. Figure 6 As shown, the first bonding layer 1 and the second bonding layer 3 are BD-bonded, so that Figure 3 and Figure 5 form Figure 6 an overall structure;

[0067] S4: Through thinning process, such as Figure 7 As shown, the thickness of the material required for the thick film layer is reduced to 50um to form Figure 7 The chip structure is that after the thick film layer is polished, the third conductive material 8 in the blind hole is exposed, so that the surface of the thick film layer 4 away from the second bonding layer 3 and the surface of the preparatory sheet 5 away from the first bonding layer 1 are electrically interconnected, and then the roughness is polished to 1nm to meet the requirements.

[0068] S5: The ion trap chip with a thick film layer obtained after bonding and thinning is annealed at a preset temperature of 300° C. for 1 hour under vacuum to allow the BD to have better bonding after bonding.

[0069] In summary, the present invention core solves the problem of preparing a dielectric layer of tens of microns in an ion trap chip, laying a foundation for quantum information processing based on ion trap chips.

[0070] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for forming a thick film layer of an ion trap chip, characterized in that: The method comprises: S1: growing a first bonding layer (1) on a substrate of the ion trap chip; S2: growing a second bonding layer (3) on the material required for the thick film layer (4); S3: bonding the first bonding layer (1) and the second bonding layer (3) through a bonding process; S4: Through a thinning process, the thickness of the material required for the thick film layer (4) is reduced to a preset thickness.

2. The method for forming a thick film layer of an ion trap chip according to claim 1, characterized in that: The thickness of the first bonding layer (1) and the second bonding layer (3) are both in the range of 10-100 nanometers.

3. The method for forming a thick film layer of an ion trap chip according to claim 2, characterized in that: In step S1, a first bonding layer (1) is grown on a substrate of an ion trap chip, and the step also includes the following steps: S11, preparing a preliminary sheet (5) having a first conductive material on a substrate of the ion trap chip; A first bonding layer (1) having a second conductive material (7) is grown on a preparatory sheet (5), and the second conductive material (7) is grown on the surface of the first conductive material (6).

4. The method for forming a thick film layer of an ion trap chip according to claim 3, characterized in that: Step S11 specifically includes: S111, growing n layers of thin film on the substrate of the ion trap chip to form a preparatory sheet (5), where n is an integer greater than or equal to 0; wherein the preparatory sheet (5) comprises a plurality of first through holes that vertically penetrate the preparatory sheet (5), and the first through holes are filled with a first conductive material (6) by metallization to achieve electrical interconnection between the upper and lower surfaces of the preparatory sheet (5); S112. A patterned first bonding layer (1) is grown on the surface of the preparatory sheet (5), wherein the first bonding layer (1) has a plurality of second through holes (9), and a second conductive material (7) is contained in the second through holes (9). The second conductive material (7) is grown on the surface of the first conductive material (6), and the second conductive material (7) is insulated from the first bonding layer (1).

5. The method for forming a thick film layer of an ion trap chip according to claim 2, characterized in that: In step S2, a second bonding layer (3) is grown on the material required for the thick film layer (4), and the step also includes the following steps: S21. Growing a second bonding layer (3) having a fourth conductive material (2) on the thick film layer (4) having a third conductive material (8).

6. The method for forming a thick film layer of an ion trap chip according to claim 5, characterized in that: Step S21 specifically includes: S211, preparing a plurality of blind holes or a plurality of third through holes on the thick film layer (4), wherein the blind holes or the third through holes are filled with a third conductive material (8) by metallization; S212. A patterned second bonding layer (3) is grown on the surface of the thick film layer (4), wherein the second bonding layer (3) has a plurality of fourth through holes (10), and a fourth conductive material (2) is contained in the fourth through holes (10). The fourth conductive material (2) is grown on the surface of the third conductive material (8), and the fourth conductive material (2) is insulated from the second bonding layer (3).

7. The method for forming a thick film layer of an ion trap chip according to claim 3, characterized in that: The number of the blind holes or the third through holes is the same as the number of the first through holes, and the arrangement positions correspond one to one.

8. The method for forming a thick film layer of an ion trap chip according to claim 3, characterized in that: S3: Bonding the first bonding layer (1) and the second bonding layer (3) through a bonding process, further comprising: Before bonding, the fourth conductive material (2) and the second conductive material (7) are aligned by infrared alignment, sheet-to-sheet alignment or surface-to-surface alignment, and then the bonding process is performed.

9. A method for forming a thick film layer of an ion trap chip according to any one of claims 1 to 8, characterized in that: Step S4 also includes: The thickness of the material required for the thick film layer (4) is reduced to a preset thickness by chemical mechanical polishing, and at the same time, the roughness is polished to a preset roughness, wherein the preset thickness is less than 200 um and the preset roughness is less than 50 nm.

10. A method for forming a thick film layer of an ion trap chip according to any one of claims 1 to 8, characterized in that: The method further comprises: S5: annealing the ion trap chip having the thick film layer (4) obtained after bonding and thinning at a preset temperature for a preset time under vacuum, so that the first bonding layer (1) and the second bonding layer (3) meet preset requirements after bonding, wherein the preset temperature is: 250 to 900° C., and the preset time is: 0.5 to 6 hours.

Images