Automatic test system and method for multi-chip integrated SIP (Session Initiation Protocol) module

Abstract

The invention discloses an automatic test system and method for a multi-chip integrated SIP (Session Initiation Protocol) module, after the test system independently tests each chip, the interconnection communication and cooperative work condition between an FPGA (Field Programmable Gate Array) and an ARM (Advanced RISC Machines) in the SIP module can be comprehensively detected through the whole system test, and the problem of multi-chip interconnection test is effectively solved. According to the automatic test system, through unified control and management of the upper computer, the full-automatic process from programming to test result output is achieved, manual intervention is reduced, and the test efficiency and accuracy are improved. Through the independent test of the upper computer on each chip and the comprehensive data collection and analysis of the whole system test, the fault location can be more accurately judged, and the troubleshooting and repairing time is greatly shortened. Therefore, the system provided by the invention improves the test automation, the test coverage rate and the test expandability of the SIP.

Description

Technical Field

[0001] The invention belongs to the technical field of testing a SIP package module, and relates to an automatic testing system and method for a multi-chip integrated SIP module. Background Art

[0002] With the rapid iteration and upgrading of semiconductor technology, the development of large-scale integrated circuits can no longer adapt to Moore's Law. The system-in-package (SIP) integrated circuit technology proposed in the 1990s is a new idea to solve this problem. SIP is an integrated circuit packaging technology that integrates multiple dies and passive devices in a single package. SIP has brought great convenience in the development of miniaturization, lightness, high density and high reliability of the system. Traditional large-scale integrated circuit chips can generally be tested through the JTAG test technology specified in the IEEE 1149.1 standard, but there is currently no complete set of mature and standard test methods for SIP.

[0003] As a complex multi-device fusion chip, the SIP package module must not only test each discrete device, but also the interconnection relationship between the devices and the relationship between the external pins. The complexity brought by the high integration and the connectivity problems of the closed micro-interconnections between chips have brought great testing difficulties to the SIP package module. ATE (automatic test equipment) testing usually targets traditional independently packaged chips, and it is difficult to directly apply a collection of single-chip testing methods to the SIP package module. ATE testing has problems such as incompatibility between multi-chip test vectors and machines, and the balance between test coverage and test time. The existing functional testing methods have many steps of human intervention and cannot realize the automation of the test process. Summary of the invention

[0004] The purpose of the present invention is to solve the problems in the prior art and to provide an automatic testing system and method for a multi-chip integrated SIP module.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] The present invention provides an automatic test system for a multi-chip integrated SIP module, comprising a host computer and a SIP to be tested installed on a test board;

[0007] The SIP to be tested includes an FPGA and an ARM; the first port of the host computer is connected to the FPGA for programming and erasing the EEPROM of the FPGA; the second port of the host computer is connected to the ARM for programming and erasing the Flash in the ARM and the Flash on the test board; the third port of the host computer is connected to the UART communication interface of the SIP to be tested for transmitting test result information; the FPGA is connected to the ARM; the SIP to be tested is connected to the external Flash on the test board.

[0008] Preferably, the first port of the host computer is connected to the FPGA via a JTAG interface; and the second port of the host computer is connected to the ARM via a JTAG interface.

[0009] Preferably, a power supply module mounted on a test board is connected to the SIP to be tested.

[0010] Preferably, the host computer includes serial port display, sending FPGA test code burning instructions, sending test start and end instructions, ARM program burning instructions, test information printing and saving functions.

[0011] Preferably, an IO Bank interconnection IP core, a functional IP core and a test IP core are provided in the FPGA.

[0012] Preferably, the IO Bank interconnection IP core is a test module implemented by GPIO IP, which is used to test the connectivity between FPGA and SIP chip pins.

[0013] Preferably, the functional IP core is a 3-way Ethernet IP core, which is used to expand the Ethernet function of the SIP to be tested.

[0014] Preferably, the test IP core is a clock detector, which is used to test the clock source in the SIP to be tested.

[0015] Preferably, the Ethernet of the SIP to be tested, the UART of the SIP to be tested, and the CAN of the SIP to be tested are all connected to a PHY chip or a transceiver, and the PHY chip or the transceiver is connected to a test board.

[0016] The present invention provides an automated testing method for a multi-chip integrated SIP module, comprising:

[0017] The host computer issues a test command to download the ARM test code and FPGA code to the external Flash and the EEPROM in the FPGA respectively;

[0018] After the SIP to be tested is powered on, the external Flash is used to start the execution of the ARM test program, which is executed together with the test program of the EEPROM in the FPGA to complete the test;

[0019] The host computer exchanges data with the UART communication interface of the SIP to be tested, obtains the status information and test data of the SIP to be tested during operation, and the host computer receives and displays the status information and test data.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention proposes an automated testing system for a multi-chip integrated SIP module. For a multi-chip integrated SIP module including FPGA and ARM, the traditional single chip testing method is difficult to meet its overall testing requirements. The testing system can simultaneously perform targeted programming and testing operations for different types of chips (FPGA and ARM), integrate the programming and erasing operations of FPGA and ARM in a host computer, and solve the problem of cumbersome multi-chip download program operations. Due to the complex interconnection relationship between the bare cores in the SIP module, it is difficult for traditional testing methods to efficiently test the functions and interconnection relationships of all bare cores. However, after testing each chip separately, the testing system can comprehensively detect the interconnection communication and collaborative working conditions between FPGA and ARM through the overall system test, effectively solving the problem of multi-chip interconnection testing. In the past, the testing process may require manual switching of different test equipment and manual input of a large number of test instructions and data, which is not only inefficient, but also prone to human errors. The automated testing system realizes a fully automated process from programming to test result output through unified control and management of the host computer, reduces manual intervention, and improves test efficiency and accuracy. Traditional chip function tests are only for a single chip, while the SIP to be tested is a multi-chip integrated module, which requires testing the interconnection channels and interconnection functions between the chips. This test system can more accurately determine the location of the fault, such as the error in the interconnection relationship of the bare core in the SIP module, the error in the connection relationship between the chip and the external pins in the SIP module, or the failure of the chip function, through the independent test of each chip by the host computer and the comprehensive data collection and analysis of the overall system test. This greatly shortens the time for troubleshooting and repairing. Therefore, the system proposed by the present invention improves the test automation, test coverage and test scalability of the SIP. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0023] Figure 1This is a structural diagram of the automated testing system for the multi-chip integrated SIP module of the present invention.

[0024] Figure 2 This is an example diagram of the modules in the FPGA of the present invention.

[0025] Figure 3 It is a schematic diagram of the host computer function of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0029] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0030] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0031] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0033] The present invention proposes an automated testing system for a multi-chip integrated SIP module, such as Figure 1 As shown, it includes a host computer and a SIP to be tested installed on a test board;

[0034] The SIP module to be tested contains FPGA and ARM; the first port of the host computer is connected to the FPGA for programming and erasing the EEPROM of the FPGA; the second port of the host computer is connected to the ARM for programming and erasing the Flash in the ARM and the Flash on the test board; the third port of the host computer is connected to the UART communication interface of the SIP to be tested for transmitting test result information; the FPGA is connected to the ARM; the SIP to be tested is connected to the external Flash on the test board for storing the test program.

[0035] The SIP to be tested is connected to a power supply module installed on a test board, and the Ethernet of the SIP to be tested, the UART of the SIP to be tested, and the CAN of the SIP to be tested are all connected to a PHY chip or a transceiver, and the PHY chip or the transceiver is connected to the test board. Among them, the PHY chip / transceiver, the power supply module, and the external Flash are all installed on the test board, and the power supply module provides power for the test board and the SIP to be tested.

[0036] like Figure 2 The figure shows the schematic diagram of each module in the FPGA, which is equipped with IO Bank interconnection IP core, functional IP core and test IP core.

[0037] The IO Bank interconnect IP core is a test module implemented by GPIO IP, which is mainly responsible for the connectivity test between the FPGA in the SIP module and the SIP pins to be tested. The IO Bank interconnect IP is a test module implemented by GPIO IP, which can simply and flexibly test the connectivity of the external interconnect test pins. Through the special GPIO IP design, test signals can be sent to each external interconnect pin in a systematic and targeted manner, and feedback can be accurately received, so as to accurately determine whether the connection between the pins is normal. This is crucial to ensure the reliability of the physical connection between the entire SIP to be tested and external devices or other modules. When there is an interconnect failure problem related to the FPGA inside the SIP package, the scope and difficulty of troubleshooting are greatly simplified because the test module can clearly point out which external interconnect test pins have connectivity problems. Designers or testers can quickly locate specific pins or connection lines, reducing the time and cost of fault diagnosis, improving the maintenance efficiency of the entire system, and ensuring the stability and availability of the SIP to be tested in actual applications. The GPIO IP here is a general test IP that can be used in other SIP tests.

[0038] The functional IP core is a 3-way Ethernet IP core, which is used to expand the Ethernet function of the SIP to be tested. The main function of the functional IP core is to expand the Ethernet function of the SIP. One of its functions is to test the interconnection with the Ethernet function of the SIP ARM itself, and the other function is to test the IP in the actual application in advance during the chip testing phase. The functional IP here can also be other functional IP modules. This method of integrating the IP in the application into the testing phase in advance greatly reduces the application risk of the SIP and improves the testing efficiency of the SIP.

[0039] The test IP core is a clock detector, which is used to test the clock source in the SIP to be tested. The test IP core is a clock detector, which can test the clock source in the SIP to be tested in real time and accurately. The clock detector can continuously monitor the status of the clock source, promptly detect abnormal conditions such as clock frequency deviation and jitter, ensure that the system runs under the drive of a stable and reliable clock signal, and avoid system errors, data loss or performance degradation caused by clock problems. Through effective testing and monitoring of the clock source, system crashes or instability caused by clock failures can be prevented in advance. In some application scenarios with extremely high requirements for system reliability, timely detection and handling of clock problems can effectively ensure the security and stability of the entire system, prevent serious accidents or erroneous operations caused by minor clock anomalies, and improve the reliability and trust of the SIP to be tested in key application areas. The test IP core here can also be other test modules used to test SIP internal resources or functions.

[0040] The first port of the host computer is connected to the FPGA via a JTAG interface; the second port of the host computer is connected to the ARM via a JTAG interface. The host computer includes serial port display, sending FPGA test code burning instructions, sending test start and end instructions, ARM program burning instructions, test information printing and saving functions.

[0041] The data transmission process of an automated test system for a multi-chip integrated SIP module: the host computer issues a test instruction and downloads the test FPGA code *.mcs to the SIP to be tested through the JTAG interface. When the test board is first obtained, the host computer downloads the test program to the external Flash on the test board through another JTAG interface, and there is no need to download the test program in subsequent tests. After power-on, the program to be tested is started and executed from the external Flash, and each test result is uploaded to the host computer through the UART communication interface and displayed. An automated test method for a multi-chip integrated SIP module, comprising the following steps:

[0042] Step 1: The host computer issues a test command to download the ARM test code and FPGA code to the external Flash and the EEPROM in the FPGA respectively;

[0043] Step 2: After the SIP to be tested is powered on, the external Flash is used to start the execution of the ARM test program, and the test program of the EEPROM in the FPGA is executed together to complete the test;

[0044] Step 3: The host computer exchanges data with the UART communication interface of the SIP to be tested to obtain the status information and test data of the SIP to be tested during operation. The host computer receives the status information and test data and displays them, thereby realizing the automated test of the SIP module.

[0045] The present invention proposes an automated test system for a multi-chip integrated SIP module, wherein the functions of the host computer mainly include starting and ending the test, displaying and saving the test results, burning the board-level flash program and the bit stream burning of the FPGA, etc. The test board provides the SIP to be tested with a power-on self-loading function, and also includes all peripheral devices required for the test process, providing a hardware basis for the test of the SIP to be tested. Functional modules, IO BANK interconnection modules, special test item modules, etc. are instantiated in the FPGA, providing hardware extension functions for the test of the SIP. The test code and the FPGA code cooperate to complete the full traversal test of the functions and interconnections of all bare cores inside the SIP chip, providing a software basis for the test, and the test code is burned into the flash of the test board. The host computer software in the present invention mainly includes functions such as serial port display, sending FPGA test code burning instructions, sending test start and end instructions, ARM program burning instructions, and printing and saving test information. The host computer can complete the erasing and burning of FPGA and ARM programs without opening the ARM development environment and GUI interfaces such as Impact, thereby reducing the number of manual operations.

[0046] The bit stream programming of FPGA in the present invention is implemented by a windows batch program *.bat script, which is integrated into the host computer software. The main steps and script codes are as follows:

[0047] (1). First set the path to ISE_DS, and then run the *.cmd script of impact.exe.

[0048] set PATH=D:\ise\14.4\ISE_DS;

[0049] settings64.bat D:\ise\14.4\ISE_DS\ISE\bin\nt64\impact.exe-batch*.cmd

[0050] (2) Execute script code to erase and program FPGA

[0051] setMode-bs

[0052] setCable-port auto

[0053] Identify-infer

[0054] identifyMPM

[0055] assignFile -p 1 -file "*.mcs"

[0056] setAttribute-position 1-attrpackageName-value""

[0057] Erase-p 1

[0058] Program-p 1-e-parallel-defaultVersion 0

[0059] Quit

[0060] The flash program burning on the test board in the present invention is implemented by using the jlink script, which is integrated in the host computer software. The main steps and script codes are as follows:

[0061] (1). First set the path to JLink, and then run the *.txt script of JLink.exe.

[0062] set PATH=C:\Program Files\SEGGER\JLink;

[0063] echo -e '\n'|JLink.exe*.txt

[0064] (2). Execute the script code to erase and burn the ARM internal storage space

[0065] usb 0

[0066] si 0

[0067] speed 4000

[0068] device device_name

[0069] r

[0070] h

[0071] erase

[0072] loadbin*.bin 0x800000

[0073] exit

[0074] like Figure 3The schematic diagram of the host computer functions is shown. It integrates the Impact script tool, JLink script tool, etc. to realize the host computer sending instructions to program and erase the FPGA and ARM in the SIP. The display and save functions refer to displaying and saving the test result information of the UART communication interface. The integration of various links of the test requirements is to provide different test information combinations according to the different production stages of the SIP, such as the parameters of the three-temperature environment, the sending of instructions in different test stages, etc. The test instruction sending refers to the instruction buttons in the host computer. Through these buttons, the host computer can send instructions to the SIP to burn the FPGA test MCS, print the test result information, etc. The function button refers to some software-related functions of the host computer, such as clearing the result display information, etc.

[0075] The present invention proposes a SIP module test system based on a test board, a host computer, test software and FPGA. The test software is burned into the flash on the test board, and the program in the flash of the test board is self-loaded after power-on, and the internal modules of the SIP are automatically tested for functions and interconnection. The FPGA in the SIP implements modules such as functional IP core, test IP core and IOBank, and mainly performs interconnection and function tests of the SIP. The host computer software completes the injection of FPGA test code in the SIP and the injection of test program in the flash, and the batch program is used to complete the injection with one key, and the program injection process is simple and easy to operate. The automated test process eliminates the need for a large amount of manual operation in the entire test process, and the host computer can quickly program, test and analyze the results of FPGA and ARM. Since the fault can be quickly located, the time spent on troubleshooting and repairing is reduced, and the turnover efficiency of the entire test and production is further improved, so that the product can be put on the market or enter the next production link faster. The host computer tests FPGA, ARM and other bare cores according to the preset precise test program and standard, avoiding the possible misoperation and subjective judgment errors in manual testing. The comprehensive test of the entire system and the detailed test result analysis can comprehensively detect various problems that may exist in the bare core and interconnection relationship of the SIP module. Whether it is a functional defect of the chip itself or an abnormality in the interconnection between chips, it can be discovered and recorded more accurately, improving the reliability of product quality. The host computer software can be easily upgraded and updated to meet the testing requirements of different versions of FPGA and ARM chips, or to add new test items and functions. The architecture design of the test system is easy to expand, and the test function of other chips or components can be added as needed.

[0076] The effects achieved by the present invention are as follows:

[0077] 1) The present invention utilizes FPGA and ARM in SIP, stores the test program in board-level flash, and completes function and interconnection tests on all modules and bare cores of SIP, with a test coverage rate close to 100%.

[0078] 2) The IP cores implemented in the FPGA of the present invention include functional IP cores, extended test IP cores, and IO BANK cores, etc. The test content is closer to the use scenario of the chip, and the IO BANK core is used to perform interconnection testing on the external pins of the SIP chip.

[0079] 3) The host computer software in the present invention integrates the FPGA program injection and ARM program injection functions into the host computer software, and can complete the loading of FGPA test code and SIP burn-in program with one click, which is simple to operate. The host computer software and the test program are independently developed with low coupling, which makes the host computer software highly portable and can be applied to the testing of other SIPs containing FPGA and ARM.

[0080] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An automated testing system for a multi-chip integrated SIP module, characterized in that: It includes a host computer and the SIP to be tested installed on a test board; The SIP to be tested includes an FPGA and an ARM; the first port of the host computer is connected to the FPGA for programming and erasing the EEPROM of the FPGA; The second port of the host computer is connected to the ARM for programming and erasing the Flash in the ARM and the Flash on the test board; the third port of the host computer is connected to the UART communication interface of the SIP to be tested for transmitting test result information; the FPGA is connected to the ARM; the SIP to be tested is connected to the external Flash on the test board.

2. The automated testing system for a multi-chip integrated SIP module according to claim 1, characterized in that: The first port of the host computer is connected to the FPGA via a JTAG interface; the second port of the host computer is connected to the ARM via a JTAG interface.

3. The automated testing system for a multi-chip integrated SIP module according to claim 1, characterized in that: The SIP to be tested is connected to a power supply module installed on a test board.

4. The automated testing system for a multi-chip integrated SIP module according to claim 1, characterized in that: The host computer includes serial port display, sending FPGA test code burning instruction, sending test start and end instructions, ARM program burning instruction, test information printing and saving functions.

5. The automated testing system for a multi-chip integrated SIP module according to claim 1, characterized in that: The FPGA is equipped with IO Bank interconnection IP core, functional IP core and test IP core.

6. The automated testing system for multi-chip integrated SIP modules according to claim 5, characterized in that: The IO Bank interconnection IP core is a test module implemented by GPIO IP, which is used to test the connectivity between FPGA and SIP chip pins.

7. The automated testing system for a multi-chip integrated SIP module according to claim 5, characterized in that: The functional IP core is a 3-way Ethernet IP core, which is used to expand the Ethernet function of the SIP to be tested.

8. The automated testing system for multi-chip integrated SIP modules according to claim 5, characterized in that: The test IP core is a clock detector, which is used to test the clock source in the SIP to be tested.

9. The automated testing system for a multi-chip integrated SIP module according to claim 1, characterized in that: The Ethernet of the SIP to be tested, the UART of the SIP to be tested, and the CAN of the SIP to be tested are all connected with a PHY chip or a transceiver, and the PHY chip or the transceiver is connected to the test board.

10. An automated testing method for a multi-chip integrated SIP module, characterized in that: An automated testing system for a multi-chip integrated SIP module according to any one of claims 1 to 9, comprising: The host computer issues a test command to download the ARM test code and FPGA code to the external Flash and the EEPROM in the FPGA respectively; After the SIP to be tested is powered on, the external Flash is used to start the execution of the ARM test program, which is executed together with the test program of the EEPROM in the FPGA to complete the test; The host computer exchanges data with the UART communication interface of the SIP to be tested, obtains the status information and test data of the SIP to be tested during operation, and the host computer receives and displays the status information and test data.

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