Clock error calculation method, device, equipment, storage medium and product

Abstract

The present application provides a clock error solution method, device, equipment, storage medium and product. The method includes: obtaining the observation data and epoch information required for the clock error solution of the current epoch; the observation data includes satellite and receiver pseudorange deviation estimates; according to the epoch information, determining the solution state information of the current epoch; when the solution state information indicates that the current epoch is not the first epoch, and no new satellites participate in the solution and no satellite restarts the solution, constructing the first observation equation corresponding to the clock error solution of the current epoch based on the satellite and receiver pseudorange deviation estimates; solving the first observation equation with the sum of the pseudorange hardware delay parameters of all satellites being 0 as the center of gravity reference constraint, and obtaining the clock error solution result of the current epoch.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a clock error solution method, device, equipment, storage medium and product. Background Art

[0002] The Global Navigation Satellite System (GNSS) has the characteristics of global coverage, all-weather and high precision, and is widely used in automobile navigation, surveying and mapping, aerospace and other fields. The high-precision positioning service of GNSS relies on satellite enhancement information.

[0003] In the prior art, satellite enhancement information requires a large number of observation stations to participate in the solution, and there are many errors and parameters involved. In the GNSS clock error solution, in order to avoid the rank deficiency of the clock error solution model, the clock error parameters are integrated with the pseudorange hardware delay parameters. It is usually assumed that the satellite and receiver pseudorange hardware delays are constants, and these two deviations are absorbed by other parameters to obtain a full-rank solution model. The satellite clock error absorbs the pseudorange hardware delay deviation, and the receiver clock error absorbs the receiver pseudorange hardware delay deviation. However, the hardware delay deviation is not a stable constant, and their time-varying parts will also cause deviations in other parameters. Since the influence of the pseudorange hardware delay deviation on the clock error solution is ignored, the clock error convergence process is relatively slow, and the clock error solution result is unstable, which is not conducive to the solution and affects the positioning accuracy. Summary of the invention

[0004] The embodiments of the present application provide a clock error solution method, device, equipment, storage medium and product, which can improve positioning accuracy.

[0005] In a first aspect, the present application provides a clock error solution method, the method comprising:

[0006] Obtaining observation data and epoch information required for clock error solution of the current epoch; the observation data includes satellite and receiver pseudorange deviation estimates;

[0007] Determining solution status information of the current epoch according to the epoch information;

[0008] When the solution status information indicates that the current epoch is not the first epoch, no new satellite participates in the solution, and no satellite restarts the solution, constructing a first observation equation corresponding to the clock error solution of the current epoch based on satellite and receiver pseudorange bias estimation;

[0009] The first observation equation is solved with the sum of the pseudorange hardware delay parameters of all satellites being 0 as a barycenter reference constraint to obtain a clock error solution result of the current epoch.

[0010] In some possible implementations, the method further includes:

[0011] When the solution state information indicates that the current epoch is the first epoch, a second observation equation corresponding to the clock error solution of the current epoch is constructed according to a preset pseudorange hardware delay.

[0012] In some possible implementations, when the solution state information indicates that the current epoch is the first epoch, after constructing a second observation equation corresponding to the clock error solution of the current epoch according to a preset pseudorange hardware delay, the method further includes:

[0013] The sum of the clock error parameters of all satellites is set to 0 as a barycenter reference constraint, and the second observation equation is solved to obtain the clock error solution result of the current epoch.

[0014] In some possible implementations, the second observation equation is:

[0015]

[0016] Among them, the superscript S represents the satellite number; the subscript r represents the receiver number; i represents the corresponding epoch number; Pseudorange phase observations without ionospheric combination; is the ionospheric-free combined carrier phase observation value; is the geometric distance between the station and the satellite; dt r is the receiver clock error; dt s is the satellite clock error; Tropospheric oblique delay; b r,if is the pseudorange hardware delay at the receiver; is the pseudorange hardware delay of the satellite end; is the phase hardware delay at the receiver end; is the phase hardware delay of the satellite end; is the phase ambiguity of the ionospheric-free combination; λ N is the phase wavelength of the ionosphere-free combination; is the sum of pseudorange multipath effects, observation noise and other unmodeled errors; is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

[0017] In some possible implementations, the first observation equation is:

[0018]

[0019] Among them, the superscript S represents the satellite number; the subscript r represents the receiver number; i represents the corresponding epoch number; Pseudorange phase observations without ionospheric combination; is the ionospheric-free combined carrier phase observation value; is the geometric distance between the station and the satellite; dt r is the receiver clock error; dt s is the satellite clock error; Tropospheric oblique delay; b r,if is the pseudorange hardware delay at the receiver; is the pseudorange hardware delay of the satellite end; is the phase hardware delay at the receiver end; is the phase hardware delay of the satellite end; is the phase ambiguity of the ionospheric-free combination; λ N is the phase wavelength of the ionosphere-free combination; is the sum of pseudorange multipath effects, observation noise and other unmodeled errors; is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

[0020] In some possible implementations, the method further includes:

[0021] When the solution state information indicates that the current epoch is not the first epoch, and a new satellite participates in the solution or a satellite restarts the solution, determining the corresponding first satellite that newly participates in the solution and the first satellite that newly starts the solution;

[0022] Determining pseudorange hardware delay parameters of satellites other than the first satellite in the observation data;

[0023] According to the pseudorange hardware delay parameter, a third observation equation corresponding to the clock error solution of the current epoch is constructed.

[0024] In some possible implementations, the obtaining of observation data required for clock error solution of the current epoch includes:

[0025] Obtain the original observation data required for clock error solution of the current epoch;

[0026] Eliminate gross error data in the original observation data;

[0027] Detect and mark cycle slip data in the original observation data to obtain observation data.

[0028] In a second aspect, the present application provides a clock error solving device, the device comprising:

[0029] An acquisition module is used to acquire the observation data and epoch information required for clock error solution of the current epoch; the observation data includes satellite and receiver pseudorange deviation estimates;

[0030] A determination module, used to determine the solution state information of the current epoch according to the epoch information;

[0031] A construction module, configured to construct a first observation equation corresponding to the clock error solution of the current epoch based on satellite and receiver pseudorange bias estimation when the solution state information indicates that the current epoch is not the first epoch, no new satellite participates in the solution, and no satellite restarts the solution;

[0032] A solution module is used to solve the first observation equation with the sum of the pseudo-range hardware delay parameters of all satellites being 0 as a center of gravity reference constraint to obtain a clock error solution result of the current epoch.

[0033] In a third aspect, the present application provides a clock error solution device, comprising: a processor, and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the clock error solution method as described above.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium having computer program instructions stored thereon, and the computer program instructions, when executed by a processor, implement the clock error solution method as described above.

[0035] In a fifth aspect, the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the clock error solution method described above.

[0036] The clock error solution method, device, equipment, storage medium and product provided in the embodiments of the present application obtain the observation data and epoch information required for the clock error solution of the current epoch, and then determine the solution status information of the current epoch based on the epoch information. When the solution status information indicates that the current epoch is not the first epoch, and no new satellites are involved in the solution and no satellite restarts the solution, the first observation equation corresponding to the clock error solution of the current epoch is constructed based on the satellite and receiver pseudorange deviation estimates, and then the sum of the pseudorange hardware delay parameters of all satellites is 0 as the center of gravity reference constraint, the first observation equation is solved to obtain the clock error solution result of the current epoch, and the convergence speed and stability of the clock error solution are improved by considering the pseudorange hardware delay deviation estimates of the satellite and the receiver, and the rank deficiency problem is solved by using the reference constraint. Through this method, the pseudorange hardware delay deviation and other solution parameters can be separated more accurately, thereby improving the stability of the clock error solution and improving the positioning accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present application can be better understood from the following description of the specific embodiments of the present application in conjunction with the accompanying drawings, in which:

[0038] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0039] Figure 1 is a flow chart of a clock error solution method provided by an embodiment of the present application;

[0040] Figure 2 is a flow chart of a clock error solution method provided by another embodiment of the present application;

[0041] Figure 3 is a flowchart of a clock error solution method provided by another embodiment of the present application;

[0042] Figure 4 It is a structural schematic diagram of a clock error solving device provided by an embodiment of the present application;

[0043] Figure 5 It is a schematic diagram of the hardware structure of the clock error solution device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0044] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0045] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0046] In order to solve the problems in the prior art, the embodiments of the present application provide a clock error solution method, device, equipment, storage medium and product. The clock error solution method provided in the embodiments of the present application is first introduced below.

[0047] Figure 1 FIG. 1 is a flow chart of a clock error calculation method provided by an embodiment of the present application. Figure 1 As shown, the method includes the following steps: S101 to S104.

[0048] S101: Obtaining the observation data and epoch information required for clock error solution of the current epoch; the above observation data includes satellite and receiver pseudorange deviation estimates.

[0049] Pseudorange deviation usually refers to the difference between the pseudorange signal observed by the receiver and the ideal value. These deviations may be caused by factors such as receiver hardware problems and satellite signal propagation environment. These pseudorange deviations are corrected based on historical data or real-time estimation.

[0050] In the specific implementation, "epoch" refers to a specific point in time, usually the observation time of the GNSS system. First, the data of the current epoch needs to be obtained, including system time, satellite and receiver status, antenna coordinates and other information. The observation data of the current epoch (including satellite pseudorange, carrier phase, etc.) is extracted from the received raw satellite signal, and the current status is also updated according to the epoch information.

[0051] S102: Determine the solution status information of the current epoch according to the epoch information.

[0052] In the specific implementation, it is necessary to analyze the status of the current epoch, including whether it is the first observation (first epoch), whether there are new satellites added to the solution, or whether there are satellites that have resumed participating in the solution. If the current epoch is the "first epoch", this usually means that the solution process starts from scratch and all relevant parameters need to be initialized. If the epoch is not the first epoch, it is necessary to compare the status of the previous epoch to determine whether there are new satellites added, or whether there are satellites that have exited the solution due to problems such as failures. Update the solution status based on the current epoch information. The solution status information involves whether there is new observation data, whether the clock error needs to be recalculated, etc.

[0053] S103: When the solution status information indicates that the current epoch is not the first epoch, and no new satellite has participated in the solution and no satellite has restarted the solution, a first observation equation corresponding to the clock error solution of the current epoch is constructed based on the satellite and receiver pseudorange deviation estimation.

[0054] In a specific implementation, when the solution status information indicates that the current epoch is not the first epoch, and no new satellites are involved in the solution and no satellite restarts the solution, a linear or nonlinear equation is constructed to represent the relationship between the clock error and the satellite pseudorange bias. In the equation, pseudorange biases of satellites and receivers are involved, and these biases need to be estimated and incorporated into the design of the equation, and these biases are integrated into the equation through a series of estimation methods.

[0055] S104: Taking the sum of the pseudorange hardware delay parameters of all satellites as 0 as the center of gravity reference constraint, solve the first observation equation to obtain the clock error solution result of the current epoch.

[0056] In the specific implementation, the sum of the pseudo-range hardware delay parameters of all satellites is 0 as the center of gravity reference constraint, and a certain numerical solution method (such as Gauss-Newton method, Kalman filter method, etc.) is used to solve this observation equation. The solution process will calculate the optimal clock error solution based on pseudo-range observation data, satellite and receiver deviation estimates, and global constraints to obtain the clock error solution result of the current epoch, that is, the receiver clock error deviation.

[0057] The clock error solution method provided in the embodiment of the present application obtains the observation data and epoch information required for the clock error solution of the current epoch, and then determines the solution status information of the current epoch based on the epoch information. When the solution status information indicates that the current epoch is not the first epoch, and no new satellites are involved in the solution and no satellite restarts the solution, the first observation equation corresponding to the clock error solution of the current epoch is constructed based on the satellite and receiver pseudorange deviation estimates, and then the sum of the pseudorange hardware delay parameters of all satellites is 0 as the center of gravity reference constraint, the first observation equation is solved to obtain the clock error solution result of the current epoch, and the convergence speed and stability of the clock error solution are improved by considering the pseudorange hardware delay deviation estimates of the satellite and the receiver, and the rank deficiency problem is solved by using the reference constraint. Through this method, the pseudorange hardware delay deviation and other solution parameters can be separated more accurately, thereby improving the stability of the clock error solution and improving the positioning accuracy.

[0058] In order to provide more accurate positioning and navigation services, in some implementations, the above method may further include the following steps:

[0059] When the above-mentioned solution state information indicates that the above-mentioned current epoch is the first epoch, a second observation equation corresponding to the clock error solution of the above-mentioned current epoch is constructed according to the preset pseudorange hardware delay.

[0060] In a specific implementation, when the above-mentioned solution state information is that the above-mentioned current epoch is the first epoch, the clock model of the receiver is initialized. Set a preset value for the satellite pseudorange hardware delay. This value is usually estimated based on the specifications and historical data of the receiver and satellite hardware equipment. Pseudorange hardware delay refers to the systematic error caused by factors such as receiver hardware, antenna, and signal processing. It is a known constant that can be obtained from the hardware specification table, and these values ​​are stored in a parameter file or database as known data for the solution process. Afterwards, based on the state information of the first epoch, combined with the preset pseudorange hardware delay, the second observation equation is constructed.

[0061] The above implementation of the embodiment of the present application determines whether the current epoch is the first epoch. If so, it initializes and prepares the preset value of the pseudorange hardware delay, corrects the pseudorange observation value based on the solution result of the first epoch, and adds the hardware delay term. Construct a new observation equation, solve it through a numerical solution (such as the least squares method or Kalman filtering), and update the clock error value. Then, it can gradually optimize the estimation of the clock error and provide more accurate positioning and navigation services.

[0062] In order to provide high-quality clock data, in some implementations, when the solution state information indicates that the current epoch is the first epoch, after constructing the second observation equation corresponding to the clock error solution of the current epoch according to the preset pseudorange hardware delay, the method further includes:

[0063] The sum of the clock error parameters of all satellites is set to 0 as the center of gravity reference constraint, and the second observation equation is solved to obtain the clock error solution result of the current epoch.

[0064] In the specific implementation, after the second observation equation is constructed, a barycentric reference constraint is introduced, that is, the sum of the clock error parameters of all satellites is set to 0. This constraint is to eliminate the overall offset caused by the receiver clock error, and it is assumed that the clock error of all satellites is statistically symmetric and the receiver clock error is a weighted average relative to these satellites. After the constraint is introduced, the second observation equation is solved by numerical methods such as least squares method or Kalman filtering to obtain the clock error solution result of the current epoch mentioned above.

[0065] The above implementation of the embodiment of the present application performs clock error calculation in each epoch based on pseudorange observations and preset hardware delay values, and ensures that the sum of all satellite clock errors is zero through the center of gravity reference constraint. The accuracy of clock error estimation is improved, and high-quality clock data is provided for the positioning and navigation of the receiver through the optimization algorithm.

[0066] In some embodiments, the second observation equation is:

[0067]

[0068] Where, the superscript S represents the satellite number, the subscript r represents the receiver number, and i represents the corresponding epoch number. Pseudorange phase observations without ionospheric combination. is the ionosphere-free combined carrier phase observation value. is the geometric distance between the station and the satellite. r is the receiver clock error. dt s is the satellite clock error. Tropospheric oblique delay. b r,if is the pseudorange hardware delay at the receiver. is the pseudorange hardware delay on the satellite side. is the phase hardware delay at the receiver end. is the phase hardware delay of the satellite end. is the phase ambiguity of the ionospheric-free combination. N is the phase wavelength of the ionosphere-free combination. is the sum of pseudorange multipath effects, observation noise and other unmodeled errors. is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

[0069] In some embodiments, the first observation equation is:

[0070]

[0071] Where, the superscript S represents the satellite number, the subscript r represents the receiver number, and i represents the corresponding epoch number. Pseudorange phase observations without ionospheric combination. is the ionosphere-free combined carrier phase observation value. is the geometric distance between the station and the satellite. r is the receiver clock error. dt s is the satellite clock error. Tropospheric oblique delay. b r,if is the pseudorange hardware delay at the receiver. is the pseudorange hardware delay on the satellite side. is the phase hardware delay at the receiver end. is the phase hardware delay of the satellite end. is the phase ambiguity of the ionospheric-free combination. N is the phase wavelength of the ionosphere-free combination. is the sum of pseudorange multipath effects, observation noise and other unmodeled errors. is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

[0072] In order to provide accurate clock synchronization information, in some implementations, the above method may further include the following steps: S105 to S107.

[0073] S105: When the solution status information indicates that the current epoch is not the first epoch and a new satellite participates in the solution or a satellite restarts the solution, determine the corresponding first satellite that newly participates in the solution and the first satellite that newly starts the solution.

[0074] In the specific implementation, the satellite observation data of the current epoch is first collected. By comparing the satellite information of the previous epoch and the current epoch, the system can determine which satellites are newly added (i.e., new satellites) and which satellites are restarting the solution. Specifically, by comparing with the satellite participation of the previous epoch, it is possible to identify which satellites are participating in the solution for the first time in the current epoch, or which satellites did not participate in the solution before due to signal interruption and are now restarting the solution.

[0075] Select one of the new satellites or the satellites that are restarted as the "first satellite". The selection of the first satellite can be determined based on factors such as the geometric distribution of the satellite and the receiver, the quality of the satellite signal, and the health status of the satellite. After the first satellite is determined, the solution status of the current epoch is updated, and the information of the new satellite participating in the solution, the satellite that is restarted, and the first satellite is recorded. This information will be used for subsequent clock error solution and observation equation construction.

[0076] S106: Determine pseudorange hardware delay parameters of satellites other than the first satellite in the observation data.

[0077] In the specific implementation, the pseudorange observation data of the current epoch is obtained from the receiver, and the corresponding pseudorange observation value is extracted according to the observation data of each satellite. The influence of hardware delay in these pseudorange observation data is identified. For all satellites except the first satellite, the system will make corrections according to the preset hardware delay parameters. Pseudorange hardware delay is usually a known delay of hardware devices such as receivers and antennas, which will affect the received pseudorange value. In order to correct these effects, the hardware delay value corresponding to each satellite is applied. For the pseudorange observation data of each satellite, the hardware delay value is subtracted to obtain more accurate pseudorange data. These corrected pseudorange values ​​will be used for subsequent observation equation construction and clock error solution.

[0078] S107: Constructing a third observation equation corresponding to the clock error solution of the current epoch according to the pseudorange hardware delay parameter.

[0079] In the specific implementation, the third observation equation of the current epoch needs to be constructed by combining the pseudorange observations of all satellites (including the pseudorange after hardware delay correction). The clock error parameters of all satellites are constrained, usually setting the sum of all satellite clock errors to 0. This constraint is used to ensure the accuracy and consistency of the receiver clock error estimation. Thus, the third observation equation corresponding to the clock error solution of the current epoch is constructed.

[0080] The above implementation method of the embodiment of the present application determines the corresponding first satellite newly participating in the solution and the first satellite newly starting the solution when the above solution status information indicates that the current epoch is not the first epoch, and a new satellite participates in the solution or a satellite restarts the solution, determines the pseudo-range hardware delay parameters of the satellites other than the first satellite in the above observation data, and then constructs the third observation equation corresponding to the clock difference solution of the current epoch based on the pseudo-range hardware delay parameters. In this way, the newly added or restarted satellite is processed, the pseudo-range hardware delay is corrected, and the third observation equation is constructed based on the corrected data. Through these steps, the accurate solution of the clock difference between each satellite and the receiver is ensured, providing accurate clock synchronization information for subsequent navigation positioning.

[0081] In order to improve the accuracy of clock error solution, you can refer to Figure 2 In some implementations, the above S101 may include the following steps: S201 to 203.

[0082] S201: Obtain the original observation data required for clock error solution of the current epoch.

[0083] In the specific implementation, the receiver receives the signals transmitted by the satellite, including various types of observation data such as pseudorange and carrier phase. These observation data will be recorded and stored in real time, usually in the form of time series. The observation data of each epoch includes satellite number, signal type, timestamp, etc. The data is usually transmitted from the receiver to the clock error solution system through serial communication or network interface. In this way, the original observation data required for the clock error solution of the current epoch is obtained.

[0084] S202: Eliminate gross error data in the above original observation data.

[0085] In the specific implementation, gross error data usually refers to outliers caused by satellite signal interruption, occlusion, propagation anomalies, etc. The appearance of these outliers usually causes a significant deviation in the solution results, so they need to be eliminated before the solution. Using the preset gross error detection method, once the gross error data is detected, it is marked and eliminated. The specific implementation method can be to delete these data from the observation data set, or to assign a special mark to them in the subsequent solution process, indicating that the data is considered invalid.

[0086] S203: Detect and mark the cycle slip data in the original observation data to obtain observation data.

[0087] In the specific implementation, a cycle slip refers to the phenomenon that the carrier phase observation value becomes discontinuous due to factors such as signal interruption, obstruction or multipath effect. This will cause the carrier phase to jump, thus affecting the accuracy of the clock error solution. A cycle slip is usually manifested as a sudden and large change in the phase observation data, such as skipping a complete wavelength. Using the preset cycle slip detection method, once a cycle slip is detected, the observation data is marked as cycle slip data and can be corrected as needed. After marking and processing the cycle slip data, a new observation data set containing the processed raw data will be generated, and which data has cycle slips will be indicated. This data set will be passed as input to the subsequent clock error solution program to obtain the observation data.

[0088] The above implementation of the embodiment of the present application obtains the original observation data required for the clock error solution of the current epoch, then removes the gross error data in the above original observation data, detects and marks the cycle slip data in the above original observation data, obtains the observation data, obtains the original observation data of the current epoch, removes the gross error data, detects and marks the cycle slip data, and completes the preprocessing of the original observation data. Specifically, gross error elimination ensures the validity of the data through thresholds and statistical methods, and cycle slip detection ensures the continuity and consistency of the carrier phase data through phase difference analysis and period correction technology, thereby improving the accuracy of clock error solution through data quality control.

[0089] As another implementation method, based on the following observation equation for GNSS satellite clock error estimation:

[0090]

[0091] Among them, the superscript S represents the satellite number; the subscript r represents the receiver number; i represents the corresponding epoch number; Pseudorange phase observations without ionospheric combination; is the ionospheric-free combined carrier phase observation value; is the geometric distance between the station and the satellite; dt r is the receiver clock error; dt s is the satellite clock error; Tropospheric oblique delay; b r,if is the pseudorange hardware delay at the receiver; is the pseudorange hardware delay of the satellite end; is the phase hardware delay at the receiver end; is the phase hardware delay of the satellite end; is the phase ambiguity of the ionospheric-free combination; λ N is the phase wavelength of the ionosphere-free combination; is the sum of pseudorange multipath effects, observation noise and other unmodeled errors; is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

[0092] It can be seen from the above observation equation that the linear correlation between the receiver clock error and the satellite clock error, and the linear correlation between the clock error and the ambiguity and bias terms lead to the design matrix of the observation equation being rank-deficient. In the traditional mode, the clock error parameters are integrated with the pseudorange hardware delay parameters, but in the process of parameter reorganization to eliminate the rank deficiency, it should be noted that the reorganized ambiguity parameters cannot change their time-invariant characteristics within the continuous arc segment, so the time-varying characteristics of each bias term must be taken into account.

[0093] Then, the hardware delay terms of pseudorange and carrier phase are decomposed into time-invariant and time-varying parts. Δ is used to represent the time-invariant part and δ is used to represent the time-varying part. Then, each deviation term can be expressed as:

[0094]

[0095] Assuming that in the observation equation, the clock error parameter absorbs all the pseudorange hardware delay bias, then this bias will be introduced into the carrier observation equation, and the time-varying pseudorange hardware delay will destroy the time-invariant characteristics of the ambiguity parameters. Similarly, if the ambiguity parameters absorb all the phase hardware delay bias, the time-invariant characteristics of the ambiguity parameters will also be destroyed. Therefore, in the observation equation, the clock error absorbs the time-invariant pseudorange hardware delay, while the time-varying pseudorange hardware delay is absorbed into the residual; in the phase observation equation, the clock error absorbs the time-varying phase hardware delay, and the time-invariant pseudorange and phase hardware delay are absorbed into the ambiguity parameters. The specific form of the model can be expressed as follows:

[0096]

[0097] in, It represents the receiver clock error after absorbing the deviation; It represents the satellite clock error after absorbing the bias term (the clock error absorbs the time-invariant part of the pseudorange hardware delay and the time-varying part of the phase hardware delay, and the ambiguity absorbs the time-invariant part), which is the traditional satellite clock error form of the International GNSS Service (IGS). The specific form of the above parameters is as follows:

[0098]

[0099] It should be noted that in the above satellite clock error estimation model, there is still rank deficiency caused by the linear correlation between the receiver clock error and the satellite clock error. The receiver clock error of the measuring station with an external high-precision atomic clock can be set as a benchmark constraint, or the sum of the clock errors of all satellites can be set to 0 to eliminate the rank deficiency.

[0100] In the traditional estimation algorithm, the disturbance term The time-varying part of the pseudorange hardware delay will eventually be absorbed by the pseudorange residual, but in practice, it may not be completely absorbed by the pseudorange residual, and may also cause disturbances to other parameters. Therefore, the patent proposes a satellite clock error estimation model that takes into account the pseudorange hardware delay bias. In the pseudorange observation equation, the receiver and satellite pseudorange hardware bias parameter estimation is added, and the phase observation equation does not perform other special processing. The clock error and phase hardware are reorganized, and the clock error estimation equation can be expressed as the following formula:

[0101]

[0102] Among them, the receiver clock error and satellite clock error Only the time-varying part of the phase hardware delay deviation is absorbed, and the time-invariant phase hardware delay is absorbed into the ambiguity parameter.

[0103]

[0104] In the above formula, b r,if (i) and The linear dependence between the parameters causes the model to be rank-deficient. To avoid rank deficiency, a barycentric reference constraint is used to solve the receiver clock error by setting the sum of the clock error parameters of all satellites to 0. and satellite clock error The rank deficiency problem caused by correlation is shown in the following formula:

[0105]

[0106] Where S represents the corresponding satellite identifier, and n is the number of satellites.

[0107] for b r,if (i) and The linear correlation between parameters leads to model rank deficiency. First, for the first epoch, the traditional IGS clock error model is used to solve the clock error, and the pseudorange observation equation does not estimate the satellite and receiver pseudorange hardware delay parameters. Then, for the second epoch and subsequent epochs, the satellite and receiver pseudorange hardware delay parameter estimation is added to the pseudorange observation equation.

[0108] Starting from the second epoch, the linear correlation between the receiver and satellite pseudorange hardware delay parameters leads to model rank deficiency. Therefore, the centroid reference constraint in which the sum of the pseudorange hardware delay parameters of all satellites is set to 0 is selected here to solve the rank deficiency problem.

[0109]

[0110] In general, since the first epoch is the traditional IGS clock error solution model, the solution equation is full rank, and the time-invariant part of the pseudorange hardware delay is absorbed by the ambiguity. For the clock error solution, the subsequent epochs are constrained by the ambiguity, a time-invariant parameter, so that the pseudorange hardware delay can be estimated (the equation is still full rank) and does not affect other parameters.

[0111] For the proposed new clock error solution model, the above constraint strategy can solve the model rank deficiency problem. However, when the solution of a single satellite is interrupted and re-solved or a new satellite is involved in the solution, the satellite clock error solution will be abnormal due to the failure of the benchmark constraint or the absence of the benchmark constraint. To address this type of problem, when it is found that the solution of a single satellite is interrupted and re-solved or a new satellite is involved in the solution, the pseudorange observation equation of the current epoch does not estimate the pseudorange hardware delay parameters of the satellite, and the pseudorange observation equation of the subsequent epoch begins to estimate the pseudorange hardware delay parameters, thereby solving the rank deficiency problem in the clock error solution process.

[0112] For the specific implementation process, please refer to Figure 3 , including the following steps S301 to S306.

[0113] S301: Obtain observation data of the current epoch. Obtain observation data required for clock error solution of the current epoch.

[0114] S302: Preprocessing the observation data. Preprocess the observation data of the current epoch, remove gross error data, and perform cycle slip detection marking.

[0115] S303: Determine the solution status. Determine the clock solution status information of the current epoch. The main status information may include whether it is the first epoch of the solution. If it is not the first solution epoch, determine whether there is a new satellite participating in the solution or whether there is a satellite restarting the solution.

[0116] S304: Perform solution equation formation. Perform observation equation formation respectively according to the judged state information. When the current is the first solution epoch, perform conventional clock error solution model observation equation formation. If it is not the first solution epoch, when there is no new satellite participating in the solution or no satellite restarts the solution, perform the proposed clock error solution model observation equation formation that takes into account the pseudorange bias estimation of the satellite and the receiver. If it is not the first solution epoch, when there is a new satellite participating in the solution or a satellite restarts the solution, when the new model equation is formed into the observation equation, the pseudorange observation equation of the current epoch does not perform the pseudorange hardware delay parameter estimation of the satellite.

[0117] S305: Determine the solution benchmark constraint. According to the above solution principle, the benchmark constraint of the clock error solution is performed to make the observation equation a full-rank solution state. If it is a traditional clock error solution model, only the satellite clock error center of gravity benchmark constraint is required.

[0118] S306: Parameter solution is completed. According to the solution equation and the solution reference constraint, the clock error parameter solution of the current epoch is performed. The clock error solution of the next epoch is started again in a loop.

[0119] In order to avoid the rank deficiency of the clock error solution model, the clock error parameters are integrated with the pseudorange hardware delay parameters in the traditional clock error solution model. The satellite clock error absorbs the pseudorange hardware delay bias, and the receiver clock error absorbs the receiver pseudorange hardware delay bias. The influence of the pseudorange hardware delay bias on the clock error solution is ignored, resulting in a slow clock error convergence process and unstable clock error solution results. Therefore, a satellite clock error estimation model that takes into account the estimation of pseudorange hardware delay bias is proposed, so that the pseudorange hardware delay bias in the clock error solution is better separated from other solution parameters, reducing the influence on the solution of other parameters, further accelerating the convergence speed of the clock error, and improving the stability of the clock error solution.

[0120] Based on the clock error calculation method provided in the above embodiment, the present application also provides a specific implementation of the clock error calculation device. Please refer to the following embodiment.

[0121] See first Figure 4 The clock error solving device 400 provided in the embodiment of the present application includes the following modules:

[0122] The acquisition module 401 is used to acquire the observation data and epoch information required for clock error solution of the current epoch. The above observation data includes satellite and receiver pseudorange deviation estimates.

[0123] The determination module 402 is used to determine the solution state information of the current epoch according to the epoch information.

[0124] Construction module 403 is used to construct the first observation equation corresponding to the clock error solution of the current epoch based on the satellite and receiver pseudorange deviation estimation when the above-mentioned solution status information indicates that the above-mentioned current epoch is not the first epoch, and there is no new satellite participating in the solution and no satellite restarts the solution.

[0125] The solving module 404 is used to solve the first observation equation with the sum of the pseudo-range hardware delay parameters of all satellites being 0 as the center of gravity reference constraint, and obtain the clock error solution result of the current epoch.

[0126] The clock error solution device provided in the embodiment of the present application obtains the observation data and epoch information required for the clock error solution of the current epoch, and then determines the solution status information of the current epoch based on the epoch information. When the solution status information indicates that the current epoch is not the first epoch, and no new satellite has participated in the solution and no satellite has restarted the solution, the first observation equation corresponding to the clock error solution of the current epoch is constructed based on the satellite and receiver pseudorange deviation estimates, and then the sum of the pseudorange hardware delay parameters of all satellites is 0 as the center of gravity reference constraint, the first observation equation is solved to obtain the clock error solution result of the current epoch, and the convergence speed and stability of the clock error solution are improved by considering the pseudorange hardware delay deviation estimates of the satellite and the receiver, and the rank deficiency problem is solved by using the reference constraint. Through this method, the pseudorange hardware delay deviation can be more accurately separated from other solution parameters, thereby improving the stability of the clock error solution and improving the positioning accuracy.

[0127] As an implementation of the present application, the clock error solving device 400 further includes:

[0128] A construction module is used to construct a second observation equation corresponding to the clock error solution of the current epoch according to a preset pseudorange hardware delay when the solution state information indicates that the current epoch is the first epoch.

[0129] As an implementation of the present application, the clock error solving device 400 further includes:

[0130] The solution module is used to solve the second observation equation by setting the sum of the clock error parameters of all satellites to 0 as the center of gravity reference constraint, and obtain the clock error solution result of the current epoch.

[0131] As an implementation of the present application, the clock error solving device 400 further includes:

[0132] The determination module is used to determine the corresponding first satellite newly participating in the solution and the first satellite newly starting the solution when the solution status information indicates that the current epoch is not the first epoch and a new satellite participates in the solution or a satellite restarts the solution.

[0133] The determination module is further used to determine the pseudorange hardware delay parameters of satellites other than the first satellite in the observation data.

[0134] A construction module is used to construct the third observation equation corresponding to the clock error solution of the current epoch according to the pseudo-range hardware delay parameters.

[0135] As an implementation of the present application, the acquisition module 401 includes:

[0136] The acquisition unit is used to obtain the original observation data required for the clock error solution of the current epoch.

[0137] The elimination unit is used to eliminate the gross error data in the above original observation data.

[0138] The marking unit is used to detect and mark the cycle slip data in the original observation data to obtain the observation data.

[0139] The various modules in the clock error solution device provided in the embodiment of the present application can implement the various steps in the above-mentioned clock error solution method and achieve the corresponding effects. For the sake of concise description, they will not be repeated here.

[0140] Figure 5 A schematic diagram of the structure of the clock error solution hardware provided in an embodiment of the present application is shown.

[0141] The clock error calculation device may include a processor 501 and a memory 502 storing computer program instructions.

[0142] Specifically, the processor 501 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0143] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 502 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.

[0144] The memory may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the clock error solution method according to any one of the embodiments of the present disclosure.

[0145] The processor 501 implements any one of the clock error calculation methods in the above embodiments by reading and executing the computer program instructions stored in the memory 502 .

[0146] In one example, the clock error calculation device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.

[0147] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0148] Bus 510 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 510 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the present application considers any suitable bus or interconnection.

[0149] In addition, in combination with the clock error solution method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any of the clock error solution methods in the above embodiment is implemented.

[0150] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed, implements any one of the clock error solution methods in the above embodiments.

[0151] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0152] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0153] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0154] Aspects of the present disclosure are described above with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable clock error solver to produce a machine so that these instructions executed by the processor of the computer or other programmable clock error solver enable the implementation of the functions / actions specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0155] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A clock error calculation method, characterized in that: The method comprises: Obtaining observation data and epoch information required for clock error solution of the current epoch; the observation data includes satellite and receiver pseudorange deviation estimates; Determining solution status information of the current epoch according to the epoch information; When the solution status information indicates that the current epoch is not the first epoch, no new satellite participates in the solution, and no satellite restarts the solution, constructing a first observation equation corresponding to the clock error solution of the current epoch based on satellite and receiver pseudorange bias estimation; The first observation equation is solved with the sum of the pseudorange hardware delay parameters of all satellites being 0 as a barycenter reference constraint to obtain a clock error solution result of the current epoch.

2. The clock error calculation method according to claim 1, characterized in that: The method further comprises: When the solution state information indicates that the current epoch is the first epoch, a second observation equation corresponding to the clock error solution of the current epoch is constructed according to a preset pseudorange hardware delay.

3. The clock error calculation method according to claim 2, characterized in that: In a case where the solution state information indicates that the current epoch is the first epoch, after constructing a second observation equation corresponding to the clock error solution of the current epoch according to a preset pseudorange hardware delay, the method further includes: The sum of the clock error parameters of all satellites is set to 0 as a barycenter reference constraint, and the second observation equation is solved to obtain the clock error solution result of the current epoch.

4. The clock error calculation method according to claim 2, characterized in that: The second observation equation is: Among them, the superscript S represents the satellite number; the subscript r represents the receiver number; i represents the corresponding epoch number; Pseudorange phase observations without ionospheric combination; is the ionospheric-free combined carrier phase observation value; is the geometric distance between the station and the satellite; dt r is the receiver clock error; dt s is the satellite clock error; Tropospheric oblique delay; b r,if is the pseudorange hardware delay at the receiver; is the pseudorange hardware delay of the satellite end; is the phase hardware delay at the receiver end; is the phase hardware delay of the satellite end; is the phase ambiguity of the ionospheric-free combination; λ N is the phase wavelength of the ionosphere-free combination; is the sum of pseudorange multipath effects, observation noise and other unmodeled errors; is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

5. The clock error calculation method according to claim 1, characterized in that: The first observation equation is: Among them, the superscript S represents the satellite number; the subscript r represents the receiver number; i represents the corresponding epoch number; Pseudorange phase observations without ionospheric combination; is the ionospheric-free combined carrier phase observation value; is the geometric distance between the station and the satellite; dt r is the receiver clock error; dt s is the satellite clock error; Tropospheric oblique delay; b r,if is the pseudorange hardware delay at the receiver; is the pseudorange hardware delay of the satellite end; is the phase hardware delay at the receiver end; is the phase hardware delay of the satellite end; is the phase ambiguity of the ionospheric-free combination; λ N is the phase wavelength of the ionosphere-free combination; is the sum of pseudorange multipath effects, observation noise and other unmodeled errors; is the sum of carrier phase multipath effects, observation noise and other unmodeled errors.

6. The clock error calculation method according to claim 1, characterized in that: The method further comprises: When the solution state information indicates that the current epoch is not the first epoch, and a new satellite participates in the solution or a satellite restarts the solution, determining the corresponding first satellite that newly participates in the solution and the first satellite that newly starts the solution; Determining pseudorange hardware delay parameters of satellites other than the first satellite in the observation data; According to the pseudorange hardware delay parameter, a third observation equation corresponding to the clock error solution of the current epoch is constructed.

7. The clock error calculation method according to any one of claims 1 to 6, characterized in that: The acquisition of observation data required for clock error solution of the current epoch includes: Obtain the original observation data required for clock error solution of the current epoch; Eliminate gross error data in the original observation data; Detect and mark cycle slip data in the original observation data to obtain observation data.

8. A clock error calculation device, characterized in that: The device comprises: An acquisition module is used to acquire the observation data and epoch information required for clock error solution of the current epoch; the observation data includes satellite and receiver pseudorange deviation estimates; A determination module, used to determine the solution state information of the current epoch according to the epoch information; A construction module, configured to construct a first observation equation corresponding to the clock error solution of the current epoch based on satellite and receiver pseudorange bias estimation when the solution state information indicates that the current epoch is not the first epoch, no new satellite participates in the solution, and no satellite restarts the solution; A solution module is used to solve the first observation equation with the sum of the pseudo-range hardware delay parameters of all satellites being 0 as a center of gravity reference constraint to obtain a clock error solution result of the current epoch.

9. A clock error calculation device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; the processor reads and executes the computer program instructions to implement the clock error solution method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the clock error solution method according to any one of claims 1 to 7 is implemented.

11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the clock error solution method as described in any one of claims 1 to 7.

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