Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a plurality of pixel structures arranged in an array, and each pixel structure comprises a first sub-pixel area, a second sub-pixel area and a third sub-pixel area which are arranged in the column direction; the first sub-pixel area comprises a first thin film transistor and a first pixel electrode, the input end of the first thin film transistor is connected with the data line, and the output end of the first thin film transistor is connected with the first pixel electrode; the second sub-pixel area comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel area comprises a third pixel electrode; the input end of the second thin film transistor is connected with the data line, the output end of the second thin film transistor is connected with the second pixel electrode and the input end of the third thin film transistor, and the output end of the third thin film transistor is connected with the third pixel electrode and the input end of the fourth thin film transistor. According to the technical scheme, the side-view visual angle of the VA type liquid crystal display device can be increased.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] An active liquid crystal display device (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) generally includes a housing, a liquid crystal display panel disposed in the housing, and a backlight module in the housing. The liquid crystal display device is a passive light-emitting display device, which requires the light source provided by the backlight module to display light normally.

[0003] Commonly used TFT-LCDs include two types, namely, Full Frame Switch (FFS) type and Vertical Alignment (VA) type. Among them, VA type liquid crystal display devices have a higher contrast ratio. However, when displaying, compared with FFS type, VA type liquid crystal display devices have a relatively poor viewing angle when viewed from the side. Summary of the invention

[0004] In view of this, embodiments of the present application provide a display panel and a display device for improving the viewing angle of a VA-type liquid crystal display device when viewed from the side.

[0005] In order to achieve the above-mentioned object, in a first aspect, an embodiment of the present application provides a display panel, comprising: a plurality of pixel structures arranged in an array, each pixel structure comprising a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged along a column direction;

[0006] The first sub-pixel region includes a first thin film transistor and a first pixel electrode, the input end of the first thin film transistor is connected to the data line, and the output end is connected to the first pixel electrode;

[0007] The second sub-pixel region includes a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel region includes a third pixel electrode;

[0008] The input end of the second thin film transistor is connected to the data line, the output end is respectively connected to the second pixel electrode and the input end of the third thin film transistor, and the output end of the third thin film transistor is respectively connected to the third pixel electrode and the input end of the fourth thin film transistor;

[0009] Control ends of the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected to the same gate scanning line;

[0010] The brightness of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region gradually decreases.

[0011] In a possible implementation of the first aspect, the gate scan line includes a first scan line and a second scan line connected to each other, the first scan line is located between two adjacent sub-pixel areas among the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area, the second scan line is located between the other two adjacent sub-pixel areas among the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area, and the first scan line and the second scan line are located in different film layers.

[0012] In a possible implementation of the first aspect, each of the pixel structures forms a plurality of pixel structure groups arranged in an array, each pixel structure group includes three pixel structures of different colors arranged along a row direction, and the pixel structures in each pixel structure group are arranged in the same color arrangement order.

[0013] In a possible implementation of the first aspect, in the pixel structure group, the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region of each pixel structure are arranged in descending order of brightness from top to bottom.

[0014] In a possible implementation of the first aspect, in the same pixel structure group, brightness of any two adjacent sub-pixel areas are different.

[0015] In a possible implementation of the first aspect, in the row direction, brightness of any three adjacent sub-pixel regions of the same color are different from each other.

[0016] In a possible implementation of the first aspect, in each pixel structure group, brightness arrangement order of sub-pixel regions of pixel structures with the same color is the same.

[0017] In a possible implementation of the first aspect, in each pixel structure, the second sub-pixel region is adjacent to the third sub-pixel region, and the third sub-pixel region has a different brightness from the adjacent sub-pixel region.

[0018] In a possible implementation of the first aspect, the areas of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region are equal; the first sub-pixel region, the second sub-pixel region and the third sub-pixel region each include 4 domains, and the output end of the fourth thin-film transistor is connected to a common signal line.

[0019] In a second aspect, an embodiment of the present application provides a display device, comprising: a backlight module and the display panel described in the first aspect or any possible implementation manner of the first aspect.

[0020] The display panel provided by the embodiment of the present application comprises: a plurality of pixel structures arranged in an array, each pixel structure comprises a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged in a column direction; the first sub-pixel region comprises a first thin film transistor and a first pixel electrode, the input end of the first thin film transistor is connected to a data line, and the output end is connected to the first pixel electrode; the second sub-pixel region comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel region comprises a third pixel electrode; the input end of the second thin film transistor is connected to the data line, the output end is respectively connected to the input end of the second pixel electrode and the third thin film transistor, and the output end of the third thin film transistor is respectively connected to the third pixel electrode and the input end of the fourth thin film transistor; the control ends of the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected to the same gate scanning line; the brightness of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region gradually decreases. The display panel described in the embodiment of the present application can improve the viewing angle of the VA type liquid crystal display device when viewed from the side. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of an equivalent circuit of a pixel structure provided in an embodiment of the present application;

[0022] Figure 2 A curve diagram showing the relationship between grayscale and Gamma value at the same side viewing angle for a liquid crystal display panel designed using the technical solution of the present application and the technical solution of the prior art, provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the arrangement of the first pixel structure group provided in an embodiment of the present application;

[0024] Figure 4 for Figure 3 An equivalent circuit diagram of the pixel structure group shown;

[0025] Figure 5 A schematic diagram of the arrangement of the second pixel structure group provided in an embodiment of the present application;

[0026] Figure 6 for Figure 5 An equivalent circuit diagram of the pixel structure group shown;

[0027] Figure 7 A schematic diagram of the arrangement of the third pixel structure group provided in an embodiment of the present application;

[0028] Fig. 8A for Figure 7 An equivalent circuit diagram of the pixel structure group G1 shown;

[0029] Figure 8B for Figure 7 An equivalent circuit diagram of the pixel structure group G2 shown;

[0030] Figure 8C for Figure 7 An equivalent circuit diagram of the pixel structure group G3 shown;

[0031] Fig. 9 A schematic diagram of the arrangement of the fourth pixel structure group provided in an embodiment of the present application;

[0032] Fig. 10A for Fig. 9 An equivalent circuit diagram of the pixel structure group G1 shown;

[0033] Fig. 10B for Fig. 9 An equivalent circuit diagram of the pixel structure group G2 shown;

[0034] Fig.11 for Fig. 9 Another equivalent circuit diagram of the pixel structure group G1 is shown;

[0035] Fig.12 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0036] Description of reference numerals:

[0037] H-first sub-pixel region; M-second sub-pixel region; L-third sub-pixel region;

[0038] T1-first thin film transistor; T2-second thin film transistor; T3-third thin film transistor; T4-fourth thin film transistor; PE1-first pixel electrode; PE2-second pixel electrode; PE3-third pixel electrode;

[0039] Data-data line; Gate-gate scan line; S1-first scan line; S2-second scan line;

[0040] 100-backlight module; 200-display panel. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0042] Liquid crystal display panels are usually made of two glass substrates (array substrate and color film substrate) bonded together, and liquid crystal is poured between the two glass substrates. Pixel electrodes and common electrodes are set on the opposite sides of the two glass substrates, respectively. The electric field strength is used to control the rotation direction of the liquid crystal molecules, and the optical rotation characteristics of the liquid crystal molecules are used to realize the picture display. The display modes of TFT-LCD are mainly divided into FFS type (horizontal electric field) and VA type (vertical electric field). VA type has a higher contrast, but a poor viewing angle. FFS has a better viewing angle, but a poor contrast.

[0043] In view of this, an embodiment of the present application provides a display panel for improving the viewing angle of a VA type display. The display panel may include a plurality of pixel structures arranged in an array. Figure 1 The equivalent circuit diagram of the pixel structure provided in the embodiment of the present application is as follows: Figure 1 As shown, the pixel structure may include a first sub-pixel region H, a second sub-pixel region M and a third sub-pixel region L arranged along a column direction, and each sub-pixel region may include four domains, so that each sub-pixel region has four liquid crystal molecule regions with arrangement structures, thereby improving the optical performance of the sub-pixel region.

[0044] The first sub-pixel region H may include a first thin film transistor T1 and a first pixel electrode PE1, the input end of the first thin film transistor T1 may be connected to the data line Data, and the output end may be connected to the first pixel electrode PE1. The second sub-pixel region M may include a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, and a second pixel electrode PE2, and the third sub-pixel region L may include a third pixel electrode PE3. The input end of the second thin film transistor T2 is connected to the data line Data, and the output end may be connected to the input end of the second pixel electrode PE2 and the third thin film transistor T3, respectively, and the output end of the third thin film transistor T3 may be connected to the input end of the third pixel electrode PE3 and the fourth thin film transistor T4, respectively. In the embodiment of the present application, the input end may be a source or a drain. When the input end is a source, the output end is a drain accordingly.

[0045] The output terminal of the fourth thin film transistor T4 may be connected to a common signal line (not shown). In some embodiments, the second sub-pixel region M may further include a common electrode, and the output terminal of the fourth thin film transistor T4 may be connected to the common electrode. The control terminals (or gates) of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may be connected to the same gate scan line Gate.

[0046] The gate scan line Gate can be connected to a gate driver, which can convert the signal output by the controller into a high-voltage, high-current scan signal, and transmit it through the gate scan line Gate to control the on and off of the thin film transistor connected to the gate scan line Gate. The data line Data can be connected to a source driver, and when the gate scan line Gate is loaded with a scan signal, it transmits a data voltage to the pixel electrode connected to the data line Data for charging.

[0047] Continue reading Figure 1 The gate scan line Gate may include a first scan line S1 and a second scan line S2 connected to each other, so that the first scan line S1 and the second scan line S2 can be loaded with scan signals at the same time. The first scan line S1 may be located between two adjacent sub-pixel areas among the first sub-pixel area H, the second sub-pixel area M, and the third sub-pixel area L, and the second scan line S2 may be located between the other two adjacent sub-pixel areas among the first sub-pixel area H, the second sub-pixel area M, and the third sub-pixel area L, so that the staggered arrangement of the first sub-pixel area H, the second sub-pixel area M, and the third sub-pixel area L can be realized later.

[0048] To increase the aperture ratio, the first scan line S1 and the second scan line S2 can be located in different film layers, so that the indium tin oxide (ITO) of the pixel routing of the second sub-pixel area M can be prevented from passing through the first sub-pixel area H or the third sub-pixel area L, thereby improving the light transmittance, reducing light loss, and improving the display effect while reducing power consumption.

[0049] For example, the first thin film transistor T1 , the second thin film transistor T2 , the third thin film transistor T3 , and the fourth thin film transistor T4 are all turned on at a high level and turned off at a low level.

[0050] For the first sub-pixel region H, when the gate scan line Gate is loaded with a high-level scan signal, the first thin film transistor T1 is turned on, and the data line Data can transmit the data voltage to the first pixel electrode PE1 through the first thin film transistor T1 for charging. For the second sub-pixel region M, when the gate scan line Gate is loaded with a high-level drive signal, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are turned on, at this time, the data line Data transmits the data voltage through the second thin film transistor T2, wherein the data voltage can charge the third pixel electrode PE3 in addition to charging the second pixel electrode PE2, that is, the third thin film transistor T3 can divide a part of the data voltage to the third pixel electrode PE3 by voltage division, so that the voltage of the third pixel electrode PE3 is lower than the voltage of the second pixel electrode PE2.

[0051] As the voltages of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 gradually decrease, the voltage difference can cause differences in the rotation angles of the liquid crystal molecules in each sub-pixel area, and the brightness (grayscale) of the first sub-pixel area H, the second sub-pixel area M and the third sub-pixel area L gradually decreases, and there are also significant differences in the displayed images, which can effectively reduce the display color deviation problem at the side viewing angle, improve the clarity of the displayed image, and thereby improve the side viewing angle.

[0052] In some embodiments, the areas of the first sub-pixel region H, the second sub-pixel region M, and the third sub-pixel region L may be equal, which can reduce the occurrence of aliasing and improve the fineness of the displayed image.

[0053] It can be understood that the above is based on the example of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 being turned on at a high level. In other embodiments, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 can also be the type of being turned on at a low level and cut off at a high level.

[0054] Figure 2 The embodiment of the present application provides a curve diagram of the relationship between grayscale and Gamma value of a liquid crystal display panel designed by using the technical solution of the present application and the technical solution of the prior art at the same side viewing angle. In the case of the same grayscale, the larger the corresponding Gamma value, the more serious the color shift phenomenon. Figure 2 As shown, compared with the prior art, at the same grayscale, the Gamma value corresponding to the technical solution of the embodiment of the present application is closer to the Gamma value of the front view angle at the grayscale, that is, the technical solution provided by the embodiment of the present application can effectively improve the side view angle.

[0055] Take the pixel structure including three colors of red, green and blue as an example. Figure 3 This is a schematic diagram of the arrangement of the first pixel structure group provided in the embodiment of the present application, Figure 4 for Figure 3 The equivalent circuit diagram of the pixel structure group shown in FIG. Figure 3 and Figure 4As shown, each pixel structure can form a plurality of pixel structure groups arranged in an array, and each pixel structure group can include three pixel structures of different colors, red, green and blue, arranged along the row direction. In the column direction, the pixel structures in each pixel structure group can be arranged in the same color arrangement order. For example, in the pixel structure group G1 and the pixel structure group G2, the pixel structures in the first column are all displayed in red, the pixel structures in the second column are all displayed in green, and the pixel structures in the third column are all displayed in blue. In the pixel structure group G1, each pixel structure is respectively a first sub-pixel area H with high brightness, a second sub-pixel area M with medium brightness, and a third sub-pixel area L with low brightness from top to bottom.

[0056] Figure 5 This is a schematic diagram of the arrangement of the second pixel structure group provided in the embodiment of the present application, Figure 6 for Figure 5 The equivalent circuit diagram of the pixel structure group shown in FIG. Figure 5 and Figure 6 As shown, compared with the first pixel structure group, the difference in the arrangement of the second pixel structure group is that in the same pixel structure group, the brightness of any two adjacent sub-pixel areas is different. Exemplarily, in the pixel structure group G1, the brightness of any sub-pixel area is different from the brightness of the sub-pixel area above, below, left, and right. For example, the top of the first column is the first sub-pixel area H with the highest brightness, and the right and bottom are the second sub-pixel areas M with medium brightness. In different pixel structure groups, the brightness arrangement order of sub-pixel areas of pixel structures with the same color is the same, for example. In the column direction, the pixel structures of the first column of the pixel structure group G1 and the pixel structure group G2 are all displayed in red, and the sub-pixel areas are arranged in the order of the first sub-pixel area H, the second sub-pixel area M, and the third sub-pixel area L from top to bottom. The pixel structures of the second column are all displayed in green, and the sub-pixel areas are arranged in the order of the second sub-pixel area M, the third sub-pixel area L, and the first sub-pixel area H from top to bottom. The pixel structures in the third column are all displayed in blue, and the sub-pixel areas are arranged in the order of the third sub-pixel area L, the first sub-pixel area H, and the second sub-pixel area M from top to bottom.

[0057] It should be noted that in the third column pixel structure, the output end of the third thin film transistor T3 is connected to the fourth thin film transistor T4 and is also connected to the third pixel electrode PE3 of the third sub-pixel area L through the first sub-pixel area H via a crossover line.

[0058] Through the above-mentioned implementation, it is possible to realize the display of an image with intermediate brightness through the staggered arrangement of the high-brightness first sub-pixel area H, the medium-brightness second sub-pixel area M and the low-brightness third sub-pixel area L, thereby improving the clarity when viewed from the side and reducing the graininess when displaying a pure color image, thereby improving the side viewing angle.

[0059] Figure 7 This is a schematic diagram of the arrangement of the third pixel structure group provided in the embodiment of the present application, Figure 8A-8C They are Figure 7 The equivalent circuit diagram of the pixel structure group G1-G3 shown in FIG. Figure 7-8C Compared with the second pixel structure group, the difference in the arrangement of the third pixel structure group is mainly that, in the row direction, the brightness of any three adjacent sub-pixel areas belonging to the same color are different from each other. For example, taking the pixel structure displaying red as an example, the first column of the pixel structure group G1 is arranged from top to bottom in the order of the first sub-pixel area H, the second sub-pixel area M and the third sub-pixel area L, the first column of the pixel structure group G2 is arranged from top to bottom in the order of the second sub-pixel area M, the third sub-pixel area L and the first sub-pixel area H, and the first column of the pixel structure group G3 is arranged from top to bottom in the order of the third sub-pixel area L, the first sub-pixel area H and the second sub-pixel area M. In this way, the granularity when displaying a pure color picture can be further reduced, and the display quality and side viewing angle of the picture can be further improved.

[0060] Fig. 9 This is a schematic diagram of the arrangement of the fourth pixel structure group provided in an embodiment of the present application, Fig. 10A and Fig. 10B They are Fig. 9 The equivalent circuit diagram of the pixel structure groups G1 and G2 shown in FIG. Figure 9-10B Compared with the third pixel structure group, the fourth pixel structure group is mainly different in that, in each pixel structure, the second sub-pixel area M and the third sub-pixel area L are adjacent; in each pixel structure group, the positions of the third sub-pixel areas of different pixel structures are different.

[0061] Exemplarily, in the first column of the pixel structure group G1, the third sub-pixel area L is located at the bottom of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and is located above the third sub-pixel area L; in the second column, the third sub-pixel area L is located in the middle of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and is located above the third sub-pixel area L; in the third column, the third sub-pixel area L is located at the top of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and is located below the third sub-pixel area L.

[0062] In the first column of the pixel structure group G2, the third sub-pixel area L is located in the middle of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and is located below the third sub-pixel area L; in the second column, the third sub-pixel area L is located at the bottom of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and is located above the third sub-pixel area L; in the third column, the third sub-pixel area L is located in the middle of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and is located above the third sub-pixel area L.

[0063] That is, although the positions of the second sub-pixel area M and the third sub-pixel area L change in different columns, the second sub-pixel area M and the third sub-pixel area L are always adjacent. In addition, there is a difference in brightness between the third sub-pixel area L and the sub-pixel area adjacent to it. Through the above-mentioned implementation, on the one hand, the light mixing effect of the pixel structure group can be improved, and the granularity can be reduced, thereby further improving the viewing angle and color deviation. On the other hand, this can also make it unnecessary to connect the second sub-pixel area M and the third sub-pixel area L through a cross-line, thereby avoiding the problem of inconsistent resistance caused by too long a cross-line, which in turn causes uneven brightness of the third sub-pixel area L, and further improves the display quality.

[0064] It can be understood that, in some embodiments, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 can also be arranged in the third sub-pixel area L, see Fig.11 The technical solution provided in the embodiment of the present application can also be applied to other display types, such as twisted nematic (TN) and FFS.

[0065] The display panel provided by the embodiment of the present application comprises: a plurality of pixel structures arranged in an array, each pixel structure comprises a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged in a column direction; the first sub-pixel region comprises a first thin film transistor and a first pixel electrode, the input end of the first thin film transistor is connected to a data line, and the output end is connected to the first pixel electrode; the second sub-pixel region comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel region comprises a third pixel electrode; the input end of the second thin film transistor is connected to the data line, the output end is respectively connected to the input end of the second pixel electrode and the third thin film transistor, and the output end of the third thin film transistor is respectively connected to the input end of the third pixel electrode and the fourth thin film transistor; the control ends of the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected to the same gate scanning line; the brightness of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region gradually decreases. The display panel provided by the embodiment of the present application can improve the viewing angle of the VA type liquid crystal display device when viewed from the side by setting three sub-pixel regions with different brightness.

[0066] Based on the same inventive concept, as an implementation of the above method, an embodiment of the present application provides a display device, and the device embodiment corresponds to the above method embodiment. For ease of reading, the present device embodiment will no longer repeat the details of the above method embodiment one by one, but it should be clear that the device in this embodiment can correspond to and implement all the contents of the above method embodiment.

[0067] Fig.12 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown in FIG. Fig.12 As shown, the display device provided in this embodiment includes: a backlight module 100 and the display panel 200 described in the above embodiment.

[0068] The display device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0069] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0070] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0071] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are merely schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0072] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0073] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0074] Furthermore, in the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0075] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0076] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0077] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel structures arranged in an array, each pixel structure comprising a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged along a column direction; The first sub-pixel region includes a first thin film transistor and a first pixel electrode, the input end of the first thin film transistor is connected to the data line, and the output end is connected to the first pixel electrode; The second sub-pixel region includes a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel region includes a third pixel electrode; The input end of the second thin film transistor is connected to the data line, the output end is respectively connected to the second pixel electrode and the input end of the third thin film transistor, and the output end of the third thin film transistor is respectively connected to the third pixel electrode and the input end of the fourth thin film transistor; Control ends of the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected to the same gate scanning line; The brightness of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region gradually decreases.

2. The display panel according to claim 1, characterized in that: The gate scan line includes a first scan line and a second scan line connected to each other, the first scan line is located between two adjacent sub-pixel areas among the first sub-pixel area, the second sub-pixel area and the third sub-pixel area, the second scan line is located between the other two adjacent sub-pixel areas among the first sub-pixel area, the second sub-pixel area and the third sub-pixel area, and the first scan line and the second scan line are located in different film layers.

3. The display panel according to claim 1, characterized in that: The pixel structures form a plurality of pixel structure groups arranged in an array, each pixel structure group includes three pixel structures of different colors arranged along a row direction, and the pixel structures in each pixel structure group are arranged in the same color arrangement order.

4. The display panel according to claim 3, characterized in that: In the pixel structure group, the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region of each pixel structure are arranged in descending order of brightness from top to bottom.

5. The display panel according to claim 3, characterized in that: In the same pixel structure group, the brightness of any two adjacent sub-pixel areas is different.

6. The display panel according to claim 5, characterized in that: In the row direction, the brightness of any three adjacent sub-pixel regions of the same color are different from each other.

7. The display panel according to claim 3, characterized in that: In each pixel structure group, the brightness arrangement order of the sub-pixel regions of the pixel structures with the same color is the same.

8. The display panel according to claim 1, characterized in that: In each pixel structure, the second sub-pixel region is adjacent to the third sub-pixel region, and the brightness of the third sub-pixel region is different from that of the adjacent sub-pixel region.

9. The display panel according to any one of claims 1 to 8, characterized in that: The areas of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region are equal; the first sub-pixel region, the second sub-pixel region and the third sub-pixel region each include 4 domains, and the output end of the fourth thin film transistor is connected to a common signal line.

10. A display device, characterized in that: include: A backlight module and a display panel as claimed in any one of claims 1 to 9.

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