Display panel and display device

Abstract

The application provides a display panel and a display device, wherein the display panel comprises a plurality of pixel structures arranged in an array, each pixel structure comprising a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged along a column direction; the first sub-pixel region comprises a first thin film transistor and a first pixel electrode, an input end of the first thin film transistor being connected with a data line and an output end being connected with the first pixel electrode; the second sub-pixel region comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode; the third sub-pixel region comprises a third pixel electrode; an input end of the second thin film transistor is connected with the data line, and an output end is connected with the second pixel electrode and an input end of the third thin film transistor respectively; an output end of the third thin film transistor is connected with the third pixel electrode and an input end of the fourth thin film transistor respectively. The technical scheme provided by the application can improve the visual angle of a VA type liquid crystal display device in side view.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] A thin film transistor-liquid crystal display (TFT-LCD) generally includes a housing, a liquid crystal display panel disposed in the housing, and a backlight module disposed in the housing. The liquid crystal display device is a passive light-emitting display device that needs to rely on a light source provided by the backlight module to normally display light.

[0003] A commonly used TFT-LCD includes two types, which are a full frame switch (FFS) type and a vertical alignment (VA) type. Among them, the VA type liquid crystal display device has a higher contrast ratio. However, compared with the FFS type, the VA type liquid crystal display device has a relatively poor viewing angle when viewed from the side during display. SUMMARY

[0004] Therefore, embodiments of the present application provide a display panel and a display device for improving the viewing angle of the VA type liquid crystal display device when viewed from the side.

[0005] To achieve the above object, in a first aspect, embodiments of the present application provide a display panel, comprising: a plurality of pixel structures arranged in an array, each pixel structure comprising a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged along a column direction;

[0006] The first sub-pixel region comprises a first thin film transistor and a first pixel electrode, an input end of the first thin film transistor is connected with a data line, and an output end of the first thin film transistor is connected with the first pixel electrode;

[0007] The second sub-pixel region comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel region comprises a third pixel electrode;

[0008] An input end of the second thin film transistor is connected with the data line, and an output end of the second thin film transistor is connected with the second pixel electrode and an input end of the third thin film transistor, respectively, an output end of the third thin film transistor is connected with the third pixel electrode and an input end of the fourth thin film transistor, respectively;

[0009] Control ends of the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected with a same gate scan line;

[0010] The luminance of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region gradually decreases.

[0011] In a possible implementation of the first aspect, the gate scanning line includes a first scanning line and a second scanning line connected to each other, the first scanning line is located between two adjacent sub-pixel regions among the first sub-pixel region, the second sub-pixel region and the third sub-pixel region, the second scanning line is located between the other two adjacent sub-pixel regions among the first sub-pixel region, the second sub-pixel region and the third sub-pixel region, and the first scanning line and the second scanning line are located in different film layers.

[0012] In a possible implementation of the first aspect, the pixel structures form an array of pixel structure groups, each pixel structure group includes three pixel structures of different colors arranged in a row direction, and the pixel structures in each pixel structure group are arranged in the same color arrangement order.

[0013] In a possible implementation of the first aspect, in the pixel structure group, the first sub-pixel region, the second sub-pixel region and the third sub-pixel region of each pixel structure are arranged in a luminance decreasing order from top to bottom.

[0014] In a possible implementation of the first aspect, in the same pixel structure group, the luminance of any two adjacent sub-pixel regions is different.

[0015] In a possible implementation of the first aspect, in the row direction, the luminance of any three adjacent sub-pixel regions of the same color is different.

[0016] In a possible implementation of the first aspect, in each pixel structure group, the luminance arrangement order of the sub-pixel regions of the pixel structures of the same color is the same.

[0017] In a possible implementation of the first aspect, in each pixel structure, the second sub-pixel region and the third sub-pixel region are adjacent, and the luminance of the third sub-pixel region is different from that of the adjacent sub-pixel region.

[0018] In a possible implementation of the first aspect, the areas of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region are equal, each of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region includes four domains, and the output end of the fourth thin film transistor is connected to a common signal line.

[0019] In the second aspect, the embodiments of the present application provide a display device, including a backlight module and the display panel of the first aspect or any possible implementation of the first aspect.

[0020] The display panel provided in this application embodiment includes: a plurality of pixel structures arranged in an array, each pixel structure including a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region arranged along a column direction; the first sub-pixel region includes a first thin-film transistor and a first pixel electrode, the input terminal of the first thin-film transistor is connected to a data line, and the output terminal is connected to the first pixel electrode; the second sub-pixel region includes a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, and a second pixel electrode, and the third sub-pixel region includes a third pixel electrode; the input terminal of the second thin-film transistor is connected to the data line, and the output terminal is connected to the second pixel electrode and the input terminal of the third thin-film transistor respectively, and the output terminal of the third thin-film transistor is connected to the third pixel electrode and the input terminal of the fourth thin-film transistor respectively; the control terminals of the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fourth thin-film transistor are connected to the same gate scan line; the brightness of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region gradually decreases. The display panel described in this application embodiment can improve the viewing angle of a VA-type liquid crystal display device when viewed from the side. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the equivalent circuit of the pixel structure provided in the embodiments of this application;

[0022] Figure 2 A graph showing the relationship between grayscale and Gamma value of a liquid crystal display panel designed using the technical solutions of this application and existing technologies, provided as an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the arrangement of the first pixel structure group provided in the embodiments of this application;

[0024] Figure 4 for Figure 3 The equivalent circuit diagram of the pixel structure group shown;

[0025] Figure 5 This is a schematic diagram of the arrangement of the second type of pixel structure group provided in the embodiments of this application;

[0026] Figure 6 for Figure 5 The equivalent circuit diagram of the pixel structure group shown;

[0027] Figure 7 This is a schematic diagram of the arrangement of the third pixel structure group provided in the embodiments of this application;

[0028] Figure 8A for Figure 7 The equivalent circuit diagram of pixel structure group G1 shown;

[0029] Figure 8B For Figure 7 the equivalent circuit schematic diagram of the pixel structure group G2 shown in FIG. 2B;

[0030] Figure 8C For Figure 7 the equivalent circuit schematic diagram of the pixel structure group G3 shown in FIG. 2C;

[0031] Figure 9 the arrangement schematic diagram of a fourth pixel structure group provided by the embodiment of the present application;

[0032] Figure 10A For Figure 9 the equivalent circuit schematic diagram of the pixel structure group G1 shown in FIG. 1B;

[0033] Figure 10B For Figure 9 the equivalent circuit schematic diagram of the pixel structure group G2 shown in FIG. 2B;

[0034] Figure 11 For Figure 9 another equivalent circuit schematic diagram of the pixel structure group G1 shown in FIG. 1B;

[0035] Figure 12 the structure schematic diagram of the display device provided by the embodiment of the present application.

[0036] Explanation of Reference Signs:

[0037] H-first sub-pixel region; M-second sub-pixel region; L-third sub-pixel region;

[0038] T1-first thin film transistor; T2-second thin film transistor; T3-third thin film transistor; T4-fourth thin film transistor; PE1-first pixel electrode; PE2-second pixel electrode; PE3-third pixel electrode;

[0039] Data-data line; Gate-gate scan line; S1-first scan line; S2-second scan line;

[0040] 100-backlight module; 200-display panel. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation manner part of the embodiments of the present application are only used for explaining the specific embodiments of the present application, and are not intended to limit the present application. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0042] Liquid crystal display panel is usually formed by pasting two glass substrates (array substrate and color film substrate) and filling liquid crystal between the two glass substrates, and pixel electrodes and common electrodes are respectively arranged on the opposite sides of the two glass substrates, the rotation direction of liquid crystal molecules is controlled by electric field intensity, and the picture display is realized by using the optical rotation characteristics of liquid crystal molecules. The display mode of TFT-LCD mainly includes FFS type (horizontal electric field) and VA type (vertical electric field), the VA type has higher contrast, but the visual viewing angle is poor, and the visual viewing angle of FFS is better, but the contrast is poor.

[0043] Therefore, the display panel provided in the embodiments of the present application is used to improve the visual angle of the VA type. The display panel can include a plurality of pixel structures arranged in an array, Figure 1 The equivalent circuit schematic diagram of the pixel structure provided in the embodiments of the present application is shown in Figure 1 As shown in the figure, the pixel structure can include a first sub-pixel region H, a second sub-pixel region M and a third sub-pixel region L arranged along the column direction, each sub-pixel region can include four domains, so that each sub-pixel region has four kinds of arrangement structure of liquid crystal molecule regions, and the optical performance of the sub-pixel region is improved.

[0044] The first sub-pixel region H can include a first thin film transistor T1 and a first pixel electrode PE1, the input end of the first thin film transistor T1 can be connected with a data line Data, and the output end can be connected with the first pixel electrode PE1. The second sub-pixel region M can include a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4 and a second pixel electrode PE2, and the third sub-pixel region L can include a third pixel electrode PE3. The input end of the second thin film transistor T2 is connected with the data line Data, and the output end can be connected with the second pixel electrode PE2 and the input end of the third thin film transistor T3, respectively, and the output end of the third thin film transistor T3 can be connected with the input end of the third pixel electrode PE3 and the fourth thin film transistor T4. In the embodiments of the present application, the input end can be a source or a drain, and when the input end is a source, the output end is a drain correspondingly.

[0045] The output end of the fourth thin film transistor T4 can be connected with a common signal line (not shown). In some embodiments, the second sub-pixel region M can further include a common electrode, and the output end of the fourth thin film transistor T4 can be connected with the common electrode. The control end (or called gate) of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 can be connected with the same gate scanning line Gate.

[0046] The gate scan line Gate can be connected to a gate driver, which can convert the signal output by the controller into a high-voltage and high-current scanning signal and transmit it through the gate scan line Gate to control the on-off of the thin film transistor connected to the gate scan line Gate. The data line Data can be connected to a source driver, and when the gate scan line Gate is loaded with a scanning signal, the data voltage is transmitted to the pixel electrode connected to the data line Data for charging.

[0047] With reference to the accompanying drawings Figure 1 The gate scan line Gate can include a first scan line S1 and a second scan line S2 connected to each other, so that the first scan line S1 and the second scan line S2 can load the scanning signal at the same time. The first scan line S1 can be located between two adjacent sub-pixel regions among the first sub-pixel region H, the second sub-pixel region M and the third sub-pixel region L, and the second scan line S2 can be located between the other two adjacent sub-pixel regions among the first sub-pixel region H, the second sub-pixel region M and the third sub-pixel region L, so that the subsequent staggered arrangement of the first sub-pixel region H, the second sub-pixel region M and the third sub-pixel region L can be facilitated.

[0048] In order to improve the aperture ratio, the first scan line S1 and the second scan line S2 can be located in different film layers, so that the pixel trace indium tin oxide (ITO) of the second sub-pixel region M can avoid crossing the first sub-pixel region H or the third sub-pixel region L, thereby improving the light transmittance, reducing light loss, and improving the display effect while reducing power consumption.

[0049] Taking the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 as examples, all of which are high-level on and low-level off.

[0050] For the first sub-pixel region H, when the gate scan line Gate loads a high-level scanning signal, the first thin film transistor T1 is turned on, and the data line Data can transmit the data voltage to the first pixel electrode PE1 through the first thin film transistor T1 for charging. For the second sub-pixel region M, when the gate scan line Gate loads a high-level driving signal, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are turned on. At this time, the data line Data transmits the data voltage through the second thin film transistor T2, wherein the data voltage can charge the third pixel electrode PE3 in addition to charging the second pixel electrode PE2, that is, the third thin film transistor T3 can divide a part of the data voltage to the third pixel electrode PE3 by voltage division, so that the voltage of the third pixel electrode PE3 is lower than that of the second pixel electrode PE2.

[0051] As the voltage of the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 gradually decreases, the voltage difference can cause the rotation angle of the liquid crystal molecules in each sub-pixel area to be different, the luminance (gray scale) of the first sub-pixel area H, the second sub-pixel area M and the third sub-pixel area L gradually decreases, and the displayed picture also has a more significant difference, thereby effectively reducing the display color deviation problem of the side view angle and improving the clarity of the display picture, and further improving the side view angle.

[0052] In some embodiments, the areas of the first sub-pixel area H, the second sub-pixel area M and the third sub-pixel area L can be equal, which can reduce the occurrence of the jagged phenomenon and improve the delicacy of the display picture.

[0053] It can be understood that the above is an example of high-level conduction of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4, and in some other embodiments, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 can also be low-level conduction and high-level cut-off type.

[0054] Figure 2 A liquid crystal display panel designed by the technical solution of the present application and the prior art technical solution in the same side view angle gray scale and Gamma value relationship curve provided by the embodiment of the present application. In the case of the same gray scale, the larger the corresponding Gamma value, the more serious the color deviation phenomenon. As shown in Figure 2 compared with the prior art, the corresponding Gamma value of the technical solution of the embodiment of the present application is closer to the Gamma value of the normal view angle at the same gray scale, that is, the technical solution provided by the embodiment of the present application can effectively improve the side view angle.

[0055] Taking a pixel structure including red, green and blue three colors as an example, Figure 3 the arrangement diagram of the first pixel structure group provided by the embodiment of the present application is shown in Figure 4 for Figure 3 the equivalent circuit diagram of the pixel structure group is shown in Figure 3 and Figure 4As shown, each pixel structure can form a plurality of pixel structure groups arranged in an array, each pixel structure group can include three pixel structures of different colors arranged in a row direction, and in a column direction, the pixel structures in each pixel structure group can be arranged in the same color arrangement sequence. For example, in the pixel structure group G1 and the pixel structure group G2, the pixel structures in the first column are all displayed in red, the pixel structures in the second column are all displayed in green, and the pixel structures in the third column are all displayed in blue. In the pixel structure group G1, each pixel structure has a first sub-pixel region H of high brightness, a second sub-pixel region M of medium brightness, and a third sub-pixel region L of low brightness from top to bottom.

[0056] Figure 5 A second pixel structure group arrangement schematic diagram provided by an embodiment of the present application is shown in the following, Figure 6 For Figure 5 An equivalent circuit schematic diagram of the pixel structure group is shown in the following, Figure 5 And Figure 6 As shown, compared with the first pixel structure group, the difference between the second pixel structure group arrangement is that in the same pixel structure group, the brightness of any two adjacent sub-pixel regions is different. For example, in the pixel structure group G1, the brightness of any sub-pixel region is different from the brightness of the sub-pixel regions above, below, left and right of it, for example, the first sub-pixel region H at the top of the first column has the highest brightness, and its right side and below are the second sub-pixel region M of medium brightness. In different pixel structure groups, the brightness arrangement sequence of the sub-pixel regions of the pixel structures of the same color is the same, for example. In the column direction, the pixel structures in the first column of the pixel structure group G1 and the pixel structure group G2 are all displayed in red, and the sub-pixel regions are arranged in the sequence of the first sub-pixel region H, the second sub-pixel region M, and the third sub-pixel region L from top to bottom. The pixel structures in the second column are all displayed in green, and the sub-pixel regions are arranged in the sequence of the second sub-pixel region M, the third sub-pixel region L, and the first sub-pixel region H from top to bottom. The pixel structures in the third column are all displayed in blue, and the sub-pixel regions are arranged in the sequence of the third sub-pixel region L, the first sub-pixel region H, and the second sub-pixel region M from top to bottom.

[0057] It should be noted that in the third column of pixel structures, the output end of the third thin film transistor T3 is connected to the fourth thin film transistor T4, and also connected to the third pixel electrode PE3 of the first sub-pixel region H and the third sub-pixel region L through a cross-line.

[0058] Through the above implementation, the display of the intermediate brightness picture can be realized by the interlaced arrangement of the first sub-pixel region H of high brightness, the second sub-pixel region M of medium brightness, and the third sub-pixel region L of low brightness, the clarity in side view is improved, and the graininess in displaying a pure color picture is reduced, and the side view angle is further improved.

[0059] Figure 7 The third pixel structure group provided in the embodiment of the present application is shown in the following arrangement diagram, Figure 8A - Figure 8C respectively, Figure 7 The equivalent circuit diagram of the pixel structure groups G1-G3 is shown in the following, Figure 7 - Figure 8C Compared with the second pixel structure group, the difference of the arrangement of the third pixel structure group mainly lies in that, in the row direction, the brightness of any three adjacent sub-pixel areas belonging to the same color is different from each other. For example, taking the pixel structure for displaying red as an example, the first column of the pixel structure group G1 is arranged in the order of the first sub-pixel area H, the second sub-pixel area M and the third sub-pixel area L from top to bottom, the first column of the pixel structure group G2 is arranged in the order of the second sub-pixel area M, the third sub-pixel area L and the first sub-pixel area H from top to bottom, and the first column of the pixel structure group G3 is arranged in the order of the third sub-pixel area L, the first sub-pixel area H and the second sub-pixel area M from top to bottom. In this way, the graininess when displaying a pure color picture can be further reduced, and the display quality and the side viewing angle of the picture can be further improved.

[0060] Figure 9 The fourth pixel structure group provided in the embodiment of the present application is shown in the following arrangement diagram, Figure 10A and Figure 10B respectively, Figure 9 The equivalent circuit diagram of the pixel structure groups G1 and G2 is shown in the following, Figure 9 - Figure 10B Compared with the third pixel structure group, the difference of the arrangement of the fourth pixel structure group mainly lies in that, in each pixel structure, the second sub-pixel area M and the third sub-pixel area L are adjacent; and in each pixel structure group, the positions of the third sub-pixel areas of different pixel structures are different.

[0061] For example, in the first column of the pixel structure group G1, the third sub-pixel area L is located at the lowermost position of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and located above the third sub-pixel area L, in the second column, the third sub-pixel area L is located at the middle position of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and located above the third sub-pixel area L, and in the third column, the third sub-pixel area L is located at the uppermost position of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and located below the third sub-pixel area L.

[0062] In the first column of the pixel structure group G2, the third sub-pixel area L is located at the middle position of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and located below the third sub-pixel area L, in the second column, the third sub-pixel area L is located at the lowermost position of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and located above the third sub-pixel area L, and in the third column, the third sub-pixel area L is located at the middle position of the column, the second sub-pixel area M is adjacent to the third sub-pixel area L and located above the third sub-pixel area L.

[0063] That is, although the positions of the second sub-pixel region M and the third sub-pixel region L change in different columns, the second sub-pixel region M and the third sub-pixel region L are always adjacent. In addition, the third sub-pixel region L has a difference in brightness with the sub-pixel region adjacent thereto. Through the above implementation, on the one hand, the light mixing effect of the pixel structure group can be improved, the graininess can be reduced, and thus the viewing angle and color cast can be further improved. On the other hand, the second sub-pixel region M and the third sub-pixel region L do not need to be connected through a cross line, and thus the problem of inconsistent resistance caused by the overlong cross line and further leading to uneven brightness of the third sub-pixel region L can be avoided, and the display quality is further improved.

[0064] It can be understood that in some embodiments, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 can also be arranged in the third sub-pixel region L, refer to Figure 11 The technical solutions provided in the embodiments of the present application can also be applied to other display types, such as a twisted nematic (TN) type and an FFS type.

[0065] The display panel provided in the embodiments of the present application comprises: a plurality of pixel structures arranged in an array, each pixel structure comprising a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged along a column direction; the first sub-pixel region comprises a first thin film transistor and a first pixel electrode, an input end of the first thin film transistor is connected with a data line, and an output end of the first thin film transistor is connected with the first pixel electrode; the second sub-pixel region comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor and a second pixel electrode, and the third sub-pixel region comprises a third pixel electrode; an input end of the second thin film transistor is connected with the data line, and an output end of the second thin film transistor is connected with the second pixel electrode and an input end of the third thin film transistor respectively, an output end of the third thin film transistor is connected with the third pixel electrode and an input end of the fourth thin film transistor respectively; control ends of the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are connected with a same gate scanning line; the brightness of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region gradually decreases. The display panel provided in the embodiments of the present application can improve the viewing angle of a VA type liquid crystal display device when viewed from the side by arranging three sub-pixel regions with different brightness.

[0066] Based on the same inventive concept, as an implementation of the above method, the embodiments of the present application provide a display device, the device embodiments correspond to the foregoing method embodiments, for the convenience of reading, the details of the foregoing method embodiments will not be described one by one, but it should be clear that the device in the embodiments can correspondingly implement all the contents in the foregoing method embodiments.

[0067] Figure 12 A structural schematic diagram of a display device provided in an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the display device provided in the embodiment includes a backlight module 100 and a display panel 200. Figure 12

[0068] The display device provided in the embodiment can execute the method embodiments described above, and the implementation principles and technical effects are similar, which will not be described herein.

[0069] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual applications, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. In addition, the specific names of the functional units and modules are only for the convenience of mutual distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be described herein.

[0070] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0071] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, and the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0072] It should be understood that when used in the specification and the appended claims of the present application, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or sets thereof.

[0073] ​In the description of the application, unless otherwise stated, " / " means that the objects before and after the correlation are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is only a description of the correlation of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone, where A, B can be singular or plural.

[0074] And, in the description of the application, unless otherwise stated, "multiple" means two or more than two. "At least one of the following" or similar expressions means any combination of the items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple.

[0075] As used in the specification and the appended claims of this application, the term "if" can be interpreted as "when" or "upon" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]" depending on the context.

[0076] In addition, in the description of the specification and the appended claims of this application, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0077] In the description of the application, the reference "one embodiment" or "some embodiments" means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the application. Therefore, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in other some embodiments" and the like appearing in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized.

[0078] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, include: Multiple pixel structures arranged in an array, each pixel structure including a first sub-pixel region, a second sub-pixel region and a third sub-pixel region arranged along the column direction; The first sub-pixel region includes a first thin-film transistor and a first pixel electrode. The input terminal of the first thin-film transistor is connected to the data line, and the output terminal is connected to the first pixel electrode. The second sub-pixel region includes a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, and a second pixel electrode; the third sub-pixel region includes a third pixel electrode. The input terminal of the second thin-film transistor is connected to the data line, and the output terminal is connected to the input terminal of the second pixel electrode and the third thin-film transistor, respectively. The output terminal of the third thin-film transistor is connected to the input terminal of the third pixel electrode and the fourth thin-film transistor, respectively. The control terminals of the first thin-film transistor, the second thin-film transistor, the third thin-film transistor, and the fourth thin-film transistor are connected to the same gate scan line; The brightness of the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area gradually decreases.

2. The display panel according to claim 1, characterized in that, The gate scan line includes a first scan line and a second scan line connected together. The first scan line is located between two adjacent sub-pixel regions among the first sub-pixel region, the second sub-pixel region and the third sub-pixel region. The second scan line is located between two other adjacent sub-pixel regions among the first sub-pixel region, the second sub-pixel region and the third sub-pixel region. The first scan line and the second scan line are located in different film layers.

3. The display panel according to claim 1, characterized in that, Each of the pixel structures forms multiple pixel structure groups arranged in an array. Each pixel structure group includes three pixel structures of different colors arranged along the row direction. The pixel structures in each pixel structure group are arranged in the same color arrangement order.

4. The display panel according to claim 3, characterized in that, In the pixel structure group, the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area of ​​each pixel structure are arranged in order of decreasing brightness from top to bottom.

5. The display panel according to claim 3, characterized in that, Within the same pixel structure group, the brightness of any two adjacent sub-pixel regions is different.

6. The display panel according to claim 5, characterized in that, Along the row direction, the brightness of any three adjacent sub-pixel regions of the same color is different from each other.

7. The display panel according to claim 3, characterized in that, In each pixel structure group, the brightness arrangement order of the sub-pixel areas of pixel structures with the same color is the same.

8. The display panel according to claim 1, characterized in that, In each pixel structure, the second sub-pixel region and the third sub-pixel region are adjacent, and the brightness of the third sub-pixel region is different from that of the adjacent sub-pixel regions.

9. The display panel according to any one of claims 1-8, characterized in that, The areas of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region are equal; each of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region includes four domains; the output terminal of the fourth thin-film transistor is connected to a common signal line.

10. A display device, characterized in that, include: The backlight module and the display panel according to any one of claims 1-9.

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