Quick response LDO with overcurrent protection

Abstract

The invention relates to the technical field of low dropout linear voltage regulators, in particular to a quick response LDO with overcurrent protection, which is characterized in that a biasing circuit and a voltage-regulator tube D1 are electrically connected with the input end of a large-bandwidth source follower, and then the large-bandwidth source follower, a reference circuit, an overcurrent protection circuit, an operational amplifier circuit and a filter circuit are electrically connected in sequence; the overcurrent protection circuit comprises a comparator bias unit, a comparator unit, a trigger unit, a driving unit, an MOS tube M9, an MOS tube M10 and an MOS tube N6. The comparator bias unit is used for generating comparator bias voltage and conducting the MOS tube M9 and the MOS tube M10; the comparison unit is used for receiving a comparator bias voltage and a reference signal generated by the reference circuit, and when the voltage of the reference signal is greater than the comparator bias voltage, the trigger unit is driven, the MOS tube N6 is switched on, and the driving unit is switched off; the problem that the protection action cannot be carried out due to the fact that the LDO internal overcurrent is rapidly responded is solved.

Description

Technical Field

[0001] The invention relates to the technical field of low voltage drop linear regulators, in particular to a fast response LDO with overcurrent protection. Background Art

[0002] LDO stands for low dropout linear regulator. In application scenarios that require high precision and stability, such as communication systems and industrial control equipment, the fast response speed of the linear regulator is particularly important. It can quickly respond to changes in input voltage and load, and quickly adjust the output voltage so that the system always operates within a stable voltage range, which helps to reduce system instability caused by voltage fluctuations or sudden load changes, such as voltage overshoot and undervoltage, thereby improving the overall stability of the system.

[0003] However, the overcurrent protection of the current fast-response LDO is integrated in the peripheral circuit of the LDO. When an overcurrent occurs, the LDO is directly shut down. However, the overcurrent fault generated inside the LDO is not taken into consideration. For example, when a micro-overcurrent occurs in the peripheral circuit of the LDO and is not sufficient to trigger the overcurrent protection, if it is transmitted to the LDO, the overcurrent fault is easily amplified during the fast response of the large-bandwidth source follower inside the LDO, resulting in an overcurrent of the signal transmitted to the operational amplifier, which breaks down the operational amplifier. Therefore, it is urgent to set an overcurrent protection inside the LDO to suppress the overcurrent signal generated during the fast response operation of the LDO. Summary of the invention

[0004] In view of the above defects, the purpose of the present invention is to provide a fast response LDO with overcurrent protection, which solves the problem that the fast response LDO cannot perform protection action due to internal overcurrent.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] A fast response LDO with overcurrent protection, comprising a bias circuit, a large bandwidth source follower, a reference circuit, a voltage regulator D1, an operational amplifier circuit, a filter circuit and an overcurrent protection circuit; the output end of the filter circuit is used as the output end of the fast response LDO;

[0007] The output end of the bias circuit and the cathode of the voltage regulator D1 are both electrically connected to the input end of the wide bandwidth source follower, the output end of the wide bandwidth source follower is electrically connected to the input end of the reference circuit, the output end of the reference circuit is electrically connected to the input end of the overcurrent protection circuit, the output end of the overcurrent protection circuit is electrically connected to the input end of the operational amplifier circuit, the output end of the operational amplifier circuit is electrically connected to the input end of the filter circuit, and the anode of the voltage regulator D1 is grounded;

[0008] The overcurrent protection circuit includes a comparator bias unit, a comparator unit, a trigger unit, a drive unit, a MOS tube M9, a MOS tube M10 and a MOS tube N6; the input end of the comparator unit is used as the input end of the overcurrent protection circuit, and the output end of the drive unit is used as the output end of the overcurrent protection circuit;

[0009] The gate of the MOS tube M9, the output end of the comparator bias unit and the bias end of the comparator unit are electrically connected, the output end of the comparator unit and the input end of the trigger unit are electrically connected, the VDD end of the comparator bias unit, the VDD end of the comparator unit and the source of the MOS tube M9 are all connected to the VDD power supply, the gate of the MOS tube M9 and the gate of the MOS tube M10 are electrically connected, the drain of the MOS tube M9 and the source of the MOS tube M10 are both electrically connected to the VDD end of the driving unit, the output end of the trigger unit and the gate of the MOS tube N6 are electrically connected, the source of the MOS tube N6 and the ground end of the driving unit are both grounded, and the drain of the MOS tube N6 and the drain of the MOS tube M10 are both electrically connected to the input end of the driving unit;

[0010] The comparator bias unit is used to generate a comparator bias voltage to turn on the MOS tube M9 and the MOS tube M10;

[0011] The comparison unit is used to receive the comparator bias voltage and the reference signal generated by the reference circuit, and when the voltage of the reference signal is greater than the comparator bias voltage, the trigger unit is driven to turn on the MOS tube N6 and turn off the driving unit.

[0012] Further, the comparison unit includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8, a MOS tube N4, a MOS tube N5, a resistor R2, a resistor R3 and a diode D2; the gate of the MOS tube M6 is used as the input end of the comparison unit, the gates of the MOS tube M5 and the MOS tube M8 are used as the bias end of the comparison unit, the source of the MOS tube M5 and the source of the MOS tube M8 are used as the VDD end of the comparison unit, and the source of the MOS tube N5 is used as the output end of the comparison unit;

[0013] The source of the MOS tube M6 and the source of the MOS tube M7 are electrically connected to the drain of the MOS tube M5, the drain of the MOS tube M6, the drain of the MOS tube N4, and the gate of the MOS tube N4 are electrically connected to the gate of the MOS tube N5, the drain of the MOS tube N5 is electrically connected to the drain of the MOS tube M7, the gate of the MOS tube M7 and one end of the resistor R2 are electrically connected to one end of the resistor R3, the anode of the diode D2, the other end of the resistor R3, the source of the MOS tube N4, and the source of the MOS tube N5 are grounded, and the other end of the resistor R2 and the cathode of the diode D2 are electrically connected to the drain of the MOS tube M8.

[0014] Further, the comparator bias unit includes MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube N1, MOS tube N2, MOS tube N3 and resistor R1; the source electrodes of the MOS tube M1, the MOS tube M2 and the MOS tube M3 are all used as the VDD terminal of the comparator bias unit, and the gate electrode of the MOS tube M3 is used as the output terminal of the comparator bias unit;

[0015] The gate and drain of the MOS tube M1 are electrically connected to one end of the resistor R1, the other end of the resistor R1 and the gate of the MOS tube M4 are electrically connected to the drain of the MOS tube N3, the gate of the MOS tube M3, the drain of the MOS tube N1, the gate of the MOS tube M2, and the drain of the MOS tube M2 are electrically connected to the source of the MOS tube M4, the gate of the MOS tube N3, the gate of the MOS tube N1, the gate of the MOS tube N2, and the drain of the MOS tube N2 are electrically connected to the drain of the MOS tube M3, and the drain of the MOS tube M4, the source of the MOS tube N1, the source of the MOS tube N2, and the source of the MOS tube N3 are grounded.

[0016] Further, the trigger unit includes MOS tube M13, MOS tube M14, MOS tube N9, MOS tube N10, MOS tube M15, MOS tube N11, MOS tube N12, MOS tube M37, resistor R4 and resistor R5; the gate of the MOS tube M14 is used as the input end of the trigger unit, and the drain of the MOS tube M37 is used as the output end of the trigger unit;

[0017] The source of the MOS tube M13 is connected to the VDD power supply, the drain of the MOS tube M13 and the source of the MOS tube M14 are electrically connected to the source of the MOS tube M15, the drain of the MOS tube M15 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is grounded, the gate of the MOS tube M13, the gate of the MOS tube M14, and the gate of the MOS tube N9 are electrically connected to the gate of the MOS tube N10, the gate of the MOS tube M37, the gate of the MOS tube N12, the gate of the MOS tube M15, the gate of the MOS tube N10 are electrically connected to the gate of the MOS tube N11, and the gate of the MOS tube M37, the gate of the MOS tube N12, the gate of the MOS tube M15, the gate of the MOS tube N11 are electrically connected to the gate of the MOS tube N12. The gate of the MOS tube N11 and the drain of the MOS tube M14 are electrically connected to the drain of the MOS tube N9, the source of the MOS tube N10 is grounded, the drain of the MOS tube N10 and the source of the MOS tube N9 are electrically connected to the source of the MOS tube N11, the drain of the MOS tube N11 is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the VDD power supply, the source of the MOS tube M37 is connected to the VDD power supply, the source of the MOS tube N12 is grounded, and the drain of the MOS tube M37 is electrically connected to the drain of the MOS tube N12.

[0018] Further, the driving unit includes a MOS tube M11, a MOS tube M12, a MOS tube N7 and a MOS tube N8; the gate of the MOS tube M11 is used as the input end of the driving unit, the drain of the MOS tube M12 is used as the output end of the driving unit, the source of the MOS tube M11 and the source of the MOS tube M12 are both used as the VDD end of the driving unit, and the source of the MOS tube N7 and the source of the MOS tube N8 are both used as the ground end of the driving unit;

[0019] The gate of the MOS tube M11 is electrically connected to the gate of the MOS tube N7, the drain of the MOS tube M11, the drain of the MOS tube N7, and the gate of the MOS tube M12 are all electrically connected to the gate of the MOS tube N8, and the drain of the MOS tube M12 is electrically connected to the drain of the MOS tube N8.

[0020] Furthermore, the filtering circuit includes a frequency band filtering unit, a first shaping filtering unit and a second shaping filtering unit; the input end of the frequency band filtering unit is used as the input end of the filtering circuit, the output end of the frequency band filtering unit is electrically connected to the input end of the first shaping filtering unit, the output end of the first shaping filtering unit is electrically connected to the input end of the second shaping filtering unit, and the output end of the second shaping filtering unit is used as the output end of the filtering circuit;

[0021] The frequency band filtering unit is used to set a cutoff frequency to filter out non-output signal frequency bands;

[0022] The first shaping filter unit is used to filter out noise and interference of the signal;

[0023] The second shaping and filtering unit is used for signal waveform shaping and signal amplification.

[0024] Further, the frequency band filtering unit includes a response speed setting circuit and a frequency band filter; the input end of the response speed setting circuit is used as the input end of the frequency band filtering unit, the output end of the response speed setting circuit is electrically connected to the input end of the frequency band filter, and the output end of the frequency band filter is used as the output end of the frequency band filtering unit;

[0025] The response speed setting circuit is used to set the conduction time of the frequency band filter;

[0026] The response speed setting circuit includes a MOS tube M15 and a MOS tube M16; the gate of the MOS tube M15 is used as the input end of the response speed setting circuit, and the drain of the MOS tube M15 is used as the output end of the response speed setting circuit;

[0027] The source of the MOS tube M15 is connected to the VDD power supply, the gate of the MOS tube M15 is electrically connected to the gate of the MOS tube M16, the drain of the MOS tube M15 is electrically connected to the drain of the MOS tube M16, and the source of the MOS tube M16 is grounded;

[0028] The frequency band filter comprises a resistor R and a capacitor C, one end of the resistor R is used as an input end of the frequency band filter, the other end of the resistor R is used as an output end of the frequency band filter, the other end of the resistor R is electrically connected to one end of the capacitor C, and the other end of the capacitor C is grounded;

[0029] The resistor R includes at least two sub-resistors R6, one end of the first sub-resistor R6 is used as one end of the resistor R, and the other end of the last sub-resistor R6 is used as the other end of the resistor R; the other end of the first sub-resistor R6 is electrically connected to one end of the last sub-resistor R6;

[0030] The capacitor C includes at least two sub-capacitors C1 , one end of each sub-capacitor C1 is used as one end of the capacitor C, and the other end of each sub-capacitor C1 is used as the other end of the capacitor C.

[0031] Further, the first shaping filter unit includes a MOS tube M17, a MOS tube M18, a MOS tube M19, a MOS tube M20, a MOS tube M21, a MOS tube M22, a resistor R7 and a resistor R8; the gate of the MOS tube M18 is used as the input end of the first shaping filter unit, and the gate of the MOS tube M21 is used as the output end of the first shaping filter unit;

[0032] The source of the MOS tube M17 and the source of the MOS tube M21 are both connected to the VDD power supply, the drain of the MOS tube M17 and the source of the MOS tube M18 are both electrically connected to the source of the MOS tube M21, the drain of the MOS tube M21 is electrically connected to one end of the resistor R7, the other end of the resistor R7 is grounded, the gate of the MOS tube M17, the gate of the MOS tube M18, and the gate of the MOS tube M19 are all electrically connected to the gate of the MOS tube M20 The drain of the MOS tube M18 is electrically connected to the drain of the MOS tube M19, the source of the MOS tube M20 and the source of the MOS tube M22 are both grounded, the drain of the MOS tube M20 and the source of the MOS tube M19 are both electrically connected to the source of the MOS tube M22, the drain of the MOS tube M22 is electrically connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the gate of the MOS tube M21 is electrically connected to the gate of the MOS tube M22.

[0033] Further, the second shaping filter unit includes a MOS tube M23, a MOS tube M24, a MOS tube M25 and a MOS tube M26; the gate of the MOS tube M23 is used as the input end of the second shaping filter unit, and the drain of the MOS tube M25 is used as the output end of the second shaping filter unit;

[0034] The gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M24, the source of the MOS tube M23 is connected to the VDD power supply, the drain of the MOS tube M23 is electrically connected to the drain of the MOS tube M24, and the source of the MOS tube M24 is grounded;

[0035] The gate of the MOS tube M25 is electrically connected to the gate of the MOS tube M26, the source of the MOS tube M25 is connected to the VDD power supply, the drain of the MOS tube M25 is electrically connected to the drain of the MOS tube M26, and the source of the MOS tube M26 is grounded.

[0036] Furthermore, the high-bandwidth source follower includes a MOS tube M27, a capacitor CL, a current mirror circuit and a bias constant current source; the gate of the MOS tube M27 is used as the input end of the high-bandwidth source follower, and the source of the MOS tube M27 is used as the output end of the high-bandwidth source follower;

[0037] The control end of the current mirror circuit is electrically connected to the output end of the bias constant current source, the first end of the current mirror circuit is electrically connected to the drain of the MOS tube M27, the second end of the current mirror circuit and one end of the capacitor CL are both electrically connected to the source of the MOS tube M27, and the other end of the capacitor CL is grounded.

[0038] The technical solution provided by the present invention may include the following beneficial effects: a fast response LDO is composed of a bias circuit and a voltage regulator tube D to form a startup circuit to generate a stable bias voltage. After being buffered and isolated by a large bandwidth source follower, the bias voltage is provided to a reference circuit to make it work at a desired static working point, thereby preventing the reference circuit from entering a zero bias current state, that is, the working current in the circuit is zero and cannot work normally; the reference circuit then generates a reference signal and provides it to the operational amplifier circuit, and the operational amplifier circuit thereby realizes voltage linear adjustment; and because a large bandwidth source follower is used, the time for the operational amplifier circuit to establish linearity is greatly shortened, thereby greatly shortening the time for the operational amplifier circuit to respond to the output signal, so if the reference signal is disturbed at this time, an overcurrent phenomenon is likely to occur, so an overcurrent protection circuit is set here to prevent the overcurrent reference signal from breaking through the operational amplifier circuit, and the final output signal is filtered by a terminal filtering circuit and the non-output signal frequency band is filtered out, so that a higher quality output signal is obtained, which is more matched with the fast response LDO and adapts to the application environment of the fast response LDO, and avoids signal distortion.

[0039] Specifically, when the overcurrent protection circuit normally receives the comparator bias voltage, MOS tube M and MOS tube M are in the on state, and the comparison unit normally receives the reference signal to drive the trigger unit to enable MOS tube M; only when the reference signal is overcurrent (that is, the voltage of the reference signal is greater than the comparator bias voltage), the MOS tube M is triggered to turn off the subsequent drive unit, thereby cutting off the overcurrent signal from being transmitted to the op amp circuit, and realizing fast response LDO internal overcurrent protection. More importantly, using a comparator with a bias voltage as an overcurrent judgment can speed up the judgment speed and adapt to the fast response characteristics of the LDO. At the same time, using the trigger method (trigger unit) to transmit the signal to the op amp circuit can play a certain role in isolation and filtering, avoiding direct conduction of the reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The schematic diagram is a fast response LDO with overcurrent protection according to one embodiment of the present invention.

[0041] Figure 2 Yes Figure 1 The circuit diagram of the overcurrent protection circuit is shown.

[0042] Figure 3 Yes Figure 1 Circuit diagram of the filter circuit shown.

[0043] Figure 4 Yes Figure 1 The circuit diagram of a high bandwidth source follower is shown.

[0044] Among them: bias circuit 1, wide bandwidth source follower 2, reference circuit 3, voltage regulator D1, operational amplifier circuit 4, filter circuit 5, overcurrent protection circuit 6, undervoltage protection circuit 7, MOS tube M37, resistor R9, resistor R10, operational amplifier A1, comparator bias unit 61, comparator unit 62, trigger unit 63, drive unit 64, MOS tube M9, MOS tube M10, MOS tube N6, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube N4 , MOS tube N5, resistor R2, resistor R3, diode D2, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube N1, MOS tube N2, MOS tube N3, resistor R1, MOS tube M13, MOS tube M14, MOS tube N9, MOS tube N10, MOS tube M15, MOS tube N11, MOS tube N12, MOS tube M37, resistor R4, resistor R5, MOS tube M11, MOS tube M12, MOS tube N7, M MOS tube N8, frequency band filtering unit 51, first shaping filter unit 52, second shaping filter unit 53, response speed setting circuit 511, frequency band filter 512, MOS tube M15, MOS tube M16, resistor R, capacitor C, resistor R6, capacitor C1, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, resistor R7, resistor R8, MOS tube M23, MOS tube M24, MOS tube M25, M OS transistor M26, MOS transistor M1, capacitor CL, current mirror circuit 21, bias constant current source 22, MOS transistor M2, MOS transistor M3, MOS transistor M4, MOS transistor M5, MOS transistor M6, MOS transistor M7, current source A2, MOS transistor M8, MOS transistor M9, MOS transistor M27, MOS transistor M28, MOS transistor M29, MOS transistor M30, MOS transistor M31, MOS transistor M32, MOS transistor M33, current source A2, MOS transistor M34, MOS transistor M35. DETAILED DESCRIPTION

[0045] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0046] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0048] Combine the following Figures 1 to 4 , describing a fast response LDO with overcurrent protection according to an embodiment of the present invention.

[0049] A fast response LDO with overcurrent protection, comprising a bias circuit 1, a large bandwidth source follower 2, a reference circuit 3, a voltage regulator D1, an operational amplifier circuit 4, a filter circuit 5 and an overcurrent protection circuit 6; the output end of the filter circuit 5 is used as the output end of the fast response LDO;

[0050] The output end of the bias circuit 1 and the cathode of the voltage regulator D1 are electrically connected to the input end of the wide bandwidth source follower 2, the output end of the wide bandwidth source follower 2 is electrically connected to the input end of the reference circuit 3, the output end of the reference circuit 3 is electrically connected to the input end of the overcurrent protection circuit 6, the output end of the overcurrent protection circuit 6 is electrically connected to the input end of the operational amplifier circuit 4, the output end of the operational amplifier circuit 4 is electrically connected to the input end of the filter circuit 5, and the anode of the voltage regulator D1 is grounded;

[0051] The overcurrent protection circuit 6 includes a comparator bias unit 61, a comparator unit 62, a trigger unit 63, a drive unit 64, a MOS tube M9, a MOS tube M10 and a MOS tube N6; the input end of the comparator unit 62 is used as the input end of the overcurrent protection circuit 6, and the output end of the drive unit 64 is used as the output end of the overcurrent protection circuit 6;

[0052] The gate of the MOS tube M9, the output end of the comparator bias unit 61 and the bias end of the comparator unit 62 are electrically connected, the output end of the comparator unit 62 and the input end of the trigger unit 63 are electrically connected, the VDD end of the comparator bias unit 61, the VDD end of the comparator unit 62 and the source of the MOS tube M9 are all connected to the VDD power supply, the gate of the MOS tube M9 and the gate of the MOS tube M10 are electrically connected, the drain of the MOS tube M9 and the source of the MOS tube M10 are both electrically connected to the VDD end of the driving unit 64, the output end of the trigger unit 63 and the gate of the MOS tube N6 are electrically connected, the source of the MOS tube N6 and the ground end of the driving unit 64 are both grounded, and the drain of the MOS tube N6 and the drain of the MOS tube M10 are both electrically connected to the input end of the driving unit 64;

[0053] The comparator bias unit 61 is used to generate a comparator bias voltage to turn on the MOS tube M9 and the MOS tube M10;

[0054] The comparison unit 62 is used to receive the comparator bias voltage and the reference signal generated by the reference circuit 3. When the voltage of the reference signal is greater than the comparator bias voltage, the trigger unit 63 is driven to turn on the MOS tube N6 and turn off the driving unit 64.

[0055] The present invention proposes a preferred embodiment of a fast response LDO with overcurrent protection, such as Figures 1 to 2 As shown, the fast response LDO is composed of a bias circuit 1 and a voltage regulator tube D1. The startup circuit generates a stable bias voltage. After being buffered and isolated by a large bandwidth source follower 2, the bias voltage is provided to a reference circuit 3, so that it works at the required static working point, and the reference circuit 3 is prevented from entering a zero bias current state, that is, the working current in the circuit is zero and cannot work normally; the reference circuit 3 then generates a reference signal and provides it to the operational amplifier circuit 4, and the operational amplifier circuit 4 implements voltage linear adjustment; and because a large bandwidth source follower 2 is used, the linear establishment time of the operational amplifier circuit 4 is greatly shortened, so that the time for the operational amplifier circuit 4 to respond to the output signal is greatly shortened. Therefore, if the reference signal is disturbed at this time, an overcurrent phenomenon may easily occur. Therefore, an overcurrent protection circuit 6 is set here to prevent the overcurrent reference signal from breaking through the operational amplifier circuit 4. The final output signal is filtered by the filter circuit 5 at the end and the non-output signal frequency band is filtered out to obtain a better quality output signal, which is more matched with the fast response LDO and adapts to the application environment of the fast response LDO, and avoids signal distortion.

[0056] Specifically, when the overcurrent protection circuit 6 normally receives the comparator bias voltage, the MOS tube M9 and the MOS tube M10 are in the on state, and the comparison unit 62 normally receives the reference signal to drive the trigger unit 63 to enable the MOS tube M6; only when the reference signal is overcurrent (that is, the voltage of the reference signal is greater than the comparator bias voltage), the MOS tube M6 is triggered to turn off the subsequent drive unit 64, thereby cutting off the overcurrent signal from being transmitted to the operational amplifier circuit 4, and realizing fast response LDO internal overcurrent protection. More importantly, using a comparator with a bias voltage as an overcurrent judgment can speed up the judgment speed and adapt to the fast response characteristics of the LDO. At the same time, using the trigger method (trigger unit 63) to transmit the signal to the operational amplifier circuit 4 can play a certain role in isolation and filtering, and avoid direct transmission of the reference signal.

[0057] The operational amplifier circuit 4 may specifically be:

[0058] The operational amplifier circuit 4 includes a MOS tube M37, a resistor R9, a resistor R10 and an operational amplifier A1; the negative input terminal of the operational amplifier A1 is used as the input terminal of the operational amplifier circuit 4, and the drain of the MOS tube M37 is used as the output terminal of the operational amplifier circuit 4; the source of the MOS tube M37 is connected to the VDD power supply, the gate of the MOS tube M37 is electrically connected to the output terminal of the operational amplifier A1, the source of the MOS tube M37 is electrically connected to one end of the resistor R9, the other end of the resistor R9 and the positive input terminal of the operational amplifier A1 are both electrically connected to one end of the resistor R10, and the other end of the resistor R10 is grounded; the operational amplifier circuit 4 with negative feedback is composed of the MOS tube M37, the resistor R9, the resistor R10 and the operational amplifier A1, so that the output makes a linear response to the input change while maintaining the balance between the output and the input. Moreover, both the MOS tube M1 and the MOS tube M37 use high-voltage LDMOS tubes, which have higher gain, faster response speed, and stronger voltage tolerance than ordinary MOS tubes, and are more suitable for a large-bandwidth source follower 2 and an LDO using the follower.

[0059] The reference circuit 3 may specifically be a bandgap reference circuit, which has the characteristics of low noise and high stability compared to ordinary reference circuits, and is more conducive to providing a stable reference signal for the operational amplifier circuit 4 .

[0060] The voltage regulator D1 can specifically be a Zener voltage regulator diode, which has fast switching characteristics, strong resistance to overcharging and over-discharging, reduces input voltage noise, avoids introducing noise into the large-bandwidth source follower 2, and adapts to the fast response characteristics of the large-bandwidth source follower 2.

[0061] It should be noted that the fast response LDO may also include an undervoltage protection circuit 7. After the output end of the operational amplifier circuit 4 is electrically connected to the input end of the undervoltage protection circuit 7, the output end of the undervoltage protection circuit 7 is electrically connected to the input end of the filter circuit 5 to avoid signal undervoltage through the operational amplifier circuit 4, which may cause a disordered final output signal.

[0062] Further, the comparison unit 62 includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8, a MOS tube N4, a MOS tube N5, a resistor R2, a resistor R3 and a diode D2; the gate of the MOS tube M6 is used as an input end of the comparison unit 62, the gates of the MOS tube M5 and the MOS tube M8 are used as bias ends of the comparison unit 62, the source of the MOS tube M5 and the source of the MOS tube M8 are used as VDD ends of the comparison unit 62, and the source of the MOS tube N5 is used as an output end of the comparison unit 62;

[0063] The source of the MOS tube M6 and the source of the MOS tube M7 are electrically connected to the drain of the MOS tube M5, the drain of the MOS tube M6, the drain of the MOS tube N4, and the gate of the MOS tube N4 are electrically connected to the gate of the MOS tube N5, the drain of the MOS tube N5 is electrically connected to the drain of the MOS tube M7, the gate of the MOS tube M7 and one end of the resistor R2 are electrically connected to one end of the resistor R3, the anode of the diode D2, the other end of the resistor R3, the source of the MOS tube N4, and the source of the MOS tube N5 are grounded, and the other end of the resistor R2 and the cathode of the diode D2 are electrically connected to the drain of the MOS tube M8.

[0064] The comparison unit 62 in this embodiment is composed of a sampling circuit consisting of a MOS tube M8, a resistor R2, a resistor R3 and a diode D2, which receives a comparator bias voltage (VB). The comparison circuit is composed of a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube N4 and a MOS tube N5, which can effectively reduce the noise generated in the fast response of the LDO and reduce power consumption. At the same time, it can make a quick judgment under the comparator bias voltage, and is more suitable for fast response LDO than directly using comparator components (slow response).

[0065] Furthermore, the comparator bias unit 61 includes MOS transistors M1, M2, M3, M4, N1, N2, N3 and a resistor R1; the sources of the MOS transistors M1, M2 and M3 are used as the VDD terminal of the comparator bias unit 61, and the gate of the MOS transistor M3 is used as the output terminal of the comparator bias unit 61;

[0066] The gate and drain of the MOS tube M1 are electrically connected to one end of the resistor R1, the other end of the resistor R1 and the gate of the MOS tube M4 are electrically connected to the drain of the MOS tube N3, the gate of the MOS tube M3, the drain of the MOS tube N1, the gate of the MOS tube M2, and the drain of the MOS tube M2 are electrically connected to the source of the MOS tube M4, the gate of the MOS tube N3, the gate of the MOS tube N1, the gate of the MOS tube N2, and the drain of the MOS tube N2 are electrically connected to the drain of the MOS tube M3, and the drain of the MOS tube M4, the source of the MOS tube N1, the source of the MOS tube N2, and the source of the MOS tube N3 are grounded.

[0067] In the comparator bias unit 61 of the present embodiment, the MOS transistor M1 and the resistor R1 play the role of branch voltage division, and the MOS transistors M2, M3, N2 and N3 form a current mirror. The MOS transistors M2 and N2 are connected by diodes, so that they are saturated when turned on, and the MOS transistors M3 and N1 work in the linear region. The comparator bias voltage (VB) can be adjusted by adjusting the width-to-length ratio of the MOS transistors N2 and M3, so that the overcurrent protection circuit 6 can adjust the comparator bias voltage according to actual needs, so as to adapt to more types of fast response LDOs.

[0068] Further, the trigger unit 63 includes a MOS tube M13, a MOS tube M14, a MOS tube N9, a MOS tube N10, a MOS tube M15, a MOS tube N11, a MOS tube N12, a MOS tube M37, a resistor R4 and a resistor R5; the gate of the MOS tube M14 is used as the input end of the trigger unit 63, and the drain of the MOS tube M37 is used as the output end of the trigger unit 63;

[0069] The source of the MOS tube M13 is connected to the VDD power supply, the drain of the MOS tube M13 and the source of the MOS tube M14 are electrically connected to the source of the MOS tube M15, the drain of the MOS tube M15 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is grounded, the gate of the MOS tube M13, the gate of the MOS tube M14, and the gate of the MOS tube N9 are electrically connected to the gate of the MOS tube N10, the gate of the MOS tube M37, the gate of the MOS tube N12, the gate of the MOS tube M15, and the gate of the MOS tube N The gate of the MOS tube M11 and the drain of the MOS tube M14 are electrically connected to the drain of the MOS tube N9, the source of the MOS tube N10 is grounded, the drain of the MOS tube N10 and the source of the MOS tube N9 are electrically connected to the source of the MOS tube N11, the drain of the MOS tube N11 is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the VDD power supply, the source of the MOS tube M37 is connected to the VDD power supply, the source of the MOS tube N12 is grounded, and the drain of the MOS tube M37 is electrically connected to the drain of the MOS tube N12.

[0070] In this embodiment, based on the need for the trigger unit 63 to be controlled and triggered while playing a certain isolation and filtering role, a Schmitt trigger is formed by MOS tube M13, MOS tube M14, MOS tube N9, MOS tube N10, MOS tube M15, MOS tube N11, MOS tube N12, MOS tube M37, resistor R4 and resistor R5.

[0071] Furthermore, the driving unit 63 includes a MOS tube M11, a MOS tube M12, a MOS tube N7 and a MOS tube N8; the gate of the MOS tube M11 is used as the input end of the driving unit 63, the drain of the MOS tube M12 is used as the output end of the driving unit 63, the source of the MOS tube M11 and the source of the MOS tube M12 are both used as the VDD end of the driving unit 63, and the source of the MOS tube N7 and the source of the MOS tube N8 are both used as the ground end of the driving unit 63;

[0072] The gate of the MOS tube M11 is electrically connected to the gate of the MOS tube N7, the drain of the MOS tube M11, the drain of the MOS tube N7, and the gate of the MOS tube M12 are all electrically connected to the gate of the MOS tube N8, and the drain of the MOS tube M12 is electrically connected to the drain of the MOS tube N8.

[0073] In this embodiment, since the trigger unit 63 is a Schmitt trigger, the output signal driving capability may be insufficient, so the driving unit 63 is composed of MOS tube M11, MOS tube M12, MOS tube N7 and MOS tube N8 to form a driver, which enhances the signal driving capability and improves the signal integrity, avoids the signal from being weakened due to attenuation or load factors during transmission, reduces signal distortion and distortion, and ensures the signal quality.

[0074] Furthermore, the filter circuit 5 includes a frequency band filter unit 51, a first shaping filter unit 52 and a second shaping filter unit 53; the input end of the frequency band filter unit 51 is used as the input end of the filter circuit, the output end of the frequency band filter unit 51 is electrically connected to the input end of the first shaping filter unit 52, the output end of the first shaping filter unit 52 is electrically connected to the input end of the second shaping filter unit 53, and the output end of the second shaping filter unit 53 is used as the output end of the filter circuit;

[0075] The frequency band filtering unit 51 is used to set the cut-off frequency to filter out the non-output signal frequency band;

[0076] The first shaping filter unit 52 is used to filter out noise and interference of the signal;

[0077] The second shaping filter unit 53 is used for signal waveform shaping and signal amplification.

[0078] In this embodiment, based on the characteristics of fast response LDO, if the filtering ability is poor, high-frequency signals are likely to cause the filtering frequency band to be uncontrollable, thereby possibly causing clutter overcurrent (i.e., excessive fluctuation). Therefore, the filtering circuit 5 is preferably composed of a frequency band filtering unit 51, a first shaping filtering unit 52, and a second shaping filtering unit 53, such as Figure 3 As shown. The signal input is first filtered out by the frequency band filtering unit 51 according to the set cutoff frequency, and only the specified signal frequency band is allowed to pass, so as to achieve frequency band filtering while avoiding uncontrollable signal frequency band filtering, and filter out the specified frequency band of the output signal; then the signal is filtered out by the first shaping filter unit 52 to remove noise and interference in the signal; finally, the signal is shaped by the second shaping filter unit 53, because the waveform of the signal may be distorted due to various factors (such as noise, attenuation, etc.) during the signal transmission process. The second shaping filter unit 53 reprocesses the signal to restore or improve the waveform quality of the signal, so that the waveform of the output signal is closer to the original signal. At the same time, the second shaping filter unit 53 also amplifies the signal to improve the signal's carrying capacity and maintain the driving capacity of the subsequent circuit. In summary, the filter circuit processes the signal in sequence through three functional modules, enhances the filtering ability of the fast response LDO signal, adapts to high-frequency signals, and can resist high-frequency noise and clutter from the fast response LDO application environment (such as high-power high-voltage switching power supply), and plays a certain role in terminal overcurrent protection.

[0079] Further, the frequency band filtering unit 51 includes a response speed setting circuit 511 and a frequency band filter 512; the input end of the response speed setting circuit 511 is used as the input end of the frequency band filtering unit 51, the output end of the response speed setting circuit 511 is electrically connected to the input end of the frequency band filter 512, and the output end of the frequency band filter 512 is used as the output end of the frequency band filtering unit 51;

[0080] The response speed setting circuit 511 is used to set the conduction time of the frequency band filter 512;

[0081] The response speed setting circuit 511 includes a MOS transistor M15 and a MOS transistor M16; the gate of the MOS transistor M15 is used as the input end of the response speed setting circuit 511, and the drain of the MOS transistor M15 is used as the output end of the response speed setting circuit 511;

[0082] The source of the MOS tube M15 is connected to the VDD power supply, the gate of the MOS tube M15 is electrically connected to the gate of the MOS tube M16, the drain of the MOS tube M15 is electrically connected to the drain of the MOS tube M16, and the source of the MOS tube M16 is grounded;

[0083] The frequency band filter 512 includes a resistor R and a capacitor C, one end of the resistor R is used as an input end of the frequency band filter 512, the other end of the resistor R is used as an output end of the frequency band filter 512, the other end of the resistor R is electrically connected to one end of the capacitor C, and the other end of the capacitor C is grounded;

[0084] The resistor R includes at least two sub-resistors R6, one end of the first sub-resistor R6 is used as one end of the resistor R, and the other end of the last sub-resistor R6 is used as the other end of the resistor R; the other end of the first sub-resistor R6 is electrically connected to one end of the last sub-resistor R6;

[0085] The capacitor C includes at least two sub-capacitors C1 , one end of each sub-capacitor C1 is used as one end of the capacitor C, and the other end of each sub-capacitor C1 is used as the other end of the capacitor C.

[0086] In this embodiment, the function of the frequency band filtering unit 51 to filter out the non-output signal frequency band according to the cut-off frequency is achieved by setting the on-time of the frequency band filter 512 by the response speed setting circuit 511, that is, by changing the response speed of the response speed setting circuit 511 itself to determine when the signal is transmitted to the frequency band filter 512 and how long it continues to pass, thereby achieving frequency band selection and filtering out the non-output signal frequency band.

[0087] The response speed setting circuit 511 is an inverter composed of MOS tube M15 and MOS tube M16. The slew rate is affected by adjusting the W / L ratio (width-to-length ratio) of the MOS tube, thereby affecting the response speed of the inverter. The W / L of the MOS tube can be set in advance according to signal requirements.

[0088] The frequency band filter 512 is an RC filter composed of a resistor R and a capacitor C. By designing resistors R with different resistance values ​​and capacitors C with different capacitance values, under the condition that the MOS tube of the response speed setting circuit 511 is fixed at W, by adjusting L in proportion, the RC filter can obtain different cut-off frequencies, play an adjustable filtering function, and filter out unnecessary output signal frequency bands. According to signal requirements, the resistance value of the resistor R and the capacitance value of the capacitor C can be set in advance in conjunction with the response speed setting circuit 511, and the filtering scheme can be determined through simulation to match the high-frequency signal of the fast-response LDO. More importantly, the resistor R is composed of multiple sub-resistors R6 connected in series, and the capacitor C is composed of multiple sub-capacitors C1 connected in parallel, which can improve the simulation accuracy and the final frequency band filtering accuracy, and the filtering effect is better.

[0089] Furthermore, the first shaping filter unit 52 includes a MOS tube M17, a MOS tube M18, a MOS tube M19, a MOS tube M20, a MOS tube M21, a MOS tube M22, a resistor R7, and a resistor R8; the gate of the MOS tube M18 is used as the input end of the first shaping filter unit 52, and the gate of the MOS tube M21 is used as the output end of the first shaping filter unit 52;

[0090] The source of the MOS tube M17 and the source of the MOS tube M21 are both connected to the VDD power supply, the drain of the MOS tube M17 and the source of the MOS tube M18 are both electrically connected to the source of the MOS tube M21, the drain of the MOS tube M21 is electrically connected to one end of the resistor R7, the other end of the resistor R7 is grounded, the gate of the MOS tube M17, the gate of the MOS tube M18, and the gate of the MOS tube M19 are all electrically connected to the gate of the MOS tube M20, the drain of the MOS tube M18 is electrically connected to the drain of the MOS tube M19, the source of the MOS tube M20 and the source of the MOS tube M22 are both grounded, the drain of the MOS tube M20 and the source of the MOS tube M19 are both electrically connected to the source of the MOS tube M22, the drain of the MOS tube M22 is electrically connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the gate of the MOS tube M21 is electrically connected to the gate of the MOS tube M22.

[0091] In this embodiment, the first shaping filter unit 52 is a Schmitt trigger composed of MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, resistor R7 and resistor R8. The hysteresis characteristic of the Schmitt trigger can effectively filter out the noise and interference of the signal, and the effect is better. More importantly, by adjusting the width-to-length ratio of the NMOS tube and the PMOS tube in the Schmitt trigger, the forward conduction threshold VTH+ and the negative conduction threshold VTH- of the Schmitt trigger can be adjusted to match the high-frequency signal of the fast response LDO, improve the filtering accuracy, and facilitate the reservation of the threshold margin to prevent misleading conduction.

[0092] Furthermore, the second shaping filter unit 53 includes a MOS tube M23, a MOS tube M24, a MOS tube M25 and a MOS tube M26; the gate of the MOS tube M23 is used as the input end of the second shaping filter unit 53, and the drain of the MOS tube M25 is used as the output end of the second shaping filter unit 53;

[0093] The gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M24, the source of the MOS tube M23 is connected to the VDD power supply, the drain of the MOS tube M23 is electrically connected to the drain of the MOS tube M24, and the source of the MOS tube M24 is grounded;

[0094] The gate of the MOS tube M25 is electrically connected to the gate of the MOS tube M26, the source of the MOS tube M25 is connected to the VDD power supply, the drain of the MOS tube M25 is electrically connected to the drain of the MOS tube M26, and the source of the MOS tube M26 is grounded.

[0095] In this embodiment, MOS tube M23 and MOS tube M24 constitute a first inverter 531, MOS tube M25 and MOS tube M26 constitute a second inverter 532, and the signal shaping and signal amplification functions of the second shaping and filtering unit 53 are realized by two-stage inverters. The first inverter 531 receives the input signal and converts it into a form suitable for processing by the second inverter 532, and the second inverter 532 further processes the signal, thereby realizing signal shaping and amplification through two signal inversions to provide a more stable and reliable output signal; therefore, the first inverter 531 and the second inverter 532 are preferably composed of MOS tubes, which can not only realize the signal shaping and signal amplification functions, but also play the role of buffering, isolation and impedance matching during the signal transmission process.

[0096] Furthermore, the high bandwidth source follower 2 includes a MOS tube M27, a capacitor CL, a current mirror circuit 21 and a bias constant current source 22; the gate of the MOS tube M27 is used as the input end of the high bandwidth source follower 2, and the source of the MOS tube M27 is used as the output end of the high bandwidth source follower 2;

[0097] The control end of the current mirror circuit 21 is electrically connected to the output end of the bias constant current source 22, the first end of the current mirror circuit 21 is electrically connected to the drain of the MOS tube M27, the second end of the current mirror circuit 21 and one end of the capacitor CL are electrically connected to the source of the MOS tube M27, and the other end of the capacitor CL is grounded.

[0098] In this embodiment, Figure 4 As shown, in order to utilize the large bandwidth characteristics of the large bandwidth source follower 2 and shorten the linear establishment time, so that the LDO can maintain the output voltage stable while accelerating the response speed of the output voltage, a closed-loop current mirror circuit 21 is provided between the drain and source of the MOS tube M27, so that the current mirror circuit 21 can effectively increase the small signal output impedance of the MOS tube M27 when the bias constant current source 22 provides a bias voltage, thereby having a larger bandwidth and making its intrinsic gain much greater than 1.

[0099] The current mirror circuit 21 may specifically be:

[0100] The current mirror circuit 21 includes a MOS tube M28, a MOS tube M29, a MOS tube M30, a MOS tube M31, a MOS tube M32 and a MOS tube M33; the drain of the MOS tube M30 is used as a control end of the current mirror circuit 21, the drain of the MOS tube M29 is used as a first end of the current mirror circuit 21, and the drain of the MOS tube M28 is used as a second end of the current mirror circuit 21; the drain and the gate of the MOS tube M29 are electrically connected to the gate of the MOS tube M30, the drain and the gate of the MOS tube M31 are electrically connected to the drain of the MOS tube M30, the drain and the gate of the MOS tube M33 are electrically connected to the drain of the MOS tube M32, the gate of the MOS tube M33 is electrically connected to the gate of the MOS tube M28, the source of the MOS tube M29, the source of the MOS tube M30, the source of the MOS tube M31 and the source of the MOS tube M32 are all connected to the VDD power supply, and the source of the MOS tube M28 and the source of the MOS tube M33 are both grounded.

[0101] The current mirror circuit 21 formed by the MOS transistor M28, the MOS transistor M29, the MOS transistor M30, the MOS transistor M31, the MOS transistor M32 and the MOS transistor M33 can have the following effects:

[0102] The open-loop conductance of the current from node 1 to node 2 is: Wherein, C1 represents the parasitic capacitance of the MOS tube M33, im2 is the current of the input MOS tube M28, gm2 is the transconductance of the MOS tube M28, gm4 is the transconductance of the MOS tube M30, gm5 is the transconductance of the MOS tube M31, gm6 is the transconductance of the MOS tube M32, and gm7 is the transconductance of the MOS tube M33. If Vin is a small signal voltage, im2 is the small signal current of the input MOS tube M28, if Vin is positive, then im2 increases; if Vin is negative, then im2 decreases; thus, the bidirectional voltage conversion rate of the source follower is improved.

[0103] The high-bandwidth source follower 2 uses current feedback to increase the conversion rate. The two main poles that affect the gain of the source follower are located at the output terminal Vout and the drain of the MOS tube M7. The closed-loop gain of the source follower is: Wherein gm1 is the transconductance of the MOS tube M27, gm3 is the transconductance of the MOS tube M29, and CL represents the capacitor CL.

[0104] And the main pole of the large bandwidth source follower 2 is also determined by its output point (Vout), so the bandwidth of the large bandwidth source follower 2 can be obtained as: Where CL is the capacitance value of capacitor CL. The bandwidth of the current source follower can be obtained by Figure 1 The analysis shows: Therefore, compared with the two, the bandwidth of the large bandwidth source follower 2 is the bandwidth of the current source follower. It is obvious that the bandwidth of the large-bandwidth source follower 2 is many times that of the current source follower, which greatly shortens the linear settling time.

[0105] Therefore, through the analysis of the current mirror circuit 21, it can be known that the bandwidth of the large bandwidth source follower 2 can be obtained by the formula: Calculated, so that source followers with different bandwidths can be selected according to actual needs.

[0106] The bias constant current source 22 may specifically be:

[0107] The bias constant current source 22 includes a current source A2, a MOS tube M34 and a MOS tube M35; the drain of the MOS tube M34 is used as the output end of the bias constant current source 22; the drain and the gate of the MOS tube M34 are electrically connected to the gate of the MOS tube M35, the source of the MOS tube M34 and the source of the MOS tube M35 are grounded, and the drain of the MOS tube M35 is electrically connected to the output end of the current source A2; the bias voltage signal quality generated by the bias constant current source composed of the MOS tube and the current source A2 is better.

[0108] Other structures and operations of a fast response LDO with overcurrent protection according to an embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0109] In the description of this specification, the description with reference to the terms "embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0110] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A fast response LDO with overcurrent protection, characterized by: It includes a bias circuit, a wide bandwidth source follower, a reference circuit, a voltage regulator D1, an operational amplifier circuit, a filter circuit and an overcurrent protection circuit; the output end of the filter circuit is used as the output end of the fast response LDO; The output end of the bias circuit and the cathode of the voltage regulator D1 are both electrically connected to the input end of the wide bandwidth source follower, the output end of the wide bandwidth source follower is electrically connected to the input end of the reference circuit, the output end of the reference circuit is electrically connected to the input end of the overcurrent protection circuit, the output end of the overcurrent protection circuit is electrically connected to the input end of the operational amplifier circuit, the output end of the operational amplifier circuit is electrically connected to the input end of the filter circuit, and the anode of the voltage regulator D1 is grounded; The overcurrent protection circuit includes a comparator bias unit, a comparator unit, a trigger unit, a drive unit, a MOS tube M9, a MOS tube M10 and a MOS tube N6; the input end of the comparator unit is used as the input end of the overcurrent protection circuit, and the output end of the drive unit is used as the output end of the overcurrent protection circuit; The gate of the MOS tube M9, the output end of the comparator bias unit and the bias end of the comparator unit are electrically connected, the output end of the comparator unit and the input end of the trigger unit are electrically connected, the VDD end of the comparator bias unit, the VDD end of the comparator unit and the source of the MOS tube M9 are all connected to the VDD power supply, the gate of the MOS tube M9 and the gate of the MOS tube M10 are electrically connected, the drain of the MOS tube M9 and the source of the MOS tube M10 are both electrically connected to the VDD end of the driving unit, the output end of the trigger unit and the gate of the MOS tube N6 are electrically connected, the source of the MOS tube N6 and the ground end of the driving unit are both grounded, and the drain of the MOS tube N6 and the drain of the MOS tube M10 are both electrically connected to the input end of the driving unit; The comparator bias unit is used to generate a comparator bias voltage to turn on the MOS tube M9 and the MOS tube M10; The comparison unit is used to receive the comparator bias voltage and the reference signal generated by the reference circuit, and when the voltage of the reference signal is greater than the comparator bias voltage, the trigger unit is driven to turn on the MOS tube N6 and turn off the driving unit.

2. A fast response LDO with overcurrent protection according to claim 1, characterized in that: The comparison unit includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8, a MOS tube N4, a MOS tube N5, a resistor R2, a resistor R3 and a diode D2; the gate of the MOS tube M6 is used as the input end of the comparison unit, the gates of the MOS tube M5 and the MOS tube M8 are used as the bias end of the comparison unit, the source of the MOS tube M5 and the source of the MOS tube M8 are used as the VDD end of the comparison unit, and the source of the MOS tube N5 is used as the output end of the comparison unit; The source of the MOS tube M6 and the source of the MOS tube M7 are electrically connected to the drain of the MOS tube M5, the drain of the MOS tube M6, the drain of the MOS tube N4, and the gate of the MOS tube N4 are electrically connected to the gate of the MOS tube N5, the drain of the MOS tube N5 is electrically connected to the drain of the MOS tube M7, the gate of the MOS tube M7 and one end of the resistor R2 are electrically connected to one end of the resistor R3, the anode of the diode D2, the other end of the resistor R3, the source of the MOS tube N4, and the source of the MOS tube N5 are grounded, and the other end of the resistor R2 and the cathode of the diode D2 are electrically connected to the drain of the MOS tube M8.

3. A fast response LDO with overcurrent protection according to claim 1, characterized in that: The comparator bias unit includes MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube N1, MOS tube N2, MOS tube N3 and resistor R1; the source electrodes of the MOS tube M1, the MOS tube M2 and the MOS tube M3 are all used as the VDD terminal of the comparator bias unit, and the gate electrode of the MOS tube M3 is used as the output terminal of the comparator bias unit; The gate and drain of the MOS tube M1 are electrically connected to one end of the resistor R1, the other end of the resistor R1 and the gate of the MOS tube M4 are electrically connected to the drain of the MOS tube N3, the gate of the MOS tube M3, the drain of the MOS tube N1, the gate of the MOS tube M2, and the drain of the MOS tube M2 are electrically connected to the source of the MOS tube M4, the gate of the MOS tube N3, the gate of the MOS tube N1, the gate of the MOS tube N2, and the drain of the MOS tube N2 are electrically connected to the drain of the MOS tube M3, and the drain of the MOS tube M4, the source of the MOS tube N1, the source of the MOS tube N2, and the source of the MOS tube N3 are grounded.

4. The fast response LDO with overcurrent protection according to claim 1, characterized in that: The trigger unit includes MOS tube M13, MOS tube M14, MOS tube N9, MOS tube N10, MOS tube M15, MOS tube N11, MOS tube N12, MOS tube M37, resistor R4 and resistor R5; the gate of the MOS tube M14 is used as the input end of the trigger unit, and the drain of the MOS tube M37 is used as the output end of the trigger unit; The source of the MOS tube M13 is connected to the VDD power supply, the drain of the MOS tube M13 and the source of the MOS tube M14 are electrically connected to the source of the MOS tube M15, the drain of the MOS tube M15 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is grounded, the gate of the MOS tube M13, the gate of the MOS tube M14, and the gate of the MOS tube N9 are electrically connected to the gate of the MOS tube N10, the gate of the MOS tube M37, the gate of the MOS tube N12, the gate of the MOS tube M15, the gate of the MOS tube N10 are electrically connected to the gate of the MOS tube N11, and the gate of the MOS tube M37, the gate of the MOS tube N12, the gate of the MOS tube M15, the gate of the MOS tube N11 are electrically connected to the gate of the MOS tube N12. The gate of the MOS tube N11 and the drain of the MOS tube M14 are electrically connected to the drain of the MOS tube N9, the source of the MOS tube N10 is grounded, the drain of the MOS tube N10 and the source of the MOS tube N9 are electrically connected to the source of the MOS tube N11, the drain of the MOS tube N11 is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the VDD power supply, the source of the MOS tube M37 is connected to the VDD power supply, the source of the MOS tube N12 is grounded, and the drain of the MOS tube M37 is electrically connected to the drain of the MOS tube N12.

5. The fast response LDO with overcurrent protection according to claim 1, characterized in that: The driving unit includes a MOS tube M11, a MOS tube M12, a MOS tube N7 and a MOS tube N8; the gate of the MOS tube M11 is used as the input end of the driving unit, the drain of the MOS tube M12 is used as the output end of the driving unit, the source of the MOS tube M11 and the source of the MOS tube M12 are both used as the VDD end of the driving unit, and the source of the MOS tube N7 and the source of the MOS tube N8 are both used as the ground end of the driving unit; The gate of the MOS tube M11 is electrically connected to the gate of the MOS tube N7, the drain of the MOS tube M11, the drain of the MOS tube N7, and the gate of the MOS tube M12 are all electrically connected to the gate of the MOS tube N8, and the drain of the MOS tube M12 is electrically connected to the drain of the MOS tube N8.

6. A fast response LDO with overcurrent protection according to claim 1, characterized in that: The filter circuit comprises a frequency band filter unit, a first shaping filter unit and a second shaping filter unit; the input end of the frequency band filter unit is used as the input end of the filter circuit, the output end of the frequency band filter unit is electrically connected to the input end of the first shaping filter unit, the output end of the first shaping filter unit is electrically connected to the input end of the second shaping filter unit, and the output end of the second shaping filter unit is used as the output end of the filter circuit; The frequency band filtering unit is used to set a cutoff frequency to filter out non-output signal frequency bands; The first shaping filter unit is used to filter out noise and interference of the signal; The second shaping and filtering unit is used for signal waveform shaping and signal amplification.

7. A fast response LDO with overcurrent protection according to claim 6, characterized in that: The frequency band filtering unit comprises a response speed setting circuit and a frequency band filter; the input end of the response speed setting circuit is used as the input end of the frequency band filtering unit, the output end of the response speed setting circuit is electrically connected to the input end of the frequency band filter, and the output end of the frequency band filter is used as the output end of the frequency band filtering unit; The response speed setting circuit is used to set the conduction time of the frequency band filter; The response speed setting circuit includes a MOS tube M15 and a MOS tube M16; the gate of the MOS tube M15 is used as the input end of the response speed setting circuit, and the drain of the MOS tube M15 is used as the output end of the response speed setting circuit; The source of the MOS tube M15 is connected to the VDD power supply, the gate of the MOS tube M15 is electrically connected to the gate of the MOS tube M16, the drain of the MOS tube M15 is electrically connected to the drain of the MOS tube M16, and the source of the MOS tube M16 is grounded; The frequency band filter comprises a resistor R and a capacitor C, one end of the resistor R is used as an input end of the frequency band filter, the other end of the resistor R is used as an output end of the frequency band filter, the other end of the resistor R is electrically connected to one end of the capacitor C, and the other end of the capacitor C is grounded; The resistor R includes at least two sub-resistors R6, one end of the first sub-resistor R6 is used as one end of the resistor R, and the other end of the last sub-resistor R6 is used as the other end of the resistor R; the other end of the first sub-resistor R6 is electrically connected to one end of the last sub-resistor R6; The capacitor C includes at least two sub-capacitors C1 , one end of each sub-capacitor C1 is used as one end of the capacitor C, and the other end of each sub-capacitor C1 is used as the other end of the capacitor C.

8. The fast response LDO with overcurrent protection according to claim 6, characterized in that: The first shaping filter unit includes a MOS tube M17, a MOS tube M18, a MOS tube M19, a MOS tube M20, a MOS tube M21, a MOS tube M22, a resistor R7 and a resistor R8; the gate of the MOS tube M18 is used as the input end of the first shaping filter unit, and the gate of the MOS tube M21 is used as the output end of the first shaping filter unit; The source of the MOS tube M17 and the source of the MOS tube M21 are both connected to the VDD power supply, the drain of the MOS tube M17 and the source of the MOS tube M18 are both electrically connected to the source of the MOS tube M21, the drain of the MOS tube M21 is electrically connected to one end of the resistor R7, the other end of the resistor R7 is grounded, the gate of the MOS tube M17, the gate of the MOS tube M18, and the gate of the MOS tube M19 are all electrically connected to the gate of the MOS tube M20 The drain of the MOS tube M18 is electrically connected to the drain of the MOS tube M19, the source of the MOS tube M20 and the source of the MOS tube M22 are both grounded, the drain of the MOS tube M20 and the source of the MOS tube M19 are both electrically connected to the source of the MOS tube M22, the drain of the MOS tube M22 is electrically connected to one end of the resistor R8, the other end of the resistor R8 is grounded, and the gate of the MOS tube M21 is electrically connected to the gate of the MOS tube M22.

9. The fast response LDO with overcurrent protection according to claim 6, characterized in that: The second shaping filter unit includes a MOS tube M23, a MOS tube M24, a MOS tube M25 and a MOS tube M26; the gate of the MOS tube M23 is used as the input end of the second shaping filter unit, and the drain of the MOS tube M25 is used as the output end of the second shaping filter unit; The gate of the MOS tube M23 is electrically connected to the gate of the MOS tube M24, the source of the MOS tube M23 is connected to the VDD power supply, the drain of the MOS tube M23 is electrically connected to the drain of the MOS tube M24, and the source of the MOS tube M24 is grounded; The gate of the MOS tube M25 is electrically connected to the gate of the MOS tube M26, the source of the MOS tube M25 is connected to the VDD power supply, the drain of the MOS tube M25 is electrically connected to the drain of the MOS tube M26, and the source of the MOS tube M26 is grounded.

10. The fast response LDO with overcurrent protection according to claim 1, characterized in that: The high-bandwidth source follower includes a MOS tube M27, a capacitor CL, a current mirror circuit and a bias constant current source; the gate of the MOS tube M27 is used as the input end of the high-bandwidth source follower, and the source of the MOS tube M27 is used as the output end of the high-bandwidth source follower; The control end of the current mirror circuit is electrically connected to the output end of the bias constant current source, the first end of the current mirror circuit is electrically connected to the drain of the MOS tube M27, the second end of the current mirror circuit and one end of the capacitor CL are both electrically connected to the source of the MOS tube M27, and the other end of the capacitor CL is grounded.

Images