A high-precision reference voltage circuit

Abstract

The present invention proposes a high-precision reference voltage circuit, which includes a process compensation circuit, a nonlinear elimination circuit and a voltage generating circuit. The process compensation circuit is connected to the voltage generating circuit, and the process compensation circuit outputs a process compensation current to the voltage generating circuit to compensate for the output voltage deviation of the voltage generating circuit caused by the process angle, thereby improving the accuracy of the system output reference voltage. The nonlinear elimination circuit is connected to the voltage generating circuit, and the nonlinear elimination circuit outputs a nonlinear elimination current to the voltage generating circuit to eliminate the nonlinear characteristics of each branch current in the voltage generating circuit, thereby enabling the voltage generating circuit to generate a reference voltage with a lower temperature coefficient.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-precision reference voltage circuit. Background Art

[0002] During the operation of integrated circuits, it is often necessary for related circuits to provide accurate and stable reference voltages as a standard for judging the working status of the circuit. In the process of generating reference voltages, due to the influence of process angles, there is a large deviation between the output reference voltage and the set value, which seriously affects the working performance of the reference voltage application circuit. In addition, the generation of reference voltage is also affected by the nonlinear characteristics of the related branch currents, and its temperature coefficient is difficult to reduce to below 12ppm / C°, which cannot meet the application requirements of related high-precision integrated circuits. Summary of the invention

[0003] The problem solved by the present invention is to propose a high-precision reference voltage circuit. By performing process compensation on the circuit and eliminating the nonlinearity of branch current, the reference voltage output by the present invention has higher precision and lower temperature coefficient.

[0004] In order to solve the above problems, the present invention provides a high-precision reference voltage circuit including a process compensation circuit, a nonlinear elimination circuit and a voltage generation circuit.

[0005] The process compensation circuit is connected to the voltage generating circuit. The process compensation circuit outputs a process compensation current Ixta to the voltage generating circuit to compensate for the output voltage deviation of the voltage generating circuit caused by the process angle, thereby improving the accuracy of the system output reference voltage.

[0006] The nonlinear elimination circuit is connected to the voltage generating circuit, and the nonlinear elimination circuit outputs a nonlinear elimination current Itcm to the voltage generating circuit to eliminate the nonlinear characteristics of each branch current in the voltage generating circuit, thereby enabling the voltage generating circuit to generate a reference voltage Vbr with a lower temperature coefficient.

[0007] The process compensation circuit includes a port GZDR and a port XTDK.

[0008] The nonlinear elimination circuit includes a port GZDI and a port SBBC.

[0009] The voltage generating circuit includes a port TRIM, a port COMT and a port VCN.

[0010] The port GZDR receives the operating current Iat provided by the peripheral circuit.

[0011] The port XTDK is connected to the port TRIM to transmit the process compensation current Ixta.

[0012] The port GZDI receives a constant current Itn provided by a peripheral circuit.

[0013] The port SBBC is connected to the port COMT and transmits the nonlinear elimination current Itcm.

[0014] The port VCN outputs a reference voltage Vbr.

[0015] The process compensation circuit includes a current adjustment circuit and a conversion output circuit.

[0016] The current adjustment circuit is connected to the conversion output circuit, which receives the working circuit input from the peripheral circuit, scales it down and transmits it to the conversion output circuit. The conversion output circuit generates a process compensation current according to the process compensation requirements and outputs it to the voltage generation circuit.

[0017] The nonlinear elimination circuit comprises a constant current circuit, a proportional current circuit and a current output stage circuit.

[0018] The constant current circuit is connected to the proportional current circuit, and the nonlinear elimination current Iceon is generated on the resistor R2 through the collector-emitter voltage difference of the transistor Q9 and the transistor Q13 in the two circuits. The proportional current circuit is connected to the current output stage circuit, and the current output stage circuit receives the current Iceon output by the proportional current circuit and amplifies it for output.

[0019] The voltage generating circuit includes a feedback stabilization circuit and a synthesis circuit.

[0020] The feedback stabilization circuit is connected to the synthesis circuit, and the feedback stabilization circuit forms a feedback loop of the synthesis circuit, so that the voltage of the key nodes in the synthesis circuit remains constant. The synthesis circuit receives the process compensation current Ixta and the nonlinear elimination current Itcm, and generates a precise and stable reference voltage Vbr and outputs it through the corresponding port.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention proposes a high-precision reference voltage circuit including a process compensation circuit, a nonlinear elimination circuit and a voltage generating circuit. Through the connection between the process compensation circuit and the voltage generating circuit, the process compensation circuit outputs a process compensation current to the voltage generating circuit, compensating for the output voltage deviation of the voltage generating circuit caused by the process angle, thereby improving the accuracy of the system output reference voltage. Through the connection between the nonlinear elimination circuit and the voltage generating circuit, the nonlinear elimination circuit outputs a nonlinear elimination current to the voltage generating circuit, eliminating the nonlinear characteristics of each branch current in the voltage generating circuit, thereby enabling the voltage generating circuit to generate a reference voltage with a lower temperature coefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0023] Figure 2 It is a schematic diagram of the principle structure of the process compensation circuit of the present invention;

[0024] Figure 3 It is a schematic diagram of the principle structure of the nonlinear elimination circuit of the present invention;

[0025] Figure 4 It is a schematic diagram of the principle structure of the voltage generating circuit of the present invention.

[0026] Description of reference numerals:

[0027] 1-process compensation circuit; 2-nonlinear elimination circuit; 3-voltage generation circuit; 11-current adjustment circuit; 12-conversion output circuit; 21-constant current circuit; 22-direct proportional current circuit; 23-current output stage circuit; 31-feedback stabilization circuit; 32-synthesis circuit. DETAILED DESCRIPTION

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] like Figure 1 As shown, a high-precision reference voltage circuit includes a process compensation circuit 1, a nonlinear elimination circuit 2 and a voltage generation circuit 3.

[0030] The process compensation circuit 1 is connected to the voltage generating circuit 3, and the process compensation circuit 1 outputs the process compensation current Ixta to the voltage generating circuit 3 to compensate for the output voltage deviation of the voltage generating circuit 3 caused by the process angle, thereby improving the accuracy of the system output reference voltage. The nonlinear elimination circuit 2 is connected to the voltage generating circuit 3, and the nonlinear elimination circuit 2 outputs the nonlinear elimination current Itcm to the voltage generating circuit 3 to eliminate the nonlinear characteristics of each branch current in the voltage generating circuit 3, thereby enabling the voltage generating circuit 3 to generate a reference voltage Vbr with a lower temperature coefficient.

[0031] The process compensation circuit 1 includes a port GZDR and a port XTDK. The nonlinear elimination circuit 2 includes a port GZDI and a port SBBC. The voltage generation circuit 3 includes a port TRIM, a port COMT and a port VCN.

[0032] Port GZDR receives the working current Iat provided by the peripheral circuit. Port XTDK is connected to port TRIM to transmit the process compensation current Ixta. Port GZDI receives the constant current Itn provided by the peripheral circuit. Port SBBC is connected to port COMT to transmit the nonlinear elimination current Itcm. Port VCN outputs the reference voltage Vbr.

[0033] like Figure 1As shown, the process compensation circuit 1 includes a current adjustment circuit 11 and a conversion output circuit 12 .

[0034] The current adjustment circuit 11 is connected to the conversion output circuit 12. The current adjustment circuit 11 receives the working circuit input from the peripheral circuit, scales it down and transmits it to the conversion output circuit 12. The conversion output circuit 12 generates a process compensation current according to the process compensation requirements and outputs it to the voltage generation circuit 3.

[0035] like Figure 1 As shown, the nonlinear elimination circuit 2 includes a constant current circuit 21, a proportional current circuit 22 and a current output stage circuit 23.

[0036] The constant current circuit 21 is connected to the proportional current circuit 22. The nonlinear elimination current Iceon is generated on the resistor R2 through the collector-emitter voltage difference of the transistor Q9 and the transistor Q13 in the two circuits. The proportional current circuit 22 is connected to the current output stage circuit 23. The current output stage circuit 23 receives the current Iceon output by the proportional current circuit 22 and amplifies it for output.

[0037] like Figure 1 As shown, the voltage generating circuit 3 includes a feedback stabilization circuit 31 and a synthesis circuit 32 .

[0038] The feedback stabilization circuit 31 is connected to the synthesis circuit 32, and the feedback stabilization circuit 31 forms a feedback loop of the synthesis circuit 32, so that the voltage of the key nodes in the synthesis circuit 32 is constant. The synthesis circuit 32 receives the process compensation current Ixta and the nonlinear elimination current Itcm, and generates a precise and stable reference voltage Vbr and outputs it through the corresponding port.

[0039] like Figure 2 As shown, the current regulating circuit 11 includes an input replica circuit 111 and a scale-down circuit 112 .

[0040] The input replica circuit 111 is connected to the scaling-down circuit 112. The input replica circuit 111 receives the operating current inputted from the peripheral circuit through the port, and scales it to the scaling-down circuit 112. The scaling-down circuit 112 scales down the input current according to the influence of the FF process angle on the reference voltage circuit system, and outputs the current that meets the process compensation requirement to the conversion output circuit 12.

[0041] The input replica circuit 111 includes a MOS transistor M1 , a MOS transistor M2 , a MOS transistor M3 , an operational amplifier OP1 , and a port GZDR.

[0042] The source of MOS tube M1 is connected to the power supply VDD, the gate of MOS tube M1 is connected to the gate of MOS tube M2, and the drain of MOS tube M1 is connected to the positive input terminal of operational amplifier OP1. The source of MOS tube M2 is connected to the source of MOS tube M1, the gate of MOS tube M2 is connected to the drain of MOS tube M2, and the drain of MOS tube M2 is connected to the output terminal of operational amplifier OP1. The positive input terminal of operational amplifier OP1 is connected to port GZDR, the inverting input terminal of operational amplifier OP1 is connected to the output terminal of operational amplifier OP1, and the output terminal of operational amplifier OP1 is connected to the gate of MOS tube M3. The source of MOS tube M3 is connected to the source of MOS tube M2, the gate of MOS tube M3 is connected to the gate of MOS tube M2, and the drain of MOS tube M3 is connected to the source of MOS tube M4.

[0043] The scaling down circuit 112 includes a MOS transistor M4 , a MOS transistor M5 , a MOS transistor M6 , a MOS transistor M7 , and an operational amplifier OP2 .

[0044] The source of MOS tube M4 is connected to the drain of MOS tube M3, the gate of MOS tube M4 is connected to the drain of MOS tube M4, and the drain of MOS tube M4 is connected to the source of MOS tube M5. The source of MOS tube M5 is connected to the gate of MOS tube M4, the gate of MOS tube M5 is connected to the gate of MOS tube M7, and the drain of MOS tube M5 is grounded. The source of MOS tube M6 is connected to the source of MOS tube M3, the gate of MOS tube M6 is connected to the gate of MOS tube M3, and the drain of MOS tube M6 is connected to the source of MOS tube M7. The source of MOS tube M7 is connected to the inverting input terminal of operational amplifier OP2, the gate of MOS tube M7 is connected to the output terminal of operational amplifier OP2, and the drain of MOS tube M7 is connected to the collector of triode Q1. The positive input terminal of operational amplifier OP2 is connected to the drain of MOS tube M1, the inverting input terminal of operational amplifier OP2 is connected to the drain of MOS tube M6, and the output terminal of operational amplifier OP2 is connected to the gate of MOS tube M5.

[0045] The current adjustment circuit 11 receives the working current Iat provided by the peripheral circuit through the port GZDR, and copies the current Iat in proportion to the branch where the drain and source of the MOS tube M5 are located through the relevant connection structure of the MOS tube M3, M2 and M1, so as to form the current Iuc. In view of the influence of the FF process angle on the reference voltage circuit system, the relevant circuit connection structure of the MOS tube M5, MOS tube M6 and MOS tube M7 reduces the current Iuc in proportion, so that the processed current Iuc meets the process compensation requirements. The current adjustment circuit 11 outputs the current Ik3, and transmits it to the conversion output circuit 12 through the connection between the drain of the MOS tube M7 and the collector of the transistor Q1. Based on the relevant circuit connection structure of the operational amplifier OP1 and the operational amplifier OP2, the drain voltage of the MOS tube M2 is equal to the drain voltage of the MOS tube M6, and is not affected by the fluctuation of the working power supply voltage VDD, which significantly improves the proportional copy accuracy of the current Iat to the current Ik3.

[0046] like Figure 2 As shown, the conversion output circuit 12 includes an impedance circuit 121 and an operation circuit 122 .

[0047] The impedance circuit 121 is connected to the operation circuit 122, and the impedance circuit 121 accurately copies the received current to the operation circuit 122, and improves the output impedance of the conversion output circuit 12. The operation circuit 122 performs proportional operation adjustment on the input current according to the process compensation requirements, and outputs the process compensation current to the voltage generating circuit 3.

[0048] The impedance circuit 121 includes a transistor Q1 , a transistor Q2 , a transistor Q3 , a transistor Q4 , and a transistor Q5 .

[0049] The collector of transistor Q1 is connected to the drain of MOS tube M7, the base of transistor Q1 is connected to the base of transistor Q4, and the emitter of transistor Q1 is connected to the collector of transistor Q2. The collector of transistor Q2 is connected to the emitter of transistor Q1, the base of transistor Q2 is connected to the base of transistor Q5, and the emitter of transistor Q2 is grounded. The collector of transistor Q3 is connected to the source of MOS tube M8, the base of transistor Q3 is connected to the base of transistor Q1, and the emitter of transistor Q3 is connected to the base of transistor Q2. The collector of transistor Q4 is connected to the drain of MOS tube M8, the base of transistor Q4 is connected to the base of transistor Q3, and the emitter of transistor Q4 is connected to the collector of transistor Q5. The collector of the transistor Q5 is connected to the emitter of the transistor Q4, the base of the transistor Q5 is connected to the emitter of the transistor Q3, and the emitter of the transistor Q5 is grounded.

[0050] The operation circuit 122 includes a MOS transistor M8 , a MOS transistor M9 , a MOS transistor M10 , a MOS transistor MFE, an operational amplifier OP3 , and a port XTDK.

[0051] The source of MOS tube M8 is connected to the power supply VDD, the gate of MOS tube M8 is connected to the gate of MOS tube M9, and the drain of MOS tube M8 is connected to the collector of triode Q4. The source of MOS tube M9 is connected to the source of MOS tube M8, the gate of MOS tube M9 is connected to the drain of MOS tube M8, and the drain of MOS tube M9 is connected to the source of MOS tube M10. The source of MOS tube M10 is connected to the drain of MOS tube M9, the gate of MOS tube M10 is connected to the drain of MOS tube M10, and the drain of MOS tube M10 is connected to the source of MOS tube MFE. The source of MOS tube MFE is connected to the gate of MOS tube M10, the gate of MOS tube MFE is connected to the output end of operational amplifier OP3, and the drain of MOS tube MFE is connected to port XTDK. The positive input end of operational amplifier OP3 is connected to port GZDR, the negative input end of operational amplifier OP3 is connected to the source of MOS tube MFE, and the output end of operational amplifier OP3 is connected to the gate of MOS tube MFE.

[0052] The related circuit connection structure of transistors Q1, Q2, Q3, Q4 and Q5 has the function of accurately proportionally replicating the current Ik3 to the branch where the drain and source of the MOS tube M8 are located, and makes the conversion output circuit 12 have a higher output impedance to improve the current output capacity of the conversion output circuit 12.

[0053] The relevant circuit structure of MOS tube M8, MOS tube M9, MOS tube M10, MOS tube MFE and operational amplifier OP3 performs proportional operation adjustment on current Ik3 and generates process compensation current Ixta in the branch where the drain and source of MOS tube MFE are located. Current Ixta is output to voltage generating circuit 3 through port XTDK.

[0054] The process compensation circuit 1 is mainly used to perform process compensation on the output voltage of the voltage generating circuit 3. Before process compensation is performed, the influence of the FF process angle on the output voltage of the voltage generating circuit 3 is shown in formula (1).

[0055] Vx=Vec-Vag=TC×10 6 ×(T-Ta)×Vsm (1)

[0056] In the formula, Vx is the voltage difference caused by the output voltage of the voltage generating circuit 3 under the FF process angle condition, Vec is the standard voltage that the voltage generating circuit 3 should output, Vag is the actual average voltage output by the voltage generating circuit 3, TC is the output voltage temperature coefficient, T is the ambient temperature, Ta is the reference temperature, and Vsm is the maximum voltage output by the voltage generating circuit 3.

[0057] When the temperature coefficient TC of the output voltage of the voltage generating circuit 3 is determined to be a constant value TCa, the voltage value Vcmp that needs to be compensated for the process can be determined, and its expression is shown in formula (2).

[0058]

[0059] In the formula, Vx is the voltage difference generated by the output voltage of the voltage generating circuit 3 under the FF process angle condition, TCa is the set temperature coefficient value of the output voltage of the voltage generating circuit 3, T is the ambient temperature, Ta is the reference temperature, and Vsm is the maximum voltage output by the voltage generating circuit 3.

[0060] like Figure 3 As shown, the constant current circuit 21 includes a bias operating circuit 211 and a base-emitter voltage circuit 212 .

[0061] The bias working circuit 211 is connected to the base-emitter voltage circuit 212. The bias working circuit 211 provides a bias working current for the transistors in the base-emitter voltage circuit 212, so that the base-emitter voltage circuit 212 generates a collector-emitter voltage Vbe9 that meets the requirements.

[0062] The bias working circuit 211 includes a transistor Q6 , a MOS transistor M11 , and a MOS transistor M13 .

[0063] The emitter of transistor Q6 is connected to the power supply VDD, the base of transistor Q6 is connected to the collector of transistor Q6, and the collector of transistor Q6 is connected to the source of MOS tube M11. The source of MOS tube M11 is connected to the base of transistor Q6, the gate of MOS tube M11 is connected to the drain of MOS tube M12, and the drain of MOS tube M11 is grounded. The drain of MOS tube M13 is connected to the emitter of transistor Q9, the gate of MOS tube M13 is connected to the drain of MOS tube M13, and the source of MOS tube M13 is grounded.

[0064] The base-emitter voltage circuit 212 includes a transistor Q8 , a resistor R1 , a transistor Q9 , and a port GZDI.

[0065] The collector of transistor Q8 is connected to the drain of MOS tube M12, the base of transistor Q8 is connected to the collector of transistor Q9, the emitter of transistor Q8 is connected to the upper end of resistor R1, and the lower end of resistor R1 is grounded. The collector of transistor Q9 is connected to port GZDI, the base of transistor Q9 is connected to the collector of transistor Q11, and the emitter of transistor Q9 is connected to the drain of MOS tube M13.

[0066] The constant current Itn is provided by the peripheral circuit and input into the constant current circuit 21 through the port GZDI. Based on their related circuit connection structures, the transistor Q6, the MOS transistor M11 and the MOS transistor M13 provide bias working conditions for the transistor Q8 and the transistor Q9, so that the transistors Q8 and Q9 both work in the amplification region. Based on the related circuit connection structure of the transistor Q9, the base-emitter voltage Vbe9 of the transistor Q9 acts on both ends of the resistor R2.

[0067] like Figure 3 As shown, the proportional current circuit 22 includes an active load circuit 221 and a voltage difference current circuit 222 .

[0068] The active load circuit 221 is connected to the voltage difference current circuit 222. The active load circuit 221 serves as a load of the voltage difference current circuit 222, so that the voltage difference current circuit 222 has a larger output impedance. The voltage difference current circuit 222 generates a current Iceon that can eliminate nonlinear characteristics based on the voltage difference across the resistor R2.

[0069] The active load circuit 221 includes a transistor Q7 , a transistor Q10 , a MOS transistor M12 , and a MOS transistor M14 .

[0070] The emitter of transistor Q7 is connected to the power supply VDD, the base of transistor Q7 is connected to the base of transistor Q10, and the collector of transistor Q7 is connected to the source of MOS tube M12. The emitter of transistor Q10 is connected to the emitter of transistor Q7, the base of transistor Q10 is connected to the base of transistor Q6, and the collector of transistor Q10 is connected to the source of MOS tube M14. The source of MOS tube M12 is connected to the collector of transistor Q7, the gate of MOS tube M12 is connected to the gate of MOS tube M14, and the drain of MOS tube M12 is connected to the collector of transistor Q8. The source of MOS tube M14 is connected to the collector of transistor Q10, the gate of MOS tube M14 is connected to the gate of MOS tube M11, and the drain of MOS tube M14 is connected to the collector of transistor Q11.

[0071] The voltage-difference current circuit 222 includes a resistor R2 , a transistor Q11 , and a transistor Q13 .

[0072] The upper end of the resistor R2 is connected to the drain of the MOS tube M14, and the lower end of the resistor R2 is connected to the drain of the MOS tube M15. The collector of the transistor Q11 is connected to the upper end of the resistor R2, the base of the transistor Q11 is connected to the base of the transistor Q13, and the emitter of the transistor Q11 is grounded. The collector of the transistor Q13 is connected to the lower end of the resistor R2, the base of the transistor Q13 is connected to the base of the transistor Q9, and the emitter of the transistor Q13 is grounded.

[0073] Based on their related circuit connection structures, transistors Q7, Q10, MOS transistors M12 and M14 act as active loads in the proportional current circuit 22, and maintain the biased working state of transistors Q11 and Q13, so that transistors Q11 and Q13 work in the saturation region. The branch current Ipt where the collector and emitter of transistor Q13 are located has a characteristic of being proportional to the temperature change. Under the action of the base-emitter voltage Vbe9 of transistor Q9, the expression of the current Iceon flowing through resistor R2 is shown in formula (3).

[0074]

[0075] In the formula, Vbe9 is the base-emitter voltage of transistor Q9, Vbe13 is the base-emitter voltage of transistor Q13, K is the Boltzmann constant, T is the ambient temperature, r1 is the resistance of resistor R1, q is the unit charge, r2 is the resistance of resistor R2, and Ta is the reference temperature.

[0076] like Figure 3 As shown, the current output stage circuit 23 includes a voltage stabilizing circuit 231 and an amplifying circuit 232 .

[0077] The voltage stabilizing circuit 231 is connected to the amplifier circuit 232, and the voltage stabilizing circuit 231 provides a stable working voltage for the amplifier circuit 232. The amplifier circuit 232 receives the current Iceon, amplifies it, and outputs it to the voltage generating circuit 3.

[0078] The voltage stabilizing circuit 231 includes a transistor Q12, a transistor Q14, a MOS transistor M15, and a MOS transistor M16.

[0079] The emitter of transistor Q12 is connected to the power supply VDD, the base of transistor Q12 is connected to the base of transistor Q14, and the collector of transistor Q12 is connected to the source of MOS tube M15. The emitter of transistor Q14 is connected to the emitter of transistor Q12, the base of transistor Q14 is connected to the base of transistor Q10, and the collector of transistor Q14 is connected to the source of MOS tube M16. The source of MOS tube M15 is connected to the collector of transistor Q12, the gate of MOS tube M15 is connected to the gate of MOS tube M16, and the drain of MOS tube M15 is connected to the collector of transistor Q13. The source of MOS tube M16 is connected to the collector of transistor Q14, the gate of MOS tube M16 is connected to the gate of MOS tube M14, and the drain of MOS tube M16 is connected to the collector of transistor Q15.

[0080] The amplifier circuit 232 includes a transistor Q15, a resistor R3, and a port SBBC.

[0081] The collector of the transistor Q15 is connected to the port SBBC, the base of the transistor Q15 is connected to the collector of the transistor Q13, the emitter of the transistor Q15 is connected to the upper end of the resistor R3, and the lower end of the resistor R3 is grounded.

[0082] The circuit connection structure of transistor Q12, transistor Q14, MOS transistor 15 and MOS transistor 16 makes the drain voltage of MOS transistor M15 equal to the drain voltage of MOS transistor M16 and is not affected by power supply fluctuation. Transistor Q15 receives current Iceon through the base, and amplifies current Iceon to current Itcm based on the negative feedback of resistor R3, current Itcm=2Iceon. Current Itcm is output to voltage generating circuit 3 through port SBBC.

[0083] like Figure 4 As shown, the feedback stabilization circuit 31 includes a bias condition circuit 311 and a node constant voltage circuit 312 .

[0084] The bias condition circuit 311 is connected to the node constant voltage circuit 312, and the bias condition circuit 311 provides bias working conditions for the node constant voltage circuit 312. The node constant voltage circuit 312 forms a feedback loop of the synthesis circuit 32 based on its connection structure, and keeps the voltage of the key node in the synthesis circuit 32 constant.

[0085] The bias condition circuit 311 includes a MOS transistor M17 , a MOS transistor M19 , and a MOS transistor M18 .

[0086] The source of MOS tube M17 is connected to the power supply VDD, the gate of MOS tube M17 is connected to the gate of MOS tube M19, and the drain of MOS tube M17 is connected to the collector of transistor Q16. The source of MOS tube M19 is connected to the source of MOS tube M17, the gate of MOS tube M19 is connected to the drain of MOS tube M17, and the drain of MOS tube M19 is connected to the collector of transistor Q18. The drain of MOS tube M18 is connected to the emitter of transistor Q17, the gate of MOS tube M18 is connected to the drain of MOS tube M18, and the source of MOS tube M18 is grounded.

[0087] The node constant voltage circuit 312 includes a transistor Q16 , a transistor Q17 , a transistor Q18 , and a MOS transistor M20 .

[0088] The collector of transistor Q16 is connected to the gate of MOS tube M17, the base of transistor Q16 is connected to the collector of transistor Q19, and the emitter of transistor Q16 is connected to the emitter of transistor Q17. The collector of transistor Q17 is connected to the collector of MOS tube M16, the base of transistor Q17 is connected to the collector of transistor Q20, and the emitter of transistor Q17 is connected to the emitter of transistor Q18. The collector of transistor Q18 is connected to the drain of MOS tube M19, the base of transistor Q18 is connected to the base of transistor Q19, and the emitter of transistor Q18 is connected to the emitter of transistor Q17. The source of MOS tube M20 is connected to the source of MOS tube M19, the gate of MOS tube M20 is connected to the drain of MOS tube M19, and the drain of MOS tube M20 is connected to the upper end of resistor R7.

[0089] Based on their related circuit connection structures, MOS transistor M17, MOS transistor M18 and MOS transistor M19 provide bias working conditions for transistor Q16, transistor Q17 and transistor Q18, so that transistor Q16, transistor Q17 and transistor Q18 all work in the amplification region. The base of transistor Q16 is connected to the collector of transistor Q19 in the synthesis circuit 32 to form a node a. The base of transistor Q17 is connected to the collector of transistor Q20 in the synthesis circuit 32 to form a node b. The related circuit connection structures of transistor Q16, transistor Q17, transistor Q18 and MOS transistor 20 form a feedback loop of the synthesis circuit 32, so that the voltage Va at node a and the voltage Vb at node b remain constant.

[0090] like Figure 4 As shown, the synthesis circuit 32 includes a node equivalent circuit 321 and a compensation output circuit 322 .

[0091] The node equivalent circuit 321 is connected to the compensation output circuit 322, and the node equivalent circuit 321 keeps the voltages of the key circuit nodes in the compensation output circuit 322 equal. Under the action of the process compensation current and the nonlinear elimination current, the compensation output circuit 322 generates a high-precision, low temperature coefficient reference voltage output by the system.

[0092] The node equivalent circuit 321 includes a resistor R4, a resistor R7, and an operational amplifier OP4.

[0093] The upper end of the resistor R4 is connected to the upper end of the resistor R7, and the lower end of the resistor R4 is connected to the collector of the transistor Q19. The upper end of the resistor R7 is connected to the drain of the MOS tube M20, and the lower end of the resistor R7 is connected to the collector of the transistor Q20. The positive input end of the operational amplifier OP4 is connected to the collector of the transistor Q20, the negative input end of the operational amplifier OP4 is connected to the collector of the transistor Q19, and the output end of the operational amplifier OP4 is connected to the base of the transistor Q18.

[0094] The compensation output circuit 322 includes a transistor Q19 , a transistor Q20 , a resistor R5 , a resistor R6 , a port TRIM, a port COMT, and a port VCN.

[0095] The collector of transistor Q19 is connected to the base of transistor Q16, the base of transistor Q19 is connected to the base of transistor Q20, and the emitter of transistor Q19 is connected to the upper end of resistor R5. The collector of transistor Q20 is connected to port TRIM, the base of transistor Q20 is connected to port VCN, and the emitter of transistor Q20 is connected to the lower end of resistor R5. The upper end of resistor R5 is connected to the emitter of transistor Q19, and the lower end of resistor R5 is connected to the upper end of resistor R6. The upper end of resistor R6 is connected to port COMT, and the lower end of resistor R6 is grounded.

[0096] The process compensation current Ixta is input to the node b in the synthesis circuit 32 through the port TRIM to increase the base-emitter voltage Vbe20 of the transistor Q20 and eliminate the influence of the FF process corner on the output current accuracy. The non-inverting input terminal of the operational amplifier OP4 is connected to the circuit node b, and the inverting input terminal of the operational amplifier OP4 is connected to the circuit node a. Based on the relevant circuit connection structure and device characteristics of the operational amplifier OP4, the node a voltage Va is kept equal to the node b voltage Vb.

[0097] The connection structure formed by transistor Q19, transistor Q20, resistor R4, resistor R5, resistor R6 and resistor R7 generates a reference voltage Vbr. In the branch where the collector and emitter of transistor Q19 are located, the branch current Isg flows through resistor R5, and the expression of current Isg is shown in formula (4).

[0098]

[0099] In the formula, K is the Boltzmann constant, T is the ambient temperature, q is the unit charge, r5 is the resistance value of the resistor R5, and Mz is the ratio of the transistor Q19 to the transistor Q20.

[0100] The nonlinear elimination current Itcm is input to the connection node of the resistor R6 and the resistor R5 through the port COMT to perform nonlinear elimination on the branch current Isg where the transistor Q19 is located and the branch current Icq where the transistor Q20 is located. Under the premise of the nonlinear elimination of the branch current, the connection node voltage Vbr of the base of the transistor Q19 and the base of the transistor Q20 is used as the reference voltage of the system output and is output through the port VCN. The expression of the reference voltage Vbr is shown in formula (5).

[0101]

[0102] In the formula, Vbe20 is the base-emitter voltage of transistor Q20, K is the Boltzmann constant, T is the ambient temperature, q is the unit charge, r5 is the resistance value of resistor R5, r6 is the resistance value of resistor R6, Mz is the ratio of transistor Q19 to transistor Q20, r2 is the resistance value of resistor R2, and Ta is the reference temperature.

[0103] It can be seen from formula (5) that in the expression of the reference voltage Vbr output by the system, the high-order terms are eliminated, and the system has good linearity and a low temperature coefficient.

Claims

1. A high-precision reference voltage circuit, characterized in that: It comprises a process compensation circuit (1), a nonlinear elimination circuit (2) and a voltage generation circuit (3); The process compensation circuit (1) is connected to the voltage generating circuit (3), and the process compensation circuit (1) outputs a process compensation current Ixta to the voltage generating circuit (3) to compensate for the output voltage deviation of the voltage generating circuit (3) caused by the process angle, thereby improving the accuracy of the system output reference voltage; The nonlinear elimination circuit (2) is connected to the voltage generating circuit (3), and the nonlinear elimination circuit (2) outputs a nonlinear elimination current Itcm to the voltage generating circuit (3), thereby eliminating the nonlinear characteristics of each branch current in the voltage generating circuit (3), thereby enabling the voltage generating circuit (3) to generate a reference voltage Vbr with a lower temperature coefficient.

2. A high-precision reference voltage circuit according to claim 1, characterized in that: The process compensation circuit (1) comprises a current adjustment circuit (11) and a conversion output circuit (12); The current regulating circuit (11) is connected to the conversion output circuit (12), and the current regulating circuit (11) receives the working circuit input from the peripheral circuit, scales it down, and transmits it to the conversion output circuit (12); The conversion output circuit (12) generates a process compensation current according to the process compensation requirement and outputs the current to the voltage generating circuit (3).

3. A high-precision reference voltage circuit according to claim 1, characterized in that: The nonlinear elimination circuit (2) comprises a constant current circuit (21), a proportional current circuit (22) and a current output stage circuit (23); The constant current circuit (21) is connected to the proportional current circuit (22), and a nonlinear elimination current Iceon is generated on the resistor R2 through the collector-emitter voltage difference of the transistor Q9 and the transistor Q13 in the two circuits; The proportional current circuit (22) is connected to the current output stage circuit (23), and the current output stage circuit (23) receives the current Iceon output by the proportional current circuit (22), amplifies it and outputs it.

4. A high-precision reference voltage circuit according to claim 1, characterized in that: The voltage generating circuit (3) comprises a feedback stabilization circuit (31) and a synthesis circuit (32); The feedback stabilization circuit (31) is connected to the synthesis circuit (32), and the feedback stabilization circuit (31) forms a feedback loop of the synthesis circuit (32), so that the voltage of the key node in the synthesis circuit (32) remains constant; The synthesis circuit (32) receives the process compensation current Ixta and the nonlinear elimination current Itcm, and generates a precise and stable reference voltage Vbr for output through a corresponding port.

5. A high-precision reference voltage circuit according to claim 2, characterized in that: The current adjustment circuit (11) comprises an input replica circuit (111) and a scaling-down circuit (112); The input replica circuit (111) is connected to the scale reduction circuit (112), and the input replica circuit (111) receives the operating current input from the peripheral circuit through a port, and copies the current in proportion to the operating current into the scale reduction circuit (112); The scaling-down circuit (112) scales down the input current according to the influence of the FF process angle on the reference voltage circuit system, and outputs a current that meets the process compensation requirements to the conversion output circuit (12).

6. A high-precision reference voltage circuit according to claim 2, characterized in that: The conversion output circuit (12) comprises an impedance circuit (121) and an operation circuit (122); The impedance circuit (121) is connected to the operation circuit (122), and the impedance circuit (121) accurately copies the received current to the operation circuit (122) and increases the output impedance of the conversion output circuit (12); The operation circuit (122) performs proportional operation adjustment on the input current according to the process compensation requirement, and outputs the process compensation current to the voltage generating circuit (3).

7. A high-precision reference voltage circuit according to claim 3, characterized in that: The constant current circuit (21) comprises a bias working circuit (211) and a base-emitter voltage circuit (212); The bias working circuit (211) is connected to the base-emitter voltage circuit (212), and the bias working circuit (211) provides a bias working current for the triode in the base-emitter voltage circuit (212), so that the base-emitter voltage circuit (212) generates a collector-emitter voltage Vbe9 that meets the requirements.

8. A high-precision reference voltage circuit according to claim 3, characterized in that: The proportional current circuit (22) comprises an active load circuit (221) and a voltage difference current circuit (222); The active load circuit (221) is connected to the voltage difference current circuit (222), and the active load circuit (221) serves as a load of the voltage difference current circuit (222), so that the voltage difference current circuit (222) has a relatively large output impedance; The voltage difference current circuit (222) generates a current Iceon that can eliminate nonlinear characteristics based on the voltage difference between the two ends of the resistor R2.

9. A high-precision reference voltage circuit according to claim 4, characterized in that: The feedback stabilization circuit (31) includes a bias condition circuit (311) and a node constant voltage circuit (312); The bias condition circuit (311) is connected to the node constant voltage circuit (312), and the bias condition circuit (311) provides bias working conditions for the node constant voltage circuit (312); The node constant voltage circuit (312) forms a feedback loop of the synthesis circuit (32) based on its connection structure, and keeps the voltage of the key node in the synthesis circuit (32) constant.

10. A high-precision reference voltage circuit according to claim 4, characterized in that: The synthesis circuit (32) includes a node equivalent circuit (321) and a compensation output circuit (322); The node equivalent circuit (321) is connected to the compensation output circuit (322), and the node equivalent circuit (321) keeps the voltages of key circuit nodes in the compensation output circuit (322) equal; The compensation output circuit (322) generates a high-precision, low-temperature-coefficient reference voltage for system output under the action of the process compensation current and the nonlinear elimination current.

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