Sequencing data of memory system

Abstract

The invention relates to serializing data for a memory system. According to examples described herein, a memory system may initialize data optimization operations by transmitting signaling to a host system. For example, the memory system may identify data associated with a non-sequential logical block address (LBA), and may indicate the discontinuous LBA to the host system. In response, the host system may indicate which of the discontinuous LBAs represent sequential data. Accordingly, the memory system may sequentialize one or more of the discontinuous LBAs to recombine the associated data.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 774,439 filed by David Aaron Palmer on July 16, 2024, entitled “SEQUENTIALIZING DATA OF A MEMORY SYSTEM” and U.S. patent application No. 63 / 542,740 filed by David Aaron Palmer on October 5, 2023, entitled “SEQUENTIALIZING DATA OF A MEMORY SYSTEM”, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to serializing data of storage systems. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of external power. Memory cells configured in a volatile configuration lose their stored state when disconnected from the external power source. Summary of the invention

[0006] A memory system is described. The memory system may include: a memory device; and a processing circuit system coupled to the memory device and configured to cause the memory system to: transmit a first request to serialize one or more sets of data stored in a memory cell block, each of the one or more sets of data being associated with a respective logical address range; receive a second request to generate a first set of logical addresses including one or more pairs of logical addresses in response to transmitting the first request, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the memory cell block and including a second logical address associated with a second physical address in the memory cell block, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses; transmit an indication of the first set of logical addresses based at least in part on receiving the second request; receive an indication of a second set of logical addresses in response to transmitting the indication of the first set of logical addresses, wherein the second set of logical addresses includes a subset of the first set of logical addresses; and perform a maintenance operation on the memory cell block to serialize the second set of logical addresses within the memory cell block based at least in part on receiving the indication of the second set of logical addresses.

[0007] A memory system is described. The memory system may include a processing circuit system configured to cause the memory system to: receive a first request to sequentially store one or more sets of data in a block of memory cells, each of the one or more sets of data being associated with a respective logical address range; transmit a second request to generate a first set of logical addresses including one or more pairs of logical addresses based at least in part on receiving the first request, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the block of memory cells and including a second logical address associated with a second physical address in the block of memory cells; receive an indication of the first set of logical addresses based at least in part on transmitting the second request; determine, for a first pair of logical addresses in the first set of logical addresses, whether the data associated with the first logical address of the first pair and the second logical address of the first pair are logically sequential; and transmit an indication of a second set of logical addresses based at least in part on determining that the data associated with the first logical address of the first pair and the second logical address of the first pair are logically sequential, wherein the second set of logical addresses includes a subset of the first set of logical addresses.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium storing code includes instructions that, when executed by one or more processors of a memory system, cause the memory system to: transmit a first request to serialize one or more sets of data stored in a memory cell block, each of the one or more sets of data being associated with a respective logical address range; receive a second request in response to transmitting the first request to generate a first set of logical addresses including one or more pairs of logical addresses, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the memory cell block and including a second logical address associated with a second physical address in the memory cell block, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses; transmit an indication of the first set of logical addresses based at least in part on receiving the second request; receive an indication of a second set of logical addresses in response to transmitting the indication of the first set of logical addresses, wherein the second set of logical addresses includes a subset of the first set of logical addresses; and perform a maintenance operation on the memory cell block to serialize the second set of logical addresses within the memory cell block based at least in part on receiving the indication of the second set of logical addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting serializing data of a memory system according to examples disclosed herein is described.

[0010] Figure 2 An example of a system supporting serializing data of a memory system according to examples disclosed herein is described.

[0011] Figure 3 An example of a process flow supporting serializing data of a memory system according to examples disclosed herein is illustrated.

[0012] Figure 4 A block diagram illustrating a memory system supporting serialization of data of the memory system according to examples disclosed herein.

[0013] Figure 5 A block diagram illustrating a host system supporting serializing data of a memory system according to examples disclosed herein.

[0014] Figure 6 and 7 The description shows a flow chart of one or several methods in support of serializing data of a memory system according to examples disclosed herein. DETAILED DESCRIPTION

[0015] In some cases, data stored to a memory system may be fragmented. For example, a host system may transfer data associated with non-sequential logical block addresses (LBAs) to a memory system, and the memory system may store (e.g., write) the data to sequential physical block addresses (PBAs). Alternatively, a host system may transfer data with sequential LBAs to a memory system, and the memory system may write the data to non-sequential PBAs. Thus, data associated with non-sequential (e.g., non-sequential) LBAs may be written to consecutive (e.g., sequential) PBAs at the memory system. Although conventional host systems may serialize (e.g., reassemble) fragmented data, it may be desirable to identify and serialize fragmented data by a memory system.

[0016] According to the examples described herein, a memory system may initiate a data optimization operation, which may optimize (e.g., serialize) stored data. For example, the memory system may identify data associated with non-sequential LBAs and may indicate the discontinuous LBAs to the host system. In response, the host system may indicate which of the discontinuous LBAs are associated with sequential data (e.g., non-fragmented data, data written to sequential PBAs). Thus, the memory system may serialize the data associated with one or more discontinuous LBAs to reorganize the associated data. In some cases, after the data is serialized, the memory system may perform one or more additional optimizations (e.g., logical to physical (L2P) table compression, granularity adjustment, and the like). By serializing fragmented data, signaling between the memory system and the host system may be reduced and the overall performance of the memory system may be improved, among other advantages.

[0017] In addition to being applied to the memory systems described herein, the techniques for serializing the data of memory systems can generally be implemented to improve the performance of various electronic devices and systems. Some electronic device applications, including games and other high-performance applications, can be associated with relatively high processing requirements while benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve the performance of electronic devices. Implementation of the techniques described herein can improve the performance of electronic devices by improving accessibility to relatively large data sequences, which can reduce read response times and improve user experience, among other benefits.

[0018] First, in reference Figures 1 to 2 Features of the present disclosure are described in the context of a system. Figure 3 These and other features of the present disclosure are described in the context of a process flow of FIG. Figures 4 to 7 The device diagrams and flow diagrams related to data of a sequential memory system are further illustrated and described in the context of the device diagrams and flow diagrams.

[0019] Figure 1An example of a system 100 supporting serializing data of a memory system according to examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device including a memory and a processing device.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0021] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0022] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate (e.g., exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105) via the physical host interface using an associated protocol. Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0023] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicated with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (such as error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (such as logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (such as physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when it is read from or written to the memory device 130, and the data may be used within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0028] although Figure 1 The example of the memory system 110 in has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistance random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLC) when configured to store two bits of information each, triple-level cells (TLC) when configured to store three bits of information each, quad-level cells (QLC) when configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, a plane 165 may refer to a number of group blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0035] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof) but may be erased at a second granularity (e.g., at a block granularity). That is, a page 175 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and a block 170 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell may be erased before it may be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 including the page 175 is erased.

[0036] In some cases, to update some data within a block 170 while leaving other data within the block 170 unchanged, the memory device 130 may copy the unchanged data to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., local controller 135) or the memory system controller 115 may mark or otherwise indicate the data remaining in the old block 170 as invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block 170, for example, due to latency or loss considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0037] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that may be outdated because a newer or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of this data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, trash collection, scrubbing, block scanning, health monitoring, or other or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting until all pages 175 in a block 170 have invalid data before erasing and reusing the block 170, an algorithm called "trash collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Trash collection may refer to a set of media management operations that include, for example: selecting a block 170 containing valid and invalid data; selecting a page 175 in a block containing valid data; copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected page 175 as invalid; and erasing the selected block 170. Thus, the number of blocks 170 that have been erased may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105).

[0039] The system 100 may include any number of non-transitory computer-readable media that support data of a sequential memory system. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0040] According to the examples described herein, the memory system 110 may initiate a data optimization operation, which may optimize (e.g., serialize) the stored data. For example, the memory system 110 may identify data associated with non-sequential LBAs and may indicate the discontinuous LBAs to the host system 105. In response, the host system 105 may indicate which of the discontinuous LBAs are associated with sequential data (e.g., non-fragmented data). Thus, the memory system 110 may serialize the data associated with one or more discontinuous LBAs to reorganize the associated data. In some cases, after the data is serialized, the memory system 110 may perform one or more additional optimizations (e.g., logical to physical (L2P) table compression, adjusting mapping granularity, and the like). By serializing the fragmented data, the signaling between the memory system 110 and the host system 105 may be reduced and the overall performance of the memory system 110 may be improved, among other advantages.

[0041] Figure 2 An example of a system 200 that supports sequential storage system data according to an example disclosed herein is described. The system 200 may implement reference Figure 1 For example, system 200 may include a host system 205 and a memory system 210, which may be referred to as Figure 1 2 is an example of a host system 105 and a memory system 110 described herein. The system 200 may include a memory system 210 operable to communicate with the host system 205 via a memory system controller 215. The memory system controller 215 may be operable to perform operations on the memory system 210 according to signaling (e.g., commands) from the host system 205. In some cases, the memory system controller 215 may be operable to serialize data stored at blocks 240, which may reduce signaling between the memory system 210 and the host system 205 and improve overall performance of the memory system 210, among other advantages.

[0042] The memory system 210 may include a non-volatile memory 220 and a volatile memory 225, which may be referenced Figure 1 1. The nonvolatile memory 220 may include a memory array 230, which may include a block of nonvolatile memory cells (e.g., NAND memory cells). Each memory cell may be addressed by a corresponding PBA. For example, the memory array 230 may include a block 240, which may be a reference Figure 1 1. For example, block 240 may include a first plane 245-a having a first physical block of memory cells and a second plane 245-b having a second physical block of memory cells. The first physical block and the second physical block may be associated with a set of pages 250-a, 250-b, 250-c, and 250-d, which may each be a reference Figure 1175 of the description. Each memory cell of block 240 may include (e.g., store) physical data associated with a respective LBA indicated by host system 205. For example, host system 205 may transmit a set of data having one or more respective LBAs to memory system controller 215, and memory system controller 215 may store the set of data at one or more respective PBAs of block 240. Thus, a set of physical data may be associated with a respective LBA range.

[0043] In some cases, the host system 205 may transfer a set of data associated with one or more non-sequential LBAs, and the memory system controller 215 may store the set of data at one or more sequential PBAs of block 240. Alternatively, the host system 205 may transfer a set of data associated with one or more sequential LBAs, and the memory system controller 215 may store the set of data across the one or more non-sequential PBAs of block 240. Thus, in order to reassemble the set of data stored at block 240, the memory system controller may serialize the associated LBAs within block 240.

[0044] The memory system 210 may exchange signaling with the host system 205 to initiate the serialization process and identify LBAs for serialization. The memory system controller 215 may transmit a first request to the host system 205 to serialize one or more sets of data stored in the block 240-a. In some cases, the memory system controller 215 may transmit the first request based on one or more characteristics of the one or more sets of data stored in the block 240-a. For example, the memory system controller 215 may identify a set of data as data that meets a threshold amount (e.g., a relatively large amount of data). Additionally or alternatively, the memory system controller 215 may identify a set of data (e.g., block 240-a) as infrequently accessed (e.g., static data, cold data, or the like). In some examples, the memory system controller 215 may identify a set of data for serialization based on the type of data stored at the block 240-a (e.g., a media file, including pictures, music, videos, or the like).

[0045] In some cases, the first request may be transmitted via one or more signals, which may be transmitted via one or more data paths. For example, the memory system controller 215 may indicate to the host system 205 an abnormal condition for serializing the block 240-a. In response, the host system 205 may transmit signaling requesting additional information associated with the abnormal condition to evaluate whether to serialize the block 240-a. Thus, the memory system controller 215 may transmit additional condition information associated with the abnormal condition based on receiving the signaling from the host system 205. In some examples, the memory system controller 215 may additionally transmit an acknowledgment message (e.g., ACK) to indicate that the transmission of the additional condition information has been completed. Based on the abnormal condition indication, the additional condition information, or both, the host system 205 may determine whether to initiate the serialization process of the block 240-a.

[0046] If the host system 205 determines to initiate the serialization process, the host system 205 may transmit additional signaling (eg, a second request) to the memory system 210. For example, the second request may be a request for the memory system controller 215 to generate a first set of candidate LBAs for the host system 205 to evaluate (eg, analyze).

[0047] To generate the first set of candidate LBAs, the memory system controller 215 may access block 240-a to identify data associated with non-sequential LBAs and sequential PBAs. In some examples, the memory system controller 215 may identify pairs of non-sequential LBAs. For example, each pair may include a first LBA (e.g., LBA 3) associated with a first PBA of block 240-a and a second LBA (e.g., LBA 100) associated with an adjacent PBA of block 240-a, as illustrated by block 240-a. In addition, the first LBA may be associated with a first set of sequential LBAs (e.g., LBA 0 to LBA 3) associated with a first PBA range (e.g., Range 1), and the second LBA may be associated with a second set of sequential LBAs (e.g., LBA 100 to LBA 105) at a second PBA range (e.g., Range 2). In some cases, the memory system controller 215 may construct (e.g., compile) a first set (e.g., a list) of candidate LBAs using identified non-sequential LBA pairs (e.g., (LBA 3, LBA 100), (LBA 105, LBA 33), (LBA 36, LBA 4), (LBA 7, LBA 250), (LBA 254, 410), (LBA 412, LBA9), (LBA 9, LBA 413), or the like).

[0048] In response to the second request, the memory system controller 215 may transmit a first indication of the first set of candidate LBAs to the host system 205. In some cases, the indication may include the first set of candidate LBAs. In other examples, the first indication may include multiple indications that each represent a corresponding LBA pair, a corresponding LBA, or the like. In some cases, the first indication may be transmitted via multiple signals. For example, after transmitting the first set of candidate LBAs, the memory system controller 215 may transmit a confirmation signal to the host system 205. The confirmation message may indicate that the second request (e.g., command) from the host system 205 has been completed.

[0049] Based on the second indication, the host system 205 may determine whether one or more LBAs (e.g., one or more pairs of non-sequential LBAs) in the first set of candidate LBAs are associated with sequential data. Sequential data may be an ordered (e.g., non-random) sequence of data. In some examples, the sequence of data may be associated with certain types of files or data (e.g., media files, pictures, music, videos, or the like). Specifically, for a first pair of non-sequential LBAs associated with sequential data, the sequential data may include a first ordered sequence of data (e.g., bits) for the first LBA and a second ordered sequence of data for the second LBA. If the first ordered sequence and the second ordered sequence represent contiguous portions of the media file, the host system 205 may determine that the first pair of non-sequential LBAs are associated with sequential data. For example, the first pair of LBAs may be associated with a set of sequential data written to the sequential PBAs of block 240-a. Therefore, although the first pair of LBAs is non-sequential (e.g., LBA 7 and LBA 250), the associated data of the LBA pair may be sequential. For example, a data group stored at range 4 of block 240-a and a data group stored at range 5 of block 240-a may be sequential subsets of the same data group. Therefore, the host system 205 may determine that the first pair of LBAs does not require additional serialization.

[0050] Additionally or alternatively, the host system 205 may identify one or more LBAs (e.g., one or more pairs of LBAs) in the first set of candidate LBAs that are associated with non-sequential data. For example, the second pair of LBAs may be associated with a set of non-sequential data written to sequential PBAs (e.g., adjacent memory cells) of block 240-a. Thus, both the LBA pair (e.g., LBA 3 and LBA 100) and the associated data may be non-sequential. Thus, the host system 205 may determine that the second pair of LBAs and the associated sequential set of LBAs (e.g., LBA 0 to LBA 3 and LBA 100 to LBA 105) may be candidates for serialization.

[0051] In some cases, the host system 205 may construct (e.g., compile) a second set (e.g., list) of LBAs with LBA pairs from the first set of LBAs. For example, the second set may include one or more pairs of LBAs associated with sequential data (e.g., (LBA 7, LBA 250), (LBA 254, 410), or the like). In an alternative example, the second set may include one or more pairs of LBAs associated with non-sequential data (e.g., (LBA 3, LBA 100), (LBA 105, LBA 33), (LBA 36, LBA 4), (LBA 412, LBA 9), (LBA 9, LBA 413), or the like). The host system 205 may transmit the second indication to the memory system 210, and the memory system 210 may receive the write command at the memory system controller 215. In some cases, the second indication may include the second set of LBAs. Alternatively, the second indication may include multiple indications that each represent a corresponding LBA pair, a corresponding LBA, or the like from the second set of LBAs.

[0052] In some cases, the second indication may be transmitted in combination with one or more additional signals. For example, the host system 205 may indicate that the host system 205 is ready to send a second group or indications of the second group to the memory system controller 215. In response, the memory system controller 215 may indicate that the memory system controller 215 is ready to handle transmissions (e.g., transfers) from the host system 205. Thus, the host system 205 may transmit the second indication based at least in part on the ready indication from the memory system controller 215. Additionally or alternatively, after the second indication is transmitted to the memory system controller 215, the memory system controller 215 may transmit an additional confirmation signal to the host system 205 indicating that the second indication has been received.

[0053] Based on receiving the second indication, the memory system controller 215 may perform a maintenance operation on the block 240. For example, the maintenance operation may include serializing one or more LBAs of the block 240. In some cases, when the second group includes one or more pairs of LBAs associated with sequential data, the memory system controller 215 may maintain (e.g., preserve) the order of each respective pair indicated by the second group. For example, for a first pair of the second group (e.g., (LBA 7, LBA 250)), the memory system controller 215 may write (e.g., rewrite) the sequential data group (e.g., LBA 4 to LBA 7 and LBA 250 to LBA 254) to a sequential PBA range of the block 240 (e.g., within range 1 of the block 240-b).

[0054] Additionally or alternatively, the memory system controller 215 may serialize (e.g., not maintain) one or more other LBAs or LBA pairs. For example, one or more pairs of non-sequential LBAs (e.g., (LBA 4, LBA 36)) included in the first group and not in the second group may be associated with non-sequential data. Thus, the memory system controller 215 may rewrite the non-sequential LBAs at the sequential PBAs in sequential order. For example, sequential data associated with LBA 4 (e.g., LBA 4 to LBA 7) may be rewritten adjacent to LBA 3, thereby creating a combined set of sequential data from LBA 0 to LBA 7.

[0055] In some cases, one or more LBAs (e.g., LBA 10, LBA 11, etc.) of the LBA sequence may not be in block 240, resulting in an LBA gap. Therefore, when an LBA gap occurs, the memory system controller 215 may write the data associated with the next available LBA (e.g., in ascending order) to the next adjacent memory cell, as illustrated by block 240-b. For example, when LBA 10 is not available, LBA 9 may be written adjacent to the next available sequential LBA range (LBA 33 to LBA 36). After LBA 36, another LBA gap may occur. Therefore, LBA 36 may be written adjacent to the next set of available sequential LBAs (LBA 100 to LBA 105). In some cases, the maintenance operation may include one or more additional or alternative operations. For example, the maintenance operation may include a static wear leveling operation, a garbage collection operation, or both.

[0056] In some cases, the host system 205 may map (e.g., remap) one or more LBAs of the block to corresponding PBAs based at least in part on the indication of transmitting the second set of LBAs. In some cases, for each pair of LBAs indicated by the second set of LBAs, the host system 205 may remap the PBAs from non-sequential LBAs to sequential LBAs. For example, the non-sequential LBAs associated with range 1 of the block 240-b may be remapped to form a complete sequence of LBAs. Thus, LBA 250 to LBA 254 may be remapped to LBA 8 to LBA 12, and LBA 410 to LBA 417 may be remapped to LBA 13 to LBA 20. Thus, after remapping, range 1 of the block 240-b may include a set of sequential LBAs 0 to LBA 20.

[0057] In some cases, after serializing the data, the memory system 210 may perform one or more additional optimizations. For example, the memory system controller 215 may compress one or more entries of the L2P table associated with the block 240-b (e.g., adjust the granularity of the L2P table from 4 kilobytes to 8 kilobytes or the like). Additionally or alternatively, the memory system controller 215 may perform a subsequent serialization obsolete item collection operation. In some cases, serializing the data and other optimizations described herein may improve the performance of the electronic device by improving accessibility to relatively large data sequences, which may reduce read response times and improve the user experience, among other benefits.

[0058] Figure 3 An example of a process flow 300 for supporting sequential storage system data according to an example disclosed herein is illustrated. The process flow 300 may illustrate a reference Figure 2 For example, process flow 300 may depict operations at host system 305 and memory system 310, which may be referenced as Figure 2 3. The host system 205 and the memory system 210 are described in detail. According to the operations described herein, the memory system 310 may include a memory system controller 315 and a block 320, which may be referred to as Figure 2 Examples of memory system controller 215 and block 240 are depicted.

[0059] In the following description of the process flow 300, the methods, techniques, processes, and operations may be performed in a different order or at a different time. In addition, certain operations may be omitted from the process flow 300, or other operations may be added to the process flow 300.

[0060] At 325, the memory system controller 315 may transmit signaling, such as a first request, to the host device 305. For example, the first request may be a request to serialize one or more sets of data stored in the block 320. In some cases, the memory system controller 315 may transmit the first request based on one or more characteristics of the one or more sets of data stored in the block 320, such as a data type, an amount of data, or the like.

[0061] At 330, the host system 305 may transmit a second request to the memory system 310 in response to the first request, and the memory system 310 may receive the write command at the memory system controller 315. The second request may be a request to the memory system controller 315 to generate a first set of candidate LBAs for evaluation (eg, analysis).

[0062] At 335, the memory system controller 315 may access the block 320. For example, the memory system controller 315 may perform a read operation on the block 320 and read one or more sets of data from the block 320 to be serialized.

[0063] At 340, the memory system controller 315 may determine which LBAs may be included in the first set of candidate LBAs requested by the host system 305. For example, based on accessing the block 320, the memory system controller 315 may identify data associated with one or more pairs of non-sequential LBAs and associated with one or more pairs of sequential PBAs (e.g., adjacent memory cells) in the block 320. In some examples, each identified pair of non-sequential LBAs may include a first LBA associated with a first PBA of the block 320 and a second LBA associated with an adjacent PBA of the block 320. In some cases, the memory system controller 315 may construct (e.g., compile) a first set (e.g., a list) of candidate LBAs using the identified pairs.

[0064] At 345, in response to the second request, the memory system controller 315 can transmit a first indication to the host system 305. In some cases, the indication can include a first set of candidate LBAs.

[0065] At 350, the host system 305 may determine whether one or more LBAs (e.g., one or more pairs of non-sequential LBAs) in the first set of candidate LBAs are associated with sequential data. For example, the first pair of LBAs may be associated with a set of sequential data written to the sequential PBAs of block 320. Therefore, the first pair of LBAs may be non-sequential and the associated data may be sequential. Therefore, the host system 305 may determine that the first LBA does not require additional serialization. Additionally or alternatively, the host system 305 may identify one or more LBAs (e.g., one or more pairs of LBAs) in the first set of candidate LBAs that are associated with non-sequential data (e.g., to be serialized).

[0066] At 355, the host system 305 may transmit a second indication to the memory system 310, and the memory system 310 may receive the second indication at the memory system controller 315. In some cases, the second indication may include the second set of LBAs. Alternatively, the second indication may include multiple indications that each represent a corresponding LBA pair, a corresponding LBA, or the like from the second set of LBAs. In some cases, the indication may be transmitted via multiple signals. In some cases, the second indication may be transmitted in combination with one or more additional signals, such as an acknowledgement message from the memory system controller 315.

[0067] At 360, the memory system controller 315 may perform a maintenance operation on the block 320 based on receiving the second indication. For example, the maintenance operation may include serializing one or more LBAs of the block 320. In some cases, when the second group includes one or more pairs of LBAs associated with sequential data, the memory system controller 315 may maintain (e.g., preserve) the order of each corresponding pair indicated by the second group. In addition, the memory system controller 315 may serialize (e.g., not preserve) one or more other LBAs or LBA pairs. In some cases, the maintenance operation may include one or more additional operations (e.g., a static wear leveling operation, a garbage collection operation, or both).

[0068] In some cases, the memory system controller 315 may perform one or more additional optimization operations at 365. For example, the memory system controller 315 may compress (e.g., reduce, minimize, etc.) an L2P table associated with the block 320 (e.g., adjust the granularity of the L2P table from 4 kilobytes to 8 kilobytes or the like). Additionally or alternatively, the memory system controller 315 may perform a subsequent serialized obsolete item collection operation.

[0069] At 370, the host system 305 may map (e.g., remap) one or more LBAs of the block to corresponding PBAs based at least in part on the indication of transmitting the second set of LBAs. In some cases, for each pair of LBAs indicated by the second set of LBAs, the host system 305 may remap the PBA from a non-sequential LBA to a sequential LBA.

[0070] Figure 4 A block diagram 400 illustrates a memory system 420 that supports sequential storage of data in a memory system according to examples disclosed herein. The memory system 420 may be a reference Figures 1 to 3 4. The memory system 420 or its various components may be examples of means for performing various aspects of serializing data of the memory system, as described herein. For example, the memory system 420 may include a first request transmitter 425, a second request receiver 430, a first set of transmitters 435, a second set of receivers 440, a serialization component 445, an LBA identification component 450, a block identification component 455, a write component 460, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0071] The first request transmitter 425 may be configured as or otherwise support means for transmitting a first request for one or more sets of data stored sequentially in a memory cell block, each of the one or more sets of data being associated with a corresponding logical address range. The second request receiver 430 may be configured as or otherwise support means for receiving, in response to transmitting the first request, a second request for generating a first set of logical addresses comprising one or more pairs of logical addresses, each of the one or more pairs of logical addresses comprising a first logical address associated with a first physical address in the memory cell block and comprising a second logical address associated with a second physical address in the memory cell block, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses. The first group transmitter 435 may be configured as or otherwise support means for transmitting an indication of the first set of logical addresses based at least in part on receiving the second request. The second group receiver 440 may be configured as or otherwise support means for receiving an indication of the second set of logical addresses in response to transmitting the indication of the first set of logical addresses, wherein the second set of logical addresses comprises a subset of the first set of logical addresses. The serialization component 445 can be configured to or otherwise support means for performing a maintenance operation on the block of memory cells to serialize the second set of logical addresses within the block of memory cells based at least in part on receiving an indication of the second set of logical addresses.

[0072] In some examples, to support performing maintenance operations on a block of memory cells, serialization component 445 can be configured or otherwise support means for serializing one or more sets of data associated with the second set of logical addresses.

[0073] In some examples, to support serializing one or more sets of data, serialization component 445 may be configured or otherwise support means for writing data associated with the second set of logical addresses to sequential physical addresses within the block of memory cells.

[0074] In some examples, LBA identification component 450 can be configured or otherwise support means for identifying one or more pairs of non-sequential logical addresses based at least in part on receiving the second request, wherein the first set of logical addresses includes the one or more pairs of non-sequential logical addresses.

[0075] In some examples, the first pair of the second set of logical addresses indicates a last logical address of the first set of data and the second pair of the second set of logical addresses indicates a first logical address of the second set of data.

[0076] In some examples, the first set of data and the second set of data are written to sequential physical addresses within a block of memory cells.

[0077] In some examples, the block identification component 455 may be configured to or otherwise support means for identifying a block of memory cells for a maintenance operation based at least in part on characteristics of one or more sets of data stored in the block, wherein transmitting the first request is based at least in part on identifying the block of memory cells.

[0078] In some examples, to support maintenance operations on a block, write component 460 may be configured or otherwise support means for writing data associated with the third set of logical addresses to one or more physical addresses within the block of memory cells.

[0079] In some examples, the third set of logical addresses includes one or more pairs of logical addresses that are included in the first set of logical addresses and not included in the second set of logical addresses.

[0080] In some examples, the second set of logical addresses is included in the first set of logical addresses.

[0081] In some examples, maintenance operations on blocks are associated with static wear leveling operations, garbage collection operations, or both.

[0082] Figure 5 A block diagram 500 illustrates a host system 520 that supports sequential storage of data in a memory system according to examples disclosed herein. The host system 520 may be a reference Figures 1 to 3 5. The host system 520 or its various components may be examples of means for performing various aspects of serializing data of a memory system, as described herein. For example, the host system 520 may include a first request receiver 525, a second request transmitter 530, a first set of receivers 535, a sequence determination component 540, a second set of transmitters 545, a mapping component 550, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0083] The first request receiver 525 may be configured to or otherwise support means for receiving a first request for one or more sets of data stored sequentially in a memory cell block, each of the one or more sets of data being associated with a respective logical address range. The second request transmitter 530 may be configured to or otherwise support means for transmitting a second request for generating a first set of logical addresses comprising one or more pairs of logical addresses based at least in part on receiving the first request, the one or more pairs of logical addresses each comprising a first logical address associated with a first physical address in the memory cell block and comprising a second logical address associated with a second physical address in the memory cell block. The first group receiver 535 may be configured to or otherwise support means for receiving an indication of the first set of logical addresses based at least in part on transmitting the second request. The sequence determination component 540 may be configured to or otherwise support means for determining whether one or more logical addresses in the first set of logical addresses are associated with data written to sequential physical addresses in the memory cell block. The second set of transmitters 545 may be configured as or otherwise support means for transmitting an indication of a second set of logical addresses based at least in part on determining that one or more logical addresses in the first set of logical addresses are associated with data written to sequential physical addresses in a block of memory cells, wherein the second set of logical addresses includes a subset of the first set of logical addresses.

[0084] In some examples, mapping component 550 can be configured or otherwise support means for mapping one or more logical addresses in the second set of logical addresses to corresponding sequential physical addresses based at least in part on transmitting an indication of the second set of logical addresses.

[0085] Figure 6 The description shows a flow chart of a method 600 for supporting sequential storage system data according to examples disclosed herein. The operations of the method 600 may be implemented by the storage system or components thereof described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 4 The memory system described herein performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0086] At 605, the method may include transmitting a first request to sequentially store one or more sets of data in a block of memory cells, each of the one or more sets of data being associated with a respective logical address range. Operation 605 may be performed according to examples disclosed herein. In some examples, aspects of operation 605 may be described with reference to Figure 4 The first request transport 425 described is executed.

[0087] At 610, the method may include receiving, in response to transmitting the first request, a second request to generate a first set of logical addresses including one or more pairs of logical addresses, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the block of memory cells and including a second logical address associated with a second physical address in the block of memory cells, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses. Operation 610 may be performed according to examples disclosed herein. In some examples, aspects of operation 610 may be described with reference to Figure 4 The second request receiver 430 described performs.

[0088] At 615, the method may include transmitting an indication of the first set of logical addresses based at least in part on receiving the second request. Operation 615 may be performed according to examples disclosed herein. In some examples, aspects of operation 615 may be described by reference to Figure 4 The first set of transmitters 435 are described as performing.

[0089] At 620, the method may include receiving an indication of a second set of logical addresses in response to transmitting an indication of the first set of logical addresses, wherein the second set of logical addresses includes a subset of the first set of logical addresses. Operation 620 may be performed according to examples disclosed herein. In some examples, aspects of operation 620 may be described with reference to Figure 4 The second set of receivers 440 is described as performing.

[0090] At 625, the method may include performing a maintenance operation on the memory cell block to serialize the second set of logical addresses within the memory cell block based at least in part on receiving an indication of the second set of logical addresses. Operation 625 may be performed according to examples disclosed herein. In some examples, aspects of operation 625 may be described with reference to Figure 4 The described serialization component 445 executes.

[0091] In some examples, the apparatus described herein may perform one or several methods, such as method 600. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0092] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for: transmitting a first request to serialize one or more sets of data stored in a memory cell block, each of the one or more sets of data being associated with a corresponding logical address range; receiving a second request to generate a first set of logical addresses comprising one or more pairs of logical addresses in response to transmitting the first request, the one or more pairs of logical addresses each comprising a first logical address associated with a first physical address in the memory cell block and comprising a second logical address associated with a second physical address in the memory cell block, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses; transmitting an indication of the first set of logical addresses based at least in part on receiving the second request; receiving an indication of a second set of logical addresses in response to transmitting the indication of the first set of logical addresses, wherein the second set of logical addresses comprises a subset of the first set of logical addresses; and performing a maintenance operation on the memory cell block to serialize the second set of logical addresses within the memory cell block based at least in part on receiving the indication of the second set of logical addresses.

[0093] Aspect 2: A method, apparatus, or non-transitory computer-readable medium according to Aspect 1, wherein performing the maintenance operation on the memory cell block includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for serializing one or more sets of data associated with the second set of logical addresses.

[0094] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein serializing the one or more sets of data includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: writing data associated with the second set of logical addresses to sequential physical addresses within the memory cell block.

[0095] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: identifying one or more pairs of non-sequential logical addresses based at least in part on receiving the second request, wherein the first set of logical addresses includes the one or more pairs of non-sequential logical addresses.

[0096] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, wherein the first pair of the second set of logical addresses indicates the last logical address of the first set of data and the second pair of the second set of logical addresses indicates the first logical address of the second set of data.

[0097] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, wherein the first set of data and the second set of data are written to sequential physical addresses within the block of memory cells.

[0098] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: identifying the memory cell block for the maintenance operation based at least in part on characteristics of the one or more sets of data stored in the block, wherein transmitting the first request is based at least in part on identifying the memory cell block.

[0099] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the maintenance operation on the block further includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: writing data associated with a third set of logical addresses to one or more physical addresses within the memory cell block.

[0100] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of aspect 8, wherein the third set of logical addresses includes one or more pairs of logical addresses included in the first set of logical addresses and not included in the second set of logical addresses.

[0101] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 9, wherein the second set of logical addresses is included in the first set of logical addresses.

[0102] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 10, wherein the maintenance operation on the block is associated with a static wear leveling operation, a garbage collection operation, or both.

[0103] Figure 7 The description shows a flow chart of a method 700 for supporting sequential storage system data according to examples disclosed herein. The operations of the method 700 may be implemented by a host system or components thereof as described herein. For example, the operations of the method 700 may be implemented by reference to Figures 1 to 3 In some examples, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0104] At 705, the method may include receiving a first request to serialize one or more sets of data stored in a block of memory cells, each of the one or more sets of data being associated with a respective logical address range. Operation 705 may be performed according to examples disclosed herein. In some examples, aspects of operation 705 may be described with reference to Figure 5 The first request receiver 525 is described as executing.

[0105] At 710, the method may include transmitting, based at least in part on receiving the first request, a second request to generate a first set of logical addresses including one or more pairs of logical addresses, each of the one or more pairs of logical addresses including a first logical address associated with a first physical address in the block of memory cells and including a second logical address associated with a second physical address in the block of memory cells. Operation 710 may be performed according to examples disclosed herein. In some examples, aspects of operation 710 may be described with reference to Figure 5 The second request transmitter 530 described above is executed.

[0106] At 715, the method may include receiving an indication of a first set of logical addresses based at least in part on transmitting a second request. Operation 715 may be performed according to examples disclosed herein. In some examples, aspects of operation 715 may be described with reference to Figure 5 The first group of receivers 535 described performs.

[0107] At 720, the method may include determining whether one or more logical addresses in the first set of logical addresses are associated with data written to sequential physical addresses in the memory cell block. Operation 720 may be performed according to examples disclosed herein. In some examples, aspects of operation 720 may be described by reference to Figure 5 The determination component 540 described performs.

[0108] At 725, the method may include transmitting an indication of a second set of logical addresses based at least in part on determining that one or more logical addresses in the first set of logical addresses are associated with data written to sequential physical addresses in the block of memory cells, wherein the second set of logical addresses includes a subset of the first set of logical addresses. Operation 725 may be performed according to examples disclosed herein. In some examples, aspects of operation 725 may be described with reference to Figure 5 The second set of transmitters 545 described above are executed.

[0109] In some examples, the apparatus described herein may perform one or several methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0110] Aspect 12: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for: receiving a first request for sequentially storing one or more sets of data in a memory cell block, each of the one or more sets of data being associated with a corresponding logical address range; transmitting a second request for generating a first set of logical addresses comprising one or more pairs of logical addresses based at least in part on receiving the first request, the one or more pairs of logical addresses each comprising a first logical address associated with a first physical address in the memory cell block and comprising a second logical address associated with a second physical address in the memory cell block; receiving an indication of the first set of logical addresses based at least in part on transmitting the second request; determining, for a first pair of logical addresses in the first set of logical addresses, whether the data associated with the first logical address of the first pair and the second logical address of the first pair are logically sequential; and transmitting an indication of a second set of logical addresses based at least in part on determining that the data associated with the first logical address of the first pair and the second logical address of the first pair are logically sequential, wherein the second set of logical addresses comprises a subset of the first set of logical addresses.

[0111] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of Aspect 12, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for mapping one or more logical addresses in the second set of logical addresses to corresponding sequential physical addresses based at least in part on transmitting the indication of the second set of logical addresses.

[0112] It should be noted that the described techniques include possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0113] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0114] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0115] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open circuit relationship between components (where signals cannot currently pass between components via conductive paths) to a closed circuit relationship between components (where signals can pass between components via conductive paths). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0116] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, then the components are isolated from each other. For example, if a switch positioned between two components is open, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0117] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a connection between conditional actions, conditional processes, or parts of processes, the terms may be interchangeable.

[0118] The term "responsive to" may refer to one condition or action occurring at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0119] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0120] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0121] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0122] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0123] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0124] For example, the various illustrative blocks and components described herein in connection with the present disclosure may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0125] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0126] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a general or special computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0127] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Persons skilled in the art will appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: Memory device; and a processing circuit system coupled to the memory device and configured to cause the memory system to: transmitting a first request to sequentially store one or more sets of data in a block of memory cells, each of the one or more sets of data being associated with a respective logical address range; receiving, in response to transmitting the first request, a second request to generate a first set of logical addresses including one or more pairs of logical addresses, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the block of memory cells and including a second logical address associated with a second physical address in the block of memory cells, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses; transmitting an indication of the first set of logical addresses based at least in part on receiving the second request; receiving an indication of a second set of logical addresses in response to transmitting the indication of the first set of logical addresses, wherein the second set of logical addresses includes a subset of the first set of logical addresses; and A maintenance operation is performed on the block of memory cells to serialize the second set of logical addresses within the block of memory cells based at least in part on receiving the indication of the second set of logical addresses.

2. The memory system of claim 1 , wherein performing the maintenance operation on the block of memory cells is configured to cause the memory system to: One or more sets of data associated with the second set of logical addresses are serialized.

3. The memory system of claim 2, wherein serializing the one or more sets of data is configured to cause the memory system to: Data associated with the second set of logical addresses is written to sequential physical addresses within the block of memory cells.

4. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: One or more pairs of non-sequential logical addresses are identified based at least in part on receiving the second request, wherein the first set of logical addresses includes the one or more pairs of non-sequential logical addresses. 5 . The memory system of claim 1 , wherein the first pair of the second set of logical addresses indicates a last logical address of a first set of data and the second pair of the second set of logical addresses indicates a first logical address of a second set of data.

6. The memory system of claim 5, wherein the first set of data and the second set of data are written to sequential physical addresses within the block of memory cells.

7. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to: The block of memory cells for the maintenance operation is identified based at least in part on characteristics of the one or more sets of data stored in the block, wherein transmitting the first request is based at least in part on identifying the block of memory cells.

8. The memory system of claim 1 , wherein the maintenance operation on the block is further configured to cause the memory system to: Data associated with a third set of logical addresses is written to one or more physical addresses within the block of memory cells.

9. The memory system of claim 8, wherein the third set of logical addresses includes one or more pairs of logical addresses included in the first set of logical addresses and not included in the second set of logical addresses.

10. The memory system of claim 1, wherein the second set of logical addresses is included in the first set of logical addresses.

11. The memory system of claim 1, wherein the maintenance operation on the block is associated with a static wear leveling operation, a garbage collection operation, or both.

12. A memory system comprising: processing circuitry configured to cause the memory system to: receiving a first request to serialize one or more sets of data stored in a block of memory cells, each of the one or more sets of data being associated with a respective logical address range; transmitting, based at least in part on receiving the first request, a second request to generate a first set of logical addresses including one or more pairs of logical addresses, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the block of memory cells and including a second logical address associated with a second physical address in the block of memory cells; receiving an indication of the first set of logical addresses based at least in part on transmitting the second request; determining, for a first pair of logical addresses in the first set of logical addresses, whether data associated with a first logical address of the first pair is logically sequential with a second logical address of the first pair; and An indication of a second set of logical addresses is transmitted based at least in part on determining that the data associated with the first logical address of the first pair is logically sequential with the second logical address of the first pair, wherein the second set of logical addresses includes a subset of the first set of logical addresses.

13. The memory system of claim 12, wherein the processing circuitry is further configured to cause the memory system to: One or more logical addresses in the second set of logical addresses are mapped to corresponding sequential physical addresses based at least in part on transmitting the indication of the second set of logical addresses.

14. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of a memory system, cause the memory system to: transmitting a first request to sequentially store one or more sets of data in a block of memory cells, each of the one or more sets of data being associated with a respective logical address range; receiving, in response to transmitting the first request, a second request to generate a first set of logical addresses including one or more pairs of logical addresses, the one or more pairs of logical addresses each including a first logical address associated with a first physical address in the block of memory cells and including a second logical address associated with a second physical address in the block of memory cells, wherein the first logical address and the second logical address are non-sequential addresses and the first physical address and the second physical address are sequential addresses; transmitting an indication of the first set of logical addresses based at least in part on receiving the second request; receiving an indication of a second set of logical addresses in response to transmitting the indication of the first set of logical addresses, wherein the second set of logical addresses comprises a subset of the first set of logical addresses; and A maintenance operation is performed on the block of memory cells to serialize the second set of logical addresses within the block of memory cells based at least in part on receiving the indication of the second set of logical addresses.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions for performing the maintenance operation on the block of memory cells are executable by the one or more processors to: One or more sets of data associated with the second set of logical addresses are serialized.

16. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: One or more pairs of non-sequential logical addresses are identified based at least in part on receiving the second request, wherein the first set of logical addresses includes the one or more pairs of non-sequential logical addresses.

17. The non-transitory computer-readable medium of claim 14, wherein a first pair of the second set of logical addresses indicates a last logical address of a first set of data and a second pair of the second set of logical addresses indicates a first logical address of a second set of data.

18. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: The block of memory cells for the maintenance operation is identified based at least in part on characteristics of the one or more sets of data stored in the block, wherein transmitting the first request is based at least in part on identifying the block of memory cells.

19. The non-transitory computer-readable medium of claim 14, wherein the instructions for performing the maintenance operation on the block are further executable by the one or more processors to: Data associated with a third set of logical addresses is written to one or more physical addresses within the block of memory cells.

20. The non-transitory computer-readable medium of claim 14, wherein the maintenance operation on the block is associated with a static wear leveling operation, a garbage collection operation, or both.

21. The non-transitory computer-readable medium of claim 14, wherein the second set of logical addresses is included in the first set of logical addresses.

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