An L2P mapping table storage method and device

Abstract

The present invention belongs to the technical field of L2P mapping tables, and provides a method and device for storing and reading an L2P mapping table. The method for storing the L2P mapping table, which is used for SSDs larger than 16TB, includes: splitting the L2P mapping table, where PA[31:0] is stored in the storage space starting from the base address A_ADDR, and PA[N:32] is stored in the storage space starting from the base address B_ADDR; PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap. By separating PA[N:0] into PA[N:32] and PA[31:0] for separate storage, the present invention saves the storage space of the L2P mapping table compared to the 8-Byte alignment method.

Description

Technical Field

[0001] The present invention relates to the technical field of L2P mapping tables, and particularly to a method and device for storing an L2P mapping table. Background Art

[0002] A solid state drive (SSD) is a non-volatile storage device composed of a controller and storage chips. Due to its advantages such as small size, light weight, low power consumption, and fast read and write speeds, it is widely used in many fields such as industrial control, video surveillance, network terminals, and navigation. The data read and write of the storage chips of the solid state drive depends on physical characteristics. The file system cannot directly access or operate the storage chips. It is necessary to use a cache chip such as SRAM or DRAM to store the L2P mapping table to convert the logical address provided by the file system into the physical address of the storage chip. The L2P (logical address to physical address) table is used for the conversion from the logical address (LA, Logic Address) to the physical address (PA, Physical Address).

[0003] If 4KB is used as the logical page and the PA is represented by 4 bytes, the theoretical maximum capacity of the SSD is 2 32 ×4KB = 16TB, and the size of the L2P table is about one-thousandth of the SSD capacity, approximately 16GB. If the SSD needs to support 32TB, in order to simplify indexing, the PA needs to be extended to 8 bytes, then the size of the L2P table is about two-thousandths of the SSD capacity, approximately 64GB. This approach not only causes waste of capacity, but also the storage medium for buffering the L2P table is DDR. In the case of full buffering, only the storage of the L2P table requires a capacity of 64GB, resulting in a significant increase in cost. Summary of the Invention

[0004] Aiming at the defects in the prior art, the present invention provides a method and device for storing and reading an L2P mapping table to solve the problem that the current L2P mapping table is stored in an integral manner, resulting in waste of capacity.

[0005] In a first aspect, a method for storing an L2P mapping table provided by the present invention, for an SSD with a capacity greater than 16TB, includes:

[0006] Splitting the L2P mapping table, where PA[31:0] is stored in the storage space starting from the base address A_ADDR, and PA[N:32] is stored in the storage space starting from the base address B_ADDR; the PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap.

[0007] As can be seen from the above technical solution, for a method of storing an L2P mapping table provided by the present invention, PA[N:0] is divided into PA[N:32] and PA[31:0] for separate storage, saving the storage space of the L2P mapping table compared with the 8-Byte alignment method.

[0008] Optionally, every 1K entries form a Group. Each Group of PA[31:0] occupies 4KB of storage space, and each Group of PA[N:32] occupies (N - 32 + 1)×128B of space.

[0009] Optionally, the PA[31:0] Group is stored in the DDR, and the PA[N:32] Group is stored in the Cache.

[0010] As can be seen from the above technical solution, storing the PA[N:32] Group in the Cache avoids frequent read / rewrite operations on the DDR. Compared with the 8-Byte L2P entry scheme, especially for continuous LA read / write operations, there is almost no performance loss.

[0011] Optionally, LA[31:10] is used to index the Group, and LA[9:0] is used to index the entries within the Group.

[0012] Optionally, LA[16:10] in LA[31:10] is used to index the tag SRAM and the data SRAM.

[0013] Optionally, when storing the L2P mapping table, the L2P mapping table is written based on the following method, including:

[0014] Obtain Group Addr1 and Group Index1, write to the DDR to overwrite PA[31:0]; at the same time, use LA[16:10] to index the tag SRAM and the data SRAM;

[0015] Indexing the tag SRAM and the data SRAM by LA[16:10] is completed within 1 clock cycle to determine whether the Cache hits;

[0016] If it hits, directly write to the tag SRAM and the data SRAM, and set the valid and dirty of the tag SRAM to 1, and the L2P writing ends;

[0017] If it does not hit, obtain Group Addr2 and Group Index2, send the write command to the DDR, wait for the writing of PA[N:32] to the DDR to complete, and after the writing of PA[N:32] is completed, the L2P writing ends.

[0018] Optionally, the address of PA[N:0] is determined according to the following formula:

[0019] The Group address where PA[31:0] is located, i.e., Group Addr1 = A_ADDR + LA[31:10] × 4K;

[0020] The Group address where PA[N:32] is located, i.e., Group Addr2 = B_ADDR + LA[31:10] × ((N - 32 + 1) × 128);

[0021] The offset of PA[31:0] within the Group, i.e., Group Index1 = LA[9:0] × 4;

[0022] The offset of PA[N:32] within the Group, i.e., Group Index2 = LA[9:0] × (N - 32 + 1) / 8.

[0023] As can be seen from the above technical solution, directly performing address conversion based on the above formula ensures that the LA address processed by the FTL does not need to change and a one-to-one mapping relationship is established with PA.

[0024] Optionally, when storing the L2P mapping table, the L2P mapping table is read based on the following method, including:

[0025] Obtain Group Addr1 and Group Index1, access the DDR to obtain PA[31:0]; at the same time, use LA[16:10] to index the tag SRAM and data SRAM;

[0026] Indexing the tag SRAM and data SRAM by LA[16:10] is completed within 1 clock cycle to determine whether the cache hits;

[0027] If it hits, directly obtain PA[N:32] from the data SRAM and end the L2P read after PA[31:0] is returned;

[0028] If it does not hit, obtain Group Addr2, send a read command to the DDR, wait for PA[31:0] to be returned; and wait for the PA[N:32] Group to return, and take out PA[N:32] from the PA[N:32] Group according to Group Index2;

[0029] At the same time, re-index the tag SRAM again and determine whether dirty is 1; if dirty is 1, write the data SRAM to the DDR, and the written DDR address is calculated using PA[31:17] in the tag SRAM; if dirty is 0, directly overwrite the original data with the PA[33:32] Group retrieved from the DDR, and the L2P read ends.

[0030] In a second aspect, an embodiment of the present invention provides an L2P mapping table storage device that implements the steps of any of the methods in the first aspect when executing a computer program.

[0031] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of any of the above methods are implemented.

[0032] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of any of the above methods are implemented.

[0033] Adopting the above technical solutions, the present application has the following beneficial effects:

[0034] An L2P mapping table storage method provided by the present invention divides PA[N:0] into PA[N:32] and PA[31:0] for separate storage, saving the storage space of the L2P mapping table compared to the 8Byte alignment method.

[0035] The present invention ensures that the LA address processed by the FTL does not need to change through address conversion and establishes a one-to-one mapping relationship with the PA.

[0036] The present invention uses the PA[N:32] Group Cache to avoid frequent read, rewrite, and write operations on the DDR. Compared with the current L2P table entry scheme of 8Bytes, especially for continuous LA read and write operations, there is almost no performance loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts do not necessarily draw according to the actual scale.

[0038] Figure 1 Shows a schematic diagram of storing the L2P mapping table according to the current integrated storage method.

[0039] Figure 2 It shows a schematic diagram of storing the L2P mapping table based on a method for storing the L2P mapping table provided by an embodiment of the present invention;

[0040] Figure 3 It shows a schematic diagram of LA[31:0] indexing PA[31:0] provided by an embodiment of the present invention;

[0041] Figure 4 It shows a schematic diagram of PA[33:32] Group Cache provided by an embodiment of the present invention. Specific embodiments

[0042] Hereinafter, embodiments of the technical solution of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and thus are only examples and cannot be used to limit the protection scope of the present invention.

[0043] It should be noted that unless otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meanings understood by those skilled in the art to which the present invention belongs.

[0044] In this embodiment, the principle is described specifically with a logical page size of 4KB, PA 34bit, LA 32bit, and a DDR full buffer scheme. Refer to Figure 1 , currently when storing the L2P table, the easiest way to implement is to store the L2P table sequentially, and each entry of the L2P table occupies 8 bytes. As Figure 1 shown, the advantage of using this method is that there is a natural one-to-one correspondence between LA and the DDR address. By directly selecting some bits of the LA part and then shifting left by 3 bits, the DDR address can be obtained, and thus the PA value stored in the L2P table entry can be obtained. The disadvantage of this method is also obvious. Each L2P table entry wastes 30 bits of storage space.

[0045] Based on this, in one embodiment, a method for storing the L2P mapping table is provided, which is applicable to SSDs larger than 16TB and includes:

[0046] Split the L2P mapping table, where PA[31:0] is stored in the storage space starting from the base address A_ADDR, and PA[N:32] is stored in the storage space starting from the base address B_ADDR; PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap.

[0047] Specifically, every 1K entries form a Group. Among them, for PA[31:0], each Group occupies 4KB of storage space, and for PA[N:32], each Group occupies (N - 32 + 1) × 128B of space, and the L2P mapping table can be hierarchically managed.

[0048] It should be noted that those skilled in the art can understand that PA[31:0] represents bit31, bit30,..., bit0 of PA; that is, the 31st bit, 30th bit,..., 0th bit of PA. PA[N:32] represents bitN, bitN - 1,..., bit32 of PA; that is, the Nth bit, (N - 1)th bit,..., 32nd bit of PA. The following will no longer elaborate on LA[31:0], etc.

[0049] The solution proposed in this embodiment is to store the L2P mapping table separately. Figure 2 The schematic diagram of the separate storage of PA[33:0] is shown. Figure 2 In it, PA[31:0] and PA[33:32] are stored separately, where Figure 2 (a), each PA[31:0] occupies 4 bytes, and each Group includes 1K entries, so the size of the PA[31:0] Group is 4KB; Figure 2 (b), the size of the PA[33:32] Group is 256B.

[0050] As Figure 3 shown, when indexing, some bits of LA are extracted as the offset. First, the group addresses of PA[31:0] and PA[N:32] are obtained, and then the offsets of PA[31:0] and PA[N:32] within the group are obtained.

[0051] LA[31:10] is used to index the Group, and LA[9:0] is used to index the entries within the Group. Specifically, the address conversion can be performed through the AT (Address Translate) module. The address of PA[N:0] is determined according to the following formula:

[0052] The group address where PA[31:0] is located, that is, Group Addr1 = A_ADDR + LA[31:10] × 4K;

[0053] The group address where PA[N:32] is located, that is, Group Addr2 = B_ADDR + LA[31:10] × ((N - 32 + 1) × 128);

[0054] The offset of PA[31:0] within the Group, i.e., Group Index1 = LA[9:0] × 4;

[0055] The offset of PA[N:32] within the Group, i.e., Group Index2 = LA[9:0] × (N - 32 + 1) / 8.

[0056] This solves the access from LA to PA. For SSDs larger than 16TB, although the storage capacity is saved, when accessing L2P, since the access to PA[N:32] is increased, the access latency of L2P will increase, reducing the SSD efficiency. How to reduce the access latency of PA[N:32] is specifically described below.

[0057] Taking PA[33:0] as an example, since the space occupied by the PA[33:32] Group is not large, only 256B is occupied, which facilitates Cache storage. That is, the PA[31:0] Group can be stored in DDR, and the PA[N:32] Group can be stored in the Cache buffer. By virtue of the characteristic of the SRAM with a 1 - clock - cycle latency, the access efficiency can be improved, reducing the impact brought by accessing PA[N:32]; thus, a 32KB Cache can buffer 128 PA[33:32] Groups, that is, 128K table entries, which can greatly improve the hit rate.

[0058] In one embodiment, when the logical page size is 4KB, PA is 34 bits, and LA is 32 bits, a 32KB Cache can be used to buffer 128 PA[33:32] Groups, as Figure 4 shown.

[0059] The structure of the Cache consists of a tag SRAM and a data SRAM. The LA part of the bits, the Valid bit, and the Dirty bit are stored in the tag; the PA[N:32] group is stored in the data.

[0060] Specifically, LA[16:10] in LA[31:10] is used to index the tag SRAM and the data SRAM.

[0061] Whenever accessing L2P, while issuing an access command to the DDR, the Cache is directly indexed. Once the Cache hits, the latency caused by accessing PA[N:32] can be saved, improving the access efficiency of L2P. If the Cache misses, then it is necessary to obtain PA[N:32] from the DDR and fill it into the Cache. The size of the Cache can be adjusted according to the size of the PA[N:32] group to achieve a balance of PPA (performance, power, area).

[0062] In one embodiment, when storing the L2P mapping table, the L2P mapping table is written based on the following method, which specifically includes the following steps:

[0063] S101. When the FTL (Flash Translation Layer) obtains Group Addr1 and Group Index1, write to the DDR to overwrite PA[31:0]; at the same time, use LA[16:10] to index the tag SRAM and data SRAM.

[0064] S102. The indexing of the tag SRAM and data SRAM by LA[16:10] is completed within 1 clock cycle to determine whether the Cache hits.

[0065] Specifically, after the indexing of the tag SRAM and data SRAM is completed, the tag value is read out, and then compared with the high bits of the LCA. If they are equal, it is a hit; if not, it is a miss.

[0066] S103a. If it hits, directly write to the tag SRAM and data SRAM, and set the valid and dirty of the tag SRAM to 1, and the writing of L2P ends;

[0067] S103b. If it does not hit, obtain Group Addr2 and Group Index2, directly send the write command to the DDR, wait for the writing of PA[N:32] to the DDR to complete, and after the writing of PA[N:32] is completed, the writing of L2P ends.

[0068] In one embodiment, when reading the L2P mapping table, the L2P mapping table is read based on the following method, which specifically includes the following steps:

[0069] S201. When the FTL (Flash Translation Layer) obtains Group Addr1 and GroupIndex1, access the DDR to obtain PA[31:0]; at the same time, use LA[16:10] to index the tag SRAM and data SRAM.

[0070] The indexing of the tag SRAM and data SRAM of S202.LA[16:10] is completed within one clock cycle to determine whether the cache hits.

[0071] S203a. If it hits, directly obtain PA[N:32] from the data SRAM, and after PA[31:0] is returned, read L2P ends.

[0072] S203b. If it does not hit, obtain Group Addr2, send a read command to the DDR, and wait for PA[31:0] to be returned; and wait for the new PA[N:32] Group to be returned, and take out PA[N:32] Group from the PA[N:32] Group according to Group Index2; at the same time, index the tag SRAM again to determine whether dirty is 1; if dirty is 1, write the data SRAM to the DDR, and the written DDR address is calculated using PA[31:17] in the tag SRAM; if dirty is 0, directly overwrite the original data with the retrieved PA[33:32] Group from the DDR, and read L2P ends.

[0073] In one embodiment, an L2P mapping table storage device for an SSD greater than 16TB is provided, and when executing a computer program, it implements the method steps provided in the foregoing embodiment.

[0074] The L2P mapping table storage device provided in the embodiments of the present application and the above L2P mapping table storage method adopt the same inventive concept and can achieve the same beneficial effects, which will not be elaborated here.

[0075] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above various methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0076] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0077] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for storing an L2P mapping table, characterized in that For SSDs larger than 16TB, including: Split the L2P mapping table, where PA[31:0] is stored in the storage space starting from the base address A_ADDR, and PA[N:32] is stored in the storage space starting from the base address B_ADDR; PA occupies N bits, N is an integer greater than 32, and the address spaces of A_ADDR and B_ADDR do not overlap; Every 1K table entries form a Group. Among them, each Group of PA[31:0] occupies 4KB of storage space, and each Group of PA[N:32] occupies (N - 32 + 1)×128B of space; The Group of PA[31:0] is stored in the DDR, and the Group of PA[N:32] is stored in the Cache cache; LA[31:10] is used to index the Group, and LA[9:0] is used to index the table entries within the Group; In LA[31:10], LA[16:10] is used to index the tag SRAM and data SRAM; When storing the L2P mapping table, the L2P mapping table is written based on the following method, including: Obtain Group Addr1 and Group Index1, write to the DDR to overwrite PA[31:0]; At the same time, use LA[16:10] to index the tag SRAM and data SRAM; The indexing of the tag SRAM and data SRAM by LA[16:10] is completed within 1 clock cycle to determine whether the Cache hits; If it hits, directly write to the tag SRAM and data SRAM, and set the valid and dirty of the tag SRAM to 1, and the write of L2P ends; If it does not hit, obtain Group Addr2 and Group Index2, send the write command to the DDR, wait for the write of PA[N:32] to the DDR to complete, and after the write of PA[N:32] is completed, the write of L2P ends.

2. The method according to claim 1, wherein The address of PA[N:0] is determined according to the following formula: The Group address where PA[31:0] is located, that is, Group Addr1 = A_ADDR + LA[31:10]×4K; The Group address where PA[N:32] is located, that is, Group Addr2 = B_ADDR + LA[31:10]×((N - 32 + 1)×128); The offset of PA[31:0] within the Group, that is, Group Index1 = LA[9:0]×4; The offset of PA[N:32] within the Group, that is, Group Index2 = LA[9:0]×(N - 32 + 1) / 8.

3. The method according to claim 1, wherein When reading the L2P mapping table, the L2P mapping table is read based on the following method, including: Obtain Group Addr1 and Group Index1, access the DDR to obtain PA[31:0]; At the same time, use LA[16:10] to index the tag SRAM and data SRAM; The indexing of LA[16:10] tag SRAM and data SRAM is completed within one clock cycle to determine whether the cache hits. If it hits, directly obtain PA[N:32] from the data SRAM, and after PA[31:0] is returned, the reading of L2P ends. If it does not hit, obtain Group Addr2, send a read command to the DDR, and wait for the return of PA[31:0]; also wait for the return of PA[N:32] Group, and take out PA[N:32] Group from PA[N:32] Group according to Group Index2. At the same time, index the tag SRAM again to determine whether dirty is 1; if dirty is 1, write the data SRAM to the DDR, and the DDR address for writing is calculated using PA[31:17] in the tag SRAM; if dirty is 0, directly overwrite the original data with the retrieved PA[33:32] Group from the DDR, and the reading of L2P ends.

4. An L2P mapping table storage device, characterized in that, For SSDs larger than 16TB, when executing a computer program, the steps of the method according to any one of claims 1 to 3 are implemented.

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