Hardware testing method, device, equipment and storage medium

Abstract

The present invention provides a hardware testing method, apparatus, device, and storage medium. The hardware testing method includes: after determining a target area from a test image, performing parallel testing on multiple data channels included in the hardware to be tested under test parameters corresponding to the target area. Compared with measuring each signal line in each data channel one by one, testing multiple data channels in parallel can significantly reduce the time required for testing and improve the efficiency of hardware testing.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of hardware testing technology, and in particular to a hardware testing method, apparatus, device, and storage medium. Background Art

[0002] Chip testing refers to a series of physical and electrical tests after chip manufacturing is completed to ensure that the chip's functions and performance meet the design specifications, while discovering and eliminating any possible defects or problems.

[0003] When testing chip performance, a Shmoo plot can be used to display the chip's performance under different conditions, helping engineers quickly identify and debug issues. The Shmoo plot scans two key performance indicators, such as reference voltage (Vref) and timing (Timing), and displays the results in a two-dimensional coordinate system, visually demonstrating the relationship between these two variables. Using Vref and Timing as test variables, the chip is tested for bit errors and the number of bit errors. By scanning all operating points (Vref, Timing), the results form a two-dimensional eye diagram on the Shmoo plot, known as a Shmoo eye diagram.

[0004] During chip testing, signal lines used for data input / output on the chip are generally tested one by one, and a Shmoo eye diagram corresponding to each signal line is generated. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a hardware testing method, apparatus, device, and storage medium to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a hardware testing method is provided, the method comprising:

[0007] Determine a target area from a test image, wherein the test image includes A×B areas, where A and B are both integers greater than 2;

[0008] Under the test parameters corresponding to the target area, performing parallel testing on multiple data channels included in the hardware to be tested, and determining the number of bit errors in data transmitted on the signal lines during the test, wherein each of the data channels includes multiple signal lines;

[0009] A test result of the hardware to be tested is generated according to the number of bit errors corresponding to each of the signal lines.

[0010] According to a second aspect of an embodiment of the present application, a hardware testing device is provided, the device comprising:

[0011] An area selection module is used to determine a target area from a test image, wherein the test image includes A×B areas, where A and B are both integers greater than 2;

[0012] a parallel testing module, configured to perform parallel testing on a plurality of data channels included in the hardware to be tested under test parameters corresponding to the target area, and determine the number of bit errors in data transmitted on the signal lines during the test, wherein each of the data channels includes a plurality of signal lines;

[0013] The result generating module is used to generate the test result of the hardware to be tested according to the number of bit errors corresponding to each of the signal lines.

[0014] According to the third aspect of the embodiment of the present application, an electronic device is provided, including: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the hardware testing method provided by the first aspect above.

[0015] According to a fourth aspect of an embodiment of the present application, a computer storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the hardware testing method described in the first aspect is implemented.

[0016] According to a fifth aspect of an embodiment of the present application, a computer program product is provided, comprising computer instructions, wherein the computer instructions instruct a computing device to execute the hardware testing method described in the first aspect above.

[0017] According to the hardware testing solution provided in the embodiment of the present application, after determining the target area from the test diagram, the multiple data channels included in the hardware to be tested are tested in parallel under the test parameters corresponding to the target area. Compared with measuring each signal line in each data channel one by one, the method of testing multiple data channels in parallel can greatly reduce the time required for testing and improve the efficiency of hardware testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0019] Figure 1 is a schematic diagram of an exemplary system used in one embodiment of the present application;

[0020] Figure 2is a flowchart of a hardware testing method according to an embodiment of the present application;

[0021] Figure 3 This is a diagram showing the test results of an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of a test result diagram of an embodiment of the present application;

[0023] Figure 5 is a flowchart of a hardware testing method according to an embodiment of the present application;

[0024] Figure 6 is a flowchart of a hardware testing method according to an embodiment of the present application;

[0025] Figure 7 is a schematic diagram of subroutine 1 of an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of subroutine 2 of an embodiment of the present application;

[0027] Figure 9 This is a schematic diagram of updating a state array according to an embodiment of the present application;

[0028] Figure 10 This is a schematic diagram of running tests on each sub-test graph according to an embodiment of the present application;

[0029] Figure 11 is a schematic diagram of a hardware testing device according to an embodiment of the present application;

[0030] Figure 12 It is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The present application is described below based on examples, but the present application is not limited to these examples. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without describing these details. To avoid obscuring the essence of the present application, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0032] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0033] A Shmoo eye diagram is a two-dimensional chart used to display chip performance under different conditions. It works by scanning two key performance indicators using automatic test equipment (ATE), an automated test system (ATS), or a traditional test platform. The test results are displayed in a two-dimensional coordinate system, forming an "eye" shape. This chart can intuitively demonstrate the chip's performance under different conditions.

[0034] Taking Vref and Timing as key performance indicators, for example, given an operating point (Vref, Timing), the transmit (Tx) side of the data input / output (I / O) channel transmits a known pattern. The receive (Rx) side receives and compares this pattern. All operating points (Vref, Timing) are scanned, and the presence or number of bit errors at each (Vref, Timing) is recorded. The corresponding test results are plotted into a two-dimensional eye diagram to obtain a Shmoo eye diagram. This Shmoo eye diagram serves as an important basis for evaluating I / O electrical performance and can also serve as basic data for post-silicon signal integrity signoff.

[0035] A data channel is a signal path used for data input / output. A data channel consists of multiple signal lines (lanes). If the bit width of a data channel is 1 byte, it consists of 8 lanes; if the bit width is 2 bytes, it consists of 16 lanes. A lane is the basic unit of a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe) link. Each lane is a bidirectional serial communication channel responsible for transmitting data between two PCIe devices.

[0036] Exemplary Systems

[0037] Figure 1 An exemplary system for the hardware testing method of the embodiment of the present application is shown. Figure 1 As shown, the system includes a Basic Input Output System (BIOS), a first chip and a second chip.

[0038] The physical layer 110 of the first chip includes a built-in self-test (BIST) unit 11, an input / output (I / O) unit 12, a comparator 13, and a result register 14. The built-in self-test unit 11 includes a parameter sweep control unit and a pattern generating unit. The parameter sweep control unit can set the sweep range of multiple test parameters. For example, the sweep range of each test parameter can include a sweep start point, a sweep end point, and a sweep offset point. The pattern generator can generate test patterns according to test requirements.

[0039] The physical layer 120 of the second chip includes an input / output unit 21. A transmission connection is established between the input / output unit 12 of the first chip and the input / output unit 21 of the second chip. The first chip transmits a test signal to the second chip according to the test pattern generated by the pattern generator through the transmission connection between the input / output unit 12 and the input / output unit 21; the second chip receives and stores the test signal; the first chip again reads the stored test signal from the memory core of the second chip through the input / output unit 12 and the input / output unit 21 to obtain a feedback signal from the second chip; the input / output unit 12 sends the read feedback signal to the comparator 13, which compares the test signal and the feedback signal to generate a test result, which is then sent to the result register 14 for storage.

[0040] In other embodiments, the physical layer 120 of the second chip includes a comparator 22. After receiving the test signal, the second chip may also input the test signal into the comparator 22 via the input / output unit 21. The comparator 22 determines whether the received test signal is consistent with the expected value, generates a test result, and sends the test result to the result register 14 for storage.

[0041] In other embodiments, the physical layer 120 of the second chip may further include a result register 23 , and the comparator 22 determines whether the received test signal is consistent with expectations and outputs the result to the result register 23 .

[0042] In other embodiments, the physical layer 120 of the second chip may further include a built-in self-test unit 24, which includes a parameter scan controller and a pattern generator. The control signal sent by the basic input / output system can be sent from the first chip to the second chip, where the built-in self-test unit 24 of the second chip performs parameter scanning and test pattern generation. A test signal is then transmitted to the first chip according to the test pattern. After receiving the test signal, the input / output unit 12 of the first chip inputs it into the comparator 13. The comparator 13 determines whether the received test signal is consistent with expectations, generates a test result, and sends the test result to the result register 14 for storage.

[0043] It should be noted that the built-in self-test unit can be arranged in the physical layer of the chip, or arranged in the controller of the chip. In this embodiment, the built-in self-test unit is arranged in the physical layer of the chip for description.

[0044] The test algorithm provided in the embodiments of the present application is used to implement the hardware testing method provided in the embodiments of the present application, wherein the hardware to be tested is the physical layer of the first chip or the second chip. The test algorithm can be run in the BIOS, or in the chip controller, or in the physical layer, or in the BIST, or in the processor, thereby testing the hardware to be tested.

[0045] Hardware testing methods

[0046] Based on the above system, an embodiment of the present application provides a hardware testing method, which can be executed by the hardware testing device 102 in the above system embodiment. The hardware testing method is described in detail below through multiple embodiments.

[0047] Figure 2 This is a flowchart of a hardware testing method according to an embodiment of the present application. Figure 2 As shown, the hardware testing method includes the following steps:

[0048] Step 210: determine the target area from the test image, where the test image includes A×B areas.

[0049] Wherein, A and B are both integers greater than 2. The test status of each area in the test diagram can be recorded through a state array, and the computer will determine the target area from the test diagram based on the state array. The test status marked in the state array includes tested and to be tested, and the target area is determined from the area marked as to be tested. Based on the state array, the computer will sequentially determine one or more areas corresponding to the test status to be tested as target areas; or based on the state array, the computer will determine one or more areas corresponding to the test status to be tested as target areas, and perform hardware testing in sequence using the test parameters corresponding to each target area.

[0050] If a region is neither marked as measured nor marked as to be measured, the region is in an unmeasured state, and the region to be measured is determined from the unmeasured region.

[0051] Exemplarily, the state array includes two arrays, one for recording the tested state of the region, and the other for recording the state of the region to be tested. For example, the state array includes state array 1 and state array 2. If the value representing the test state of the region in state array 1 is the first value, and the value representing the test state of the region in state array 2 is the third value, then the test state of the region is to be tested. If the value representing the test state of the region in state array 1 is the second value, and the value representing the test state of the region in state array 2 is the fourth value, then the test state of the region is tested. If the value representing the test state of the region in state array 1 is the second value, and the value representing the test state of the region in state array 2 is the third value, then the test state of the region is untested. Based on state array 2, the computer determines the target region from the regions whose corresponding test state values are the third value.

[0052] After completing the parallel test under the test parameters corresponding to the target area, the state array needs to be updated: in the state array, the test status of the target area is updated to tested; and if the number of bit errors corresponding to at least one signal line after the parallel test is within the value range, the test status of the untested area adjacent to the target area is marked as pending test. If the number of bit errors of multiple signal lines after the parallel test is not within the value range, the state update operation for the relevant area to be tested is not performed. The above value range is pre-set. Optionally, the value range is (0, 255), that is, greater than 0 and less than 255. Exemplarily, the computer updates the value representing the test status of the target area in state array 1 from the first value to the second value, and updates the value representing the test status of the target area in state array 2 from the third value to the fourth value, that is, updating the test status of the target area to tested. The computer updates the value representing the test status of the area to be tested in state array 2 from the fourth value to the third value, that is, updating the test status of the area to be tested to pending test. The area to be tested is the untested area adjacent to the target area in the test diagram. The above state array can be a Boolean matrix.

[0053] Step 220 , performing parallel testing on multiple data channels included in the hardware to be tested under test parameters corresponding to the target area, and determining the number of bit errors in data transmitted on the signal lines during the test, wherein each data channel includes multiple signal lines.

[0054] A target signal line is identified in each data channel. Under the test parameters corresponding to the target area, multiple target signal lines corresponding to the multiple data channels are tested in parallel. For example, g target signal lines corresponding to g data channels are tested in parallel, where g is an integer greater than 1. If the hardware under test includes G data channels, each g data channel is tested in parallel, where G is an integer greater than 1 and less than or equal to G.

[0055] Optionally, each signal line in the data channel is determined as a target signal line in turn, and the following is performed: first test data and second test data are transmitted in parallel through multiple data channels, the first test data is transmitted through the target signal line, and the second test data is transmitted through signal lines other than the target signal line in the data channel; the number of bit errors after the first test data is transmitted through the target signal line is determined as the number of bit errors of the data transmitted on the target signal line.

[0056] A parallel test is performed on g signal lines in g data channels. First, the sth signal line in each data channel is determined to be a target signal line. First test data and second test data are transmitted in parallel through the g data channels. The first test data is transmitted on the g target signal lines respectively, and the second test data is transmitted on the signal lines other than the target signal lines in the g data channels respectively. Finally, the number of bit errors when each of the g target signal lines transmits the first test data is obtained.

[0057] The bit width of each data channel is w. Each signal line in the data channel is identified as the target signal line in turn. After w rounds of parallel testing of g data channels, the test of each signal line in the g data channels is completed, where w is an integer greater than 1 and the value of s is less than or equal to w.

[0058] Optionally, the first test signal is a test signal generated in a signal pattern (victim pattern) as an observation object, and the second test signal is a test signal generated in an interference signal pattern (aggressor pattern).

[0059] Assume that 10 data channels are tested in parallel, and the bit width of each data channel is 1 byte, as shown in Table 1 below. In the first test round, Test0, the signal line at Bit 0 of each of the 10 data channels is determined as the target signal line. A first test signal and a second test signal are transmitted in parallel through the 10 data channels. The first test signal is transmitted through the 10 signal lines at Bit 0, and the second test signal is transmitted through the 70 signal lines at other bits. The number of bit errors in the data transmitted by the 10 signal lines at Bit 0 can be obtained. In the second test round, Test1, the signal line at Bit 1 of each of the 10 data channels is determined as the target signal line. The first test signal and the second test signal are transmitted in parallel through the 10 data channels. The first test signal is transmitted through the 10 signal lines at Bit 1, and the second test signal is transmitted through the 70 signal lines at other bits. The number of bit errors in the data transmitted by the 10 signal lines at Bit 1 can be obtained. This process continues in this manner. After eight test rounds, the test of each signal line in the 10 data channels is completed.

[0060] Table 1

[0061]

[0062] Optionally, in the sth round of testing, the sth signal line in each data channel is determined to be the target signal line, and the following is performed: under the test parameters corresponding to the target area, the first test data and the second test data are transmitted in parallel through multiple data channels, the first test data is transmitted on multiple target signal lines, and the second test data is transmitted on signal lines other than the target signal line in the multiple data channels, to obtain the number of bit errors corresponding to each of the multiple target signal lines; thereafter, the test status of the target area is updated to tested in the state array, and if the number of bit errors corresponding to at least one target signal line is within the value range after the parallel test, the test status of the untested area adjacent to the target area is marked as to be tested; again, according to the state array, the target area is determined from the test diagram until there is no state value to be tested in the state array. If the bit width of the data channel is w, then w rounds of testing are required to complete the testing of each target signal line in the multiple data channels.

[0063] Step 230: Generate a test result of the hardware to be tested according to the number of bit errors corresponding to each signal line.

[0064] The test results include: the number of bit errors of each signal line under the test parameters corresponding to each target area; or the number of bit errors of each signal line under the test parameters corresponding to each area.

[0065] For example, a scan of multiple target signal lines is completed under the test parameters corresponding to one area, and the computer can output the error data obtained from each scan of the multiple target signal lines in each round of testing. Figure 3 As shown, assuming that 10 data channels are tested in parallel, a scan of the 10 target signal lines DQ0-DQ9 is completed under the test parameters corresponding to one area. The computer outputs the number of bit errors obtained from each scan of the 10 target signal lines DQ0-DQ9 in each round of testing in groups. For example, the test parameters corresponding to scan1 are Vref_0, delay_0, and the number of bit errors corresponding to DQ0-DQ9 is "FF, FF, FF, FF, FF, FF, FF, FF, FF" respectively. The test parameters corresponding to scan2 are Vref_0, delay_1, and the number of bit errors corresponding to DQ0-DQ9 is "FF, FF, FF, FF, FF, FF, FF, FF, FF" respectively. "FF" is a hexadecimal value.

[0066] Optionally, the test result may be a test result graph. After completing the test of one or more sub-test graphs, the computer generates a test result graph corresponding to each signal line based on the number of bit errors obtained by testing each signal line on the test parameters corresponding to the multiple target areas.

[0067] The test result diagram can be a Shmoo eye diagram. For example, Figure 4 As shown, according to Figure 3 The number of bit errors corresponding to each of the target signal lines DQ0-DQ9 is shown, and an eye diagram corresponding to each signal line is generated, thereby obtaining 10 eye diagrams corresponding to DQ0-DQ9.

[0068] If the above-mentioned test result graph is a Shmoo eye diagram, in one possible implementation, the target area on the test result graph corresponding to each signal line is filled according to the number of bit errors corresponding to each signal line. The filling process can be digital filling or color filling. If data filling is used, the number of bit errors is filled into the target area of the test result graph. If color filling is used, if the number of bit errors is within a value range, the color corresponding to the value range is filled into the target area of the test result graph; wherein the value range includes at least three, and different value ranges correspond to different filling colors. For example, if the number of bit errors is within (0,255), the target area is filled with yellow; if the number of bit errors is 0, the target area is filled with green; if the number of bit errors is 255, the target area is filled with red.

[0069] Here, "multiple" means two or more.

[0070] Table 2

[0071] Index Scan Traditional Test - Shmoo Eye Diagram Parallel Testing - Shmoo Eye Diagram 1 Vref=0,phase=0 DQ0 Result DQ0-9 Result 2 Vref=1,phase=0 DQ0 Result DQ0-9 Result … … … … 64 Vref=63,phase=0 DQ0 Result DQ0-9 Result 65 Vref=0,phase=1 DQ0 Result DQ0-9 Result … … … … 8192 Vref=63, phase=127 DQ0 Result DQ0-9 Result 8193 Vref=0,phase=0 DQ1 Result Done … … … 81920 Vref=63, phase=127 DQ9 Result Done

[0072] Among them, Vref represents the reference voltage, phase represents the phase, and Result represents the result.

[0073] In summary, the hardware testing method provided in this embodiment, after determining the target area from the test map, performs parallel testing on multiple data channels included in the hardware to be tested, using the test parameters corresponding to the target area. Compared to measuring each signal line in each data channel one by one, testing multiple data channels in parallel can significantly reduce the time required for testing and improve hardware testing efficiency. For example, as shown in Table 2, if 10 data channels are tested in parallel, a single test cycle can output test results for all 10 signal lines, increasing testing efficiency by 10 times compared to the original method of testing each signal line sequentially.

[0074] In a possible implementation, the test graph can be divided and then the hardware to be tested can be tested by partitioning. Figure 5 As shown, the implementation steps are as follows.

[0075] Step 510: Divide the test image into at least two sub-test images, each sub-test image including a×b areas.

[0076] The test image includes A×B areas, a and b are both integers equal to or greater than 2, and a is smaller than A, and b is smaller than B.

[0077] The total size of the test image and the partition size used to divide the sub-test images are pre-set in the computer, for example, the partition size is a rows and b columns; the test image is divided into at least two sub-test images according to the partition size, so that each sub-test image includes a×b areas. If the total size of the test image is (a×m)×(b×n), the test image is divided into m×n sub-test images, where m and n are both integers greater than 1. For example, the total size of the test image pre-set in the computer is 128×64, and the partition size is 32×32. According to the partition size, the test image can be divided into 4×2 sub-test images, each sub-test image includes 32×32 areas.

[0078] The total size of the test chart is set according to the number of combinations of the two test variables. For example, by taking different values for the two test variables, we get (c×m)×(d×n) combinations, that is, (c×m)×(d×n) test working points. Then the total size of the test chart is set to (a×m)×(b×n), where c and d are both integers greater than 2, a is e times c, b is f times d, and e and f are both positive integers.

[0079] The above-mentioned area refers to a pixel area, and each pixel area may be composed of e×f pixels.

[0080] Step 520: Generate a sub-image state array, wherein the sub-image state array is used to record the test state of the region in the sub-test image.

[0081] The sub-image state array is used to record the test status of regions within the sub-test image. The sub-image state array includes two arrays, a first array and a second array. The first array is used to record the tested status of regions within the sub-test image, and the second array is used to record the pending test status of regions within the sub-test image. Optionally, the sub-image state array can be in the form of a matrix, such as a Boolean matrix.

[0082] The computer can generate a sub-image state array according to the size of the sub-test image; or, generate a sub-image state array according to the number of areas included in the sub-test image. Optionally, the number of elements contained in each array in the sub-image state array is the same as the number of areas included in the sub-test image, and one element corresponds to the test state of one area. For example, if the sub-test image includes a×b areas, the sub-image state array includes 2×a×b elements. If the sub-image state array is a Boolean matrix, the size of the Boolean matrix corresponding to each array is also the same as the size of the sub-test image, and the sizes of both are a×b. Alternatively, the number of elements contained in each array is greater than the number of areas included in the sub-test image and less than twice the number of areas included in the sub-test image. For example, if the sub-test image includes a×b areas, the sub-image state array includes 2×(a+1)×(b+1) elements.

[0083] Step 530, performing the following processing on one or more sub-test patterns in the at least two sub-test patterns: determining a target area from the sub-test pattern according to the sub-pattern state array; performing parallel testing on multiple data channels included in the hardware to be tested, each data channel including multiple signal lines, under test parameters corresponding to the target area; updating the sub-pattern state array according to the number of bit errors in the data transmitted on the signal lines during the test, and initializing the sub-pattern state array after the sub-pattern state array indicates that there is no target area in the sub-test pattern.

[0084] The computer performs the following processing on each of the one or more sub-test patterns:

[0085] determining, from the sub-test graph, a target area to be tested as the test state according to the test state marked in the sub-graph state array; performing parallel testing on multiple data channels under test parameters corresponding to the target area to determine the number of bit errors in data transmitted on the signal line during the test; and updating the sub-graph state array according to the number of bit errors in data transmitted on the signal line during the test.

[0086] If it is determined that the sub-graph state array still includes state information to be tested, the process returns to the step of determining the target area and continues to perform parallel testing on multiple data channels for the sub-test graph;

[0087] If it is determined that the sub-image state array does not include the state information to be tested, the sub-image state array is initialized, and the next sub-test image is determined. The above processing is performed for the next sub-test image until the hardware test for one or more sub-test images is completed.

[0088] During the test, one or more target areas can be determined at a time. If there are multiple target areas, the following processing can be performed on each target area in turn: multiple data channels are tested in parallel under the test parameters corresponding to the target area to determine the number of bit errors in the data transmitted on the signal line during the test; and the sub-graph state array is updated based on the number of bit errors in the data transmitted on the signal line during the test.

[0089] About parallel testing

[0090] Regarding the process of performing parallel testing on multiple data channels included in the hardware to be tested under the test parameters corresponding to the target area, please refer to the detailed description of step 220 above, which will not be repeated here.

[0091] Status updates

[0092] After multiple data channels are tested in parallel under the test parameters corresponding to the target area, the sub-image state array is updated according to the number of bit errors of the data transmitted on the signal line during the test. After the sub-image state array indicates that there is no target area in the sub-test image, the sub-image state array is initialized.

[0093] After parallel testing of multiple data channels according to the test parameters corresponding to the target area, the test status of the target area is updated to tested in the sub-graph status array. If the number of bit errors corresponding to at least one signal line is within the value range after the parallel test, the test status of the untested area adjacent to the target area is also marked as pending test, completing the update of the sub-graph status array.

[0094] For example, assuming that 10 data channels are tested in parallel, a scan of 10 target signal lines DQ0-DQ9 is completed under the test parameters corresponding to a target area, and the number of bit errors corresponding to each of the 10 target signal lines DQ0-DQ9 is obtained. If the number of bit errors corresponding to at least one of the 10 target signal lines DQ0-DQ9 is within a value range, the test status of the untested area adjacent to the target area is marked as to be tested. For example, the number of bit errors of the 10 target signal lines DQ0-DQ9 is "0, 0, 0, 0, FF, 0, 0, 0, 0" respectively, and the number of bit errors corresponding to DQ5 is within the value range (0.255), then the test status of the untested area adjacent to the target area is marked as to be tested.

[0095] Regarding the update of the test status of the target area, the value representing the test status of the target area in the first array is updated from the first value to the second value, and the value representing the test status of the target area in the second array is updated from the third value to the fourth value, which indicates that the target area is updated to be tested. Regarding the update of the test status of the untested area adjacent to the target area, the value representing the test status of the area to be tested in the second array is updated from the fourth value to the third value, wherein the area to be tested is the untested area adjacent to the target area in the test diagram. For example, the first array and the second array are both Boolean matrices. If the test status of a region is tested, the value representing the test status of the region in the first array is 1, and the value representing the test status of the region in the second array is 0; if the test status of a region is to be tested, the value representing the test status of the region in the first array is 0, and the test status of the region in the second array is 1; if the test status of a region is untested, the value representing the test status of the region in the first array is 0, and the test status of the region in the second array is 0. Here, the test status of "untested" refers to a test status other than tested and to be tested. After the test, the test status of the target area is updated, the value representing the test status of the target area in the first array is updated from 0 to 1, and the value representing the test status of the target area in the second array is updated from 1 to 0; the test status of the area to be tested is updated, the value representing the test status of the area to be tested in the second array is updated from 0 to 1, and the value representing the test status of the area to be tested in the first array remains unchanged and remains 0.

[0096] Determination of target areas

[0097] Alternatively, based on the second array, the regions in the sub-test graph corresponding to the test state with the third value may be individually determined as target regions; or, based on the second array, the regions in the sub-test graph corresponding to the test state with the third value may all be determined as target regions. For example, the region in the sub-test graph corresponding to the value 1 in the second array may be determined as the target region.

[0098] When the values representing the test status in the second array are all fourth values, it means that there is no area to be tested in the sub-test image of the current test, the test of the sub-test image is ended, and the next sub-test image is determined and the test is continued for the next sub-test image.

[0099] Determination of the area to be tested

[0100] It is necessary to determine the area to be tested based on the number of bit errors when transmitting data on the signal line. A value range is pre-set in the computer. If the number of bit errors indicated by the test result is within the value range, the test status of the untested area adjacent to the target area is marked as to be tested. If the number of bit errors indicated by the test result is outside the value range, the status update of the relevant area to be tested is not performed. Optionally, the value range is (0,255), that is, greater than 0 and less than 255. If the number of bit errors indicated by the test result is within (0,255), the test status of the untested area adjacent to the target area is marked as to be tested; if the number of bit errors indicated by the test result is 0 or 255, the status update of the relevant area to be tested is not performed.

[0101] Step 540: Generate a test result of the hardware to be tested according to the number of bit errors corresponding to each signal line.

[0102] For the detailed implementation process of step 540, please refer to the description in step 230, which will not be repeated here.

[0103] To summarize, the hardware testing method provided in the embodiment of the present application divides the original test graph into multiple sub-test graphs, each sub-test graph includes a×b areas, and generates a sub-graph state array to record the test status of the areas in the sub-test graph. By reusing the sub-graph state array, parallel testing of multiple data channels is performed for each sub-test graph in one or part of the multiple sub-test graphs. Compared with recording the test status of the entire test graph, the memory required to record the test status of the sub-test graph is significantly reduced, thereby greatly reducing the memory requirement during hardware testing.

[0104] In one possible implementation, based on Figure 5 The illustrated embodiment also uses an edge state array to record the test status of edge regions in multiple sub-test patterns. After a sub-test pattern is tested, the next sub-test pattern is determined based on the edge state array. The edge state array is described in three parts below.

[0105] Generation of edge state array

[0106] The computer also generates an edge state array; the edge state array is used to record the test states of the edge regions in the at least two sub-test images. The edge state array includes two arrays, a third array and a fourth array. The third array is used to record the tested states of the edge regions in the at least two sub-test images, and the fourth array is used to record the pending states of the edge regions in the at least two sub-test images. Optionally, the edge state array can take the form of a matrix, such as a Boolean matrix.

[0107] The computer can generate an edge state array based on the size of the sub-test image; or, generate an edge state array based on the number of edge regions included in the sub-test image. Optionally, the number of elements contained in each array in the edge state array is the same as the sum of the edge regions in at least two sub-test images. For example, if a sub-test image includes a×b regions, then the sub-test image uses (2a+2b-4)×2 elements in the edge state array; if the sub-test image includes m×n regions, then the edge state array includes (2a+2b-4)×2×m×n elements. Alternatively, the number of elements used in each array for each sub-test image is 4 more than the number of edge regions in the sub-test image. For example, if a sub-test image includes a×b regions, then the sub-test image uses (2a+2b)×2 elements in the edge state array; if the sub-test image includes m×n regions, then the edge state array includes (2a+2b)×2×m×n elements.

[0108] Optionally, the edge state array may be in the form of a matrix, for example, the edge state array may be a Boolean matrix. For example, each array in the edge state array may be a Boolean matrix of size m×n×(2a+2b).

[0109] The edge state array can be used to record the test states of the edge regions of all sub-test patterns. In the embodiment provided in this application, the edge state array is used to record the test states of the edge regions of one or a portion of sub-test patterns.

[0110] The subgraph state array and the edge state array can be generated in sequence or simultaneously, and there is no restriction on the generation order of the two.

[0111] Update of edge state array

[0112] After parallel testing of multiple data channels according to the test parameters corresponding to the target area, it is determined that the target area is located at the edge of the sub-test image, and the test status of the target area in the edge status array is updated to tested.

[0113] That is, during the test status update process, it is also necessary to determine whether the target area is located at the edge of the sub-test image. If the target area is located at the edge of the sub-test image, the test status of the target area in the edge status array is updated. If the target area is not at the edge of the sub-test image, the test status of the target area in the edge status array is not updated.

[0114] For the update of the edge status array, if the test status of the target area is updated to tested, the value representing the test status of the target area in the third array is updated from the fifth value to the sixth value, and the value representing the test status of the target area in the fourth array is updated from the seventh value to the eighth value.

[0115] Regarding the test status update of the edge area, if the test status of an edge area is tested, the value of the test status of the edge area in the third array is 1, and the value of the test status of the edge area in the fourth array is 0; if the test status of an edge area is to be tested, the value of the test status of the edge area in the third array is 0, and the test status of the edge area in the fourth array is 1; if the test status of an edge area is untested, the value of the test status of the edge area in the third array is 0, and the test status of the edge area in the fourth array is 0.

[0116] After the test, the test status of the target area is updated. If the target area is the edge area of the sub-test image, the value representing the test status of the target area in the third array is updated from 0 to 1, and the value representing the test status of the target area in the fourth array is updated from 1 to 0.

[0117] Optionally, after determining that the area to be tested is located at the edge of any sub-test image, the computer updates the test status of the area to be tested in the edge status array, that is, if the area to be tested is located at the edge of any sub-test image in at least two sub-test images, the test status of the area to be tested in the edge status array is marked as to be tested, wherein the area to be tested is an untested area adjacent to the target area in the test image.

[0118] The area to be tested can be located at the edge of the sub-test image being tested, or at the edge of another sub-test image adjacent to the sub-test image. If the area to be tested is located at the edge of the sub-test image being tested, the test status of the area to be tested in the sub-image state array and the edge state array needs to be updated to "to be tested." If the area to be tested is located at the edge of another sub-test image adjacent to the sub-test image, the test status of the area to be tested in the edge state array needs to be updated to "to be tested." If the area to be tested does not belong to the edge of any sub-test image, the test status of the area to be tested in the edge state array will not be updated.

[0119] If the test status of the area to be tested is updated to under test, the value representing the test status of the area to be tested in the fourth array is updated from the eighth value to the seventh value, for example, the value representing the test status of the edge area in the fourth array is updated from 0 to 1.

[0120] If there is an update of the edge state array, it can be executed simultaneously or sequentially with the update of the subgraph state array, and there is no restriction on the execution order of the two.

[0121] Determine the subtest graph for the next test based on the edge state array

[0122] After completing the test of each target area in the sub-test image, determine the sub-test image for the next test based on the edge area to be tested corresponding to the test state in the edge state array; update the test state of the edge area of the sub-test image for the next test from the edge state array to the initialized sub-image state array, and perform the test of each target area in the sub-test image for the next test.

[0123] For example, when there is a seventh value in the fourth array, the sub-test graph where the area corresponding to the test state has the seventh value is determined as the sub-test graph of the next test; the value of the test state of the edge area of the sub-test graph of the next test is copied from the fourth array to the initialized second array.

[0124] If the sub-image state array indicates that there is no area to be tested in the sub-test image, the test of each target area in the sub-test image is completed. Thereafter, based on the edge state array, the sub-test image with the edge area to be tested is determined as the sub-test image for the next test. The test state of the edge area of the sub-test image for the next test is updated from the edge state array to the corresponding position in the initialized sub-image state array. Then, the process returns to step 330 and determines the sub-test image for the next test based on the edge state array again until the edge state array indicates that there is no sub-test image to be tested, thereby completing the hardware test corresponding to one or more sub-test images.

[0125] To sum up, the hardware testing method provided in the embodiment of the present application divides the original test graph into multiple sub-test graphs, each sub-test graph includes a×b areas, and generates a sub-graph state array to record the test status of the areas in the sub-test graph. After each test of a sub-test graph is completed, the sub-graph state array is initialized, and the initialized sub-graph state array is used to continue to participate in the test of the next sub-test graph. By reusing the sub-graph state array, the test processing of one or more sub-test graphs is completed, and the sub-graph state array and edge state data can be reused for each round of parallel testing of multiple data channels. Compared with recording the test status of the entire test graph, the memory required to record the test status of the sub-test graph is significantly reduced, so the generation and reuse of the sub-graph state array can greatly reduce the memory requirements during hardware testing.

[0126] The method also generates an edge state array to record the test states of edge areas of multiple sub-test images. In the process of selecting a to-be-tested area, a to-be-tested area may be selected from edge areas of other sub-test images adjacent to the sub-test image, and the to-be-tested state of the to-be-tested area is updated to the edge state array. After completing the test of the sub-test image, the to-be-tested state in the edge state array can be used to accurately locate the sub-test image for the next test, without having to test the sub-test image where the target area does not exist, thereby reducing the workload of hardware testing and improving the speed of hardware testing.

[0127] Figure 6 This is a flowchart of a hardware testing method according to an embodiment of the present application. Figure 6 As shown, it provides an exemplary description of the testing process of each round in the w rounds of testing of multiple data channels in the hardware testing method provided in the above embodiment, and the steps are as follows:

[0128] Step 601, start.

[0129] Step 602, partition size: (a×b); total size of the test pattern: (a×m)×(b×n); number of sub-test patterns: (m×n).

[0130] The pre-set partition size is (a×b) and the total size of the test image is (a×m)×(b×n). The computer divides the test image with a total size of (a×m)×(b×n) into (m×n) sub-test images according to the partition size (a×b). The partition size refers to the size used to divide the sub-test images.

[0131] Among them, (a×b) means a rows×b columns; (m×n) means m rows×n columns; (a×m)×(b×n) means (a×m) rows×(b×n) columns.

[0132] Step 603 , initialize the following Boolean arrays to all False: visited; to_visit; edge_visited; edge_to_visit.

[0133] In a Boolean array, the value 0 represents False, and the value 1 represents True. Generate and initialize the following Boolean arrays: visited, to_visit, edge_visited, and edge_to_visit. Here, visited refers to the first array, to_visit refers to the second array, edge_visited refers to the third array, and edge_to_visit refers to the fourth array.

[0134] The Boolean array is generated according to the size of the subtest graph. Visited and to_visit are Boolean matrices of size (a×b), and edge_visited and edge_to_visit are Boolean matrices of size m×n×(2a+2b).

[0135] Step 604: Obtain the center point (V0, T0) of the test graph through I / O Training.

[0136] The computer determines the center point (V0, T0) from the test image through input / output (I / O) training.

[0137] This embodiment uses the test variables Vref and Timing as an example. Each area in the test chart is represented by a grid. In the test chart configured based on the test variables, each grid corresponds to an operating point, and each operating point corresponds to a set of test parameters (Vref, Timing). The center point refers to the operating point at the center of the test chart.

[0138] Step 605: Start from (V0, T0) and move in one direction. Each time you move one grid, run a test for the corresponding test parameters. Test multiple target signal lines in parallel until the number of bit errors corresponding to at least one target signal line is within the range of interest. Use the last tested working point (V, T) as the initial working point.

[0139] The range of interest is the range of values. Starting from (V0, T0), move in one direction, either up, down, left, or right. For example, starting from (V0, T0) and moving downward, run a test (i.e., a sweep) for each corresponding test parameter for each downward movement until at least one target signal line has a bit error count within the range (0, 255). The last operating point (V, T) tested is used as the initial operating point.

[0140] Step 606: Calculate the sub-test graph where the initial working point is located.

[0141] The test pattern is divided into m rows × n columns of sub-test patterns, and the initial working point is located at the position (ri, rj) in the above m × n sub-test pattern array. The floor function is used to calculate (ri, rj):

[0142] ri=floor(V / a);

[0143] rj = floor(T / b);

[0144] Among them, the values of i and j are both positive integers.

[0145] Step 607, set visited to all False; set to_visit to all False.

[0146] Before the test of each sub-test graph begins, initialize visited and to_visit, and set both visited and to_visit to all False.

[0147] Step 608: Copy the 2 (a+b) values in edge_to_visit[ri,rj] to the upper, lower, left, and right edges of to_visit.

[0148] Where edge_to_visit[ri,rj] represents the address of the test state of the edge region of the sub-test graph (ri,rj) in edge_to_visit. The relationship of copying 2 (a+b) values from edge_to_visit[ri,rj] to to_visit is as follows:

[0149] Upper edge: to_visit[0,:] = edge_to_visit[ri,rj,2a:2a+b];

[0150] Lower edge: to_visit[a-1,:] = edge_to_visit[ri,rj,2a+b:2a+2b];

[0151] Left edge: to_visit[:,0] = edge_to_visit[ri,rj,:a];

[0152] Right edge: to_visit[:,b-1] = edge_to_visit[ri,rj,a:2a];

[0153] Among them, to_visit is a two-dimensional Boolean matrix of a×b, to_visit[0,:] represents the b positions of the upper edge with the starting position of 0 in to_visit, to_visit[a-1,:] represents the b positions of the lower edge with the starting position of (a-1) in to_visit, to_visit[:,0] represents the a positions of the left edge with the ending position of 0 in to_visit, to_visit[:,b-1] represents the a positions of the right edge with the ending position of (b-1) in to_visit; edge_to_visit is a three-dimensional Boolean matrix of m×n×2(a+b), edge_to_visit[ri,rj,:a] represents the position of the left edge with the ending position of 0 in to_visit, and edge_to_visit[ri,rj,:a] represents the position of the right edge with the ending position of (b-1) in edge_to_visit. In the example, edge_to_visit[ri,rj,2a:2a+b] represents the positions (2a-1) to (2a+b-1) among the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit, and edge_to_visit[ri,rj,2a+b:2a+2b] represents the positions (2a+b) to (2a+2b-1) among the 2(a+b) positions corresponding to (ri,rj) in edge_to_visit.

[0154] Step 609: Calculate the position (ci, cj) of the working point (V, T) in the sub-test graph.

[0155] The sub-test graph includes a rows and b columns, and the working point (V, T) is determined to be located at the position (ci, cj) in the above a×b sub-test graph.

[0156] Use the modulo function to calculate (ci,cj):

[0157] ci=V mod a;

[0158] cj=T mod b.

[0159] Step 610: Configure the I / O operating point to (V, T), run the test and record the results.

[0160] The computer configures the test parameters of the I / O operation as V and T, runs the test, and records the results of the test on the hardware under test, such as the number of error codes corresponding to each target signal line. For example, when performing a parallel test on 10 data channels included in the hardware under test, the number of error codes corresponding to 10 target signal lines can be obtained in each scan, and the number of error codes corresponding to 10 target signal lines is recorded.

[0161] Step 611, update visited and to_visit.

[0162] Update the values at the position (ci, cj) in to_visit and visited:

[0163] to_visit[ci,cj] = False;

[0164] visited[ci,cj] = True.

[0165] Step 612, execute Subroutine 1: update edge_to_visit[ci,cj] and edge_visited[ci,cj].

[0166] Execute Subroutine 1 to determine the position of the operating point (V, T) in the sub-test graph. If the operating point (V, T) is located at the edge of the sub-test graph, update edge_to_visit and edge_visited. As Figure 7 shown, the update process of Subroutine 1 is as follows:

[0167] Judge the value of ci;

[0168] If ci = 0, it means that the operating point (V, T) is at the upper edge of the sub-test graph, and update edge_to_visit and edge_visited:

[0169] edge_to_visit[ri,rj,2a+cj] = False; edge_visited[ri,rj,2a+cj] = Ture;

[0170] If ci = a - 1, it means that the operating point (V, T) is at the lower edge of the sub-test graph, and update edge_to_visit and edge_visited:

[0171] edge_to_visit[ri,rj,2a+b+cj] = False; edge_visited[ri,rj,2a+b+cj] = Ture;

[0172] If 0 < ci < a - 1, then judge the value of cj;

[0173] If cj = 0, it indicates the left edge of the sub-test pattern at the working point (V, T), and update edge_to_visit and edge_visited:

[0174] edge_to_visit[ri, rj, ci] = False; edge_visited[ri, rj, ci] = True;

[0175] If cj = b - 1, it indicates the right edge of the sub-test pattern at the working point (V, T), and update edge_to_visit and edge_visited:

[0176] edge_to_visit[ri, rj, a + ci] = False; edge_visited[ri, rj, a + ci] = True;

[0177] If 0 < cj < b - 1, it indicates that the working point (V, T) is not located at the edge of the sub-test pattern.

[0178] Step 613, determine whether there is at least one target signal line with the number of error codes within the range of interest.

[0179] If there is at least one target signal line with the number of error codes within the range of interest, execute Step 614; if not, that is, there is no target signal line with the number of error codes within the range of interest, execute Step 615. For example, determine whether there is at least one target signal line with the number of error codes within (0, 255). If so, execute Step 614; if not, execute Step 615.

[0180] Step 614, execute Subroutine 2: update to_visit and edge_to_visit.

[0181] Execute Subroutine 2 to determine whether there are still untested areas in the upper, lower, left, and right regions adjacent to (ci, cj). If so, mark them as to be tested. As Figure 8 shown, the update process of Subroutine 2 is as follows:

[0182] · Judge the value of ci.

[0183] 1) If ci = 0, it indicates that the working point (V, T) is located at the upper edge of the sub-test pattern. Mark the area (ci + 1, cj) below (ci, cj) as to be tested, that is, update to_visit:

[0184] to_visit[ci + 1, cj] = ~visited[ci + 1, cj], where "~" represents the negation operation. For example, if visited[ci + 1, cj] = False, then ~visited[ci + 1, cj] = True, and after update, to_visit[ci + 1, cj] = True. On the contrary, if visited[ci + 1, cj] = True, then ~visited[ci + 1, cj] = False, and after update, to_visit[ci + 1, cj] = False;

[0185] After updating to_visit, determine whether ri > 0;

[0186] If ri > 0, it means that there is a sub-test graph (ri - 1, rj) above the sub-test graph (ri, rj) in the sub-test graph array. Update the test status of the area adjacent to (ci, cj) and above (ci, cj) in the sub-test graph (ri - 1, rj) in edge_to_visit:

[0187] edge_to_visit[ri - 1, rj, k] = ~edge_visited[ri - 1, rj, k], k = 2a + b + cj;

[0188] If ri > 0 is not true, it means that the sub-test graph (ri, rj) is located at the upper edge of the sub-test graph array, and execute the step of "judging the value of cj". [[ID=第十三]]

[0189] 2) If ci = a - 1, it means that the working point (V, T) is located at the lower edge of the sub-test graph. Mark the area (ci - 1, cj) above (ci, cj) as to be tested, that is, update to_visit as:

[0190] to_visit[ci - 1, cj] = ~visited[ci - 1, cj];

[0191] After updating to_visit, determine whether ri < m - 1;

[0192] If ri < m - 1, it means that there is a sub-test graph (ri + 1, rj) below the sub-test graph (ri, rj) in the sub-test graph array. Update the test status of the area adjacent to (ci, cj) and below (ci, cj) in the sub-test graph (ri + 1, rj) in edge_to_visit:

[0193] edge_to_visit[ri + 1, rj, k] = ~edge_visited[ri + 1, rj, k], k = 2a + cj;

[0194] If ri < m - 1 does not hold, it means that the sub-test pattern (ri, rj) is located at the lower edge of the sub-test pattern array, and the step of "judging the value of cj" is executed.

[0195] 3) If 0 < ci < a - 1, it means that the operating point (V, T) is not located at the upper or lower edge position of the sub-test pattern. Mark the area (ci - 1, cj) above (ci, cj) and the area (ci + 1, cj) below it as to be measured. That is, update to_visit as follows:

[0196] to_visit[ci - 1, cj] = ~visited[ci - 1, cj]; to_visit[ci + 1, cj] = ~visited[ci + 1, cj];

[0197] After updating to_visit, execute the step of "judging the value of cj".

[0198] · Judge the value of cj.

[0199] 1) If cj = 0, it means that the operating point (V, T) is located at the left edge of the sub-test pattern. Mark the area (ci, cj + 1) on the right side of (ci, cj) as to be measured. That is, update to_visit:

[0200] to_visit[ci, cj + 1] = ~visited[ci, cj + 1];

[0201] After updating to_visit, judge whether rj > 0;

[0202] If rj > 0, it means that there is a sub-test pattern (ri, rj - 1) on the left side of the sub-test pattern (ri, rj) in the sub-test pattern array. Update the test status of the area adjacent to (ci, cj) and on the left side of (ci, cj) in the sub-test pattern (ri, rj - 1) in edge_to_visit:

[0203] edge_to_visit[ri, rj - 1, k] = ~edge_visited[ri, rj - 1, k], where k = a + ci;

[0204] If ri > 0 does not hold, it means that the sub-test pattern (ri, rj) is located at the left edge of the sub-test pattern array, and execute step 615.

[0205] 2) If cj = b - 1, it means that the operating point (V, T) is located at the right edge of the sub-test pattern. Mark the area (ci, cj - 1) on the left side of (ci, cj) as to be measured. That is, update to_visit:

[0206] to_visit[ci, cj - 1] = ~visited[ci, cj - 1];

[0207] After updating to_visit, determine whether rj < n - 1;

[0208] If rj < n - 1, it means that there is a sub-test graph (ri, rj + 1) on the right side of the sub-test graph (ri, rj) in the sub-test graph array. Update the test status of the area adjacent to (ci, cj) and on the right side of (ci, cj) in the sub-test graph (ri, rj + 1) in edge_to_visit:

[0209] edge_to_visit[ri, rj + 1, k] = ~edge_visited[ri, rj + 1, k], k = ci;

[0210] If ri is not < n - 1, it means that the sub-test graph (ri, rj) is located at the right edge of the sub-test graph array, and execute step 615.

[0211] 3) If 0 < cj < b - 1, it means that the working point (V, T) is not located at the left or right edge position of the sub-test graph. Mark the left area (ci, cj - 1) and the right area (ci, cj + 1) of (ci, cj) as to be tested, that is, update to_visit as follows:

[0212] to_visit[ci, cj - 1] = ~visited[ci, cj - 1]; to_visit[ci, cj + 1] = ~visited[ci, cj + 1];

[0213] After updating to_visit, execute step 615.

[0214] Step 615, determine whether to_visit is all False.

[0215] After completing the test of the working point (V, T), determine whether to_visit is all False, that is, determine whether there is still an area to be tested in the sub-test graph. If so, execute step 618; if not, execute step 616.

[0216] Step 616, find a new set of (ci, cj) such that to_visit[ci, cj] = True and visited[ci, cj] = False.

[0217] Redetermine a (ci, cj) in the sub-test graph. This redetermined (ci, cj) has to_visit[ci, cj] = True and visited[ci, cj] = False, that is, this is an area to be tested.

[0218] Step 617: Calculate the new working point corresponding to (ci, cj).

[0219] According to the re-determined working point corresponding to (ci, cj) in the test diagram, the calculation method is as follows:

[0220] v=ri×a+ci;

[0221] t=rj×b+cj.

[0222] After executing step 617 , return to step 610 .

[0223] Step 618: Determine whether all edge_to_visit values are False.

[0224] Determine whether edge_to_visit is all False, that is, determine whether there is a sub-test graph to be tested. If edge_to_visit is all False, it means there is no sub-test graph to be tested, and execute step 620; if not, that is, edge_to_visit is not all False, it means there is a sub-test graph to be tested, and execute step 619.

[0225] Step 619, find a new set of (ri, rj) so that edge_to_visit[ri, rj] is not all False.

[0226] A sub-test graph (ri, rj) is re-determined in the sub-test graph. In the re-determined sub-test graph (ri, rj), not all edge_to_visit[ri, rj] are False, that is, this is a sub-test graph to be tested.

[0227] like Figure 9As shown in the figure, an example of a test run is given. First, for the sub-test graph (ri, rj) on the right side of the demarcation line, multiple data channels included in the hardware under test are tested in parallel. The test is run at the working point 701, and the average number of error codes (errcnt) is recorded as 64. The status of the working point 701 is marked as measured in this area. If 0 < errcnt = 64 < the maximum number of error codes (err_max), the working points on the lower three sides (left, lower, and right) of the working point 701 are marked as to be tested in this area; move one grid to the left, run the test at the working point 702, record the average number of error codes as 133, and mark the status of the working point 702 as measured in this area. If 0 < errcnt = 133 < err_max, the working points on the lower left sides of the working point 702 are marked as to be tested in this area; continue to move one grid to the left, run the test at the working point 703, record the average number of error codes as 169, and mark the status of the working point 703 as measured in this area. If 0 < errcnt = 169 < err_max, the working point 703 is located at the left edge of the sub-test graph (ri, rj), the working points on the upper and lower sides of the working point 703 are marked as to be tested in this area, and the working points on the left side of the working point 703 are marked as to be tested at the edge; move one grid down, run the test at the working point 704, record the average number of error codes as 194, and mark the status of the working point 704 as measured in this area. If 0 < errcnt = 194 < err_max, the working point 704 is located at the left edge of the sub-test graph (ri, rj), the working point on the lower side of the working point 704 is marked as to be tested in this area, and the working points on the left side of the working point 704 are marked as to be tested at the edge;... until the measurement of the sub-test graph (ri, rj) is completed. According to the marking of to be tested at the edge, the measurement of the next sub-test graph (ri, rj - 1) is started. The test is run starting from the working point 705, and the average number of error codes is recorded as 209. The status of the working point 705 is marked as measured in this area. If 0 < errcnt = 209 < err_max, the working point 705 is located at the right edge of the sub-test graph (ri, rj - 1), the working points on the upper, lower, and left three sides of the working point 705 are marked as to be tested in this area,... until the measurement of the sub-test graph (ri, rj - 1) is completed. Again, according to the marking of to be tested at the edge, the measurement of the next sub-test is started, and so on. Among them, the above average number of error codes refers to the average value of the number of error codes corresponding to multiple target signal lines during one scan. For example Figure 10 , after the measurement of the sub-test graph 801 is completed, the measurement of the sub-test graph 802 is started according to the marking of to be tested at the edge, and then the tests of the sub-test graph 803, sub-test graph 804, sub-test graph 805, and sub-test graph 806 are completed in sequence until the measurement of the test graph is completed. Among them, marking measured in this area and to be tested in this area is to mark the test status in the sub-graph status array; marking to be tested at the edge is to mark the test status in the edge status array.

[0228] Step 620, end.

[0229] The test result diagram in this embodiment is an eye diagram. If an eye diagram of (a×m)×(b×n) is to be generated, the sub-test diagram is divided according to the size of a×b. The memory requirements for visited require a×b / 8 (bytes), to_visit requires a×b / 8 (bytes), edge_to_visit requires m×n×(2×a+2×b) / 8 (bytes), and edge_visited requires m×n×(2×a+2×b) / 8 (bytes). Table 3 below shows the memory requirements for testing the hardware under test when combining different eye diagram sizes and different partition sizes. If the eye diagram size is 128×128 and the partition size is 32×32, the total memory required for testing is 0.75 kB (kilobytes). Bytes represents bytes, and 1 kB = 1024 bytes. As shown in Table 3, if the partition size is 32*32, then Shmoo measurements below 128*128 can all be satisfied by 1kB of memory.

[0230] Table 3

[0231]

[0232]

[0233] The hardware testing method provided in the embodiment of the present application reduces the memory requirements required for hardware testing, and can solve the problem that the Basic Input / Output System (BIOS) resources are limited and memory usage needs to be limited to within 1kB. For a 128×128 eye diagram, 34kB of memory is required when performing Shmoo measurement in a recursive manner, and 4kB of memory is required when performing Shmoo measurement in a non-recursive manner, both of which cannot meet the memory requirements.

[0234] Hardware test equipment

[0235] Corresponding to the above method embodiment, Figure 11 A schematic diagram of a hardware testing device is shown in FIG. Figure 11 As shown, the hardware test device includes:

[0236] The region selection module 901 is used to determine the target region from the test image, where the test image includes A×B regions, where A and B are both integers greater than 2;

[0237] A parallel testing module 902 is configured to perform parallel testing on multiple data channels included in the hardware under test under test parameters corresponding to the target area, and to determine the number of bit errors in data transmitted on the signal lines during the test, wherein each data channel includes multiple signal lines;

[0238] The result generating module 903 is configured to generate a test result of the hardware to be tested according to the number of bit errors corresponding to each signal line.

[0239] In one possible implementation, the parallel testing module 902 performs parallel testing on multiple data channels included in the hardware to be tested and determines the number of bit errors in data transmitted on the signal lines during the test, including:

[0240] Each signal line in the data channel is determined as a target signal line in turn, and the following steps are performed: first test data and second test data are transmitted in parallel through multiple data channels, with the first test data being transmitted through the target signal line and the second test data being transmitted through signal lines other than the target signal line in the data channel; and the number of bit errors after the first test data is transmitted through the target signal line is determined as the number of bit errors of the data transmitted on the target signal line.

[0241] In one possible implementation, the parallel testing module 902 determines a target area from a test chart, including: dividing the test chart into at least two sub-test charts, each sub-test chart including a×b areas, where a and b are integers equal to or greater than 2, and a is less than A, and b is less than B; generating a sub-chart state array, wherein the sub-chart state array is used to record the test status of the area in the sub-test chart; and performing the following processing on one or more sub-test charts in the at least two sub-test charts: determining a target area from the sub-test chart according to the sub-chart state array, and after parallel testing multiple data channels under test parameters corresponding to the target area, updating the sub-chart state array according to the number of bit errors of data transmitted on the signal line during the test, and initializing the sub-chart state array after the sub-chart state array indicates that there is no target area in the sub-test chart.

[0242] In one possible implementation, the parallel test module 902 updates the sub-graph state array according to the number of bit errors in the data transmitted on the signal line during the test process, including: updating the test status of the target area in the sub-graph state array to tested; if the number of bit errors corresponding to at least one signal line is within the value range after the parallel test, then marking the test status of the untested area adjacent to the target area as to be tested; wherein, the target area is determined from the area marked as to be tested in the sub-test graph.

[0243] In one possible implementation, the subgraph state array includes a first array and a second array;

[0244] The parallel testing module 902 updates the test status of the target area to tested in the subgraph status array, including: updating the value representing the test status of the target area in the first array from a first value to a second value, and updating the value representing the test status of the target area in the second array from a third value to a fourth value;

[0245] The parallel testing module 902 marks the test status of the untested area adjacent to the target area as to be tested, including: updating the value representing the test status of the to-be-tested area in the second array from the fourth value to the third value, wherein the to-be-tested area is the untested area adjacent to the target area in the test diagram.

[0246] In one possible implementation, the parallel testing module 902 determines the target area from the sub-test graph according to the sub-graph state array, including: according to the second array, determining the areas in the sub-test graph whose corresponding test state values are third values as target areas.

[0247] In one possible implementation, the parallel testing module 902 is further configured to generate an edge state array, wherein the edge state array is configured to record the test states of edge areas in at least two sub-test images; after performing parallel testing on multiple data channels under the test parameters corresponding to the target area, it is determined that the target area is located at the edge of the sub-test image, and the test state of the target area in the edge state array is updated to "tested."

[0248] In one possible implementation, the edge state array includes a third array and a fourth array;

[0249] The parallel testing module 902 updates the to-be-tested state of the target area in the edge state array to tested, including: updating the value representing the test state of the target area in the third array from the fifth value to the sixth value, and updating the value representing the test state of the target area in the fourth array from the seventh value to the eighth value.

[0250] In one possible implementation, the parallel testing module 902 is further configured to mark the test status of the area to be tested in the edge state array as to be tested if the area to be tested is located at the edge of any sub-test image in at least two sub-test images, wherein the area to be tested is an untested area adjacent to the target area in the test image.

[0251] In a possible implementation, the parallel testing module 902 marks the test status of the area to be tested in the edge status array as to be tested, including updating the value representing the test status of the area to be tested in the fourth array from the eighth value to the seventh value.

[0252] In one possible implementation, the parallel testing module 902 is further configured to, after completing the test of each target area in the sub-test image, determine the sub-test image for the next test based on the edge area to be tested corresponding to the test state in the edge state array; update the test state of the edge area of the sub-test image for the next test from the edge state array to the initialized sub-image state array, and perform the test of each target area in the sub-test image for the next test.

[0253] In one possible implementation, the result generation module 903 generates a test result graph corresponding to each signal line based on the number of bit errors corresponding to each signal line and the test results of the hardware to be tested, including: after the test of one or more sub-test graphs is completed, based on the number of bit errors obtained by testing each signal line on the test parameters corresponding to multiple target areas, generating a test result graph corresponding to each signal line.

[0254] It should be noted that the hardware testing device of this embodiment is used to implement the corresponding hardware testing method in the aforementioned method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0255] electronic devices

[0256] Figure 12 This is a schematic block diagram of an electronic device provided in an embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the electronic device. Figure 12 As shown, the electronic device may include: a processor 1002, a communications interface 1004, a memory 1006, and a communication bus 1008.

[0257] The processor 1002 , the communication interface 1004 , and the memory 1006 communicate with each other via a communication bus 1008 .

[0258] The communication interface 1004 is used to communicate with other electronic devices or servers.

[0259] The processor 1002 is configured to execute the program 1010 , and specifically may execute the relevant steps in any of the aforementioned hardware testing method embodiments.

[0260] Specifically, the program 1010 may include program codes, which include computer operation instructions.

[0261] The processor 1002 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs, or may be processors of different types, such as one or more CPUs and one or more ASICs.

[0262] RISC-V is an open-source instruction set architecture based on the principles of the Reduced Instruction Set (RISC). It can be applied to various fields, including microcontrollers and FPGA chips. Specifically, it has applications in areas such as IoT security, industrial control, mobile phones, and personal computers. Designed with small size, high speed, and low power consumption in mind, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. With the rise of the artificial intelligence (AI) Internet of Things (AIoT), the RISC-V instruction set architecture has also received increasing attention and support, and is expected to become the next generation of widely used CPU architecture.

[0263] The computer operation instructions in the embodiments of the present application may be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 1002 may be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in the embodiments of the present application may be a chip designed using the RISC-V instruction set. The chip may execute executable code based on the configured instructions, thereby implementing the hardware testing method in the above embodiments.

[0264] The memory 1006 is used to store the program 1010. The memory 1006 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0265] The program 1010 can be specifically used to enable the processor 1002 to execute the hardware testing method in any of the aforementioned embodiments.

[0266] The specific implementation of each step in program 1010 can refer to the corresponding description of the corresponding steps and units in any of the aforementioned hardware testing method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0267] Computer storage media

[0268] This application also provides a computer-readable storage medium storing instructions for causing a machine to execute the hardware testing method described herein. Specifically, a system or device equipped with a storage medium can be provided, wherein the storage medium stores software program code that implements the functions of any of the above-described embodiments, and a computer (or CPU or MPU) of the system or device can read and execute the program code stored in the storage medium.

[0269] In this case, the program code read from the storage medium itself can realize the function of any one of the above embodiments, so the program code and the storage medium storing the program code constitute part of this application.

[0270] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0271] Computer program product

[0272] An embodiment of the present application also provides a computer program product, including computer instructions, which instruct a computing device to perform any corresponding operation in the above-mentioned multiple method embodiments.

[0273] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0274] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as software or computer code that can be stored in a recording medium (such as CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or can be implemented as computer code that is originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded via a network and will be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a special-purpose processor or programmable or special-purpose hardware (such as ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a special-purpose computer for executing the method shown here.

[0275] Those skilled in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0276] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A hardware testing method, comprising: Determine a target area from a test image, wherein the test image includes A×B areas, where A and B are both integers greater than 2; Performing parallel testing on multiple data channels included in the hardware to be tested under test parameters corresponding to the target area, and determining the number of bit errors in data transmitted on the signal lines during the test, wherein each of the data channels includes multiple signal lines; Generating a test result of the hardware to be tested according to the number of bit errors corresponding to each of the signal lines; The method of determining a target area from a test chart includes: dividing the test chart into at least two sub-test charts, the sub-test chart including a×b areas, where a and b are both integers equal to or greater than 2, and a is less than A, and b is less than B; generating a sub-chart state array, wherein the sub-chart state array is used to record the test status of the areas in the sub-test chart; and performing the following processing on one or more sub-test charts of the at least two sub-test charts: determining the target area from the sub-test chart according to the sub-chart state array, and after parallel testing the multiple data channels under the test parameters corresponding to the target area, updating the sub-chart state array according to the number of bit errors of the data transmitted on the signal line during the test, and initializing the sub-chart state array after the sub-chart state array indicates that the target area does not exist in the sub-test chart.

2. The method according to claim 1, wherein The method of performing parallel testing on multiple data channels included in the hardware to be tested and determining the number of bit errors in data transmitted on the signal lines during the test includes: Each signal line in the data channel is determined as a target signal line in turn, and the following operations are performed: Transmitting first test data and second test data in parallel through the multiple data channels, wherein the first test data is transmitted through the target signal line, and the second test data is transmitted through signal lines in the data channels except the target signal line; The number of bit errors after the first test data is transmitted through the target signal line is determined as the number of bit errors of the data transmitted on the target signal line.

3. The method according to claim 1, wherein The updating of the subgraph state array according to the number of bit errors of the data transmitted on the signal line during the test process includes: Updating the test status of the target area to tested in the sub-graph status array; If the number of bit errors corresponding to at least one of the signal lines is within the value range after the parallel test, the test status of the untested area adjacent to the target area is marked as pending test; The target area is determined from the area marked as to-be-tested in the sub-test image.

4. The method according to claim 3, wherein: The subgraph state array includes a first array and a second array; Updating the test status of the target area to tested in the sub-graph status array includes: updating the value representing the test status of the target area in the first array from a first value to a second value, and updating the value representing the test status of the target area in the second array from a third value to a fourth value; Marking the test status of the untested area adjacent to the target area as to be tested includes: updating the value representing the test status of the to-be-tested area in the second array from the fourth value to the third value, wherein the to-be-tested area is the untested area adjacent to the target area in the test image.

5. The method according to claim 4, wherein The step of determining the target area from the sub-test image according to the sub-image state array includes: According to the second array, the regions in the sub-test graph whose values of the corresponding test states are the third values are respectively determined as the target regions.

6. The method according to claim 1, wherein The method further comprises: generating an edge state array, wherein the edge state array is used to record the test states of the edge areas in the at least two sub-test images; After performing parallel testing on the multiple data channels under the test parameters corresponding to the target area, it is determined that the target area is located at an edge of the sub-test pattern, and the test status of the target area in the edge status array is updated to tested.

7. The method according to claim 6, wherein: The edge state array includes a third array and a fourth array; The updating the to-be-tested state of the target area in the edge state array to tested includes: The value representing the test status of the target area in the third array is updated from the fifth value to the sixth value, and the value representing the test status of the target area in the fourth array is updated from the seventh value to the eighth value.

8. The method according to claim 7, wherein: The method further comprises: If the area to be tested is located at the edge of any of the at least two sub-test images, the test status of the area to be tested in the edge status array is marked as to be tested, wherein the area to be tested is an untested area in the test image adjacent to the target area.

9. The method according to claim 8, wherein The step of marking the test state of the to-be-tested area in the edge state array as to-be-tested comprises: The value representing the test status of the area to be tested in the fourth array is updated from the eighth value to the seventh value.

10. The method according to claim 6, wherein: The method further comprises: After completing the test of each target area in the sub-test image, determining the sub-test image to be tested next according to the edge area whose test state is to be tested in the edge state array; The test status of the edge area of the sub-test image of the next test is updated from the edge status array to the initialized sub-image status array, and the test of each target area in the sub-test image of the next test is performed.

11. The method according to claim 1, wherein Generating a test result of the hardware to be tested according to the number of bit errors corresponding to each of the signal lines includes: After the test of the one or more sub-test patterns is completed, a test result graph corresponding to each signal line is generated according to the number of bit errors obtained by testing each signal line on the test parameters corresponding to the multiple target areas.

12. A hardware testing device, comprising: An area selection module is used to determine a target area from a test image, wherein the test image includes A×B areas, where A and B are both integers greater than 2; a parallel testing module configured to perform parallel testing on a plurality of data channels included in the hardware to be tested under test parameters corresponding to the target area, and to determine the number of bit errors in data transmitted on the signal lines during the test, wherein each of the data channels includes a plurality of signal lines; A result generating module, configured to generate a test result of the hardware to be tested according to the number of bit errors corresponding to each of the signal lines; The area selection module determines a target area from a test chart, including: dividing the test chart into at least two sub-test charts, the sub-test chart including a×b areas, where a and b are both integers equal to or greater than 2, and a is less than A, and b is less than B; generating a sub-chart state array, wherein the sub-chart state array is used to record the test status of the areas in the sub-test chart; and performing the following processing on one or more sub-test charts of the at least two sub-test charts: determining the target area from the sub-test chart according to the sub-chart state array, and after parallel testing the multiple data channels under the test parameters corresponding to the target area, updating the sub-chart state array according to the number of bit errors of the data transmitted on the signal line during the test, until the sub-chart state array indicates that the target area does not exist in the sub-test chart, and then initializing the sub-chart state array.

13. An electronic device comprising: Processor, memory, communication interface and communication bus, the processor, memory and communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute an operation corresponding to the hardware testing method according to any one of claims 1 to 11.

14. A computer storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the hardware testing method according to any one of claims 1 to 11 is implemented.

15. A computer program product comprising computer instructions, wherein the computer instructions instruct a computing device to execute the hardware testing method according to any one of claims 1 to 11.

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